# Routing Mux Bits

# Non-Routing Configuration
.config DCU.CH0_LDR_CORE2TX_SEL 0
F27B1

.config DCU.CH0_LDR_RX2CORE_SEL 0
F77B1

.config DCU.CH0_LEQ_OFFSET_SEL 0
F90B1

.config DCU.CH0_LEQ_OFFSET_TRIM 000
F91B1
F92B1
F93B1

.config DCU.CH0_RATE_MODE_RX 0
F75B1

.config DCU.CH0_RATE_MODE_TX 0
F25B1

.config DCU.CH0_RCV_DCC_EN 0
F79B1

.config DCU.CH0_REQ_EN 0
F98B1

.config DCU.CH0_REQ_LVL_SET 00
F103B1
F104B1

.config DCU.CH0_RPWDNB 0
F74B1

.config DCU.CH0_RTERM_RX 00000
F82B1
F83B1
F84B1
F85B1
F86B1

.config DCU.CH0_RTERM_TX 00000
F32B1
F33B1
F34B1
F35B1
F36B1

.config DCU.CH0_RXIN_CM 00
F88B1
F89B1

.config DCU.CH0_RXTERM_CM 00
F80B1
F81B1

.config DCU.CH0_RX_DIV11_SEL 0
F76B1

.config DCU.CH0_RX_RATE_SEL 0000
F99B1
F100B1
F101B1
F102B1

.config DCU.CH0_TDRV_DAT_SEL 00
F70B1
F71B1

.config DCU.CH0_TDRV_POST_EN 0
F29B1

.config DCU.CH0_TDRV_PRE_EN 0
F28B1

.config DCU.CH0_TDRV_SLICE0_CUR 000
F58B1
F59B1
F60B1

.config DCU.CH0_TDRV_SLICE0_SEL 00
F40B1
F41B1

.config DCU.CH0_TDRV_SLICE1_CUR 000
F61B1
F62B1
F63B1

.config DCU.CH0_TDRV_SLICE1_SEL 00
F42B1
F43B1

.config DCU.CH0_TDRV_SLICE2_CUR 00
F64B1
F65B1

.config DCU.CH0_TDRV_SLICE2_SEL 00
F44B1
F45B1

.config DCU.CH0_TDRV_SLICE3_CUR 00
F54B1
F55B1

.config DCU.CH0_TDRV_SLICE3_SEL 00
F46B1
F47B1

.config DCU.CH0_TDRV_SLICE4_CUR 00
F56B1
F57B1

.config DCU.CH0_TDRV_SLICE4_SEL 00
F48B1
F49B1

.config DCU.CH0_TDRV_SLICE5_CUR 00
F72B1
F73B1

.config DCU.CH0_TDRV_SLICE5_SEL 00
F50B1
F51B1

.config DCU.CH0_TPWDNB 0
F24B1

.config DCU.CH0_TX_CM_SEL 00
F37B1
F38B1

.config DCU.CH0_TX_DIV11_SEL 0
F26B1

.config DCU.CH0_TX_POST_SIGN 0
F31B1

.config DCU.CH0_TX_PRE_SIGN 0
F30B1

.config DCU.CH0_UDF_COMMA_A 0011111111
-
-
-
-
-
-
-
-
F14B1
F15B1

.config DCU.CH0_UDF_COMMA_B 0000000000
F0B1
F1B1
F2B1
F3B1
F4B1
F5B1
F6B1
F7B1
F12B1
F13B1

.config DCU.CH0_UDF_COMMA_MASK 0011111111
-
-
-
-
-
-
-
-
F10B1
F11B1


# Fixed Connections