# Routing Mux Bits

# Non-Routing Configuration
.config DCU.CH1_CC_MATCH_1 0011111111
-
-
-
-
-
-
-
-
F16B1
F17B1

.config DCU.CH1_CC_MATCH_2 0011111111
-
-
-
-
-
-
-
-
F18B1
F19B1

.config DCU.CH1_CC_MATCH_3 0000000000
F0B1
F1B1
F2B1
F3B1
F4B1
F5B1
F6B1
F7B1
F20B1
F21B1

.config DCU.CH1_CC_MATCH_4 0000000000
F8B1
F9B1
F10B1
F11B1
F12B1
F13B1
F14B1
F15B1
F22B1
F23B1

.config DCU.CH1_LDR_CORE2TX_SEL 0
F69B1

.config DCU.CH1_RATE_MODE_TX 0
F67B1

.config DCU.CH1_RTERM_TX 00000
F74B1
F75B1
F76B1
F77B1
F78B1

.config DCU.CH1_TDRV_POST_EN 0
F71B1

.config DCU.CH1_TDRV_PRE_EN 0
F70B1

.config DCU.CH1_TDRV_SLICE0_CUR 000
F98B1
F99B1
F100B1

.config DCU.CH1_TDRV_SLICE0_SEL 00
F82B1
F83B1

.config DCU.CH1_TDRV_SLICE1_CUR 000
F101B1
F102B1
F103B1

.config DCU.CH1_TDRV_SLICE1_SEL 00
F84B1
F85B1

.config DCU.CH1_TDRV_SLICE2_CUR 00
F104B1
F105B1

.config DCU.CH1_TDRV_SLICE2_SEL 00
F86B1
F87B1

.config DCU.CH1_TDRV_SLICE3_CUR 00
F94B1
F95B1

.config DCU.CH1_TDRV_SLICE3_SEL 00
F88B1
F89B1

.config DCU.CH1_TDRV_SLICE4_CUR 00
F96B1
F97B1

.config DCU.CH1_TDRV_SLICE4_SEL 00
F90B1
F91B1

.config DCU.CH1_TDRV_SLICE5_SEL 00
F92B1
F93B1

.config DCU.CH1_TPWDNB 0
F66B1

.config DCU.CH1_TX_CM_SEL 00
F79B1
F80B1

.config DCU.CH1_TX_DIV11_SEL 0
F68B1

.config DCU.CH1_TX_POST_SIGN 0
F73B1

.config DCU.CH1_TX_PRE_SIGN 0
F72B1

.config DCU.CH1_UDF_COMMA_A 0000000000
F32B1
F33B1
F34B1
F35B1
F36B1
F37B1
F38B1
F39B1
F56B1
F57B1

.config DCU.CH1_UDF_COMMA_B 0000000000
F40B1
F41B1
F42B1
F43B1
F44B1
F45B1
F46B1
F47B1
F54B1
F55B1

.config DCU.CH1_UDF_COMMA_MASK 0000000000
F24B1
F25B1
F26B1
F27B1
F28B1
F29B1
F30B1
F31B1
F50B1
F51B1


# Fixed Connections