Update to prjtrellis b2754c6ce4697d8dd3245163dbc74a45394c5642
Signed-off-by: David Shah <davey1576@gmail.com>
diff --git a/ECP5/tiledata/MIB2_DSP1/bits.db b/ECP5/tiledata/MIB2_DSP1/bits.db
index df36eab..e08a6e4 100644
--- a/ECP5/tiledata/MIB2_DSP1/bits.db
+++ b/ECP5/tiledata/MIB2_DSP1/bits.db
@@ -197,6 +197,10 @@
CLK3 F98B1 F101B1
NONE -
+.config_enum DSP_LEFT.CIBOUT OFF
+OFF -
+ON F14B1 F16B1
+
.config_enum MULT18_0.MODE NONE
MULT18X18D F72B0 F90B0 F101B0
NONE -
diff --git a/ECP5/tiledata/MIB2_DSP3/bits.db b/ECP5/tiledata/MIB2_DSP3/bits.db
index 717e509..17d669e 100644
--- a/ECP5/tiledata/MIB2_DSP3/bits.db
+++ b/ECP5/tiledata/MIB2_DSP3/bits.db
@@ -454,6 +454,10 @@
ASYNC F2B1 F12B1
SYNC -
+.config_enum DSP_LEFT.CIBOUT OFF
+OFF -
+ON F90B1 F91B1 F92B1 F93B1
+
.config_enum MULT18_0.MODE NONE
MULT18X18D F30B0 F34B1
NONE -
diff --git a/ECP5/tiledata/MIB2_DSP4/bits.db b/ECP5/tiledata/MIB2_DSP4/bits.db
index d3165ce..5346001 100644
--- a/ECP5/tiledata/MIB2_DSP4/bits.db
+++ b/ECP5/tiledata/MIB2_DSP4/bits.db
@@ -194,6 +194,10 @@
CLK3 F95B1 F96B1
NONE -
+.config_enum DSP_RIGHT.CIBOUT OFF
+OFF -
+ON F69B1 F70B1
+
.config_enum MULT18_0.REG_INPUTA_CE CE3
CE0 F2B1 F3B1 F17B1 F18B1 F42B1 F43B1
CE1 F3B1 F17B1 F43B1
diff --git a/ECP5/tiledata/MIB2_DSP8/bits.db b/ECP5/tiledata/MIB2_DSP8/bits.db
index 7cfd6e3..1f5be81 100644
--- a/ECP5/tiledata/MIB2_DSP8/bits.db
+++ b/ECP5/tiledata/MIB2_DSP8/bits.db
@@ -200,6 +200,10 @@
CLK3 F49B1 F66B1
NONE -
+.config_enum DSP_RIGHT.CIBOUT OFF
+OFF -
+ON F20B1 F21B1 F22B1 F25B1
+
.config_enum MULT18_4.REG_INPUTA_CE CE3
CE0 F54B1 F55B1 F68B1 F69B1 F91B1 F92B1
CE1 F54B1 F68B1 F92B1
