Update to prjtrellis 36f34fe5398bdb14c074a317dd0674fcb7742c35 Signed-off-by: David Shah <dave@ds0.me>
diff --git a/ECP5/tiledata/DSP_CMUX_UL/bits.db b/ECP5/tiledata/DSP_CMUX_UL/bits.db index d7377f6..c8f8437 100644 --- a/ECP5/tiledata/DSP_CMUX_UL/bits.db +++ b/ECP5/tiledata/DSP_CMUX_UL/bits.db
@@ -1,6 +1,19 @@ # Routing Mux Bits # Non-Routing Configuration +.config_enum DCS0.DCSMODE NEG +CLK0 F70B0 F72B0 F75B0 F77B0 +CLK0_HIGH F72B0 F73B0 F77B0 F78B0 +CLK0_LOW F72B0 F77B0 +CLK1 F70B0 F72B0 F73B0 F75B0 F77B0 F78B0 +CLK1_HIGH F71B0 F73B0 F76B0 F78B0 +CLK1_LOW F71B0 F76B0 +HIGH F70B0 F71B0 F72B0 F73B0 F75B0 F76B0 F77B0 F78B0 +LOW F70B0 F71B0 F72B0 F75B0 F76B0 F77B0 +NEG - +NONE - +POS F73B0 F78B0 + # Fixed Connections .fixed_conn G_CLK0_DCS0 G_DCS0CLK0
diff --git a/ECP5/tiledata/EBR_CMUX_LL/bits.db b/ECP5/tiledata/EBR_CMUX_LL/bits.db index c37c120..0cd0b8b 100644 --- a/ECP5/tiledata/EBR_CMUX_LL/bits.db +++ b/ECP5/tiledata/EBR_CMUX_LL/bits.db
@@ -12,6 +12,19 @@ - - +.config_enum DCS1.DCSMODE NEG +CLK0 F70B0 F72B0 F75B0 F77B0 +CLK0_HIGH F72B0 F73B0 F77B0 F78B0 +CLK0_LOW F72B0 F77B0 +CLK1 F70B0 F72B0 F73B0 F75B0 F77B0 F78B0 +CLK1_HIGH F71B0 F73B0 F76B0 F78B0 +CLK1_LOW F71B0 F76B0 +HIGH F70B0 F71B0 F72B0 F73B0 F75B0 F76B0 F77B0 F78B0 +LOW F70B0 F71B0 F72B0 F75B0 F76B0 F77B0 +NEG - +NONE - +POS F73B0 F78B0 + .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 1 F55B0 18 !F55B0
diff --git a/ECP5/tiledata/EBR_CMUX_LL_25K/bits.db b/ECP5/tiledata/EBR_CMUX_LL_25K/bits.db index d13466e..fbd3e86 100644 --- a/ECP5/tiledata/EBR_CMUX_LL_25K/bits.db +++ b/ECP5/tiledata/EBR_CMUX_LL_25K/bits.db
@@ -1,5 +1,18 @@ # Routing Mux Bits # Non-Routing Configuration +.config_enum DCS1.DCSMODE NEG +CLK0 F70B0 F72B0 F75B0 F77B0 +CLK0_HIGH F72B0 F73B0 F77B0 F78B0 +CLK0_LOW F72B0 F77B0 +CLK1 F70B0 F72B0 F73B0 F75B0 F77B0 F78B0 +CLK1_HIGH F71B0 F73B0 F76B0 F78B0 +CLK1_LOW F71B0 F76B0 +HIGH F70B0 F71B0 F72B0 F73B0 F75B0 F76B0 F77B0 F78B0 +LOW F70B0 F71B0 F72B0 F75B0 F76B0 F77B0 +NEG - +NONE - +POS F73B0 F78B0 + # Fixed Connections
diff --git a/ECP5/tiledata/EBR_CMUX_UL/bits.db b/ECP5/tiledata/EBR_CMUX_UL/bits.db index a0ee5f2..851e9b1 100644 --- a/ECP5/tiledata/EBR_CMUX_UL/bits.db +++ b/ECP5/tiledata/EBR_CMUX_UL/bits.db
@@ -12,6 +12,19 @@ - - +.config_enum DCS0.DCSMODE NEG +CLK0 F70B0 F72B0 F75B0 F77B0 +CLK0_HIGH F72B0 F73B0 F77B0 F78B0 +CLK0_LOW F72B0 F77B0 +CLK1 F70B0 F72B0 F73B0 F75B0 F77B0 F78B0 +CLK1_HIGH F71B0 F73B0 F76B0 F78B0 +CLK1_LOW F71B0 F76B0 +HIGH F70B0 F71B0 F72B0 F73B0 F75B0 F76B0 F77B0 F78B0 +LOW F70B0 F71B0 F72B0 F75B0 F76B0 F77B0 +NEG - +NONE - +POS F73B0 F78B0 + .config_enum EBR3.DP16KD.DATA_WIDTH_B 18 1 F55B0 18 !F55B0