diff --git a/ECP5/timing/cell_timing_6.html b/ECP5/timing/cell_timing_6.html
index e0b835e..9ddd5a6 100644
--- a/ECP5/timing/cell_timing_6.html
+++ b/ECP5/timing/cell_timing_6.html
@@ -13,6 +13,13 @@
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH</a></li>
+<li><a href='#IOLOGIC:MODE=IDDRX1F'>IOLOGIC:MODE=IDDRX1F</a></li>
+<li><a href='#IOLOGIC:MODE=IDDRX2F'>IOLOGIC:MODE=IDDRX2F</a></li>
+<li><a href='#IOLOGIC:MODE=IREG'>IOLOGIC:MODE=IREG</a></li>
+<li><a href='#IOLOGIC:MODE=ODDRX1F'>IOLOGIC:MODE=ODDRX1F</a></li>
+<li><a href='#IOLOGIC:MODE=ODDRX2F'>IOLOGIC:MODE=ODDRX2F</a></li>
+<li><a href='#IOLOGIC:MODE=OREG'>IOLOGIC:MODE=OREG</a></li>
+<li><a href='#IOLOGIC:MODE=TSREG'>IOLOGIC:MODE=TSREG</a></li>
 <li><a href='#MULT18X18D:REGS=ALL'>MULT18X18D:REGS=ALL</a></li>
 <li><a href='#MULT18X18D:REGS=INPUT'>MULT18X18D:REGS=INPUT</a></li>
 <li><a href='#MULT18X18D:REGS=NONE'>MULT18X18D:REGS=NONE</a></li>
@@ -4353,6 +4360,397 @@
 </tbody>
 </table>
 <hr/>
+<a name='IOLOGIC:MODE=IDDRX1F'/>
+<h2>IOLOGIC:MODE=IDDRX1F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>RXDATA0</td>
+<td>356</td><td>356</td><td>356</td>
+<td>356</td><td>356</td><td>356</td>
+</tr>
+<tr >
+<td>CLK</td><td>RXDATA1</td>
+<td>356</td><td>356</td><td>356</td>
+<td>356</td><td>356</td><td>356</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>DI</td><td>posedge CLK</td>
+<td>401</td><td>401</td><td>401</td>
+<td>235</td><td>235</td><td>235</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=IDDRX2F'/>
+<h2>IOLOGIC:MODE=IDDRX2F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>RXDATA0</td>
+<td>453</td><td>453</td><td>453</td>
+<td>453</td><td>453</td><td>453</td>
+</tr>
+<tr >
+<td>CLK</td><td>RXDATA1</td>
+<td>453</td><td>453</td><td>453</td>
+<td>453</td><td>453</td><td>453</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>RXDATA2</td>
+<td>453</td><td>453</td><td>453</td>
+<td>453</td><td>453</td><td>453</td>
+</tr>
+<tr >
+<td>CLK</td><td>RXDATA3</td>
+<td>453</td><td>453</td><td>453</td>
+<td>453</td><td>453</td><td>453</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>DI</td><td>posedge ECLK</td>
+<td>445</td><td>445</td><td>445</td>
+<td>12</td><td>12</td><td>12</td>
+</tr>
+<tr >
+<td>posedge ECLK</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge ECLK</td>
+<td>1799</td><td>1799</td><td>1799</td>
+<td>278</td><td>278</td><td>278</td>
+</tr>
+<tr >
+<td>posedge ECLK</td>
+<td>1799</td><td>1799</td><td>1799</td>
+<td>278</td><td>278</td><td>278</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=IREG'/>
+<h2>IOLOGIC:MODE=IREG</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>INFF</td>
+<td>474</td><td>474</td><td>474</td>
+<td>474</td><td>474</td><td>474</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CE</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>77</td><td>77</td><td>77</td>
+</tr>
+<tr >
+<td>DI</td><td>posedge CLK</td>
+<td>439</td><td>439</td><td>439</td>
+<td>311</td><td>311</td><td>311</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>LSR</td><td>posedge CLK</td>
+<td>128</td><td>128</td><td>128</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>1945</td><td>1945</td><td>1945</td>
+<td>257</td><td>257</td><td>257</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>1945</td><td>1945</td><td>1945</td>
+<td>257</td><td>257</td><td>257</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=ODDRX1F'/>
+<h2>IOLOGIC:MODE=ODDRX1F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>IOLDO</td>
+<td>983</td><td>985</td><td>987</td>
+<td>983</td><td>985</td><td>987</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=ODDRX2F'/>
+<h2>IOLOGIC:MODE=ODDRX2F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>ECLK</td><td>IOLDO</td>
+<td>1287</td><td>1295</td><td>1303</td>
+<td>1287</td><td>1295</td><td>1303</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>TXDATA0</td><td>posedge CLK</td>
+<td>113</td><td>113</td><td>113</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>TXDATA1</td><td>posedge CLK</td>
+<td>113</td><td>113</td><td>113</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>TXDATA2</td><td>posedge CLK</td>
+<td>113</td><td>113</td><td>113</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>TXDATA3</td><td>posedge CLK</td>
+<td>113</td><td>113</td><td>113</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>posedge CLK</td><td>posedge ECLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge ECLK</td>
+<td>1600</td><td>1600</td><td>1600</td>
+<td>312</td><td>312</td><td>312</td>
+</tr>
+<tr >
+<td>posedge ECLK</td>
+<td>1600</td><td>1600</td><td>1600</td>
+<td>312</td><td>312</td><td>312</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=OREG'/>
+<h2>IOLOGIC:MODE=OREG</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>IOLDO</td>
+<td>1200</td><td>1200</td><td>1200</td>
+<td>1200</td><td>1200</td><td>1200</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CE</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>74</td><td>74</td><td>74</td>
+</tr>
+<tr >
+<td>LSR</td><td>posedge CLK</td>
+<td>141</td><td>141</td><td>141</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>TXDATA0</td><td>posedge CLK</td>
+<td>148</td><td>148</td><td>148</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>1945</td><td>1945</td><td>1945</td>
+<td>257</td><td>257</td><td>257</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>1945</td><td>1945</td><td>1945</td>
+<td>257</td><td>257</td><td>257</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=TSREG'/>
+<h2>IOLOGIC:MODE=TSREG</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>IOLTO</td>
+<td>1031</td><td>1031</td><td>1031</td>
+<td>1031</td><td>1031</td><td>1031</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CE</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>74</td><td>74</td><td>74</td>
+</tr>
+<tr >
+<td>LSR</td><td>posedge CLK</td>
+<td>141</td><td>141</td><td>141</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>TSDATA0</td><td>posedge CLK</td>
+<td>205</td><td>205</td><td>205</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>1945</td><td>1945</td><td>1945</td>
+<td>257</td><td>257</td><td>257</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>1945</td><td>1945</td><td>1945</td>
+<td>257</td><td>257</td><td>257</td>
+</tr>
+</tbody>
+</table>
+<hr/>
 <a name='MULT18X18D:REGS=ALL'/>
 <h2>MULT18X18D:REGS=ALL</h2>
 <h3>Propagation Delays</h3>
diff --git a/ECP5/timing/cell_timing_7.html b/ECP5/timing/cell_timing_7.html
index 45b7431..0c0a842 100644
--- a/ECP5/timing/cell_timing_7.html
+++ b/ECP5/timing/cell_timing_7.html
@@ -13,6 +13,13 @@
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH</a></li>
+<li><a href='#IOLOGIC:MODE=IDDRX1F'>IOLOGIC:MODE=IDDRX1F</a></li>
+<li><a href='#IOLOGIC:MODE=IDDRX2F'>IOLOGIC:MODE=IDDRX2F</a></li>
+<li><a href='#IOLOGIC:MODE=IREG'>IOLOGIC:MODE=IREG</a></li>
+<li><a href='#IOLOGIC:MODE=ODDRX1F'>IOLOGIC:MODE=ODDRX1F</a></li>
+<li><a href='#IOLOGIC:MODE=ODDRX2F'>IOLOGIC:MODE=ODDRX2F</a></li>
+<li><a href='#IOLOGIC:MODE=OREG'>IOLOGIC:MODE=OREG</a></li>
+<li><a href='#IOLOGIC:MODE=TSREG'>IOLOGIC:MODE=TSREG</a></li>
 <li><a href='#MULT18X18D:REGS=ALL'>MULT18X18D:REGS=ALL</a></li>
 <li><a href='#MULT18X18D:REGS=INPUT'>MULT18X18D:REGS=INPUT</a></li>
 <li><a href='#MULT18X18D:REGS=NONE'>MULT18X18D:REGS=NONE</a></li>
@@ -4353,6 +4360,397 @@
 </tbody>
 </table>
 <hr/>
+<a name='IOLOGIC:MODE=IDDRX1F'/>
+<h2>IOLOGIC:MODE=IDDRX1F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>RXDATA0</td>
+<td>318</td><td>318</td><td>318</td>
+<td>318</td><td>318</td><td>318</td>
+</tr>
+<tr >
+<td>CLK</td><td>RXDATA1</td>
+<td>318</td><td>318</td><td>318</td>
+<td>318</td><td>318</td><td>318</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>DI</td><td>posedge CLK</td>
+<td>353</td><td>353</td><td>353</td>
+<td>215</td><td>215</td><td>215</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=IDDRX2F'/>
+<h2>IOLOGIC:MODE=IDDRX2F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>RXDATA0</td>
+<td>403</td><td>403</td><td>403</td>
+<td>403</td><td>403</td><td>403</td>
+</tr>
+<tr >
+<td>CLK</td><td>RXDATA1</td>
+<td>403</td><td>403</td><td>403</td>
+<td>403</td><td>403</td><td>403</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>RXDATA2</td>
+<td>403</td><td>403</td><td>403</td>
+<td>403</td><td>403</td><td>403</td>
+</tr>
+<tr >
+<td>CLK</td><td>RXDATA3</td>
+<td>403</td><td>403</td><td>403</td>
+<td>403</td><td>403</td><td>403</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>DI</td><td>posedge ECLK</td>
+<td>365</td><td>365</td><td>365</td>
+<td>55</td><td>55</td><td>55</td>
+</tr>
+<tr >
+<td>posedge ECLK</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge ECLK</td>
+<td>1524</td><td>1524</td><td>1524</td>
+<td>328</td><td>328</td><td>328</td>
+</tr>
+<tr >
+<td>posedge ECLK</td>
+<td>1524</td><td>1524</td><td>1524</td>
+<td>328</td><td>328</td><td>328</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=IREG'/>
+<h2>IOLOGIC:MODE=IREG</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>INFF</td>
+<td>419</td><td>419</td><td>419</td>
+<td>419</td><td>419</td><td>419</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CE</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>69</td><td>69</td><td>69</td>
+</tr>
+<tr >
+<td>DI</td><td>posedge CLK</td>
+<td>378</td><td>378</td><td>378</td>
+<td>285</td><td>285</td><td>285</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>LSR</td><td>posedge CLK</td>
+<td>105</td><td>105</td><td>105</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>1648</td><td>1648</td><td>1648</td>
+<td>303</td><td>303</td><td>303</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>1648</td><td>1648</td><td>1648</td>
+<td>303</td><td>303</td><td>303</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=ODDRX1F'/>
+<h2>IOLOGIC:MODE=ODDRX1F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>IOLDO</td>
+<td>861</td><td>863</td><td>865</td>
+<td>861</td><td>863</td><td>865</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=ODDRX2F'/>
+<h2>IOLOGIC:MODE=ODDRX2F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>ECLK</td><td>IOLDO</td>
+<td>1131</td><td>1136</td><td>1141</td>
+<td>1131</td><td>1136</td><td>1141</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>TXDATA0</td><td>posedge CLK</td>
+<td>103</td><td>103</td><td>103</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>TXDATA1</td><td>posedge CLK</td>
+<td>103</td><td>103</td><td>103</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>TXDATA2</td><td>posedge CLK</td>
+<td>103</td><td>103</td><td>103</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>TXDATA3</td><td>posedge CLK</td>
+<td>103</td><td>103</td><td>103</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>posedge CLK</td><td>posedge ECLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge ECLK</td>
+<td>1425</td><td>1425</td><td>1425</td>
+<td>351</td><td>351</td><td>351</td>
+</tr>
+<tr >
+<td>posedge ECLK</td>
+<td>1425</td><td>1425</td><td>1425</td>
+<td>351</td><td>351</td><td>351</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=OREG'/>
+<h2>IOLOGIC:MODE=OREG</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>IOLDO</td>
+<td>1109</td><td>1109</td><td>1109</td>
+<td>1109</td><td>1109</td><td>1109</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CE</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>66</td><td>66</td><td>66</td>
+</tr>
+<tr >
+<td>LSR</td><td>posedge CLK</td>
+<td>117</td><td>117</td><td>117</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>TXDATA0</td><td>posedge CLK</td>
+<td>130</td><td>130</td><td>130</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>1648</td><td>1648</td><td>1648</td>
+<td>303</td><td>303</td><td>303</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>1648</td><td>1648</td><td>1648</td>
+<td>303</td><td>303</td><td>303</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=TSREG'/>
+<h2>IOLOGIC:MODE=TSREG</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>IOLTO</td>
+<td>898</td><td>898</td><td>898</td>
+<td>898</td><td>898</td><td>898</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CE</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>66</td><td>66</td><td>66</td>
+</tr>
+<tr >
+<td>LSR</td><td>posedge CLK</td>
+<td>117</td><td>117</td><td>117</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>TSDATA0</td><td>posedge CLK</td>
+<td>180</td><td>180</td><td>180</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>1648</td><td>1648</td><td>1648</td>
+<td>303</td><td>303</td><td>303</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>1648</td><td>1648</td><td>1648</td>
+<td>303</td><td>303</td><td>303</td>
+</tr>
+</tbody>
+</table>
+<hr/>
 <a name='MULT18X18D:REGS=ALL'/>
 <h2>MULT18X18D:REGS=ALL</h2>
 <h3>Propagation Delays</h3>
diff --git a/ECP5/timing/cell_timing_8.html b/ECP5/timing/cell_timing_8.html
index 7d52c14..ffc7b1d 100644
--- a/ECP5/timing/cell_timing_8.html
+++ b/ECP5/timing/cell_timing_8.html
@@ -13,6 +13,13 @@
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH</a></li>
+<li><a href='#IOLOGIC:MODE=IDDRX1F'>IOLOGIC:MODE=IDDRX1F</a></li>
+<li><a href='#IOLOGIC:MODE=IDDRX2F'>IOLOGIC:MODE=IDDRX2F</a></li>
+<li><a href='#IOLOGIC:MODE=IREG'>IOLOGIC:MODE=IREG</a></li>
+<li><a href='#IOLOGIC:MODE=ODDRX1F'>IOLOGIC:MODE=ODDRX1F</a></li>
+<li><a href='#IOLOGIC:MODE=ODDRX2F'>IOLOGIC:MODE=ODDRX2F</a></li>
+<li><a href='#IOLOGIC:MODE=OREG'>IOLOGIC:MODE=OREG</a></li>
+<li><a href='#IOLOGIC:MODE=TSREG'>IOLOGIC:MODE=TSREG</a></li>
 <li><a href='#MULT18X18D:REGS=ALL'>MULT18X18D:REGS=ALL</a></li>
 <li><a href='#MULT18X18D:REGS=INPUT'>MULT18X18D:REGS=INPUT</a></li>
 <li><a href='#MULT18X18D:REGS=NONE'>MULT18X18D:REGS=NONE</a></li>
@@ -4353,6 +4360,397 @@
 </tbody>
 </table>
 <hr/>
+<a name='IOLOGIC:MODE=IDDRX1F'/>
+<h2>IOLOGIC:MODE=IDDRX1F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>RXDATA0</td>
+<td>281</td><td>281</td><td>281</td>
+<td>281</td><td>281</td><td>281</td>
+</tr>
+<tr >
+<td>CLK</td><td>RXDATA1</td>
+<td>281</td><td>281</td><td>281</td>
+<td>281</td><td>281</td><td>281</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>DI</td><td>posedge CLK</td>
+<td>305</td><td>305</td><td>305</td>
+<td>197</td><td>197</td><td>197</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=IDDRX2F'/>
+<h2>IOLOGIC:MODE=IDDRX2F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>RXDATA0</td>
+<td>353</td><td>353</td><td>353</td>
+<td>353</td><td>353</td><td>353</td>
+</tr>
+<tr >
+<td>CLK</td><td>RXDATA1</td>
+<td>353</td><td>353</td><td>353</td>
+<td>353</td><td>353</td><td>353</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>RXDATA2</td>
+<td>353</td><td>353</td><td>353</td>
+<td>353</td><td>353</td><td>353</td>
+</tr>
+<tr >
+<td>CLK</td><td>RXDATA3</td>
+<td>353</td><td>353</td><td>353</td>
+<td>353</td><td>353</td><td>353</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>DI</td><td>posedge ECLK</td>
+<td>284</td><td>284</td><td>284</td>
+<td>98</td><td>98</td><td>98</td>
+</tr>
+<tr >
+<td>posedge ECLK</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge ECLK</td>
+<td>1250</td><td>1250</td><td>1250</td>
+<td>400</td><td>400</td><td>400</td>
+</tr>
+<tr >
+<td>posedge ECLK</td>
+<td>1250</td><td>1250</td><td>1250</td>
+<td>400</td><td>400</td><td>400</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=IREG'/>
+<h2>IOLOGIC:MODE=IREG</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>INFF</td>
+<td>364</td><td>364</td><td>364</td>
+<td>364</td><td>364</td><td>364</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CE</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>62</td><td>62</td><td>62</td>
+</tr>
+<tr >
+<td>DI</td><td>posedge CLK</td>
+<td>317</td><td>317</td><td>317</td>
+<td>258</td><td>258</td><td>258</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>LSR</td><td>posedge CLK</td>
+<td>81</td><td>81</td><td>81</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>1351</td><td>1351</td><td>1351</td>
+<td>370</td><td>370</td><td>370</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>1351</td><td>1351</td><td>1351</td>
+<td>370</td><td>370</td><td>370</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=ODDRX1F'/>
+<h2>IOLOGIC:MODE=ODDRX1F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>IOLDO</td>
+<td>739</td><td>741</td><td>743</td>
+<td>739</td><td>741</td><td>743</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=ODDRX2F'/>
+<h2>IOLOGIC:MODE=ODDRX2F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>ECLK</td><td>IOLDO</td>
+<td>973</td><td>975</td><td>977</td>
+<td>973</td><td>975</td><td>977</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>TXDATA0</td><td>posedge CLK</td>
+<td>92</td><td>92</td><td>92</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>TXDATA1</td><td>posedge CLK</td>
+<td>92</td><td>92</td><td>92</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>TXDATA2</td><td>posedge CLK</td>
+<td>92</td><td>92</td><td>92</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>TXDATA3</td><td>posedge CLK</td>
+<td>92</td><td>92</td><td>92</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>posedge CLK</td><td>posedge ECLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge ECLK</td>
+<td>1250</td><td>1250</td><td>1250</td>
+<td>400</td><td>400</td><td>400</td>
+</tr>
+<tr >
+<td>posedge ECLK</td>
+<td>1250</td><td>1250</td><td>1250</td>
+<td>400</td><td>400</td><td>400</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=OREG'/>
+<h2>IOLOGIC:MODE=OREG</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>IOLDO</td>
+<td>1018</td><td>1018</td><td>1018</td>
+<td>1018</td><td>1018</td><td>1018</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CE</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>59</td><td>59</td><td>59</td>
+</tr>
+<tr >
+<td>LSR</td><td>posedge CLK</td>
+<td>92</td><td>92</td><td>92</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>TXDATA0</td><td>posedge CLK</td>
+<td>113</td><td>113</td><td>113</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>1351</td><td>1351</td><td>1351</td>
+<td>370</td><td>370</td><td>370</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>1351</td><td>1351</td><td>1351</td>
+<td>370</td><td>370</td><td>370</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=TSREG'/>
+<h2>IOLOGIC:MODE=TSREG</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>IOLTO</td>
+<td>763</td><td>763</td><td>763</td>
+<td>763</td><td>763</td><td>763</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CE</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>59</td><td>59</td><td>59</td>
+</tr>
+<tr >
+<td>LSR</td><td>posedge CLK</td>
+<td>92</td><td>92</td><td>92</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>TSDATA0</td><td>posedge CLK</td>
+<td>155</td><td>155</td><td>155</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>1351</td><td>1351</td><td>1351</td>
+<td>370</td><td>370</td><td>370</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>1351</td><td>1351</td><td>1351</td>
+<td>370</td><td>370</td><td>370</td>
+</tr>
+</tbody>
+</table>
+<hr/>
 <a name='MULT18X18D:REGS=ALL'/>
 <h2>MULT18X18D:REGS=ALL</h2>
 <h3>Propagation Delays</h3>
diff --git a/ECP5/timing/cell_timing_8_5G.html b/ECP5/timing/cell_timing_8_5G.html
index d63209e..9a2c5ed 100644
--- a/ECP5/timing/cell_timing_8_5G.html
+++ b/ECP5/timing/cell_timing_8_5G.html
@@ -13,6 +13,13 @@
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH</a></li>
+<li><a href='#IOLOGIC:MODE=IDDRX1F'>IOLOGIC:MODE=IDDRX1F</a></li>
+<li><a href='#IOLOGIC:MODE=IDDRX2F'>IOLOGIC:MODE=IDDRX2F</a></li>
+<li><a href='#IOLOGIC:MODE=IREG'>IOLOGIC:MODE=IREG</a></li>
+<li><a href='#IOLOGIC:MODE=ODDRX1F'>IOLOGIC:MODE=ODDRX1F</a></li>
+<li><a href='#IOLOGIC:MODE=ODDRX2F'>IOLOGIC:MODE=ODDRX2F</a></li>
+<li><a href='#IOLOGIC:MODE=OREG'>IOLOGIC:MODE=OREG</a></li>
+<li><a href='#IOLOGIC:MODE=TSREG'>IOLOGIC:MODE=TSREG</a></li>
 <li><a href='#MULT18X18D:REGS=ALL'>MULT18X18D:REGS=ALL</a></li>
 <li><a href='#MULT18X18D:REGS=INPUT'>MULT18X18D:REGS=INPUT</a></li>
 <li><a href='#MULT18X18D:REGS=NONE'>MULT18X18D:REGS=NONE</a></li>
@@ -4353,6 +4360,397 @@
 </tbody>
 </table>
 <hr/>
+<a name='IOLOGIC:MODE=IDDRX1F'/>
+<h2>IOLOGIC:MODE=IDDRX1F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>RXDATA0</td>
+<td>232</td><td>232</td><td>232</td>
+<td>232</td><td>232</td><td>232</td>
+</tr>
+<tr >
+<td>CLK</td><td>RXDATA1</td>
+<td>232</td><td>232</td><td>232</td>
+<td>232</td><td>232</td><td>232</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>DI</td><td>posedge CLK</td>
+<td>254</td><td>254</td><td>254</td>
+<td>164</td><td>164</td><td>164</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=IDDRX2F'/>
+<h2>IOLOGIC:MODE=IDDRX2F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>RXDATA0</td>
+<td>291</td><td>291</td><td>291</td>
+<td>291</td><td>291</td><td>291</td>
+</tr>
+<tr >
+<td>CLK</td><td>RXDATA1</td>
+<td>291</td><td>291</td><td>291</td>
+<td>291</td><td>291</td><td>291</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>RXDATA2</td>
+<td>291</td><td>291</td><td>291</td>
+<td>291</td><td>291</td><td>291</td>
+</tr>
+<tr >
+<td>CLK</td><td>RXDATA3</td>
+<td>291</td><td>291</td><td>291</td>
+<td>291</td><td>291</td><td>291</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>DI</td><td>posedge ECLK</td>
+<td>236</td><td>236</td><td>236</td>
+<td>81</td><td>81</td><td>81</td>
+</tr>
+<tr >
+<td>posedge ECLK</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge ECLK</td>
+<td>1250</td><td>1250</td><td>1250</td>
+<td>400</td><td>400</td><td>400</td>
+</tr>
+<tr >
+<td>posedge ECLK</td>
+<td>1250</td><td>1250</td><td>1250</td>
+<td>400</td><td>400</td><td>400</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=IREG'/>
+<h2>IOLOGIC:MODE=IREG</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>INFF</td>
+<td>301</td><td>301</td><td>301</td>
+<td>301</td><td>301</td><td>301</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CE</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>51</td><td>51</td><td>51</td>
+</tr>
+<tr >
+<td>DI</td><td>posedge CLK</td>
+<td>264</td><td>264</td><td>264</td>
+<td>215</td><td>215</td><td>215</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>LSR</td><td>posedge CLK</td>
+<td>66</td><td>66</td><td>66</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>1351</td><td>1351</td><td>1351</td>
+<td>370</td><td>370</td><td>370</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>1351</td><td>1351</td><td>1351</td>
+<td>370</td><td>370</td><td>370</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=ODDRX1F'/>
+<h2>IOLOGIC:MODE=ODDRX1F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>IOLDO</td>
+<td>611</td><td>612</td><td>614</td>
+<td>611</td><td>612</td><td>614</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>2000</td><td>2000</td><td>2000</td>
+<td>250</td><td>250</td><td>250</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=ODDRX2F'/>
+<h2>IOLOGIC:MODE=ODDRX2F</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>ECLK</td><td>IOLDO</td>
+<td>804</td><td>805</td><td>807</td>
+<td>804</td><td>805</td><td>807</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>TXDATA0</td><td>posedge CLK</td>
+<td>76</td><td>76</td><td>76</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>TXDATA1</td><td>posedge CLK</td>
+<td>76</td><td>76</td><td>76</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>TXDATA2</td><td>posedge CLK</td>
+<td>76</td><td>76</td><td>76</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>TXDATA3</td><td>posedge CLK</td>
+<td>76</td><td>76</td><td>76</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>posedge CLK</td><td>posedge ECLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge ECLK</td>
+<td>1250</td><td>1250</td><td>1250</td>
+<td>400</td><td>400</td><td>400</td>
+</tr>
+<tr >
+<td>posedge ECLK</td>
+<td>1250</td><td>1250</td><td>1250</td>
+<td>400</td><td>400</td><td>400</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=OREG'/>
+<h2>IOLOGIC:MODE=OREG</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>IOLDO</td>
+<td>841</td><td>841</td><td>841</td>
+<td>841</td><td>841</td><td>841</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CE</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>48</td><td>48</td><td>48</td>
+</tr>
+<tr >
+<td>LSR</td><td>posedge CLK</td>
+<td>76</td><td>76</td><td>76</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>TXDATA0</td><td>posedge CLK</td>
+<td>93</td><td>93</td><td>93</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>1351</td><td>1351</td><td>1351</td>
+<td>370</td><td>370</td><td>370</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>1351</td><td>1351</td><td>1351</td>
+<td>370</td><td>370</td><td>370</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='IOLOGIC:MODE=TSREG'/>
+<h2>IOLOGIC:MODE=TSREG</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK</td><td>IOLTO</td>
+<td>631</td><td>631</td><td>631</td>
+<td>631</td><td>631</td><td>631</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CE</td><td>posedge CLK</td>
+<td>0</td><td>0</td><td>0</td>
+<td>48</td><td>48</td><td>48</td>
+</tr>
+<tr >
+<td>LSR</td><td>posedge CLK</td>
+<td>76</td><td>76</td><td>76</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>TSDATA0</td><td>posedge CLK</td>
+<td>128</td><td>128</td><td>128</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<h3>Width Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>Clock</th>
+<th colspan='3'>Width (ps)</th><th colspan='3'>Equiv. Freq (MHz)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>negedge CLK</td>
+<td>1351</td><td>1351</td><td>1351</td>
+<td>370</td><td>370</td><td>370</td>
+</tr>
+<tr >
+<td>posedge CLK</td>
+<td>1351</td><td>1351</td><td>1351</td>
+<td>370</td><td>370</td><td>370</td>
+</tr>
+</tbody>
+</table>
+<hr/>
 <a name='MULT18X18D:REGS=ALL'/>
 <h2>MULT18X18D:REGS=ALL</h2>
 <h3>Propagation Delays</h3>