diff --git a/ECP5/timing/cell_timing_6.html b/ECP5/timing/cell_timing_6.html
index f4fc85f..e0b835e 100644
--- a/ECP5/timing/cell_timing_6.html
+++ b/ECP5/timing/cell_timing_6.html
@@ -13,6 +13,11 @@
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH</a></li>
+<li><a href='#MULT18X18D:REGS=ALL'>MULT18X18D:REGS=ALL</a></li>
+<li><a href='#MULT18X18D:REGS=INPUT'>MULT18X18D:REGS=INPUT</a></li>
+<li><a href='#MULT18X18D:REGS=NONE'>MULT18X18D:REGS=NONE</a></li>
+<li><a href='#MULT18X18D:REGS=OUTPUT'>MULT18X18D:REGS=OUTPUT</a></li>
+<li><a href='#MULT18X18D:REGS=PIPELINE'>MULT18X18D:REGS=PIPELINE</a></li>
 <li><a href='#PIO:IOTYPE=LVCMOS12'>PIO:IOTYPE=LVCMOS12</a></li>
 <li><a href='#PIO:IOTYPE=LVCMOS15'>PIO:IOTYPE=LVCMOS15</a></li>
 <li><a href='#PIO:IOTYPE=LVCMOS18'>PIO:IOTYPE=LVCMOS18</a></li>
@@ -4348,6 +4353,253 @@
 </tbody>
 </table>
 <hr/>
+<a name='MULT18X18D:REGS=ALL'/>
+<h2>MULT18X18D:REGS=ALL</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>578</td><td>656</td><td>735</td>
+<td>578</td><td>656</td><td>735</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>53</td><td>68</td><td>84</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>53</td><td>68</td><td>84</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>147</td><td>199</td><td>252</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>63</td><td>79</td><td>95</td>
+<td>63</td><td>73</td><td>84</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>137</td><td>152</td><td>168</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>137</td><td>152</td><td>168</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=INPUT'/>
+<h2>MULT18X18D:REGS=INPUT</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>2856</td><td>3360</td><td>3864</td>
+<td>2856</td><td>3360</td><td>3864</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>53</td><td>68</td><td>84</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>53</td><td>68</td><td>84</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>147</td><td>199</td><td>252</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>63</td><td>79</td><td>95</td>
+<td>63</td><td>73</td><td>84</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>137</td><td>152</td><td>168</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>137</td><td>152</td><td>168</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=NONE'/>
+<h2>MULT18X18D:REGS=NONE</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>P</td>
+<td>2909</td><td>3418</td><td>3927</td>
+<td>2909</td><td>3418</td><td>3927</td>
+</tr>
+<tr >
+<td>B</td><td>P</td>
+<td>2909</td><td>3418</td><td>3927</td>
+<td>2909</td><td>3418</td><td>3927</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>P</td>
+<td>2740</td><td>3234</td><td>3728</td>
+<td>2740</td><td>3234</td><td>3728</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>P</td>
+<td>2740</td><td>3234</td><td>3728</td>
+<td>2740</td><td>3234</td><td>3728</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=OUTPUT'/>
+<h2>MULT18X18D:REGS=OUTPUT</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>578</td><td>656</td><td>735</td>
+<td>578</td><td>656</td><td>735</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>3035</td><td>3260</td><td>3486</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>3035</td><td>3260</td><td>3486</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>147</td><td>199</td><td>252</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>63</td><td>79</td><td>95</td>
+<td>63</td><td>73</td><td>84</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>2877</td><td>3082</td><td>3287</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>2877</td><td>3082</td><td>3287</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=PIPELINE'/>
+<h2>MULT18X18D:REGS=PIPELINE</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>1302</td><td>1318</td><td>1334</td>
+<td>1302</td><td>1318</td><td>1334</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>2405</td><td>2515</td><td>2625</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>2405</td><td>2515</td><td>2625</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>147</td><td>199</td><td>252</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>63</td><td>79</td><td>95</td>
+<td>63</td><td>73</td><td>84</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>2247</td><td>2336</td><td>2425</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>2247</td><td>2336</td><td>2425</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<hr/>
 <a name='PIO:IOTYPE=LVCMOS12'/>
 <h2>PIO:IOTYPE=LVCMOS12</h2>
 <h3>Propagation Delays</h3>
diff --git a/ECP5/timing/cell_timing_7.html b/ECP5/timing/cell_timing_7.html
index 51e5034..45b7431 100644
--- a/ECP5/timing/cell_timing_7.html
+++ b/ECP5/timing/cell_timing_7.html
@@ -13,6 +13,11 @@
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH</a></li>
+<li><a href='#MULT18X18D:REGS=ALL'>MULT18X18D:REGS=ALL</a></li>
+<li><a href='#MULT18X18D:REGS=INPUT'>MULT18X18D:REGS=INPUT</a></li>
+<li><a href='#MULT18X18D:REGS=NONE'>MULT18X18D:REGS=NONE</a></li>
+<li><a href='#MULT18X18D:REGS=OUTPUT'>MULT18X18D:REGS=OUTPUT</a></li>
+<li><a href='#MULT18X18D:REGS=PIPELINE'>MULT18X18D:REGS=PIPELINE</a></li>
 <li><a href='#PIO:IOTYPE=LVCMOS12'>PIO:IOTYPE=LVCMOS12</a></li>
 <li><a href='#PIO:IOTYPE=LVCMOS15'>PIO:IOTYPE=LVCMOS15</a></li>
 <li><a href='#PIO:IOTYPE=LVCMOS18'>PIO:IOTYPE=LVCMOS18</a></li>
@@ -4348,6 +4353,253 @@
 </tbody>
 </table>
 <hr/>
+<a name='MULT18X18D:REGS=ALL'/>
+<h2>MULT18X18D:REGS=ALL</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>530</td><td>593</td><td>656</td>
+<td>530</td><td>593</td><td>656</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>37</td><td>50</td><td>63</td>
+<td>0</td><td>0</td><td>26</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>37</td><td>50</td><td>63</td>
+<td>0</td><td>0</td><td>26</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>147</td><td>189</td><td>231</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>74</td><td>89</td><td>105</td>
+<td>53</td><td>63</td><td>74</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>131</td><td>144</td><td>158</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>131</td><td>144</td><td>158</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=INPUT'/>
+<h2>MULT18X18D:REGS=INPUT</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>2583</td><td>3019</td><td>3455</td>
+<td>2583</td><td>3019</td><td>3455</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>37</td><td>50</td><td>63</td>
+<td>0</td><td>0</td><td>26</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>37</td><td>50</td><td>63</td>
+<td>0</td><td>0</td><td>26</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>147</td><td>189</td><td>231</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>74</td><td>89</td><td>105</td>
+<td>53</td><td>63</td><td>74</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>131</td><td>144</td><td>158</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>131</td><td>144</td><td>158</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=NONE'/>
+<h2>MULT18X18D:REGS=NONE</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>P</td>
+<td>2620</td><td>3058</td><td>3497</td>
+<td>2620</td><td>3058</td><td>3497</td>
+</tr>
+<tr >
+<td>B</td><td>P</td>
+<td>2620</td><td>3058</td><td>3497</td>
+<td>2620</td><td>3058</td><td>3497</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>P</td>
+<td>2473</td><td>2898</td><td>3323</td>
+<td>2473</td><td>2898</td><td>3323</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>P</td>
+<td>2473</td><td>2898</td><td>3323</td>
+<td>2473</td><td>2898</td><td>3323</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=OUTPUT'/>
+<h2>MULT18X18D:REGS=OUTPUT</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>530</td><td>593</td><td>656</td>
+<td>530</td><td>593</td><td>656</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>2699</td><td>2880</td><td>3061</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>2699</td><td>2880</td><td>3061</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>147</td><td>189</td><td>231</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>74</td><td>89</td><td>105</td>
+<td>53</td><td>63</td><td>74</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>2557</td><td>2722</td><td>2888</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>2557</td><td>2722</td><td>2888</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=PIPELINE'/>
+<h2>MULT18X18D:REGS=PIPELINE</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>1192</td><td>1207</td><td>1223</td>
+<td>1192</td><td>1207</td><td>1223</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>2121</td><td>2213</td><td>2305</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>2121</td><td>2213</td><td>2305</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>147</td><td>189</td><td>231</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>74</td><td>89</td><td>105</td>
+<td>53</td><td>63</td><td>74</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>1979</td><td>2055</td><td>2131</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>1979</td><td>2055</td><td>2131</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<hr/>
 <a name='PIO:IOTYPE=LVCMOS12'/>
 <h2>PIO:IOTYPE=LVCMOS12</h2>
 <h3>Propagation Delays</h3>
diff --git a/ECP5/timing/cell_timing_8.html b/ECP5/timing/cell_timing_8.html
index 37455d4..7d52c14 100644
--- a/ECP5/timing/cell_timing_8.html
+++ b/ECP5/timing/cell_timing_8.html
@@ -13,6 +13,11 @@
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH</a></li>
+<li><a href='#MULT18X18D:REGS=ALL'>MULT18X18D:REGS=ALL</a></li>
+<li><a href='#MULT18X18D:REGS=INPUT'>MULT18X18D:REGS=INPUT</a></li>
+<li><a href='#MULT18X18D:REGS=NONE'>MULT18X18D:REGS=NONE</a></li>
+<li><a href='#MULT18X18D:REGS=OUTPUT'>MULT18X18D:REGS=OUTPUT</a></li>
+<li><a href='#MULT18X18D:REGS=PIPELINE'>MULT18X18D:REGS=PIPELINE</a></li>
 <li><a href='#PIO:IOTYPE=LVCMOS12'>PIO:IOTYPE=LVCMOS12</a></li>
 <li><a href='#PIO:IOTYPE=LVCMOS15'>PIO:IOTYPE=LVCMOS15</a></li>
 <li><a href='#PIO:IOTYPE=LVCMOS18'>PIO:IOTYPE=LVCMOS18</a></li>
@@ -4348,6 +4353,253 @@
 </tbody>
 </table>
 <hr/>
+<a name='MULT18X18D:REGS=ALL'/>
+<h2>MULT18X18D:REGS=ALL</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>483</td><td>530</td><td>578</td>
+<td>483</td><td>530</td><td>578</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>21</td><td>31</td><td>42</td>
+<td>0</td><td>5</td><td>32</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>21</td><td>31</td><td>42</td>
+<td>0</td><td>5</td><td>32</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>147</td><td>178</td><td>210</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>84</td><td>100</td><td>116</td>
+<td>42</td><td>52</td><td>63</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>126</td><td>136</td><td>147</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>126</td><td>136</td><td>147</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=INPUT'/>
+<h2>MULT18X18D:REGS=INPUT</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>2310</td><td>2677</td><td>3045</td>
+<td>2310</td><td>2677</td><td>3045</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>21</td><td>31</td><td>42</td>
+<td>0</td><td>5</td><td>32</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>21</td><td>31</td><td>42</td>
+<td>0</td><td>5</td><td>32</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>147</td><td>178</td><td>210</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>84</td><td>100</td><td>116</td>
+<td>42</td><td>52</td><td>63</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>126</td><td>136</td><td>147</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>126</td><td>136</td><td>147</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=NONE'/>
+<h2>MULT18X18D:REGS=NONE</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>P</td>
+<td>2331</td><td>2698</td><td>3066</td>
+<td>2331</td><td>2698</td><td>3066</td>
+</tr>
+<tr >
+<td>B</td><td>P</td>
+<td>2331</td><td>2698</td><td>3066</td>
+<td>2331</td><td>2698</td><td>3066</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>P</td>
+<td>2205</td><td>2562</td><td>2919</td>
+<td>2205</td><td>2562</td><td>2919</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>P</td>
+<td>2205</td><td>2562</td><td>2919</td>
+<td>2205</td><td>2562</td><td>2919</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=OUTPUT'/>
+<h2>MULT18X18D:REGS=OUTPUT</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>483</td><td>530</td><td>578</td>
+<td>483</td><td>530</td><td>578</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>2363</td><td>2499</td><td>2635</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>2363</td><td>2499</td><td>2635</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>147</td><td>178</td><td>210</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>84</td><td>100</td><td>116</td>
+<td>42</td><td>52</td><td>63</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>2236</td><td>2362</td><td>2489</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>2236</td><td>2362</td><td>2489</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=PIPELINE'/>
+<h2>MULT18X18D:REGS=PIPELINE</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>1082</td><td>1097</td><td>1113</td>
+<td>1082</td><td>1097</td><td>1113</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>1838</td><td>1911</td><td>1985</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>1838</td><td>1911</td><td>1985</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>147</td><td>178</td><td>210</td>
+<td>0</td><td>0</td><td>21</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>84</td><td>100</td><td>116</td>
+<td>42</td><td>52</td><td>63</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>1712</td><td>1775</td><td>1838</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>1712</td><td>1775</td><td>1838</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<hr/>
 <a name='PIO:IOTYPE=LVCMOS12'/>
 <h2>PIO:IOTYPE=LVCMOS12</h2>
 <h3>Propagation Delays</h3>
diff --git a/ECP5/timing/cell_timing_8_5G.html b/ECP5/timing/cell_timing_8_5G.html
index 0d78730..d63209e 100644
--- a/ECP5/timing/cell_timing_8_5G.html
+++ b/ECP5/timing/cell_timing_8_5G.html
@@ -13,6 +13,11 @@
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE</a></li>
 <li><a href='#DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH'>DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH</a></li>
+<li><a href='#MULT18X18D:REGS=ALL'>MULT18X18D:REGS=ALL</a></li>
+<li><a href='#MULT18X18D:REGS=INPUT'>MULT18X18D:REGS=INPUT</a></li>
+<li><a href='#MULT18X18D:REGS=NONE'>MULT18X18D:REGS=NONE</a></li>
+<li><a href='#MULT18X18D:REGS=OUTPUT'>MULT18X18D:REGS=OUTPUT</a></li>
+<li><a href='#MULT18X18D:REGS=PIPELINE'>MULT18X18D:REGS=PIPELINE</a></li>
 <li><a href='#PIO:IOTYPE=LVCMOS12'>PIO:IOTYPE=LVCMOS12</a></li>
 <li><a href='#PIO:IOTYPE=LVCMOS15'>PIO:IOTYPE=LVCMOS15</a></li>
 <li><a href='#PIO:IOTYPE=LVCMOS18'>PIO:IOTYPE=LVCMOS18</a></li>
@@ -4348,6 +4353,253 @@
 </tbody>
 </table>
 <hr/>
+<a name='MULT18X18D:REGS=ALL'/>
+<h2>MULT18X18D:REGS=ALL</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>399</td><td>438</td><td>478</td>
+<td>399</td><td>438</td><td>478</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>17</td><td>25</td><td>34</td>
+<td>0</td><td>4</td><td>26</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>17</td><td>25</td><td>34</td>
+<td>0</td><td>4</td><td>26</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>121</td><td>147</td><td>173</td>
+<td>0</td><td>0</td><td>17</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>69</td><td>82</td><td>96</td>
+<td>34</td><td>43</td><td>52</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>104</td><td>112</td><td>121</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>104</td><td>112</td><td>121</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=INPUT'/>
+<h2>MULT18X18D:REGS=INPUT</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>1912</td><td>2216</td><td>2521</td>
+<td>1912</td><td>2216</td><td>2521</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>17</td><td>25</td><td>34</td>
+<td>0</td><td>4</td><td>26</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>17</td><td>25</td><td>34</td>
+<td>0</td><td>4</td><td>26</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>121</td><td>147</td><td>173</td>
+<td>0</td><td>0</td><td>17</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>69</td><td>82</td><td>96</td>
+<td>34</td><td>43</td><td>52</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>104</td><td>112</td><td>121</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>0</td><td>0</td><td>0</td>
+<td>104</td><td>112</td><td>121</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=NONE'/>
+<h2>MULT18X18D:REGS=NONE</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>P</td>
+<td>1930</td><td>2234</td><td>2538</td>
+<td>1930</td><td>2234</td><td>2538</td>
+</tr>
+<tr >
+<td>B</td><td>P</td>
+<td>1930</td><td>2234</td><td>2538</td>
+<td>1930</td><td>2234</td><td>2538</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>P</td>
+<td>1825</td><td>2120</td><td>2416</td>
+<td>1825</td><td>2120</td><td>2416</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>P</td>
+<td>1825</td><td>2120</td><td>2416</td>
+<td>1825</td><td>2120</td><td>2416</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=OUTPUT'/>
+<h2>MULT18X18D:REGS=OUTPUT</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>399</td><td>438</td><td>478</td>
+<td>399</td><td>438</td><td>478</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>1956</td><td>2068</td><td>2181</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>1956</td><td>2068</td><td>2181</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>121</td><td>147</td><td>173</td>
+<td>0</td><td>0</td><td>17</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>69</td><td>82</td><td>96</td>
+<td>34</td><td>43</td><td>52</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>1851</td><td>1955</td><td>2060</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>1851</td><td>1955</td><td>2060</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<hr/>
+<a name='MULT18X18D:REGS=PIPELINE'/>
+<h2>MULT18X18D:REGS=PIPELINE</h2>
+<h3>Propagation Delays</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Port</th>
+<th colspan='3'>Low-High Transition (ps)</th><th colspan='3'>High-Low Transition (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>CLK0</td><td>P</td>
+<td>895</td><td>908</td><td>921</td>
+<td>895</td><td>908</td><td>921</td>
+</tr>
+</tbody>
+</table>
+<h3>Setup/Hold Checks</h3>
+<table width='800'>
+<tbody>
+<tr><th rowspan='2'>From Port</th><th rowspan='2'>To Clock</th>
+<th colspan='3'>Setup (ps)</th><th colspan='3'>Hold (ps)</th></tr>
+<tr><th>Min</th><th>Typ</th><th>Max</th><th>Min</th><th>Typ</th><th>Max</th></tr>
+<tr  bgcolor="#dddddd">
+<td>A</td><td>posedge CLK0</td>
+<td>1521</td><td>1582</td><td>1643</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>B</td><td>posedge CLK0</td>
+<td>1521</td><td>1582</td><td>1643</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>CE0</td><td>posedge CLK0</td>
+<td>121</td><td>147</td><td>173</td>
+<td>0</td><td>0</td><td>17</td>
+</tr>
+<tr >
+<td>RST0</td><td>posedge CLK0</td>
+<td>69</td><td>82</td><td>96</td>
+<td>34</td><td>43</td><td>52</td>
+</tr>
+<tr  bgcolor="#dddddd">
+<td>SIGNEDA</td><td>posedge CLK0</td>
+<td>1417</td><td>1469</td><td>1521</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+<tr >
+<td>SIGNEDB</td><td>posedge CLK0</td>
+<td>1417</td><td>1469</td><td>1521</td>
+<td>0</td><td>0</td><td>0</td>
+</tr>
+</tbody>
+</table>
+<hr/>
 <a name='PIO:IOTYPE=LVCMOS12'/>
 <h2>PIO:IOTYPE=LVCMOS12</h2>
 <h3>Propagation Delays</h3>
diff --git a/index.html b/index.html
index 3b064b8..1131339 100644
--- a/index.html
+++ b/index.html
@@ -16,8 +16,8 @@
 <p>More human-readable documentation on the ECP5 architecture and the Project Trellis methodology can be found
 on the <a href="http://prjtrellis.readthedocs.io/en/latest/">Read the Docs</a> site.</p>
 
-<p>This HTML documentation was generated at 2019-02-28 23:43:30 from prjtrellis-db commit
-<a href="https://github.com/SymbiFlow/prjtrellis-db/tree/d0b219af41ae3da6150645fbc5cc5613b530603f">d0b219af41ae3da6150645fbc5cc5613b530603f</a>.</p>
+<p>This HTML documentation was generated at 2019-06-17 15:33:09 from prjtrellis-db commit
+<a href="https://github.com/SymbiFlow/prjtrellis-db/tree/b4d626b6402c131e9a035470ffe4cf33ccbe7986">b4d626b6402c131e9a035470ffe4cf33ccbe7986</a>.</p>
 <hr/>
 <h3>ECP5 Family</h3><h4>Bitstream Documentation</h4><ul><li><a href="ECP5/LFE5U-25F/index.html">LFE5U-25F Documentation</a></li><li><a href="ECP5/LFE5U-45F/index.html">LFE5U-45F Documentation</a></li><li><a href="ECP5/LFE5U-85F/index.html">LFE5U-85F Documentation</a></li><li><a href="ECP5/LFE5UM-25F/index.html">LFE5UM-25F Documentation</a></li><li><a href="ECP5/LFE5UM-45F/index.html">LFE5UM-45F Documentation</a></li><li><a href="ECP5/LFE5UM-85F/index.html">LFE5UM-85F Documentation</a></li><li><a href="ECP5/LFE5UM5G-25F/index.html">LFE5UM5G-25F Documentation</a></li><li><a href="ECP5/LFE5UM5G-45F/index.html">LFE5UM5G-45F Documentation</a></li><li><a href="ECP5/LFE5UM5G-85F/index.html">LFE5UM5G-85F Documentation</a></li></ul><h4>Cell Timing Documentation</h4><ul><li><a href="ECP5/timing/cell_timing_6.html">Speed Grade -6</a></li><li><a href="ECP5/timing/cell_timing_7.html">Speed Grade -7</a></li><li><a href="ECP5/timing/cell_timing_8.html">Speed Grade -8</a></li><li><a href="ECP5/timing/cell_timing_8_5G.html">Speed Grade -8_5G</a></li></ul><h4>Interconnect Timing Documentation</h4><ul><li><a href="ECP5/timing/interconn_timing_6.html">Speed Grade -6</a></li><li><a href="ECP5/timing/interconn_timing_7.html">Speed Grade -7</a></li><li><a href="ECP5/timing/interconn_timing_8.html">Speed Grade -8</a></li><li><a href="ECP5/timing/interconn_timing_8_5G.html">Speed Grade -8_5G</a></li></ul>
 <hr/>