diff --git a/ECP5/tiledata/BANKREF8/bits.db b/ECP5/tiledata/BANKREF8/bits.db
index d13466e..bcfc3b7 100644
--- a/ECP5/tiledata/BANKREF8/bits.db
+++ b/ECP5/tiledata/BANKREF8/bits.db
@@ -1,4 +1,16 @@
 # Routing Mux Bits
+.mux N1W1_JCLKOP_PLL
+N1W1_CLKI_PLL F73B0 F77B0
+
+.mux N1W1_JCLKOS2_PLL
+N1W1_CLKI_PLL F75B0 F79B0
+
+.mux N1W1_JCLKOS3_PLL
+N1W1_CLKI_PLL F76B0 F80B0
+
+.mux N1W1_JCLKOS_PLL
+N1W1_CLKI_PLL F74B0 F78B0
+
 
 # Non-Routing Configuration
 
diff --git a/ECP5/tiledata/MIB_EBR7/bits.db b/ECP5/tiledata/MIB_EBR7/bits.db
index f9e295c..e7c449b 100644
--- a/ECP5/tiledata/MIB_EBR7/bits.db
+++ b/ECP5/tiledata/MIB_EBR7/bits.db
@@ -12,11 +12,6 @@
 !F34B0
 
 .config EBR3.WID 000011111
-
-
-
-
-
 F105B0
 F104B0
 F92B0
diff --git a/ECP5/tiledata/MIB_EBR8/bits.db b/ECP5/tiledata/MIB_EBR8/bits.db
index 6fbca03..5b78b09 100644
--- a/ECP5/tiledata/MIB_EBR8/bits.db
+++ b/ECP5/tiledata/MIB_EBR8/bits.db
@@ -8,10 +8,6 @@
 F2B0
 F1B0
 
-
-
-
-
 .config_enum EBR3.GSR ENABLED
 DISABLED F41B0
 ENABLED !F41B0
diff --git a/ECP5/tiledata/PICL1/bits.db b/ECP5/tiledata/PICL1/bits.db
index bed34cf..709fb7b 100644
--- a/ECP5/tiledata/PICL1/bits.db
+++ b/ECP5/tiledata/PICL1/bits.db
@@ -99,7 +99,7 @@
 
 .config_enum PIOA.OPENDRAIN
 OFF F4B1 F5B1 !F5B2 F6B1
-ON !F4B1 !F5B1 F5B2 !F6B1
+ON !F4B1 F5B2 !F5B1 !F6B1
 
 .config_enum PIOA.PULLMODE DOWN
 DOWN !F7B0 !F8B0
@@ -164,7 +164,7 @@
 
 .config_enum PIOB.OPENDRAIN
 OFF F0B4 F8B3 F9B3 !F9B4
-ON !F0B4 !F8B3 !F9B3 F9B4
+ON !F0B4 !F8B3 F9B4 !F9B3
 
 .config_enum PIOB.PULLMODE DOWN
 DOWN !F1B3 !F2B3
@@ -269,7 +269,7 @@
 
 .config_enum PIOC.OPENDRAIN
 OFF F2B6 F3B6 !F3B7 F4B6
-ON !F2B6 F3B7 !F3B6 !F4B6
+ON !F2B6 !F3B6 F3B7 !F4B6
 
 .config_enum PIOC.PULLMODE DOWN
 DOWN !F5B5 !F6B5
@@ -334,7 +334,7 @@
 
 .config_enum PIOD.OPENDRAIN
 OFF F6B8 F7B8 !F7B9 F8B8
-ON !F6B8 F7B9 !F7B8 !F8B8
+ON !F6B8 !F7B8 F7B9 !F8B8
 
 .config_enum PIOD.PULLMODE DOWN
 DOWN !F0B8 !F9B7
diff --git a/ECP5/tiledata/PICL1_DQS0/bits.db b/ECP5/tiledata/PICL1_DQS0/bits.db
index 709fb7b..bed34cf 100644
--- a/ECP5/tiledata/PICL1_DQS0/bits.db
+++ b/ECP5/tiledata/PICL1_DQS0/bits.db
@@ -99,7 +99,7 @@
 
 .config_enum PIOA.OPENDRAIN
 OFF F4B1 F5B1 !F5B2 F6B1
-ON !F4B1 F5B2 !F5B1 !F6B1
+ON !F4B1 !F5B1 F5B2 !F6B1
 
 .config_enum PIOA.PULLMODE DOWN
 DOWN !F7B0 !F8B0
@@ -164,7 +164,7 @@
 
 .config_enum PIOB.OPENDRAIN
 OFF F0B4 F8B3 F9B3 !F9B4
-ON !F0B4 !F8B3 F9B4 !F9B3
+ON !F0B4 !F8B3 !F9B3 F9B4
 
 .config_enum PIOB.PULLMODE DOWN
 DOWN !F1B3 !F2B3
@@ -269,7 +269,7 @@
 
 .config_enum PIOC.OPENDRAIN
 OFF F2B6 F3B6 !F3B7 F4B6
-ON !F2B6 !F3B6 F3B7 !F4B6
+ON !F2B6 F3B7 !F3B6 !F4B6
 
 .config_enum PIOC.PULLMODE DOWN
 DOWN !F5B5 !F6B5
@@ -334,7 +334,7 @@
 
 .config_enum PIOD.OPENDRAIN
 OFF F6B8 F7B8 !F7B9 F8B8
-ON !F6B8 !F7B8 F7B9 !F8B8
+ON !F6B8 F7B9 !F7B8 !F8B8
 
 .config_enum PIOD.PULLMODE DOWN
 DOWN !F0B8 !F9B7
diff --git a/ECP5/tiledata/PICL1_DQS3/bits.db b/ECP5/tiledata/PICL1_DQS3/bits.db
index e6cb9fa..f134d0c 100644
--- a/ECP5/tiledata/PICL1_DQS3/bits.db
+++ b/ECP5/tiledata/PICL1_DQS3/bits.db
@@ -99,7 +99,7 @@
 
 .config_enum PIOA.OPENDRAIN
 OFF F4B1 F5B1 !F5B2 F6B1
-ON !F4B1 F5B2 !F5B1 !F6B1
+ON !F4B1 !F5B1 F5B2 !F6B1
 
 .config_enum PIOA.PULLMODE DOWN
 DOWN !F7B0 !F8B0
@@ -164,7 +164,7 @@
 
 .config_enum PIOB.OPENDRAIN
 OFF F0B4 F8B3 F9B3 !F9B4
-ON !F0B4 !F8B3 !F9B3 F9B4
+ON !F0B4 !F8B3 F9B4 !F9B3
 
 .config_enum PIOB.PULLMODE DOWN
 DOWN !F1B3 !F2B3
@@ -269,7 +269,7 @@
 
 .config_enum PIOC.OPENDRAIN
 OFF F2B6 F3B6 !F3B7 F4B6
-ON !F2B6 F3B7 !F3B6 !F4B6
+ON !F2B6 !F3B6 F3B7 !F4B6
 
 .config_enum PIOC.PULLMODE DOWN
 DOWN !F5B5 !F6B5
@@ -334,7 +334,7 @@
 
 .config_enum PIOD.OPENDRAIN
 OFF F6B8 F7B8 !F7B9 F8B8
-ON !F6B8 F7B9 !F7B8 !F8B8
+ON !F6B8 !F7B8 F7B9 !F8B8
 
 .config_enum PIOD.PULLMODE DOWN
 DOWN !F0B8 !F9B7
diff --git a/ECP5/tiledata/PICR1/bits.db b/ECP5/tiledata/PICR1/bits.db
index 97bf59f..ca91418 100644
--- a/ECP5/tiledata/PICR1/bits.db
+++ b/ECP5/tiledata/PICR1/bits.db
@@ -99,7 +99,7 @@
 
 .config_enum PIOA.OPENDRAIN
 OFF F3B1 F4B1 !F4B2 F5B1
-ON !F3B1 F4B2 !F4B1 !F5B1
+ON !F3B1 !F4B1 F4B2 !F5B1
 
 .config_enum PIOA.PULLMODE DOWN
 DOWN !F1B0 !F2B0
@@ -164,7 +164,7 @@
 
 .config_enum PIOB.OPENDRAIN
 OFF F0B3 !F0B4 F1B3 F9B4
-ON F0B4 !F0B3 !F1B3 !F9B4
+ON !F0B3 F0B4 !F1B3 !F9B4
 
 .config_enum PIOB.PULLMODE DOWN
 DOWN !F7B3 !F8B3
@@ -269,7 +269,7 @@
 
 .config_enum PIOC.OPENDRAIN
 OFF F5B6 F6B6 !F6B7 F7B6
-ON !F5B6 F6B7 !F6B6 !F7B6
+ON !F5B6 !F6B6 F6B7 !F7B6
 
 .config_enum PIOC.PULLMODE DOWN
 DOWN !F3B5 !F4B5
@@ -334,7 +334,7 @@
 
 .config_enum PIOD.OPENDRAIN
 OFF F1B8 F2B8 !F2B9 F3B8
-ON !F1B8 !F2B8 F2B9 !F3B8
+ON !F1B8 F2B9 !F2B8 !F3B8
 
 .config_enum PIOD.PULLMODE DOWN
 DOWN !F0B7 !F9B8
diff --git a/ECP5/tiledata/PICR1_DQS0/bits.db b/ECP5/tiledata/PICR1_DQS0/bits.db
index ca91418..97bf59f 100644
--- a/ECP5/tiledata/PICR1_DQS0/bits.db
+++ b/ECP5/tiledata/PICR1_DQS0/bits.db
@@ -99,7 +99,7 @@
 
 .config_enum PIOA.OPENDRAIN
 OFF F3B1 F4B1 !F4B2 F5B1
-ON !F3B1 !F4B1 F4B2 !F5B1
+ON !F3B1 F4B2 !F4B1 !F5B1
 
 .config_enum PIOA.PULLMODE DOWN
 DOWN !F1B0 !F2B0
@@ -164,7 +164,7 @@
 
 .config_enum PIOB.OPENDRAIN
 OFF F0B3 !F0B4 F1B3 F9B4
-ON !F0B3 F0B4 !F1B3 !F9B4
+ON F0B4 !F0B3 !F1B3 !F9B4
 
 .config_enum PIOB.PULLMODE DOWN
 DOWN !F7B3 !F8B3
@@ -269,7 +269,7 @@
 
 .config_enum PIOC.OPENDRAIN
 OFF F5B6 F6B6 !F6B7 F7B6
-ON !F5B6 !F6B6 F6B7 !F7B6
+ON !F5B6 F6B7 !F6B6 !F7B6
 
 .config_enum PIOC.PULLMODE DOWN
 DOWN !F3B5 !F4B5
@@ -334,7 +334,7 @@
 
 .config_enum PIOD.OPENDRAIN
 OFF F1B8 F2B8 !F2B9 F3B8
-ON !F1B8 F2B9 !F2B8 !F3B8
+ON !F1B8 !F2B8 F2B9 !F3B8
 
 .config_enum PIOD.PULLMODE DOWN
 DOWN !F0B7 !F9B8
diff --git a/ECP5/tiledata/PICR1_DQS3/bits.db b/ECP5/tiledata/PICR1_DQS3/bits.db
index ca91418..97bf59f 100644
--- a/ECP5/tiledata/PICR1_DQS3/bits.db
+++ b/ECP5/tiledata/PICR1_DQS3/bits.db
@@ -99,7 +99,7 @@
 
 .config_enum PIOA.OPENDRAIN
 OFF F3B1 F4B1 !F4B2 F5B1
-ON !F3B1 !F4B1 F4B2 !F5B1
+ON !F3B1 F4B2 !F4B1 !F5B1
 
 .config_enum PIOA.PULLMODE DOWN
 DOWN !F1B0 !F2B0
@@ -164,7 +164,7 @@
 
 .config_enum PIOB.OPENDRAIN
 OFF F0B3 !F0B4 F1B3 F9B4
-ON !F0B3 F0B4 !F1B3 !F9B4
+ON F0B4 !F0B3 !F1B3 !F9B4
 
 .config_enum PIOB.PULLMODE DOWN
 DOWN !F7B3 !F8B3
@@ -269,7 +269,7 @@
 
 .config_enum PIOC.OPENDRAIN
 OFF F5B6 F6B6 !F6B7 F7B6
-ON !F5B6 !F6B6 F6B7 !F7B6
+ON !F5B6 F6B7 !F6B6 !F7B6
 
 .config_enum PIOC.PULLMODE DOWN
 DOWN !F3B5 !F4B5
@@ -334,7 +334,7 @@
 
 .config_enum PIOD.OPENDRAIN
 OFF F1B8 F2B8 !F2B9 F3B8
-ON !F1B8 F2B9 !F2B8 !F3B8
+ON !F1B8 !F2B8 F2B9 !F3B8
 
 .config_enum PIOD.PULLMODE DOWN
 DOWN !F0B7 !F9B8
diff --git a/ECP5/tiledata/PLL0_LL/bits.db b/ECP5/tiledata/PLL0_LL/bits.db
index d13466e..ede7340 100644
--- a/ECP5/tiledata/PLL0_LL/bits.db
+++ b/ECP5/tiledata/PLL0_LL/bits.db
@@ -1,5 +1,117 @@
 # Routing Mux Bits
+.mux N1_CLKFB
+N1_CLKINTFB 
+N1_JCLKFB1 F11B0
+N1_JCLKFB2 F12B0
+N1_JCLKFB3 F11B0 F12B0
+
+.mux N1_JCLKOP_PLL
+N1_CLKI_PLL F0B0
+
+.mux N1_JCLKOS2_PLL
+N1_CLKI_PLL F0B0
+
+.mux N1_JCLKOS3_PLL
+N1_CLKI_PLL F0B0
+
+.mux N1_JCLKOS_PLL
+N1_CLKI_PLL F0B0
+
+.mux N1_REFCLK0
+N1_JREFCLK0_0 
+N1_JREFCLK0_1 F5B0
+N1_JREFCLK0_2 F6B0
+N1_JREFCLK0_3 F5B0 F6B0
+
+.mux N1_REFCLK1
+N1_JREFCLK1_0 
+N1_JREFCLK1_1 F8B0
+N1_JREFCLK1_2 F9B0
+N1_JREFCLK1_3 F8B0 F9B0
+
 
 # Non-Routing Configuration
 
 # Fixed Connections
+.fixed_conn G_JLLCPLL0CLKOP N1_JCLKOP_PLL
+
+.fixed_conn G_JLLCPLL0CLKOS N1_JCLKOS_PLL
+
+.fixed_conn G_JLLCPLL0CLKOS2 N1_JCLKOS2_PLL
+
+.fixed_conn G_JLLCPLL0CLKOS3 N1_JCLKOS3_PLL
+
+.fixed_conn N1_CLK0_PLLREFCS N1_REFCLK0
+
+.fixed_conn N1_CLK1_PLLREFCS N1_REFCLK1
+
+.fixed_conn N1_CLKFB_PLL N1_CLKFB
+
+.fixed_conn N1_CLKINTFB N1_CLKINTFB_PLL
+
+.fixed_conn N1_CLKI_PLL N1_PLLCSOUT_PLLREFCS
+
+.fixed_conn N1_JCLKFB1 45K_N36W2_JECLK0
+
+.fixed_conn N1_JCLKFB2 45K_N36W2_JECLK1
+
+.fixed_conn N1_JCLKFB3 N1E1_JCLK0
+
+.fixed_conn N1_JENCLKOP_PLL N1_JD2
+
+.fixed_conn N1_JENCLKOS2_PLL N1_JB3
+
+.fixed_conn N1_JENCLKOS3_PLL N1_JC3
+
+.fixed_conn N1_JENCLKOS_PLL N1_JA3
+
+.fixed_conn N1_JF0 N1_JCLKOP_PLL
+
+.fixed_conn N1_JF2 N1_JCLKOS_PLL
+
+.fixed_conn N1_JF4 N1_JCLKOS2_PLL
+
+.fixed_conn N1_JF6 N1_JCLKOS3_PLL
+
+.fixed_conn N1_JPHASEDIR_PLL N1_JD4
+
+.fixed_conn N1_JPHASELOADREG_PLL N1_JD3
+
+.fixed_conn N1_JPHASESEL0_PLL N1_JB4
+
+.fixed_conn N1_JPHASESEL1_PLL N1_JA4
+
+.fixed_conn N1_JPHASESTEP_PLL N1_JC4
+
+.fixed_conn N1_JPLLWAKESYNC_PLL N1_JC2
+
+.fixed_conn N1_JQ0 N1_JREFCLK_PLL
+
+.fixed_conn N1_JQ2 N1_JLOCK_PLL
+
+.fixed_conn N1_JQ4 N1_JINTLOCK_PLL
+
+.fixed_conn N1_JREFCLK0_0 N1_JCLK0
+
+.fixed_conn N1_JREFCLK0_1 45K_N36W2_JPADDIC_PIO
+
+.fixed_conn N1_JREFCLK0_2 45K_N36W2_JPADDIA_PIO
+
+.fixed_conn N1_JREFCLK0_3 45K_N3W2_JPADDIC_PIO
+
+.fixed_conn N1_JREFCLK1_0 N1_JCLK1
+
+.fixed_conn N1_JREFCLK1_1 45K_N36W2_JPADDIC_PIO
+
+.fixed_conn N1_JREFCLK1_2 45K_N36W2_JPADDIA_PIO
+
+.fixed_conn N1_JREFCLK1_3 45K_N3W2_JPADDIC_PIO
+
+.fixed_conn N1_JREFCLK_PLL N1_CLKI_PLL
+
+.fixed_conn N1_JRST_PLL N1_JB1
+
+.fixed_conn N1_JSEL_PLLREFCS N1_JB2
+
+.fixed_conn N1_JSTDBY_PLL N1_JLSR0
+
diff --git a/ECP5/tiledata/PLL0_LR/bits.db b/ECP5/tiledata/PLL0_LR/bits.db
index d13466e..e2b484f 100644
--- a/ECP5/tiledata/PLL0_LR/bits.db
+++ b/ECP5/tiledata/PLL0_LR/bits.db
@@ -1,5 +1,117 @@
 # Routing Mux Bits
+.mux N1_CLKFB
+N1_CLKINTFB 
+N1_JCLKFB1 F11B0
+N1_JCLKFB2 F12B0
+N1_JCLKFB3 F11B0 F12B0
+
+.mux N1_JCLKOP_PLL
+N1_CLKI_PLL F0B0
+
+.mux N1_JCLKOS2_PLL
+N1_CLKI_PLL F0B0
+
+.mux N1_JCLKOS3_PLL
+N1_CLKI_PLL F0B0
+
+.mux N1_JCLKOS_PLL
+N1_CLKI_PLL F0B0
+
+.mux N1_REFCLK0
+N1_JREFCLK0_0 
+N1_JREFCLK0_1 F5B0
+N1_JREFCLK0_2 F6B0
+N1_JREFCLK0_3 F5B0 F6B0
+
+.mux N1_REFCLK1
+N1_JREFCLK1_0 
+N1_JREFCLK1_1 F8B0
+N1_JREFCLK1_2 F9B0
+N1_JREFCLK1_3 F8B0 F9B0
+
 
 # Non-Routing Configuration
 
 # Fixed Connections
+.fixed_conn G_JLRCPLL0CLKOP N1_JCLKOP_PLL
+
+.fixed_conn G_JLRCPLL0CLKOS N1_JCLKOS_PLL
+
+.fixed_conn G_JLRCPLL0CLKOS2 N1_JCLKOS2_PLL
+
+.fixed_conn G_JLRCPLL0CLKOS3 N1_JCLKOS3_PLL
+
+.fixed_conn N1_CLK0_PLLREFCS N1_REFCLK0
+
+.fixed_conn N1_CLK1_PLLREFCS N1_REFCLK1
+
+.fixed_conn N1_CLKFB_PLL N1_CLKFB
+
+.fixed_conn N1_CLKINTFB N1_CLKINTFB_PLL
+
+.fixed_conn N1_CLKI_PLL N1_PLLCSOUT_PLLREFCS
+
+.fixed_conn N1_JCLKFB1 45K_N36E2_JECLK0
+
+.fixed_conn N1_JCLKFB2 45K_N36E2_JECLK1
+
+.fixed_conn N1_JCLKFB3 N1W1_JCLK0
+
+.fixed_conn N1_JENCLKOP_PLL N1_JD2
+
+.fixed_conn N1_JENCLKOS2_PLL N1_JB3
+
+.fixed_conn N1_JENCLKOS3_PLL N1_JC3
+
+.fixed_conn N1_JENCLKOS_PLL N1_JA3
+
+.fixed_conn N1_JF0 N1_JCLKOP_PLL
+
+.fixed_conn N1_JF2 N1_JCLKOS_PLL
+
+.fixed_conn N1_JF4 N1_JCLKOS2_PLL
+
+.fixed_conn N1_JF6 N1_JCLKOS3_PLL
+
+.fixed_conn N1_JPHASEDIR_PLL N1_JD4
+
+.fixed_conn N1_JPHASELOADREG_PLL N1_JD3
+
+.fixed_conn N1_JPHASESEL0_PLL N1_JB4
+
+.fixed_conn N1_JPHASESEL1_PLL N1_JA4
+
+.fixed_conn N1_JPHASESTEP_PLL N1_JC4
+
+.fixed_conn N1_JPLLWAKESYNC_PLL N1_JC2
+
+.fixed_conn N1_JQ0 N1_JREFCLK_PLL
+
+.fixed_conn N1_JQ2 N1_JLOCK_PLL
+
+.fixed_conn N1_JQ4 N1_JINTLOCK_PLL
+
+.fixed_conn N1_JREFCLK0_0 N1_JCLK0
+
+.fixed_conn N1_JREFCLK0_1 45K_N36E2_JPADDIC_PIO
+
+.fixed_conn N1_JREFCLK0_2 45K_N36E2_JPADDIA_PIO
+
+.fixed_conn N1_JREFCLK0_3 45K_N3E2_JPADDIC_PIO
+
+.fixed_conn N1_JREFCLK1_0 N1_JCLK1
+
+.fixed_conn N1_JREFCLK1_1 45K_N36E2_JPADDIC_PIO
+
+.fixed_conn N1_JREFCLK1_2 45K_N36E2_JPADDIA_PIO
+
+.fixed_conn N1_JREFCLK1_3 45K_N3E2_JPADDIC_PIO
+
+.fixed_conn N1_JREFCLK_PLL N1_CLKI_PLL
+
+.fixed_conn N1_JRST_PLL N1_JB1
+
+.fixed_conn N1_JSEL_PLLREFCS N1_JB2
+
+.fixed_conn N1_JSTDBY_PLL N1_JLSR0
+
diff --git a/ECP5/tiledata/PLL0_UL/bits.db b/ECP5/tiledata/PLL0_UL/bits.db
index d13466e..6acd12b 100644
--- a/ECP5/tiledata/PLL0_UL/bits.db
+++ b/ECP5/tiledata/PLL0_UL/bits.db
@@ -1,5 +1,123 @@
 # Routing Mux Bits
+.mux E1_CLKFB
+E1_CLKINTFB 
+E1_JCLKFB1 F1B1
+E1_JCLKFB2 F2B1
+E1_JCLKFB3 F1B1 F2B1
+
+.mux E1_REFCLK0
+E1_JREFCLK0_0 
+E1_JREFCLK0_1 F5B0
+E1_JREFCLK0_2 F6B0
+E1_JREFCLK0_3 F5B0 F6B0
+E1_JREFCLK0_4 F7B0
+E1_JREFCLK0_5 F5B0 F7B0
+E1_JREFCLK0_6 F6B0 F7B0
+
+.mux E1_REFCLK1
+E1_JREFCLK1_0 
+E1_JREFCLK1_1 F8B0
+E1_JREFCLK1_2 F9B0
+E1_JREFCLK1_3 F8B0 F9B0
+E1_JREFCLK1_4 F0B1
+E1_JREFCLK1_5 F0B1 F8B0
+E1_JREFCLK1_6 F0B1 F9B0
+
 
 # Non-Routing Configuration
 
 # Fixed Connections
+.fixed_conn E1_CLK0_PLLREFCS E1_REFCLK0
+
+.fixed_conn E1_CLK1_PLLREFCS E1_REFCLK1
+
+.fixed_conn E1_CLKFB_PLL E1_CLKFB
+
+.fixed_conn E1_CLKINTFB E1_CLKINTFB_PLL
+
+.fixed_conn E1_CLKI_PLL E1_PLLCSOUT_PLLREFCS
+
+.fixed_conn E1_JCLKFB1 45K_S30_JECLK0
+
+.fixed_conn E1_JCLKFB2 45K_S30_JECLK1
+
+.fixed_conn E1_JCLKFB3 S1E1_JCLK0
+
+.fixed_conn E1_JENCLKOP_PLL E1_JD2
+
+.fixed_conn E1_JENCLKOS2_PLL E1_JB3
+
+.fixed_conn E1_JENCLKOS3_PLL E1_JC3
+
+.fixed_conn E1_JENCLKOS_PLL E1_JA3
+
+.fixed_conn E1_JF0 E1_JCLKOP_PLL
+
+.fixed_conn E1_JF2 E1_JCLKOS_PLL
+
+.fixed_conn E1_JF4 E1_JCLKOS2_PLL
+
+.fixed_conn E1_JF6 E1_JCLKOS3_PLL
+
+.fixed_conn E1_JPHASEDIR_PLL E1_JD4
+
+.fixed_conn E1_JPHASELOADREG_PLL E1_JD3
+
+.fixed_conn E1_JPHASESEL0_PLL E1_JB4
+
+.fixed_conn E1_JPHASESEL1_PLL E1_JA4
+
+.fixed_conn E1_JPHASESTEP_PLL E1_JC4
+
+.fixed_conn E1_JPLLWAKESYNC_PLL E1_JC2
+
+.fixed_conn E1_JQ0 E1_JREFCLK_PLL
+
+.fixed_conn E1_JQ2 E1_JLOCK_PLL
+
+.fixed_conn E1_JQ4 E1_JINTLOCK_PLL
+
+.fixed_conn E1_JREFCLK0_0 E1_JCLK0
+
+.fixed_conn E1_JREFCLK0_1 45K_S28_JPADDIC_PIO
+
+.fixed_conn E1_JREFCLK0_2 45K_S28_JPADDIA_PIO
+
+.fixed_conn E1_JREFCLK0_3 45K_S7_JPADDIA_PIO
+
+.fixed_conn E1_JREFCLK0_4 45K_N4E4_JPADDIA_PIO
+
+.fixed_conn E1_JREFCLK0_5 45K_N4E36_JPADDIA_PIO
+
+.fixed_conn E1_JREFCLK0_6 45K_N4E38_JPADDIA_PIO
+
+.fixed_conn E1_JREFCLK1_0 E1_JCLK1
+
+.fixed_conn E1_JREFCLK1_1 45K_S28_JPADDIC_PIO
+
+.fixed_conn E1_JREFCLK1_2 45K_S28_JPADDIA_PIO
+
+.fixed_conn E1_JREFCLK1_3 45K_S7_JPADDIA_PIO
+
+.fixed_conn E1_JREFCLK1_4 45K_N4E4_JPADDIA_PIO
+
+.fixed_conn E1_JREFCLK1_5 45K_N4E36_JPADDIA_PIO
+
+.fixed_conn E1_JREFCLK1_6 45K_N4E38_JPADDIA_PIO
+
+.fixed_conn E1_JREFCLK_PLL E1_CLKI_PLL
+
+.fixed_conn E1_JRST_PLL E1_JB1
+
+.fixed_conn E1_JSEL_PLLREFCS E1_JB2
+
+.fixed_conn E1_JSTDBY_PLL E1_JLSR0
+
+.fixed_conn G_JULCPLL0CLKOP E1_JCLKOP_PLL
+
+.fixed_conn G_JULCPLL0CLKOS E1_JCLKOS_PLL
+
+.fixed_conn G_JULCPLL0CLKOS2 E1_JCLKOS2_PLL
+
+.fixed_conn G_JULCPLL0CLKOS3 E1_JCLKOS3_PLL
+
diff --git a/ECP5/tiledata/PLL0_UR/bits.db b/ECP5/tiledata/PLL0_UR/bits.db
index d13466e..dbf1fde 100644
--- a/ECP5/tiledata/PLL0_UR/bits.db
+++ b/ECP5/tiledata/PLL0_UR/bits.db
@@ -1,5 +1,135 @@
 # Routing Mux Bits
+.mux W1_CLKFB
+W1_CLKINTFB 
+W1_JCLKFB1 F8B1
+W1_JCLKFB2 F7B1
+W1_JCLKFB3 F7B1 F8B1
+
+.mux W1_JCLKOP_PLL
+W1_CLKI_PLL F9B0
+
+.mux W1_JCLKOS2_PLL
+W1_CLKI_PLL F9B0
+
+.mux W1_JCLKOS3_PLL
+W1_CLKI_PLL F9B0
+
+.mux W1_JCLKOS_PLL
+W1_CLKI_PLL F9B0
+
+.mux W1_REFCLK0
+W1_JREFCLK0_0 
+W1_JREFCLK0_1 F4B0
+W1_JREFCLK0_2 F3B0
+W1_JREFCLK0_3 F3B0 F4B0
+W1_JREFCLK0_4 F2B0
+W1_JREFCLK0_5 F2B0 F4B0
+W1_JREFCLK0_6 F2B0 F3B0
+
+.mux W1_REFCLK1
+W1_JREFCLK1_0 
+W1_JREFCLK1_1 F1B0
+W1_JREFCLK1_2 F0B0
+W1_JREFCLK1_3 F0B0 F1B0
+W1_JREFCLK1_4 F9B1
+W1_JREFCLK1_5 F1B0 F9B1
+W1_JREFCLK1_6 F0B0 F9B1
+
 
 # Non-Routing Configuration
 
 # Fixed Connections
+.fixed_conn G_JURCPLL0CLKOP W1_JCLKOP_PLL
+
+.fixed_conn G_JURCPLL0CLKOS W1_JCLKOS_PLL
+
+.fixed_conn G_JURCPLL0CLKOS2 W1_JCLKOS2_PLL
+
+.fixed_conn G_JURCPLL0CLKOS3 W1_JCLKOS3_PLL
+
+.fixed_conn W1_CLK0_PLLREFCS W1_REFCLK0
+
+.fixed_conn W1_CLK1_PLLREFCS W1_REFCLK1
+
+.fixed_conn W1_CLKFB_PLL W1_CLKFB
+
+.fixed_conn W1_CLKINTFB W1_CLKINTFB_PLL
+
+.fixed_conn W1_CLKI_PLL W1_PLLCSOUT_PLLREFCS
+
+.fixed_conn W1_JCLKFB1 45K_S30_JECLK0
+
+.fixed_conn W1_JCLKFB2 45K_S30_JECLK1
+
+.fixed_conn W1_JCLKFB3 S1W1_JCLK0
+
+.fixed_conn W1_JENCLKOP_PLL W1_JD2
+
+.fixed_conn W1_JENCLKOS2_PLL W1_JB3
+
+.fixed_conn W1_JENCLKOS3_PLL W1_JC3
+
+.fixed_conn W1_JENCLKOS_PLL W1_JA3
+
+.fixed_conn W1_JF0 W1_JCLKOP_PLL
+
+.fixed_conn W1_JF2 W1_JCLKOS_PLL
+
+.fixed_conn W1_JF4 W1_JCLKOS2_PLL
+
+.fixed_conn W1_JF6 W1_JCLKOS3_PLL
+
+.fixed_conn W1_JPHASEDIR_PLL W1_JD4
+
+.fixed_conn W1_JPHASELOADREG_PLL W1_JD3
+
+.fixed_conn W1_JPHASESEL0_PLL W1_JB4
+
+.fixed_conn W1_JPHASESEL1_PLL W1_JA4
+
+.fixed_conn W1_JPHASESTEP_PLL W1_JC4
+
+.fixed_conn W1_JPLLWAKESYNC_PLL W1_JC2
+
+.fixed_conn W1_JQ0 W1_JREFCLK_PLL
+
+.fixed_conn W1_JQ2 W1_JLOCK_PLL
+
+.fixed_conn W1_JQ4 W1_JINTLOCK_PLL
+
+.fixed_conn W1_JREFCLK0_0 W1_JCLK0
+
+.fixed_conn W1_JREFCLK0_1 45K_S28_JPADDIC_PIO
+
+.fixed_conn W1_JREFCLK0_2 45K_S28_JPADDIA_PIO
+
+.fixed_conn W1_JREFCLK0_3 45K_S7_JPADDIA_PIO
+
+.fixed_conn W1_JREFCLK0_4 45K_N4W5_JPADDIA_PIO
+
+.fixed_conn W1_JREFCLK0_5 45K_N4W48_JPADDIA_PIO
+
+.fixed_conn W1_JREFCLK0_6 45K_N4W46_JPADDIA_PIO
+
+.fixed_conn W1_JREFCLK1_0 W1_JCLK1
+
+.fixed_conn W1_JREFCLK1_1 45K_S28_JPADDIC_PIO
+
+.fixed_conn W1_JREFCLK1_2 45K_S28_JPADDIA_PIO
+
+.fixed_conn W1_JREFCLK1_3 45K_S7_JPADDIA_PIO
+
+.fixed_conn W1_JREFCLK1_4 45K_N4W5_JPADDIA_PIO
+
+.fixed_conn W1_JREFCLK1_5 45K_N4W48_JPADDIA_PIO
+
+.fixed_conn W1_JREFCLK1_6 45K_N4W46_JPADDIA_PIO
+
+.fixed_conn W1_JREFCLK_PLL W1_CLKI_PLL
+
+.fixed_conn W1_JRST_PLL W1_JB1
+
+.fixed_conn W1_JSEL_PLLREFCS W1_JB2
+
+.fixed_conn W1_JSTDBY_PLL W1_JLSR0
+
diff --git a/ECP5/tiledata/PLL1_LR/bits.db b/ECP5/tiledata/PLL1_LR/bits.db
index d13466e..129d6ff 100644
--- a/ECP5/tiledata/PLL1_LR/bits.db
+++ b/ECP5/tiledata/PLL1_LR/bits.db
@@ -1,4 +1,16 @@
 # Routing Mux Bits
+.mux N1E1_JCLKOP_PLL
+N1E1_CLKI_PLL F73B0 F77B0
+
+.mux N1E1_JCLKOS2_PLL
+N1E1_CLKI_PLL F75B0 F79B0
+
+.mux N1E1_JCLKOS3_PLL
+N1E1_CLKI_PLL F76B0 F80B0
+
+.mux N1E1_JCLKOS_PLL
+N1E1_CLKI_PLL F74B0 F78B0
+
 
 # Non-Routing Configuration
 
diff --git a/ECP5/tiledata/PLL1_UL/bits.db b/ECP5/tiledata/PLL1_UL/bits.db
index d13466e..8bd325b 100644
--- a/ECP5/tiledata/PLL1_UL/bits.db
+++ b/ECP5/tiledata/PLL1_UL/bits.db
@@ -1,4 +1,16 @@
 # Routing Mux Bits
+.mux N1E1_JCLKOP_PLL
+N1E1_CLKI_PLL F3B7 F7B7
+
+.mux N1E1_JCLKOS2_PLL
+N1E1_CLKI_PLL F5B7 F9B7
+
+.mux N1E1_JCLKOS3_PLL
+N1E1_CLKI_PLL F0B8 F6B7
+
+.mux N1E1_JCLKOS_PLL
+N1E1_CLKI_PLL F4B7 F8B7
+
 
 # Non-Routing Configuration
 
diff --git a/ECP5/tiledata/PLL1_UR/bits.db b/ECP5/tiledata/PLL1_UR/bits.db
index d13466e..1f9a51c 100644
--- a/ECP5/tiledata/PLL1_UR/bits.db
+++ b/ECP5/tiledata/PLL1_UR/bits.db
@@ -1,4 +1,16 @@
 # Routing Mux Bits
+.mux N1W1_JCLKOP_PLL
+N1W1_CLKI_PLL F2B7 F6B7
+
+.mux N1W1_JCLKOS2_PLL
+N1W1_CLKI_PLL F0B7 F4B7
+
+.mux N1W1_JCLKOS3_PLL
+N1W1_CLKI_PLL F3B7 F9B8
+
+.mux N1W1_JCLKOS_PLL
+N1W1_CLKI_PLL F1B7 F5B7
+
 
 # Non-Routing Configuration