# Routing Mux Bits
.mux N2_ECLKC
BNK_ECLK1 F4B1

.mux N2_ECLKD
BNK_ECLK1 F6B6

.mux N2_JDIC
N2_INDDC_IOLOGIC F8B1

.mux N2_JDID
N2_INDDD_IOLOGIC F0B7


# Non-Routing Configuration
.config IOLOGICC.DELAY.DEL_VALUE 0000000
F0B1
F9B0
F8B0
F7B0
F6B0
F5B0
F4B0

.config IOLOGICD.DELAY.DEL_VALUE 0000000
F2B6
F1B6
F0B6
F9B5
F8B5
F7B5
F6B5

.config_enum IOLOGICC.CEIMUX CEMUX
1 F0B5
CEMUX -

.config_enum IOLOGICC.CEMUX INV
CE F3B0
INV -

.config_enum IOLOGICC.CEOMUX CEMUX
1 F8B2
CEMUX -

.config_enum IOLOGICC.CLKIMUX 0
0 -
CLK F6B1
INV F6B1 F7B1

.config_enum IOLOGICC.CLKOMUX 0
0 -
CLK F9B2
INV F0B3 F9B2

.config_enum IOLOGICC.DELAY.OUTDEL DISABLED
DISABLED -
ENABLED F1B3

.config_enum IOLOGICC.DELAY.WAIT_FOR_EDGE DISABLED
DISABLED -
ENABLED F6B2

.config_enum IOLOGICC.FF.INREGMODE FF
FF -
LATCH F3B2

.config_enum IOLOGICC.FF.REGSET RESET
RESET -
SET F5B1

.config_enum IOLOGICC.GSR ENABLED
DISABLED F2B1
ENABLED -

.config_enum IOLOGICC.IDDRXN.MODE NONE
IDDR71 F1B2 F2B2 F3B7 F4B7
IDDRX2 F1B2
NONE -

.config_enum IOLOGICC.IOLTOMUX TS
NONE -
TDDR F5B4
TS -

.config_enum IOLOGICC.LSRIMUX 0
0 -
LSRMUX F9B1

.config_enum IOLOGICC.LSRMUX INV
INV -
LSR F4B2

.config_enum IOLOGICC.LSROMUX 0
0 -
LSRMUX F2B3

.config_enum IOLOGICC.MIDDRX.MODE NONE
MIDDRX2 F1B2 F6B10
NONE -

.config_enum IOLOGICC.MIDDRX_MODDRX.WRCLKMUX NONE
DQSW F7B4
DQSW270 F7B4 F8B4
NONE -

.config_enum IOLOGICC.MODDRX.MODE NONE
MODDRX2 F8B3
MOSHX2 F8B4 F9B3
NONE -

.config_enum IOLOGICC.MODE NONE
IDDRX1_ODDRX1 F0B5 F2B2 !F3B3 F8B2 F9B4
IDDRXN F0B5 !F3B3 F8B2 F9B4
IREG_OREG !F3B3 F9B4
MIDDRX_MODDRX F0B5 F3B3 F8B2 F9B4
NONE !F3B3
ODDRXN F0B5 !F3B3 F6B3 F7B3 F8B2 F9B4

.config_enum IOLOGICC.MTDDRX.DQSW_INVERT DISABLED
DISABLED -
ENABLED F0B4

.config_enum IOLOGICC.MTDDRX.MODE NONE
MTSHX2 F8B3
NONE -

.config_enum IOLOGICC.MTDDRX.REGSET RESET
RESET -
SET F3B4

.config_enum IOLOGICC.ODDRXN.MODE NONE
NONE -
ODDR71 F0B9 F1B9 F2B9 F8B3 F8B4 F9B3 F9B8
ODDRX2 F8B3 F8B4

.config_enum IOLOGICC.OUTREG.OUTREGMODE FF
FF -
LATCH F3B5

.config_enum IOLOGICC.OUTREG.REGSET RESET
RESET -
SET F7B2

.config_enum IOLOGICC.SRMODE ASYNC
ASYNC -
LSR_OVER_CE F2B0

.config_enum IOLOGICC.TSREG.OUTREGMODE FF
FF -
LATCH F2B5

.config_enum IOLOGICC.TSREG.REGSET RESET
RESET -
SET F3B4

.config_enum IOLOGICD.CEIMUX CEMUX
1 F3B10
CEMUX -

.config_enum IOLOGICD.CEMUX INV
CE F5B5
INV -

.config_enum IOLOGICD.CEOMUX CEMUX
1 F0B8
CEMUX -

.config_enum IOLOGICD.CLKIMUX 0
0 -
CLK F8B6
INV F8B6 F9B6

.config_enum IOLOGICD.CLKOMUX 0
0 -
CLK F1B8
INV F1B8 F2B8

.config_enum IOLOGICD.DELAY.OUTDEL DISABLED
DISABLED -
ENABLED F3B8

.config_enum IOLOGICD.DELAY.WAIT_FOR_EDGE DISABLED
DISABLED -
ENABLED F8B7

.config_enum IOLOGICD.FF.INREGMODE FF
FF -
LATCH F5B7

.config_enum IOLOGICD.FF.REGSET RESET
RESET -
SET F7B6

.config_enum IOLOGICD.GSR ENABLED
DISABLED F4B6
ENABLED -

.config_enum IOLOGICD.IDDRXN.MODE NONE
IDDR71 F3B7 F4B7
IDDRX2 F3B7
NONE -

.config_enum IOLOGICD.IOLTOMUX TS
NONE -
TDDR F8B9
TS -

.config_enum IOLOGICD.LSRIMUX 0
0 -
LSRMUX F1B7

.config_enum IOLOGICD.LSRMUX INV
INV -
LSR F6B7

.config_enum IOLOGICD.LSROMUX 0
0 -
LSRMUX F4B8

.config_enum IOLOGICD.MIDDRX.MODE NONE
MIDDRX2 F3B7 F7B10
NONE -

.config_enum IOLOGICD.MIDDRX_MODDRX.WRCLKMUX NONE
DQSW F0B10
DQSW270 F0B10 F1B10
NONE -

.config_enum IOLOGICD.MODDRX.MODE NONE
MODDRX2 F1B9
MOSHX2 F1B10 F2B9
NONE -

.config_enum IOLOGICD.MODE NONE
IDDRX1_ODDRX1 F0B8 F2B10 F3B10 F4B7 !F5B6
IDDRXN F0B8 F2B10 F3B10 !F5B6
IREG_OREG F2B10 !F5B6
MIDDRX_MODDRX F0B8 F2B10 F3B10 F5B6
NONE !F5B6
ODDRXN F0B8 F0B9 F2B10 F3B10 !F5B6 F9B8

.config_enum IOLOGICD.MTDDRX.DQSW_INVERT DISABLED
DISABLED -
ENABLED F3B9

.config_enum IOLOGICD.MTDDRX.MODE NONE
MTSHX2 F1B9
NONE -

.config_enum IOLOGICD.MTDDRX.REGSET RESET
RESET -
SET F6B9

.config_enum IOLOGICD.ODDRXN.MODE NONE
NONE -
ODDR71 F1B9 F1B10 F2B9
ODDRX2 F1B9 F1B10

.config_enum IOLOGICD.OUTREG.OUTREGMODE FF
FF -
LATCH F5B10

.config_enum IOLOGICD.OUTREG.REGSET RESET
RESET -
SET F9B7

.config_enum IOLOGICD.SRMODE ASYNC
ASYNC -
LSR_OVER_CE F4B5

.config_enum IOLOGICD.TSREG.OUTREGMODE FF
FF -
LATCH F4B10

.config_enum IOLOGICD.TSREG.REGSET RESET
RESET -
SET F6B9

.config_enum PIOC.BASE_TYPE INPUT_LVCMOS18D
BIDIR_BLVDS25E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
BIDIR_HSUL12 F1B4 F2B4
BIDIR_HSUL12D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
BIDIR_LVCMOS12 F1B4 F2B4
BIDIR_LVCMOS15 F1B4 F2B4
BIDIR_LVCMOS18 F1B4 F2B4
BIDIR_LVCMOS25 F1B4 F2B4
BIDIR_LVCMOS25D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
BIDIR_LVCMOS33 F1B4 F2B4
BIDIR_LVCMOS33D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
BIDIR_LVTTL33 F1B4 F2B4
BIDIR_MLVDS25E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
BIDIR_SSTL135D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
BIDIR_SSTL135D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
BIDIR_SSTL135_I F1B4 F2B4
BIDIR_SSTL135_II F1B4 F2B4
BIDIR_SSTL15D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
BIDIR_SSTL15D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
BIDIR_SSTL15_I F1B4 F2B4
BIDIR_SSTL15_II F1B4 F2B4
BIDIR_SSTL18D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
BIDIR_SSTL18D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
BIDIR_SSTL18_I F1B4 F2B4
BIDIR_SSTL18_II F1B4 F2B4
INPUT_BLVDS25 -
INPUT_HSUL12 -
INPUT_HSUL12D -
INPUT_LVCMOS12 -
INPUT_LVCMOS15 -
INPUT_LVCMOS18 -
INPUT_LVCMOS18D -
INPUT_LVCMOS25 -
INPUT_LVCMOS25D -
INPUT_LVCMOS33 -
INPUT_LVCMOS33D -
INPUT_LVDS -
INPUT_LVPECL33 -
INPUT_LVTTL33 -
INPUT_MLVDS25 -
INPUT_SLVS -
INPUT_SSTL135D_I -
INPUT_SSTL135D_II -
INPUT_SSTL135_I -
INPUT_SSTL135_II -
INPUT_SSTL15D_I -
INPUT_SSTL15D_II -
INPUT_SSTL15_I -
INPUT_SSTL15_II -
INPUT_SSTL18D_I -
INPUT_SSTL18D_II -
INPUT_SSTL18_I -
INPUT_SSTL18_II -
INPUT_SUBLVDS -
NONE -
OUTPUT_BLVDS25E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
OUTPUT_HSUL12 F1B4 F2B4
OUTPUT_HSUL12D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
OUTPUT_LVCMOS12 F1B4 F2B4
OUTPUT_LVCMOS15 F1B4 F2B4
OUTPUT_LVCMOS18 F1B4 F2B4
OUTPUT_LVCMOS25 F1B4 F2B4
OUTPUT_LVCMOS25D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
OUTPUT_LVCMOS33 F1B4 F2B4
OUTPUT_LVCMOS33D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
OUTPUT_LVDS25E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
OUTPUT_LVPECL33E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
OUTPUT_LVTTL33 F1B4 F2B4
OUTPUT_MLVDS25E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
OUTPUT_SSTL135D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
OUTPUT_SSTL135D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
OUTPUT_SSTL135_I F1B4 F2B4
OUTPUT_SSTL135_II F1B4 F2B4
OUTPUT_SSTL15D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
OUTPUT_SSTL15D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
OUTPUT_SSTL15_I F1B4 F2B4
OUTPUT_SSTL15_II F1B4 F2B4
OUTPUT_SSTL18D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
OUTPUT_SSTL18D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
OUTPUT_SSTL18_I F1B4 F2B4
OUTPUT_SSTL18_II F1B4 F2B4

.config_enum PIOC.DATAMUX_MDDR PADDO
IOLDO F6B3 F7B3
PADDO -

.config_enum PIOC.DATAMUX_ODDR PADDO
IOLDO F6B3
PADDO -

.config_enum PIOC.DATAMUX_OREG PADDO
IOLDO F7B3
PADDO -

.config_enum PIOC.TRIMUX_TSREG PADDT
IOLTO F6B4
PADDT -

.config_enum PIOD.BASE_TYPE INPUT_HSUL12
BIDIR_HSUL12 F4B9 F5B9
BIDIR_LVCMOS12 F4B9 F5B9
BIDIR_LVCMOS15 F4B9 F5B9
BIDIR_LVCMOS18 F4B9 F5B9
BIDIR_LVCMOS25 F4B9 F5B9
BIDIR_LVCMOS33 F4B9 F5B9
BIDIR_LVTTL33 F4B9 F5B9
BIDIR_SSTL135_I F4B9 F5B9
BIDIR_SSTL135_II F4B9 F5B9
BIDIR_SSTL15_I F4B9 F5B9
BIDIR_SSTL15_II F4B9 F5B9
BIDIR_SSTL18_I F4B9 F5B9
BIDIR_SSTL18_II F4B9 F5B9
INPUT_HSUL12 -
INPUT_LVCMOS12 -
INPUT_LVCMOS15 -
INPUT_LVCMOS18 -
INPUT_LVCMOS25 -
INPUT_LVCMOS33 -
INPUT_LVTTL33 -
INPUT_SSTL135_I -
INPUT_SSTL135_II -
INPUT_SSTL15_I -
INPUT_SSTL15_II -
INPUT_SSTL18_I -
INPUT_SSTL18_II -
NONE -
OUTPUT_HSUL12 F4B9 F5B9
OUTPUT_LVCMOS12 F4B9 F5B9
OUTPUT_LVCMOS15 F4B9 F5B9
OUTPUT_LVCMOS18 F4B9 F5B9
OUTPUT_LVCMOS25 F4B9 F5B9
OUTPUT_LVCMOS33 F4B9 F5B9
OUTPUT_LVTTL33 F4B9 F5B9
OUTPUT_SSTL135_I F4B9 F5B9
OUTPUT_SSTL135_II F4B9 F5B9
OUTPUT_SSTL15_I F4B9 F5B9
OUTPUT_SSTL15_II F4B9 F5B9
OUTPUT_SSTL18_I F4B9 F5B9
OUTPUT_SSTL18_II F4B9 F5B9

.config_enum PIOD.DATAMUX_MDDR PADDO
IOLDO F0B9 F9B8
PADDO -

.config_enum PIOD.DATAMUX_ODDR PADDO
IOLDO F9B8
PADDO -

.config_enum PIOD.DATAMUX_OREG PADDO
IOLDO F0B9
PADDO -

.config_enum PIOD.TRIMUX_TSREG PADDT
IOLTO F9B9
PADDT -


# Fixed Connections