Update to prjtrellis 97109259c7243415ce61e80c2072b9c4a58c4544
Signed-off-by: David Shah <davey1576@gmail.com>
diff --git a/ECP5/tiledata/EFB0_PICB0/bits.db b/ECP5/tiledata/EFB0_PICB0/bits.db
index 8b13789..cd39643 100644
--- a/ECP5/tiledata/EFB0_PICB0/bits.db
+++ b/ECP5/tiledata/EFB0_PICB0/bits.db
@@ -1 +1,162 @@
+# Routing Mux Bits
+.mux JDIA
+INDDA_SIOLOGIC F21B0
+
+
+# Non-Routing Configuration
+.config_enum PIOA.BASE_TYPE NONE
+BIDIR_LVCMOS12 F0B1 F2B1 F7B1 F54B0 F55B0
+BIDIR_LVCMOS15 F5B1 F23B1 F54B0 F55B0
+BIDIR_LVCMOS18 F7B1 F54B0 F55B0
+BIDIR_LVCMOS25 F0B1 F1B1 F7B1 F11B1 F54B0 F55B0
+BIDIR_LVCMOS33 F0B1 F1B1 F2B1 F7B1 F11B1 F12B1 F13B1 F14B1 F54B0 F55B0
+BIDIR_LVTTL33 F0B1 F1B1 F2B1 F7B1 F11B1 F12B1 F13B1 F14B1 F54B0 F55B0
+INPUT_LVCMOS12 F0B1 F2B1 F7B1
+INPUT_LVCMOS15 F7B1
+INPUT_LVCMOS18 F7B1
+INPUT_LVCMOS25 F0B1 F1B1 F7B1 F11B1
+INPUT_LVCMOS33 F0B1 F1B1 F2B1 F7B1 F11B1
+INPUT_LVTTL33 F0B1 F1B1 F2B1 F7B1 F11B1
+NONE
+OUTPUT_LVCMOS12 F5B1 F7B1 F54B0 F55B0
+OUTPUT_LVCMOS15 F5B1 F7B1 F54B0 F55B0
+OUTPUT_LVCMOS18 F5B1 F7B1 F54B0 F55B0
+OUTPUT_LVCMOS25 F5B1 F7B1 F54B0 F55B0
+OUTPUT_LVCMOS33 F5B1 F7B1 F12B1 F13B1 F14B1 F54B0 F55B0
+OUTPUT_LVTTL33 F5B1 F7B1 F12B1 F13B1 F14B1 F54B0 F55B0
+
+.config_enum PIOA.DRIVE
+12 !F12B1 !F13B1 !F14B1 F15B1 !F16B1
+16 F12B1 F13B1 F14B1 F15B1 !F16B1
+4 !F12B1 !F13B1 F14B1 F15B1 F16B1
+8 F12B1 F13B1 F14B1 !F15B1 !F16B1
+
+.config_enum PIOA.HYSTERESIS OFF
+OFF !F11B1
+ON F11B1
+
+.config_enum PIOA.OPENDRAIN
+OFF F7B1 F12B1 F13B1 F14B1 !F23B1
+ON !F7B1 !F12B1 !F13B1 !F14B1 F23B1
+
+.config_enum PIOA.PULLMODE DOWN
+DOWN !F5B1 !F6B1
+NONE F5B1 !F6B1
+UP F5B1 F6B1
+
+.config_enum PIOA.SLEWRATE SLOW
+FAST F22B1
+SLOW !F22B1
+
+
+# Fixed Connections
+.fixed_conn DIA_SIOLOGIC JDIA
+
+.fixed_conn DIB_SIOLOGIC JDIB
+
+.fixed_conn IOLDOA IOLDOA_SIOLOGIC
+
+.fixed_conn IOLDOA IOLDODA_SIOLOGIC
+
+.fixed_conn IOLDOA_PIO IOLDOA
+
+.fixed_conn IOLDOB IOLDOB_SIOLOGIC
+
+.fixed_conn IOLDOB IOLDODB_SIOLOGIC
+
+.fixed_conn IOLDOB_PIO IOLDOB
+
+.fixed_conn IOLDOIA_SIOLOGIC IOLDOA_SIOLOGIC
+
+.fixed_conn IOLDOIB_SIOLOGIC IOLDOB_SIOLOGIC
+
+.fixed_conn IOLTOA_PIO IOLTOA_SIOLOGIC
+
+.fixed_conn IOLTOB_PIO IOLTOB_SIOLOGIC
+
+.fixed_conn JCEA_SIOLOGIC N1_JCE0
+
+.fixed_conn JCEB_SIOLOGIC N1E1_JCE0
+
+.fixed_conn JCLKA_SIOLOGIC N1_JCLK0
+
+.fixed_conn JCLKB_SIOLOGIC N1E1_JCLK0
+
+.fixed_conn JDIA JPADDIA_PIO
+
+.fixed_conn JDIB JPADDIB_PIO
+
+.fixed_conn JDIRECTIONA_SIOLOGIC N1_JB1
+
+.fixed_conn JDIRECTIONB_SIOLOGIC N1E1_JB1
+
+.fixed_conn JLOADNA_SIOLOGIC N1_JD1
+
+.fixed_conn JLOADNB_SIOLOGIC N1E1_JD1
+
+.fixed_conn JLSRA_SIOLOGIC N1_JLSR0
+
+.fixed_conn JLSRB_SIOLOGIC N1E1_JLSR0
+
+.fixed_conn JMOVEA_SIOLOGIC N1_JC1
+
+.fixed_conn JMOVEB_SIOLOGIC N1E1_JC1
+
+.fixed_conn JPADDOA N1_JA0
+
+.fixed_conn JPADDOB N1E1_JA0
+
+.fixed_conn JPADDTA N1_JB0
+
+.fixed_conn JPADDTB N1E1_JB0
+
+.fixed_conn JTSDATA0A_SIOLOGIC N1_JB0
+
+.fixed_conn JTSDATA0B_SIOLOGIC N1E1_JB0
+
+.fixed_conn JTXDATA0A_SIOLOGIC N1_JA0
+
+.fixed_conn JTXDATA0B_SIOLOGIC N1E1_JA0
+
+.fixed_conn JTXDATA1A_SIOLOGIC N1_JC0
+
+.fixed_conn JTXDATA1B_SIOLOGIC N1E1_JC0
+
+.fixed_conn N1E1_HL7W0001 N1E1_JF3
+
+.fixed_conn N1E1_JF0 JRXDATA0B_SIOLOGIC
+
+.fixed_conn N1E1_JF1 JRXDATA1B_SIOLOGIC
+
+.fixed_conn N1E1_JF2 JINFFB_SIOLOGIC
+
+.fixed_conn N1E1_JF3 JCFLAGB_SIOLOGIC
+
+.fixed_conn N1E1_JQ0 JDIB
+
+.fixed_conn N1E2_HL7W0001 N1E2_JF3
+
+.fixed_conn N1_HL7W0001 N1_JF3
+
+.fixed_conn N1_JF0 JRXDATA0A_SIOLOGIC
+
+.fixed_conn N1_JF1 JRXDATA1A_SIOLOGIC
+
+.fixed_conn N1_JF2 JINFFA_SIOLOGIC
+
+.fixed_conn N1_JF3 JCFLAGA_SIOLOGIC
+
+.fixed_conn N1_JQ0 JDIA
+
+.fixed_conn PADDIA_SIOLOGIC JPADDIA_PIO
+
+.fixed_conn PADDIB_SIOLOGIC JPADDIB_PIO
+
+.fixed_conn PADDOA_PIO JPADDOA
+
+.fixed_conn PADDOB_PIO JPADDOB
+
+.fixed_conn PADDTA_PIO JPADDTA
+
+.fixed_conn PADDTB_PIO JPADDTB
diff --git a/ECP5/tiledata/EFB1_PICB1/bits.db b/ECP5/tiledata/EFB1_PICB1/bits.db
index 8b13789..3804f51 100644
--- a/ECP5/tiledata/EFB1_PICB1/bits.db
+++ b/ECP5/tiledata/EFB1_PICB1/bits.db
@@ -1 +1,52 @@
+# Routing Mux Bits
+.mux W1_JDIB
+W1_INDDB_SIOLOGIC F21B0
+
+# Non-Routing Configuration
+.config_enum PIOB.BASE_TYPE NONE
+BIDIR_LVCMOS12 F0B1 F2B1 F7B1 F54B0 F55B0
+BIDIR_LVCMOS15 F5B1 F23B1 F54B0 F55B0
+BIDIR_LVCMOS18 F7B1 F54B0 F55B0
+BIDIR_LVCMOS25 F0B1 F1B1 F7B1 F11B1 F54B0 F55B0
+BIDIR_LVCMOS33 F0B1 F1B1 F2B1 F7B1 F11B1 F12B1 F13B1 F14B1 F54B0 F55B0
+BIDIR_LVTTL33 F0B1 F1B1 F2B1 F7B1 F11B1 F12B1 F13B1 F14B1 F54B0 F55B0
+INPUT_LVCMOS12 F0B1 F2B1 F7B1
+INPUT_LVCMOS15 F7B1
+INPUT_LVCMOS18 F7B1
+INPUT_LVCMOS25 F0B1 F1B1 F7B1 F11B1
+INPUT_LVCMOS33 F0B1 F1B1 F2B1 F7B1 F11B1
+INPUT_LVTTL33 F0B1 F1B1 F2B1 F7B1 F11B1
+NONE
+OUTPUT_LVCMOS12 F5B1 F7B1 F54B0 F55B0
+OUTPUT_LVCMOS15 F5B1 F7B1 F54B0 F55B0
+OUTPUT_LVCMOS18 F5B1 F7B1 F54B0 F55B0
+OUTPUT_LVCMOS25 F5B1 F7B1 F54B0 F55B0
+OUTPUT_LVCMOS33 F5B1 F7B1 F12B1 F13B1 F14B1 F54B0 F55B0
+OUTPUT_LVTTL33 F5B1 F7B1 F12B1 F13B1 F14B1 F54B0 F55B0
+
+.config_enum PIOB.DRIVE
+12 !F12B1 !F13B1 !F14B1 F15B1 !F16B1
+16 F12B1 F13B1 F14B1 F15B1 !F16B1
+4 !F12B1 !F13B1 F14B1 F15B1 F16B1
+8 F12B1 F13B1 F14B1 !F15B1 !F16B1
+
+.config_enum PIOB.HYSTERESIS OFF
+OFF !F11B1
+ON F11B1
+
+.config_enum PIOB.OPENDRAIN
+OFF F7B1 F12B1 F13B1 F14B1 !F23B1
+ON !F7B1 !F12B1 !F13B1 !F14B1 F23B1
+
+.config_enum PIOB.PULLMODE DOWN
+DOWN !F5B1 !F6B1
+NONE F5B1 !F6B1
+UP F5B1 F6B1
+
+.config_enum PIOB.SLEWRATE SLOW
+FAST F22B1
+SLOW !F22B1
+
+
+# Fixed Connections
diff --git a/ECP5/tiledata/EFB2_PICB0/bits.db b/ECP5/tiledata/EFB2_PICB0/bits.db
index 8238397..cd39643 100644
--- a/ECP5/tiledata/EFB2_PICB0/bits.db
+++ b/ECP5/tiledata/EFB2_PICB0/bits.db
@@ -1,4 +1,7 @@
# Routing Mux Bits
+.mux JDIA
+INDDA_SIOLOGIC F21B0
+
# Non-Routing Configuration
.config_enum PIOA.BASE_TYPE NONE
@@ -47,3 +50,113 @@
# Fixed Connections
+.fixed_conn DIA_SIOLOGIC JDIA
+
+.fixed_conn DIB_SIOLOGIC JDIB
+
+.fixed_conn IOLDOA IOLDOA_SIOLOGIC
+
+.fixed_conn IOLDOA IOLDODA_SIOLOGIC
+
+.fixed_conn IOLDOA_PIO IOLDOA
+
+.fixed_conn IOLDOB IOLDOB_SIOLOGIC
+
+.fixed_conn IOLDOB IOLDODB_SIOLOGIC
+
+.fixed_conn IOLDOB_PIO IOLDOB
+
+.fixed_conn IOLDOIA_SIOLOGIC IOLDOA_SIOLOGIC
+
+.fixed_conn IOLDOIB_SIOLOGIC IOLDOB_SIOLOGIC
+
+.fixed_conn IOLTOA_PIO IOLTOA_SIOLOGIC
+
+.fixed_conn IOLTOB_PIO IOLTOB_SIOLOGIC
+
+.fixed_conn JCEA_SIOLOGIC N1_JCE0
+
+.fixed_conn JCEB_SIOLOGIC N1E1_JCE0
+
+.fixed_conn JCLKA_SIOLOGIC N1_JCLK0
+
+.fixed_conn JCLKB_SIOLOGIC N1E1_JCLK0
+
+.fixed_conn JDIA JPADDIA_PIO
+
+.fixed_conn JDIB JPADDIB_PIO
+
+.fixed_conn JDIRECTIONA_SIOLOGIC N1_JB1
+
+.fixed_conn JDIRECTIONB_SIOLOGIC N1E1_JB1
+
+.fixed_conn JLOADNA_SIOLOGIC N1_JD1
+
+.fixed_conn JLOADNB_SIOLOGIC N1E1_JD1
+
+.fixed_conn JLSRA_SIOLOGIC N1_JLSR0
+
+.fixed_conn JLSRB_SIOLOGIC N1E1_JLSR0
+
+.fixed_conn JMOVEA_SIOLOGIC N1_JC1
+
+.fixed_conn JMOVEB_SIOLOGIC N1E1_JC1
+
+.fixed_conn JPADDOA N1_JA0
+
+.fixed_conn JPADDOB N1E1_JA0
+
+.fixed_conn JPADDTA N1_JB0
+
+.fixed_conn JPADDTB N1E1_JB0
+
+.fixed_conn JTSDATA0A_SIOLOGIC N1_JB0
+
+.fixed_conn JTSDATA0B_SIOLOGIC N1E1_JB0
+
+.fixed_conn JTXDATA0A_SIOLOGIC N1_JA0
+
+.fixed_conn JTXDATA0B_SIOLOGIC N1E1_JA0
+
+.fixed_conn JTXDATA1A_SIOLOGIC N1_JC0
+
+.fixed_conn JTXDATA1B_SIOLOGIC N1E1_JC0
+
+.fixed_conn N1E1_HL7W0001 N1E1_JF3
+
+.fixed_conn N1E1_JF0 JRXDATA0B_SIOLOGIC
+
+.fixed_conn N1E1_JF1 JRXDATA1B_SIOLOGIC
+
+.fixed_conn N1E1_JF2 JINFFB_SIOLOGIC
+
+.fixed_conn N1E1_JF3 JCFLAGB_SIOLOGIC
+
+.fixed_conn N1E1_JQ0 JDIB
+
+.fixed_conn N1E2_HL7W0001 N1E2_JF3
+
+.fixed_conn N1_HL7W0001 N1_JF3
+
+.fixed_conn N1_JF0 JRXDATA0A_SIOLOGIC
+
+.fixed_conn N1_JF1 JRXDATA1A_SIOLOGIC
+
+.fixed_conn N1_JF2 JINFFA_SIOLOGIC
+
+.fixed_conn N1_JF3 JCFLAGA_SIOLOGIC
+
+.fixed_conn N1_JQ0 JDIA
+
+.fixed_conn PADDIA_SIOLOGIC JPADDIA_PIO
+
+.fixed_conn PADDIB_SIOLOGIC JPADDIB_PIO
+
+.fixed_conn PADDOA_PIO JPADDOA
+
+.fixed_conn PADDOB_PIO JPADDOB
+
+.fixed_conn PADDTA_PIO JPADDTA
+
+.fixed_conn PADDTB_PIO JPADDTB
+
diff --git a/ECP5/tiledata/EFB3_PICB1/bits.db b/ECP5/tiledata/EFB3_PICB1/bits.db
index 6e97304..3804f51 100644
--- a/ECP5/tiledata/EFB3_PICB1/bits.db
+++ b/ECP5/tiledata/EFB3_PICB1/bits.db
@@ -1,4 +1,7 @@
# Routing Mux Bits
+.mux W1_JDIB
+W1_INDDB_SIOLOGIC F21B0
+
# Non-Routing Configuration
.config_enum PIOB.BASE_TYPE NONE
diff --git a/ECP5/tiledata/MIB_CIB_LR/bits.db b/ECP5/tiledata/MIB_CIB_LR/bits.db
index c654018..210d9b4 100644
--- a/ECP5/tiledata/MIB_CIB_LR/bits.db
+++ b/ECP5/tiledata/MIB_CIB_LR/bits.db
@@ -1,4 +1,16 @@
# Routing Mux Bits
+.mux N2_ECLKC
+BNK_ECLK1 F4B1
+
+.mux N2_ECLKD
+BNK_ECLK1 F6B6
+
+.mux N2_JDIC
+N2_INDDC_IOLOGIC F8B1
+
+.mux N2_JDID
+N2_INDDD_IOLOGIC F0B7
+
# Non-Routing Configuration
.config_enum PIOC.BASE_TYPE INPUT_LVCMOS18D
diff --git a/ECP5/tiledata/MIB_CIB_LR_A/bits.db b/ECP5/tiledata/MIB_CIB_LR_A/bits.db
index 693154a..c486cf3 100644
--- a/ECP5/tiledata/MIB_CIB_LR_A/bits.db
+++ b/ECP5/tiledata/MIB_CIB_LR_A/bits.db
@@ -1,4 +1,16 @@
# Routing Mux Bits
+.mux N2_ECLKC
+BNK_ECLK1 F5B1
+
+.mux N2_ECLKD
+BNK_ECLK1 F3B6
+
+.mux N2_JDIC
+N2_INDDC_IOLOGIC F1B1
+
+.mux N2_JDID
+N2_INDDD_IOLOGIC F9B7
+
# Non-Routing Configuration
.config_enum PIOC.BASE_TYPE INPUT_LVCMOS18D
diff --git a/ECP5/tiledata/PICL0_DQS2/bits.db b/ECP5/tiledata/PICL0_DQS2/bits.db
index c6bd7e3..2011a67 100644
--- a/ECP5/tiledata/PICL0_DQS2/bits.db
+++ b/ECP5/tiledata/PICL0_DQS2/bits.db
@@ -1,4 +1,16 @@
# Routing Mux Bits
+.mux ECLKA
+BNK_ECLK1 F4B1
+
+.mux ECLKB
+BNK_ECLK1 F6B6
+
+.mux JDIA
+INDDA_IOLOGIC F8B1
+
+.mux JDIB
+INDDB_IOLOGIC F0B7
+
# Non-Routing Configuration
.config_enum PIOA.BASE_TYPE INPUT_LVCMOS18D
@@ -131,3 +143,387 @@
# Fixed Connections
+.fixed_conn DIA_IOLOGIC JDIA
+
+.fixed_conn DIB_IOLOGIC JDIB
+
+.fixed_conn DIC_IOLOGIC JDIC
+
+.fixed_conn DID_IOLOGIC JDID
+
+.fixed_conn DQSR90A_IOLOGIC DQSG_DQSR90
+
+.fixed_conn DQSR90B_IOLOGIC DQSG_DQSR90
+
+.fixed_conn DQSR90C_IOLOGIC DQSG_DQSR90
+
+.fixed_conn DQSR90D_IOLOGIC DQSG_DQSR90
+
+.fixed_conn DQSW270A_IOLOGIC DQSG_DQSW270
+
+.fixed_conn DQSW270B_IOLOGIC DQSG_DQSW270
+
+.fixed_conn DQSW270C_IOLOGIC DQSG_DQSW270
+
+.fixed_conn DQSW270D_IOLOGIC DQSG_DQSW270
+
+.fixed_conn DQSWA_IOLOGIC DQSG_DQSW
+
+.fixed_conn DQSWB_IOLOGIC DQSG_DQSW
+
+.fixed_conn DQSWC_IOLOGIC DQSG_DQSW
+
+.fixed_conn DQSWD_IOLOGIC DQSG_DQSW
+
+.fixed_conn E1_JF0 JRXDATA0A_IOLOGIC
+
+.fixed_conn E1_JF1 JRXDATA1A_IOLOGIC
+
+.fixed_conn E1_JF2 JRXDATA2A_IOLOGIC
+
+.fixed_conn E1_JF3 JRXDATA3A_IOLOGIC
+
+.fixed_conn E1_JF4 JINFFA_IOLOGIC
+
+.fixed_conn E1_JF5 JDIA
+
+.fixed_conn E1_JF6 JCFLAGA_IOLOGIC
+
+.fixed_conn E1_JF7 JCFLAGB_IOLOGIC
+
+.fixed_conn E1_JQ0 JRXDATA0B_IOLOGIC
+
+.fixed_conn E1_JQ1 JRXDATA1B_IOLOGIC
+
+.fixed_conn E1_JQ1 JRXDATA4A_IOLOGIC
+
+.fixed_conn E1_JQ2 JRXDATA2B_IOLOGIC
+
+.fixed_conn E1_JQ2 JRXDATA5A_IOLOGIC
+
+.fixed_conn E1_JQ3 JRXDATA3B_IOLOGIC
+
+.fixed_conn E1_JQ3 JRXDATA6A_IOLOGIC
+
+.fixed_conn E1_JQ4 JINFFB_IOLOGIC
+
+.fixed_conn E1_JQ5 JDIB
+
+.fixed_conn ECLKA BNK_ECLK0
+
+.fixed_conn ECLKA_IOLOGIC ECLKA
+
+.fixed_conn ECLKB BNK_ECLK0
+
+.fixed_conn ECLKB_IOLOGIC ECLKB
+
+.fixed_conn ECLKC BNK_ECLK0
+
+.fixed_conn ECLKC_IOLOGIC ECLKC
+
+.fixed_conn ECLKD BNK_ECLK0
+
+.fixed_conn ECLKD_IOLOGIC ECLKD
+
+.fixed_conn INRDA_PIO BNK_INRD
+
+.fixed_conn INRDB_PIO BNK_INRD
+
+.fixed_conn INRDC_PIO BNK_INRD
+
+.fixed_conn INRDD_PIO BNK_INRD
+
+.fixed_conn IOLDOA IOLDOA_IOLOGIC
+
+.fixed_conn IOLDOA IOLDODA_IOLOGIC
+
+.fixed_conn IOLDOA_PIO IOLDOA
+
+.fixed_conn IOLDOB IOLDOB_IOLOGIC
+
+.fixed_conn IOLDOB IOLDODB_IOLOGIC
+
+.fixed_conn IOLDOB_PIO IOLDOB
+
+.fixed_conn IOLDOC IOLDOC_IOLOGIC
+
+.fixed_conn IOLDOC IOLDODC_IOLOGIC
+
+.fixed_conn IOLDOC_PIO IOLDOC
+
+.fixed_conn IOLDOD IOLDODD_IOLOGIC
+
+.fixed_conn IOLDOD IOLDOD_IOLOGIC
+
+.fixed_conn IOLDOD_PIO IOLDOD
+
+.fixed_conn IOLDOIA_IOLOGIC IOLDOA_IOLOGIC
+
+.fixed_conn IOLDOIB_IOLOGIC IOLDOB_IOLOGIC
+
+.fixed_conn IOLDOIC_IOLOGIC IOLDOC_IOLOGIC
+
+.fixed_conn IOLDOID_IOLOGIC IOLDOD_IOLOGIC
+
+.fixed_conn IOLTOA_PIO IOLTOA_IOLOGIC
+
+.fixed_conn IOLTOB_PIO IOLTOB_IOLOGIC
+
+.fixed_conn IOLTOC_PIO IOLTOC_IOLOGIC
+
+.fixed_conn IOLTOD_PIO IOLTOD_IOLOGIC
+
+.fixed_conn JCEA_IOLOGIC E1_JCE0
+
+.fixed_conn JCEB_IOLOGIC E1_JCE1
+
+.fixed_conn JCEC_IOLOGIC S2E1_JCE0
+
+.fixed_conn JCED_IOLOGIC S2E1_JCE1
+
+.fixed_conn JCLKA_IOLOGIC E1_JCLK0
+
+.fixed_conn JCLKB_IOLOGIC E1_JCLK1
+
+.fixed_conn JCLKC_IOLOGIC S2E1_JCLK0
+
+.fixed_conn JCLKD_IOLOGIC S2E1_JCLK1
+
+.fixed_conn JDIA JPADDIA_PIO
+
+.fixed_conn JDIB JPADDIB_PIO
+
+.fixed_conn JDIC JPADDIC_PIO
+
+.fixed_conn JDID JPADDID_PIO
+
+.fixed_conn JDIRECTIONA_IOLOGIC E1_JA2
+
+.fixed_conn JDIRECTIONB_IOLOGIC E1_JA5
+
+.fixed_conn JDIRECTIONC_IOLOGIC S2E1_JA2
+
+.fixed_conn JDIRECTIOND_IOLOGIC S2E1_JA5
+
+.fixed_conn JLOADNA_IOLOGIC E1_JC2
+
+.fixed_conn JLOADNB_IOLOGIC E1_JC5
+
+.fixed_conn JLOADNC_IOLOGIC S2E1_JC2
+
+.fixed_conn JLOADND_IOLOGIC S2E1_JC5
+
+.fixed_conn JLSRA_IOLOGIC E1_JLSR0
+
+.fixed_conn JLSRB_IOLOGIC E1_JLSR1
+
+.fixed_conn JLSRC_IOLOGIC S2E1_JLSR0
+
+.fixed_conn JLSRD_IOLOGIC S2E1_JLSR1
+
+.fixed_conn JMOVEA_IOLOGIC E1_JB2
+
+.fixed_conn JMOVEB_IOLOGIC E1_JB5
+
+.fixed_conn JMOVEC_IOLOGIC S2E1_JB2
+
+.fixed_conn JMOVED_IOLOGIC S2E1_JB5
+
+.fixed_conn JPADDOA E1_JA0
+
+.fixed_conn JPADDOB E1_JA3
+
+.fixed_conn JPADDOC S2E1_JA0
+
+.fixed_conn JPADDOD S2E1_JA3
+
+.fixed_conn JPADDTA E1_JB0
+
+.fixed_conn JPADDTB E1_JB3
+
+.fixed_conn JPADDTC S2E1_JB0
+
+.fixed_conn JPADDTD S2E1_JB3
+
+.fixed_conn JSLIPA_IOLOGIC E1_JB1
+
+.fixed_conn JSLIPB_IOLOGIC E1_JB4
+
+.fixed_conn JSLIPC_IOLOGIC S2E1_JB1
+
+.fixed_conn JSLIPD_IOLOGIC S2E1_JB4
+
+.fixed_conn JTSDATA0A_IOLOGIC E1_JB0
+
+.fixed_conn JTSDATA0B_IOLOGIC E1_JB3
+
+.fixed_conn JTSDATA0C_IOLOGIC S2E1_JB0
+
+.fixed_conn JTSDATA0D_IOLOGIC S2E1_JB3
+
+.fixed_conn JTSDATA1A_IOLOGIC E1_JC1
+
+.fixed_conn JTSDATA1B_IOLOGIC E1_JC4
+
+.fixed_conn JTSDATA1C_IOLOGIC S2E1_JC1
+
+.fixed_conn JTSDATA1D_IOLOGIC S2E1_JC4
+
+.fixed_conn JTXDATA0A_IOLOGIC E1_JA0
+
+.fixed_conn JTXDATA0B_IOLOGIC E1_JA3
+
+.fixed_conn JTXDATA0C_IOLOGIC S2E1_JA0
+
+.fixed_conn JTXDATA0D_IOLOGIC S2E1_JA3
+
+.fixed_conn JTXDATA1A_IOLOGIC E1_JC0
+
+.fixed_conn JTXDATA1B_IOLOGIC E1_JC3
+
+.fixed_conn JTXDATA1C_IOLOGIC S2E1_JC0
+
+.fixed_conn JTXDATA1D_IOLOGIC S2E1_JC3
+
+.fixed_conn JTXDATA2A_IOLOGIC E1_JD0
+
+.fixed_conn JTXDATA2B_IOLOGIC E1_JD3
+
+.fixed_conn JTXDATA2C_IOLOGIC S2E1_JD0
+
+.fixed_conn JTXDATA2D_IOLOGIC S2E1_JD3
+
+.fixed_conn JTXDATA3A_IOLOGIC E1_JA1
+
+.fixed_conn JTXDATA3B_IOLOGIC E1_JA4
+
+.fixed_conn JTXDATA3C_IOLOGIC S2E1_JA1
+
+.fixed_conn JTXDATA3D_IOLOGIC S2E1_JA4
+
+.fixed_conn JTXDATA4A_IOLOGIC E1_JA3
+
+.fixed_conn JTXDATA4C_IOLOGIC S2E1_JA3
+
+.fixed_conn JTXDATA5A_IOLOGIC E1_JC3
+
+.fixed_conn JTXDATA5C_IOLOGIC S2E1_JC3
+
+.fixed_conn JTXDATA6A_IOLOGIC E1_JD3
+
+.fixed_conn JTXDATA6C_IOLOGIC S2E1_JD3
+
+.fixed_conn LVDSA_PIO BNK_LVDS
+
+.fixed_conn LVDSB_PIO BNK_LVDS
+
+.fixed_conn LVDSC_PIO BNK_LVDS
+
+.fixed_conn LVDSD_PIO BNK_LVDS
+
+.fixed_conn PADDIA_IOLOGIC JPADDIA_PIO
+
+.fixed_conn PADDIB_IOLOGIC JPADDIB_PIO
+
+.fixed_conn PADDIC_IOLOGIC JPADDIC_PIO
+
+.fixed_conn PADDID_IOLOGIC JPADDID_PIO
+
+.fixed_conn PADDOA_PIO JPADDOA
+
+.fixed_conn PADDOB_PIO JPADDOB
+
+.fixed_conn PADDOC_PIO JPADDOC
+
+.fixed_conn PADDOD_PIO JPADDOD
+
+.fixed_conn PADDTA_PIO JPADDTA
+
+.fixed_conn PADDTB_PIO JPADDTB
+
+.fixed_conn PADDTC_PIO JPADDTC
+
+.fixed_conn PADDTD_PIO JPADDTD
+
+.fixed_conn RDPNTR0A_IOLOGIC DQSG_RDPNTR0
+
+.fixed_conn RDPNTR0B_IOLOGIC DQSG_RDPNTR0
+
+.fixed_conn RDPNTR0C_IOLOGIC DQSG_RDPNTR0
+
+.fixed_conn RDPNTR0D_IOLOGIC DQSG_RDPNTR0
+
+.fixed_conn RDPNTR1A_IOLOGIC DQSG_RDPNTR1
+
+.fixed_conn RDPNTR1B_IOLOGIC DQSG_RDPNTR1
+
+.fixed_conn RDPNTR1C_IOLOGIC DQSG_RDPNTR1
+
+.fixed_conn RDPNTR1D_IOLOGIC DQSG_RDPNTR1
+
+.fixed_conn RDPNTR2A_IOLOGIC DQSG_RDPNTR2
+
+.fixed_conn RDPNTR2B_IOLOGIC DQSG_RDPNTR2
+
+.fixed_conn RDPNTR2C_IOLOGIC DQSG_RDPNTR2
+
+.fixed_conn RDPNTR2D_IOLOGIC DQSG_RDPNTR2
+
+.fixed_conn S2E1_JF0 JRXDATA0C_IOLOGIC
+
+.fixed_conn S2E1_JF1 JRXDATA1C_IOLOGIC
+
+.fixed_conn S2E1_JF2 JRXDATA2C_IOLOGIC
+
+.fixed_conn S2E1_JF3 JRXDATA3C_IOLOGIC
+
+.fixed_conn S2E1_JF4 JINFFC_IOLOGIC
+
+.fixed_conn S2E1_JF5 JDIC
+
+.fixed_conn S2E1_JF6 JCFLAGC_IOLOGIC
+
+.fixed_conn S2E1_JF7 JCFLAGD_IOLOGIC
+
+.fixed_conn S2E1_JQ0 JRXDATA0D_IOLOGIC
+
+.fixed_conn S2E1_JQ1 JRXDATA1D_IOLOGIC
+
+.fixed_conn S2E1_JQ1 JRXDATA4C_IOLOGIC
+
+.fixed_conn S2E1_JQ2 JRXDATA2D_IOLOGIC
+
+.fixed_conn S2E1_JQ2 JRXDATA5C_IOLOGIC
+
+.fixed_conn S2E1_JQ3 JRXDATA3D_IOLOGIC
+
+.fixed_conn S2E1_JQ3 JRXDATA6C_IOLOGIC
+
+.fixed_conn S2E1_JQ4 JINFFD_IOLOGIC
+
+.fixed_conn S2E1_JQ5 JDID
+
+.fixed_conn WRPNTR0A_IOLOGIC DQSG_WRPNTR0
+
+.fixed_conn WRPNTR0B_IOLOGIC DQSG_WRPNTR0
+
+.fixed_conn WRPNTR0C_IOLOGIC DQSG_WRPNTR0
+
+.fixed_conn WRPNTR0D_IOLOGIC DQSG_WRPNTR0
+
+.fixed_conn WRPNTR1A_IOLOGIC DQSG_WRPNTR1
+
+.fixed_conn WRPNTR1B_IOLOGIC DQSG_WRPNTR1
+
+.fixed_conn WRPNTR1C_IOLOGIC DQSG_WRPNTR1
+
+.fixed_conn WRPNTR1D_IOLOGIC DQSG_WRPNTR1
+
+.fixed_conn WRPNTR2A_IOLOGIC DQSG_WRPNTR2
+
+.fixed_conn WRPNTR2B_IOLOGIC DQSG_WRPNTR2
+
+.fixed_conn WRPNTR2C_IOLOGIC DQSG_WRPNTR2
+
+.fixed_conn WRPNTR2D_IOLOGIC DQSG_WRPNTR2
+
diff --git a/ECP5/tiledata/PICL2_DQS1/bits.db b/ECP5/tiledata/PICL2_DQS1/bits.db
index c654018..210d9b4 100644
--- a/ECP5/tiledata/PICL2_DQS1/bits.db
+++ b/ECP5/tiledata/PICL2_DQS1/bits.db
@@ -1,4 +1,16 @@
# Routing Mux Bits
+.mux N2_ECLKC
+BNK_ECLK1 F4B1
+
+.mux N2_ECLKD
+BNK_ECLK1 F6B6
+
+.mux N2_JDIC
+N2_INDDC_IOLOGIC F8B1
+
+.mux N2_JDID
+N2_INDDD_IOLOGIC F0B7
+
# Non-Routing Configuration
.config_enum PIOC.BASE_TYPE INPUT_LVCMOS18D
diff --git a/ECP5/tiledata/PICR0_DQS2/bits.db b/ECP5/tiledata/PICR0_DQS2/bits.db
index 8b13789..360eed8 100644
--- a/ECP5/tiledata/PICR0_DQS2/bits.db
+++ b/ECP5/tiledata/PICR0_DQS2/bits.db
@@ -1 +1,529 @@
+# Routing Mux Bits
+.mux ECLKA
+BNK_ECLK1 F5B1
+
+.mux ECLKB
+BNK_ECLK1 F3B6
+
+.mux JDIA
+INDDA_IOLOGIC F1B1
+
+.mux JDIB
+INDDB_IOLOGIC F9B7
+
+
+# Non-Routing Configuration
+.config_enum PIOA.BASE_TYPE INPUT_LVCMOS18D
+BIDIR_BLVDS25E F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_HSUL12 F7B4 F8B4
+BIDIR_HSUL12D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_LVCMOS12 F7B4 F8B4
+BIDIR_LVCMOS15 F7B4 F8B4
+BIDIR_LVCMOS18 F7B4 F8B4
+BIDIR_LVCMOS18D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_LVCMOS25 F7B4 F8B4
+BIDIR_LVCMOS25D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_LVCMOS33 F7B4 F8B4
+BIDIR_LVCMOS33D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_LVDS F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_LVTTL33 F7B4 F8B4
+BIDIR_MLVDS25E F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_SSTL135D_I F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_SSTL135D_II F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_SSTL135_I F7B4 F8B4
+BIDIR_SSTL135_II F7B4 F8B4
+BIDIR_SSTL15D_I F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_SSTL15D_II F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_SSTL15_I F7B4 F8B4
+BIDIR_SSTL15_II F7B4 F8B4
+BIDIR_SSTL18D_I F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_SSTL18D_II F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_SSTL18_I F7B4 F8B4
+BIDIR_SSTL18_II F7B4 F8B4
+INPUT_BLVDS25
+INPUT_HSUL12
+INPUT_HSUL12D
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS18D
+INPUT_LVCMOS25
+INPUT_LVCMOS25D
+INPUT_LVCMOS33
+INPUT_LVCMOS33D
+INPUT_LVDS
+INPUT_LVPECL33
+INPUT_LVTTL33
+INPUT_MLVDS25
+INPUT_SLVS
+INPUT_SSTL135D_I
+INPUT_SSTL135D_II
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15D_I
+INPUT_SSTL15D_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18D_I
+INPUT_SSTL18D_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+INPUT_SUBLVDS
+NONE
+OUTPUT_BLVDS25E F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_HSUL12 F7B4 F8B4
+OUTPUT_HSUL12D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_LVCMOS12 F7B4 F8B4
+OUTPUT_LVCMOS15 F7B4 F8B4
+OUTPUT_LVCMOS18 F7B4 F8B4
+OUTPUT_LVCMOS18D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_LVCMOS25 F7B4 F8B4
+OUTPUT_LVCMOS25D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_LVCMOS33 F7B4 F8B4
+OUTPUT_LVCMOS33D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_LVDS F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_LVDS25E F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_LVPECL33E F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_LVTTL33 F7B4 F8B4
+OUTPUT_MLVDS25E F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_SSTL135D_I F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_SSTL135D_II F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_SSTL135_I F7B4 F8B4
+OUTPUT_SSTL135_II F7B4 F8B4
+OUTPUT_SSTL15D_I F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_SSTL15D_II F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_SSTL15_I F7B4 F8B4
+OUTPUT_SSTL15_II F7B4 F8B4
+OUTPUT_SSTL18D_I F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_SSTL18D_II F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_SSTL18_I F7B4 F8B4
+OUTPUT_SSTL18_II F7B4 F8B4
+
+.config_enum PIOB.BASE_TYPE INPUT_HSUL12
+BIDIR_HSUL12 F5B9 F6B9
+BIDIR_LVCMOS12 F5B9 F6B9
+BIDIR_LVCMOS15 F5B9 F6B9
+BIDIR_LVCMOS18 F5B9 F6B9
+BIDIR_LVCMOS25 F5B9 F6B9
+BIDIR_LVCMOS33 F5B9 F6B9
+BIDIR_LVTTL33 F5B9 F6B9
+BIDIR_SSTL135_I F5B9 F6B9
+BIDIR_SSTL135_II F5B9 F6B9
+BIDIR_SSTL15_I F5B9 F6B9
+BIDIR_SSTL15_II F5B9 F6B9
+BIDIR_SSTL18_I F5B9 F6B9
+BIDIR_SSTL18_II F5B9 F6B9
+INPUT_HSUL12
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS25
+INPUT_LVCMOS33
+INPUT_LVTTL33
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+NONE
+OUTPUT_HSUL12 F5B9 F6B9
+OUTPUT_LVCMOS12 F5B9 F6B9
+OUTPUT_LVCMOS15 F5B9 F6B9
+OUTPUT_LVCMOS18 F5B9 F6B9
+OUTPUT_LVCMOS25 F5B9 F6B9
+OUTPUT_LVCMOS33 F5B9 F6B9
+OUTPUT_LVTTL33 F5B9 F6B9
+OUTPUT_SSTL135_I F5B9 F6B9
+OUTPUT_SSTL135_II F5B9 F6B9
+OUTPUT_SSTL15_I F5B9 F6B9
+OUTPUT_SSTL15_II F5B9 F6B9
+OUTPUT_SSTL18_I F5B9 F6B9
+OUTPUT_SSTL18_II F5B9 F6B9
+
+
+# Fixed Connections
+.fixed_conn DIA_IOLOGIC JDIA
+
+.fixed_conn DIB_IOLOGIC JDIB
+
+.fixed_conn DIC_IOLOGIC JDIC
+
+.fixed_conn DID_IOLOGIC JDID
+
+.fixed_conn DQSR90A_IOLOGIC DQSG_DQSR90
+
+.fixed_conn DQSR90B_IOLOGIC DQSG_DQSR90
+
+.fixed_conn DQSR90C_IOLOGIC DQSG_DQSR90
+
+.fixed_conn DQSR90D_IOLOGIC DQSG_DQSR90
+
+.fixed_conn DQSW270A_IOLOGIC DQSG_DQSW270
+
+.fixed_conn DQSW270B_IOLOGIC DQSG_DQSW270
+
+.fixed_conn DQSW270C_IOLOGIC DQSG_DQSW270
+
+.fixed_conn DQSW270D_IOLOGIC DQSG_DQSW270
+
+.fixed_conn DQSWA_IOLOGIC DQSG_DQSW
+
+.fixed_conn DQSWB_IOLOGIC DQSG_DQSW
+
+.fixed_conn DQSWC_IOLOGIC DQSG_DQSW
+
+.fixed_conn DQSWD_IOLOGIC DQSG_DQSW
+
+.fixed_conn ECLKA BNK_ECLK0
+
+.fixed_conn ECLKA_IOLOGIC ECLKA
+
+.fixed_conn ECLKB BNK_ECLK0
+
+.fixed_conn ECLKB_IOLOGIC ECLKB
+
+.fixed_conn ECLKC BNK_ECLK0
+
+.fixed_conn ECLKC_IOLOGIC ECLKC
+
+.fixed_conn ECLKD BNK_ECLK0
+
+.fixed_conn ECLKD_IOLOGIC ECLKD
+
+.fixed_conn INRDA_PIO BNK_INRD
+
+.fixed_conn INRDB_PIO BNK_INRD
+
+.fixed_conn INRDC_PIO BNK_INRD
+
+.fixed_conn INRDD_PIO BNK_INRD
+
+.fixed_conn IOLDOA IOLDOA_IOLOGIC
+
+.fixed_conn IOLDOA IOLDODA_IOLOGIC
+
+.fixed_conn IOLDOA_PIO IOLDOA
+
+.fixed_conn IOLDOB IOLDOB_IOLOGIC
+
+.fixed_conn IOLDOB IOLDODB_IOLOGIC
+
+.fixed_conn IOLDOB_PIO IOLDOB
+
+.fixed_conn IOLDOC IOLDOC_IOLOGIC
+
+.fixed_conn IOLDOC IOLDODC_IOLOGIC
+
+.fixed_conn IOLDOC_PIO IOLDOC
+
+.fixed_conn IOLDOD IOLDODD_IOLOGIC
+
+.fixed_conn IOLDOD IOLDOD_IOLOGIC
+
+.fixed_conn IOLDOD_PIO IOLDOD
+
+.fixed_conn IOLDOIA_IOLOGIC IOLDOA_IOLOGIC
+
+.fixed_conn IOLDOIB_IOLOGIC IOLDOB_IOLOGIC
+
+.fixed_conn IOLDOIC_IOLOGIC IOLDOC_IOLOGIC
+
+.fixed_conn IOLDOID_IOLOGIC IOLDOD_IOLOGIC
+
+.fixed_conn IOLTOA_PIO IOLTOA_IOLOGIC
+
+.fixed_conn IOLTOB_PIO IOLTOB_IOLOGIC
+
+.fixed_conn IOLTOC_PIO IOLTOC_IOLOGIC
+
+.fixed_conn IOLTOD_PIO IOLTOD_IOLOGIC
+
+.fixed_conn JCEA_IOLOGIC W1_JCE0
+
+.fixed_conn JCEB_IOLOGIC W1_JCE1
+
+.fixed_conn JCEC_IOLOGIC S2W1_JCE0
+
+.fixed_conn JCED_IOLOGIC S2W1_JCE1
+
+.fixed_conn JCLKA_IOLOGIC W1_JCLK0
+
+.fixed_conn JCLKB_IOLOGIC W1_JCLK1
+
+.fixed_conn JCLKC_IOLOGIC S2W1_JCLK0
+
+.fixed_conn JCLKD_IOLOGIC S2W1_JCLK1
+
+.fixed_conn JDIA JPADDIA_PIO
+
+.fixed_conn JDIB JPADDIB_PIO
+
+.fixed_conn JDIC JPADDIC_PIO
+
+.fixed_conn JDID JPADDID_PIO
+
+.fixed_conn JDIRECTIONA_IOLOGIC W1_JA2
+
+.fixed_conn JDIRECTIONB_IOLOGIC W1_JA5
+
+.fixed_conn JDIRECTIONC_IOLOGIC S2W1_JA2
+
+.fixed_conn JDIRECTIOND_IOLOGIC S2W1_JA5
+
+.fixed_conn JLOADNA_IOLOGIC W1_JC2
+
+.fixed_conn JLOADNB_IOLOGIC W1_JC5
+
+.fixed_conn JLOADNC_IOLOGIC S2W1_JC2
+
+.fixed_conn JLOADND_IOLOGIC S2W1_JC5
+
+.fixed_conn JLSRA_IOLOGIC W1_JLSR0
+
+.fixed_conn JLSRB_IOLOGIC W1_JLSR1
+
+.fixed_conn JLSRC_IOLOGIC S2W1_JLSR0
+
+.fixed_conn JLSRD_IOLOGIC S2W1_JLSR1
+
+.fixed_conn JMOVEA_IOLOGIC W1_JB2
+
+.fixed_conn JMOVEB_IOLOGIC W1_JB5
+
+.fixed_conn JMOVEC_IOLOGIC S2W1_JB2
+
+.fixed_conn JMOVED_IOLOGIC S2W1_JB5
+
+.fixed_conn JPADDOA W1_JA0
+
+.fixed_conn JPADDOB W1_JA3
+
+.fixed_conn JPADDOC S2W1_JA0
+
+.fixed_conn JPADDOD S2W1_JA3
+
+.fixed_conn JPADDTA W1_JB0
+
+.fixed_conn JPADDTB W1_JB3
+
+.fixed_conn JPADDTC S2W1_JB0
+
+.fixed_conn JPADDTD S2W1_JB3
+
+.fixed_conn JSLIPA_IOLOGIC W1_JB1
+
+.fixed_conn JSLIPB_IOLOGIC W1_JB4
+
+.fixed_conn JSLIPC_IOLOGIC S2W1_JB1
+
+.fixed_conn JSLIPD_IOLOGIC S2W1_JB4
+
+.fixed_conn JTSDATA0A_IOLOGIC W1_JB0
+
+.fixed_conn JTSDATA0B_IOLOGIC W1_JB3
+
+.fixed_conn JTSDATA0C_IOLOGIC S2W1_JB0
+
+.fixed_conn JTSDATA0D_IOLOGIC S2W1_JB3
+
+.fixed_conn JTSDATA1A_IOLOGIC W1_JC1
+
+.fixed_conn JTSDATA1B_IOLOGIC W1_JC4
+
+.fixed_conn JTSDATA1C_IOLOGIC S2W1_JC1
+
+.fixed_conn JTSDATA1D_IOLOGIC S2W1_JC4
+
+.fixed_conn JTXDATA0A_IOLOGIC W1_JA0
+
+.fixed_conn JTXDATA0B_IOLOGIC W1_JA3
+
+.fixed_conn JTXDATA0C_IOLOGIC S2W1_JA0
+
+.fixed_conn JTXDATA0D_IOLOGIC S2W1_JA3
+
+.fixed_conn JTXDATA1A_IOLOGIC W1_JC0
+
+.fixed_conn JTXDATA1B_IOLOGIC W1_JC3
+
+.fixed_conn JTXDATA1C_IOLOGIC S2W1_JC0
+
+.fixed_conn JTXDATA1D_IOLOGIC S2W1_JC3
+
+.fixed_conn JTXDATA2A_IOLOGIC W1_JD0
+
+.fixed_conn JTXDATA2B_IOLOGIC W1_JD3
+
+.fixed_conn JTXDATA2C_IOLOGIC S2W1_JD0
+
+.fixed_conn JTXDATA2D_IOLOGIC S2W1_JD3
+
+.fixed_conn JTXDATA3A_IOLOGIC W1_JA1
+
+.fixed_conn JTXDATA3B_IOLOGIC W1_JA4
+
+.fixed_conn JTXDATA3C_IOLOGIC S2W1_JA1
+
+.fixed_conn JTXDATA3D_IOLOGIC S2W1_JA4
+
+.fixed_conn JTXDATA4A_IOLOGIC W1_JA3
+
+.fixed_conn JTXDATA4C_IOLOGIC S2W1_JA3
+
+.fixed_conn JTXDATA5A_IOLOGIC W1_JC3
+
+.fixed_conn JTXDATA5C_IOLOGIC S2W1_JC3
+
+.fixed_conn JTXDATA6A_IOLOGIC W1_JD3
+
+.fixed_conn JTXDATA6C_IOLOGIC S2W1_JD3
+
+.fixed_conn LVDSA_PIO BNK_LVDS
+
+.fixed_conn LVDSB_PIO BNK_LVDS
+
+.fixed_conn LVDSC_PIO BNK_LVDS
+
+.fixed_conn LVDSD_PIO BNK_LVDS
+
+.fixed_conn PADDIA_IOLOGIC JPADDIA_PIO
+
+.fixed_conn PADDIB_IOLOGIC JPADDIB_PIO
+
+.fixed_conn PADDIC_IOLOGIC JPADDIC_PIO
+
+.fixed_conn PADDID_IOLOGIC JPADDID_PIO
+
+.fixed_conn PADDOA_PIO JPADDOA
+
+.fixed_conn PADDOB_PIO JPADDOB
+
+.fixed_conn PADDOC_PIO JPADDOC
+
+.fixed_conn PADDOD_PIO JPADDOD
+
+.fixed_conn PADDTA_PIO JPADDTA
+
+.fixed_conn PADDTB_PIO JPADDTB
+
+.fixed_conn PADDTC_PIO JPADDTC
+
+.fixed_conn PADDTD_PIO JPADDTD
+
+.fixed_conn RDPNTR0A_IOLOGIC DQSG_RDPNTR0
+
+.fixed_conn RDPNTR0B_IOLOGIC DQSG_RDPNTR0
+
+.fixed_conn RDPNTR0C_IOLOGIC DQSG_RDPNTR0
+
+.fixed_conn RDPNTR0D_IOLOGIC DQSG_RDPNTR0
+
+.fixed_conn RDPNTR1A_IOLOGIC DQSG_RDPNTR1
+
+.fixed_conn RDPNTR1B_IOLOGIC DQSG_RDPNTR1
+
+.fixed_conn RDPNTR1C_IOLOGIC DQSG_RDPNTR1
+
+.fixed_conn RDPNTR1D_IOLOGIC DQSG_RDPNTR1
+
+.fixed_conn RDPNTR2A_IOLOGIC DQSG_RDPNTR2
+
+.fixed_conn RDPNTR2B_IOLOGIC DQSG_RDPNTR2
+
+.fixed_conn RDPNTR2C_IOLOGIC DQSG_RDPNTR2
+
+.fixed_conn RDPNTR2D_IOLOGIC DQSG_RDPNTR2
+
+.fixed_conn S2W1_JF0 JRXDATA0C_IOLOGIC
+
+.fixed_conn S2W1_JF1 JRXDATA1C_IOLOGIC
+
+.fixed_conn S2W1_JF2 JRXDATA2C_IOLOGIC
+
+.fixed_conn S2W1_JF3 JRXDATA3C_IOLOGIC
+
+.fixed_conn S2W1_JF4 JINFFC_IOLOGIC
+
+.fixed_conn S2W1_JF5 JDIC
+
+.fixed_conn S2W1_JF6 JCFLAGC_IOLOGIC
+
+.fixed_conn S2W1_JF7 JCFLAGD_IOLOGIC
+
+.fixed_conn S2W1_JQ0 JRXDATA0D_IOLOGIC
+
+.fixed_conn S2W1_JQ1 JRXDATA1D_IOLOGIC
+
+.fixed_conn S2W1_JQ1 JRXDATA4C_IOLOGIC
+
+.fixed_conn S2W1_JQ2 JRXDATA2D_IOLOGIC
+
+.fixed_conn S2W1_JQ2 JRXDATA5C_IOLOGIC
+
+.fixed_conn S2W1_JQ3 JRXDATA3D_IOLOGIC
+
+.fixed_conn S2W1_JQ3 JRXDATA6C_IOLOGIC
+
+.fixed_conn S2W1_JQ4 JINFFD_IOLOGIC
+
+.fixed_conn S2W1_JQ5 JDID
+
+.fixed_conn W1_JF0 JRXDATA0A_IOLOGIC
+
+.fixed_conn W1_JF1 JRXDATA1A_IOLOGIC
+
+.fixed_conn W1_JF2 JRXDATA2A_IOLOGIC
+
+.fixed_conn W1_JF3 JRXDATA3A_IOLOGIC
+
+.fixed_conn W1_JF4 JINFFA_IOLOGIC
+
+.fixed_conn W1_JF5 JDIA
+
+.fixed_conn W1_JF6 JCFLAGA_IOLOGIC
+
+.fixed_conn W1_JF7 JCFLAGB_IOLOGIC
+
+.fixed_conn W1_JQ0 JRXDATA0B_IOLOGIC
+
+.fixed_conn W1_JQ1 JRXDATA1B_IOLOGIC
+
+.fixed_conn W1_JQ1 JRXDATA4A_IOLOGIC
+
+.fixed_conn W1_JQ2 JRXDATA2B_IOLOGIC
+
+.fixed_conn W1_JQ2 JRXDATA5A_IOLOGIC
+
+.fixed_conn W1_JQ3 JRXDATA3B_IOLOGIC
+
+.fixed_conn W1_JQ3 JRXDATA6A_IOLOGIC
+
+.fixed_conn W1_JQ4 JINFFB_IOLOGIC
+
+.fixed_conn W1_JQ5 JDIB
+
+.fixed_conn WRPNTR0A_IOLOGIC DQSG_WRPNTR0
+
+.fixed_conn WRPNTR0B_IOLOGIC DQSG_WRPNTR0
+
+.fixed_conn WRPNTR0C_IOLOGIC DQSG_WRPNTR0
+
+.fixed_conn WRPNTR0D_IOLOGIC DQSG_WRPNTR0
+
+.fixed_conn WRPNTR1A_IOLOGIC DQSG_WRPNTR1
+
+.fixed_conn WRPNTR1B_IOLOGIC DQSG_WRPNTR1
+
+.fixed_conn WRPNTR1C_IOLOGIC DQSG_WRPNTR1
+
+.fixed_conn WRPNTR1D_IOLOGIC DQSG_WRPNTR1
+
+.fixed_conn WRPNTR2A_IOLOGIC DQSG_WRPNTR2
+
+.fixed_conn WRPNTR2B_IOLOGIC DQSG_WRPNTR2
+
+.fixed_conn WRPNTR2C_IOLOGIC DQSG_WRPNTR2
+
+.fixed_conn WRPNTR2D_IOLOGIC DQSG_WRPNTR2
diff --git a/ECP5/tiledata/PICR1_DQS0/bits.db b/ECP5/tiledata/PICR1_DQS0/bits.db
index 8b13789..97bf59f 100644
--- a/ECP5/tiledata/PICR1_DQS0/bits.db
+++ b/ECP5/tiledata/PICR1_DQS0/bits.db
@@ -1 +1,349 @@
+# Routing Mux Bits
+# Non-Routing Configuration
+.config_enum PIOA.BASE_TYPE NONE
+BIDIR_BLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+BIDIR_HSUL12 F0B0 F2B0 F3B0 F4B0 F7B0
+BIDIR_HSUL12D F0B0 F2B0 F4B0 F7B0
+BIDIR_LVCMOS12 F0B0 F5B0 F7B0
+BIDIR_LVCMOS15 F0B0 !F7B0
+BIDIR_LVCMOS18 F0B0 !F7B0
+BIDIR_LVCMOS18D F0B0 F1B1 F2B0 F4B0 F7B0 F7B1 F7B4 F8B3
+BIDIR_LVCMOS25 F0B0 F6B0 F6B1 F7B0
+BIDIR_LVCMOS25D F0B0 F2B0 F4B0 F7B0 F8B3
+BIDIR_LVCMOS33 F0B0 F3B1 F4B1 F5B0 F5B1 F6B0 F6B1 F7B0
+BIDIR_LVCMOS33D F0B0 F0B3 F1B3 F2B0 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F9B4
+BIDIR_LVDS F0B0 F1B1 F2B0 F4B0 F7B0 F7B1 F7B4 F8B3
+BIDIR_LVTTL33 F0B0 F3B1 F4B1 F5B0 F5B1 F6B0 F6B1 F7B0
+BIDIR_MLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+BIDIR_SSTL135D_I F0B0 F0B3 F2B0 F4B0 F4B1 F7B0 F8B3
+BIDIR_SSTL135D_II F0B0 F2B0 F3B1 F4B0 F7B0 F8B3 F8B4
+BIDIR_SSTL135_I F0B0 F2B0 F3B0 F4B0 F4B1 F7B0
+BIDIR_SSTL135_II F0B0 F2B0 F3B0 F3B1 F4B0 F7B0
+BIDIR_SSTL15D_I F0B0 F0B3 F2B0 F4B0 F4B1 F7B0 F8B3
+BIDIR_SSTL15D_II F0B0 F2B0 F3B1 F4B0 F7B0 F8B3 F8B4
+BIDIR_SSTL15_I F0B0 F2B0 F3B0 F4B0 F4B1 F7B0
+BIDIR_SSTL15_II F0B0 F2B0 F3B0 F3B1 F4B0 F7B0
+BIDIR_SSTL18D_I F0B0 F2B0 F4B0 F7B0 F8B3
+BIDIR_SSTL18D_II F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+BIDIR_SSTL18_I F0B0 F2B0 F3B0 F4B0 F7B0
+BIDIR_SSTL18_II F0B0 F2B0 F2B1 F3B0 F3B1 F4B0 F4B1 F5B1 F7B0
+INPUT_BLVDS25 F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_HSUL12 F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_HSUL12D F0B0 F2B0 F4B0 F7B0
+INPUT_LVCMOS12 F0B0 F5B0 F7B0
+INPUT_LVCMOS15 F0B0 !F7B0
+INPUT_LVCMOS18 F0B0 !F7B0
+INPUT_LVCMOS18D F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_LVCMOS25 F0B0 F6B0 F6B1 F7B0
+INPUT_LVCMOS25D F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_LVCMOS33 F0B0 F5B0 F6B0 F6B1 F7B0
+INPUT_LVCMOS33D F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_LVDS F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_LVPECL33 F0B0 F2B0 F4B0 F7B0
+INPUT_LVTTL33 F0B0 F5B0 F6B0 F6B1 F7B0
+INPUT_MLVDS25 F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SLVS F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL135D_I F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL135D_II F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL135_I F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SSTL135_II F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SSTL15D_I F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL15D_II F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL15_I F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SSTL15_II F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SSTL18D_I F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL18D_II F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL18_I F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SSTL18_II F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SUBLVDS F0B0 F2B0 F4B0 F7B0 F8B3
+NONE F7B0
+OUTPUT_BLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+OUTPUT_HSUL12 F0B0 F2B0 F7B0
+OUTPUT_HSUL12D F0B0 F2B0 F7B0
+OUTPUT_LVCMOS12 F0B0 F2B0 F7B0
+OUTPUT_LVCMOS15 F0B0 F2B0 F7B0
+OUTPUT_LVCMOS18 F0B0 F2B0 F7B0
+OUTPUT_LVCMOS18D F0B0 F1B1 F2B0 F7B0 F7B1 F7B4 F8B3
+OUTPUT_LVCMOS25 F0B0 F2B0 F7B0
+OUTPUT_LVCMOS25D F0B0 F2B0 F7B0 F8B3
+OUTPUT_LVCMOS33 F0B0 F2B0 F3B1 F4B1 F5B1 F7B0
+OUTPUT_LVCMOS33D F0B0 F0B3 F1B3 F2B0 F3B1 F4B1 F5B1 F7B0 F8B3 F9B4
+OUTPUT_LVDS F0B0 F1B1 F2B0 F7B0 F7B1 F7B4 F8B3
+OUTPUT_LVDS25E F0B0 F2B0 F7B0 F8B3
+OUTPUT_LVPECL33E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+OUTPUT_LVTTL33 F0B0 F2B0 F3B1 F4B1 F5B1 F7B0
+OUTPUT_MLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+OUTPUT_SSTL135D_I F0B0 F0B3 F2B0 F4B1 F7B0 F8B3
+OUTPUT_SSTL135D_II F0B0 F2B0 F3B1 F7B0 F8B3 F8B4
+OUTPUT_SSTL135_I F0B0 F2B0 F4B1 F7B0
+OUTPUT_SSTL135_II F0B0 F2B0 F3B1 F7B0
+OUTPUT_SSTL15D_I F0B0 F0B3 F2B0 F4B1 F7B0 F8B3
+OUTPUT_SSTL15D_II F0B0 F2B0 F3B1 F7B0 F8B3 F8B4
+OUTPUT_SSTL15_I F0B0 F2B0 F4B1 F7B0
+OUTPUT_SSTL15_II F0B0 F2B0 F3B1 F7B0
+OUTPUT_SSTL18D_I F0B0 F2B0 F7B0 F8B3
+OUTPUT_SSTL18D_II F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+OUTPUT_SSTL18_I F0B0 F2B0 F7B0
+OUTPUT_SSTL18_II F0B0 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0
+
+.config_enum PIOA.DRIVE
+12 !F1B1 F2B1 !F3B1 !F4B1 !F5B1
+16 !F1B1 F2B1 F3B1 F4B1 F5B1
+4 F1B1 F2B1 F3B1 !F4B1 !F5B1
+8 !F1B1 !F2B1 F3B1 F4B1 F5B1
+
+.config_enum PIOA.HYSTERESIS OFF
+OFF !F6B1
+ON F6B1
+
+.config_enum PIOA.OPENDRAIN
+OFF F3B1 F4B1 !F4B2 F5B1
+ON !F3B1 F4B2 !F4B1 !F5B1
+
+.config_enum PIOA.PULLMODE DOWN
+DOWN !F1B0 !F2B0
+NONE !F1B0 F2B0
+UP F1B0 F2B0
+
+.config_enum PIOA.SLEWRATE SLOW
+FAST F5B2
+SLOW !F5B2
+
+.config_enum PIOB.BASE_TYPE NONE
+BIDIR_HSUL12 F0B2 F3B2 F6B3 F8B3 F9B3
+BIDIR_LVCMOS12 F1B2 F3B2 F6B3
+BIDIR_LVCMOS15 !F3B2 F6B3
+BIDIR_LVCMOS18 !F3B2 F6B3
+BIDIR_LVCMOS25 F2B2 F2B3 F3B2 F6B3
+BIDIR_LVCMOS33 F0B3 F1B2 F1B3 F2B2 F2B3 F3B2 F6B3 F9B4
+BIDIR_LVTTL33 F0B3 F1B2 F1B3 F2B2 F2B3 F3B2 F6B3 F9B4
+BIDIR_SSTL135_I F0B2 F0B3 F3B2 F6B3 F8B3 F9B3
+BIDIR_SSTL135_II F0B2 F3B2 F6B3 F8B3 F9B3 F9B4
+BIDIR_SSTL15_I F0B2 F0B3 F3B2 F6B3 F8B3 F9B3
+BIDIR_SSTL15_II F0B2 F3B2 F6B3 F8B3 F9B3 F9B4
+BIDIR_SSTL18_I F0B2 F3B2 F6B3 F8B3 F9B3
+BIDIR_SSTL18_II F0B2 F0B3 F1B3 F3B2 F6B3 F8B3 F8B4 F9B3 F9B4
+INPUT_HSUL12 F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_LVCMOS12 F1B2 F3B2 F6B3
+INPUT_LVCMOS15 !F3B2 F6B3
+INPUT_LVCMOS18 !F3B2 F6B3
+INPUT_LVCMOS25 F2B2 F2B3 F3B2 F6B3
+INPUT_LVCMOS33 F1B2 F2B2 F2B3 F3B2 F6B3
+INPUT_LVTTL33 F1B2 F2B2 F2B3 F3B2 F6B3
+INPUT_SSTL135_I F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_SSTL135_II F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_SSTL15_I F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_SSTL15_II F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_SSTL18_I F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_SSTL18_II F0B2 F3B2 F6B3 F8B3 F9B3
+NONE F3B2
+OUTPUT_HSUL12 F3B2 F6B3 F8B3
+OUTPUT_LVCMOS12 F3B2 F6B3 F8B3
+OUTPUT_LVCMOS15 F3B2 F6B3 F8B3
+OUTPUT_LVCMOS18 F3B2 F6B3 F8B3
+OUTPUT_LVCMOS25 F3B2 F6B3 F8B3
+OUTPUT_LVCMOS33 F0B3 F1B3 F3B2 F6B3 F8B3 F9B4
+OUTPUT_LVTTL33 F0B3 F1B3 F3B2 F6B3 F8B3 F9B4
+OUTPUT_SSTL135_I F0B3 F3B2 F6B3 F8B3
+OUTPUT_SSTL135_II F3B2 F6B3 F8B3 F9B4
+OUTPUT_SSTL15_I F0B3 F3B2 F6B3 F8B3
+OUTPUT_SSTL15_II F3B2 F6B3 F8B3 F9B4
+OUTPUT_SSTL18_I F3B2 F6B3 F8B3
+OUTPUT_SSTL18_II F0B3 F1B3 F3B2 F6B3 F8B3 F8B4 F9B4
+
+.config_enum PIOB.DRIVE
+12 !F0B3 !F1B3 !F7B4 F8B4 !F9B4
+16 F0B3 F1B3 !F7B4 F8B4 F9B4
+4 !F0B3 !F1B3 F7B4 F8B4 F9B4
+8 F0B3 F1B3 !F7B4 !F8B4 F9B4
+
+.config_enum PIOB.HYSTERESIS OFF
+OFF !F2B3
+ON F2B3
+
+.config_enum PIOB.OPENDRAIN
+OFF F0B3 !F0B4 F1B3 F9B4
+ON F0B4 !F0B3 !F1B3 !F9B4
+
+.config_enum PIOB.PULLMODE DOWN
+DOWN !F7B3 !F8B3
+NONE !F7B3 F8B3
+UP F7B3 F8B3
+
+.config_enum PIOB.SLEWRATE SLOW
+FAST F1B4
+SLOW !F1B4
+
+.config_enum PIOC.BASE_TYPE NONE
+BIDIR_BLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B5 F6B6 F7B6 F9B5
+BIDIR_HSUL12 F2B5 F4B5 F5B5 F6B5 F9B5
+BIDIR_HSUL12D F2B5 F4B5 F6B5 F9B5
+BIDIR_LVCMOS12 F2B5 F7B5 F9B5
+BIDIR_LVCMOS15 F2B5 !F9B5
+BIDIR_LVCMOS18 F2B5 !F9B5
+BIDIR_LVCMOS25 F2B5 F8B5 F8B6 F9B5
+BIDIR_LVCMOS25D F0B7 F2B5 F4B5 F6B5 F9B5
+BIDIR_LVCMOS33 F2B5 F5B6 F6B6 F7B5 F7B6 F8B5 F8B6 F9B5
+BIDIR_LVCMOS33D F0B7 F1B8 F2B5 F2B8 F3B8 F4B5 F5B6 F6B5 F6B6 F7B6 F9B5
+BIDIR_LVTTL33 F2B5 F5B6 F6B6 F7B5 F7B6 F8B5 F8B6 F9B5
+BIDIR_MLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B5 F6B6 F7B6 F9B5
+BIDIR_SSTL135D_I F0B7 F2B5 F2B8 F4B5 F6B5 F6B6 F9B5
+BIDIR_SSTL135D_II F0B7 F0B8 F2B5 F4B5 F5B6 F6B5 F9B5
+BIDIR_SSTL135_I F2B5 F4B5 F5B5 F6B5 F6B6 F9B5
+BIDIR_SSTL135_II F2B5 F4B5 F5B5 F5B6 F6B5 F9B5
+BIDIR_SSTL15D_I F0B7 F2B5 F2B8 F4B5 F6B5 F6B6 F9B5
+BIDIR_SSTL15D_II F0B7 F0B8 F2B5 F4B5 F5B6 F6B5 F9B5
+BIDIR_SSTL15_I F2B5 F4B5 F5B5 F6B5 F6B6 F9B5
+BIDIR_SSTL15_II F2B5 F4B5 F5B5 F5B6 F6B5 F9B5
+BIDIR_SSTL18D_I F0B7 F2B5 F4B5 F6B5 F9B5
+BIDIR_SSTL18D_II F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B5 F6B6 F7B6 F9B5
+BIDIR_SSTL18_I F2B5 F4B5 F5B5 F6B5 F9B5
+BIDIR_SSTL18_II F2B5 F4B5 F4B6 F5B5 F5B6 F6B5 F6B6 F7B6 F9B5
+INPUT_BLVDS25 F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_HSUL12 F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_HSUL12D F2B5 F4B5 F6B5 F9B5
+INPUT_LVCMOS12 F2B5 F7B5 F9B5
+INPUT_LVCMOS15 F2B5 !F9B5
+INPUT_LVCMOS18 F2B5 !F9B5
+INPUT_LVCMOS18D F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_LVCMOS25 F2B5 F8B5 F8B6 F9B5
+INPUT_LVCMOS25D F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_LVCMOS33 F2B5 F7B5 F8B5 F8B6 F9B5
+INPUT_LVCMOS33D F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_LVDS F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_LVPECL33 F2B5 F4B5 F6B5 F9B5
+INPUT_LVTTL33 F2B5 F7B5 F8B5 F8B6 F9B5
+INPUT_MLVDS25 F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SLVS F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL135D_I F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL135D_II F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL135_I F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SSTL135_II F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SSTL15D_I F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL15D_II F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL15_I F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SSTL15_II F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SSTL18D_I F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL18D_II F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL18_I F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SSTL18_II F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SUBLVDS F0B7 F2B5 F4B5 F6B5 F9B5
+NONE F9B5
+OUTPUT_BLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
+OUTPUT_HSUL12 F2B5 F4B5 F9B5
+OUTPUT_HSUL12D F2B5 F4B5 F9B5
+OUTPUT_LVCMOS12 F2B5 F4B5 F9B5
+OUTPUT_LVCMOS15 F2B5 F4B5 F9B5
+OUTPUT_LVCMOS18 F2B5 F4B5 F9B5
+OUTPUT_LVCMOS25 F2B5 F4B5 F9B5
+OUTPUT_LVCMOS25D F0B7 F2B5 F4B5 F9B5
+OUTPUT_LVCMOS33 F2B5 F4B5 F5B6 F6B6 F7B6 F9B5
+OUTPUT_LVCMOS33D F0B7 F1B8 F2B5 F2B8 F3B8 F4B5 F5B6 F6B6 F7B6 F9B5
+OUTPUT_LVDS25E F0B7 F2B5 F4B5 F9B5
+OUTPUT_LVPECL33E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
+OUTPUT_LVTTL33 F2B5 F4B5 F5B6 F6B6 F7B6 F9B5
+OUTPUT_MLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
+OUTPUT_SSTL135D_I F0B7 F2B5 F2B8 F4B5 F6B6 F9B5
+OUTPUT_SSTL135D_II F0B7 F0B8 F2B5 F4B5 F5B6 F9B5
+OUTPUT_SSTL135_I F2B5 F4B5 F6B6 F9B5
+OUTPUT_SSTL135_II F2B5 F4B5 F5B6 F9B5
+OUTPUT_SSTL15D_I F0B7 F2B5 F2B8 F4B5 F6B6 F9B5
+OUTPUT_SSTL15D_II F0B7 F0B8 F2B5 F4B5 F5B6 F9B5
+OUTPUT_SSTL15_I F2B5 F4B5 F6B6 F9B5
+OUTPUT_SSTL15_II F2B5 F4B5 F5B6 F9B5
+OUTPUT_SSTL18D_I F0B7 F2B5 F4B5 F9B5
+OUTPUT_SSTL18D_II F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
+OUTPUT_SSTL18_I F2B5 F4B5 F9B5
+OUTPUT_SSTL18_II F2B5 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
+
+.config_enum PIOC.DRIVE
+12 !F3B6 F4B6 !F5B6 !F6B6 !F7B6
+16 !F3B6 F4B6 F5B6 F6B6 F7B6
+4 F3B6 F4B6 F5B6 !F6B6 !F7B6
+8 !F3B6 !F4B6 F5B6 F6B6 F7B6
+
+.config_enum PIOC.HYSTERESIS OFF
+OFF !F8B6
+ON F8B6
+
+.config_enum PIOC.OPENDRAIN
+OFF F5B6 F6B6 !F6B7 F7B6
+ON !F5B6 F6B7 !F6B6 !F7B6
+
+.config_enum PIOC.PULLMODE DOWN
+DOWN !F3B5 !F4B5
+NONE !F3B5 F4B5
+UP F3B5 F4B5
+
+.config_enum PIOC.SLEWRATE SLOW
+FAST F7B7
+SLOW !F7B7
+
+.config_enum PIOD.BASE_TYPE NONE
+BIDIR_HSUL12 F0B7 F1B7 F2B7 F5B7 F8B8
+BIDIR_LVCMOS12 F3B7 F5B7 F8B8
+BIDIR_LVCMOS15 !F5B7 F8B8
+BIDIR_LVCMOS18 !F5B7 F8B8
+BIDIR_LVCMOS25 F4B7 F4B8 F5B7 F8B8
+BIDIR_LVCMOS33 F1B8 F2B8 F3B7 F3B8 F4B7 F4B8 F5B7 F8B8
+BIDIR_LVTTL33 F1B8 F2B8 F3B7 F3B8 F4B7 F4B8 F5B7 F8B8
+BIDIR_SSTL135_I F0B7 F1B7 F2B7 F2B8 F5B7 F8B8
+BIDIR_SSTL135_II F0B7 F1B7 F1B8 F2B7 F5B7 F8B8
+BIDIR_SSTL15_I F0B7 F1B7 F2B7 F2B8 F5B7 F8B8
+BIDIR_SSTL15_II F0B7 F1B7 F1B8 F2B7 F5B7 F8B8
+BIDIR_SSTL18_I F0B7 F1B7 F2B7 F5B7 F8B8
+BIDIR_SSTL18_II F0B7 F0B8 F1B7 F1B8 F2B7 F2B8 F3B8 F5B7 F8B8
+INPUT_HSUL12 F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_LVCMOS12 F3B7 F5B7 F8B8
+INPUT_LVCMOS15 !F5B7 F8B8
+INPUT_LVCMOS18 !F5B7 F8B8
+INPUT_LVCMOS25 F4B7 F4B8 F5B7 F8B8
+INPUT_LVCMOS33 F3B7 F4B7 F4B8 F5B7 F8B8
+INPUT_LVTTL33 F3B7 F4B7 F4B8 F5B7 F8B8
+INPUT_SSTL135_I F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_SSTL135_II F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_SSTL15_I F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_SSTL15_II F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_SSTL18_I F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_SSTL18_II F0B7 F1B7 F2B7 F5B7 F8B8
+NONE F5B7
+OUTPUT_HSUL12 F0B7 F5B7 F8B8
+OUTPUT_LVCMOS12 F0B7 F5B7 F8B8
+OUTPUT_LVCMOS15 F0B7 F5B7 F8B8
+OUTPUT_LVCMOS18 F0B7 F5B7 F8B8
+OUTPUT_LVCMOS25 F0B7 F5B7 F8B8
+OUTPUT_LVCMOS33 F0B7 F1B8 F2B8 F3B8 F5B7 F8B8
+OUTPUT_LVTTL33 F0B7 F1B8 F2B8 F3B8 F5B7 F8B8
+OUTPUT_SSTL135_I F0B7 F2B8 F5B7 F8B8
+OUTPUT_SSTL135_II F0B7 F1B8 F5B7 F8B8
+OUTPUT_SSTL15_I F0B7 F2B8 F5B7 F8B8
+OUTPUT_SSTL15_II F0B7 F1B8 F5B7 F8B8
+OUTPUT_SSTL18_I F0B7 F5B7 F8B8
+OUTPUT_SSTL18_II F0B7 F0B8 F1B8 F2B8 F3B8 F5B7 F8B8
+
+.config_enum PIOD.DRIVE
+12 F0B8 !F1B8 !F2B8 !F3B8 !F9B9
+16 F0B8 F1B8 F2B8 F3B8 !F9B9
+4 F0B8 F1B8 !F2B8 !F3B8 F9B9
+8 !F0B8 F1B8 F2B8 F3B8 !F9B9
+
+.config_enum PIOD.HYSTERESIS OFF
+OFF !F4B8
+ON F4B8
+
+.config_enum PIOD.OPENDRAIN
+OFF F1B8 F2B8 !F2B9 F3B8
+ON !F1B8 !F2B8 F2B9 !F3B8
+
+.config_enum PIOD.PULLMODE DOWN
+DOWN !F0B7 !F9B8
+NONE F0B7 !F9B8
+UP F0B7 F9B8
+
+.config_enum PIOD.SLEWRATE SLOW
+FAST F3B9
+SLOW !F3B9
+
+
+# Fixed Connections
diff --git a/ECP5/tiledata/PICR1_DQS3/bits.db b/ECP5/tiledata/PICR1_DQS3/bits.db
index 8b13789..97bf59f 100644
--- a/ECP5/tiledata/PICR1_DQS3/bits.db
+++ b/ECP5/tiledata/PICR1_DQS3/bits.db
@@ -1 +1,349 @@
+# Routing Mux Bits
+# Non-Routing Configuration
+.config_enum PIOA.BASE_TYPE NONE
+BIDIR_BLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+BIDIR_HSUL12 F0B0 F2B0 F3B0 F4B0 F7B0
+BIDIR_HSUL12D F0B0 F2B0 F4B0 F7B0
+BIDIR_LVCMOS12 F0B0 F5B0 F7B0
+BIDIR_LVCMOS15 F0B0 !F7B0
+BIDIR_LVCMOS18 F0B0 !F7B0
+BIDIR_LVCMOS18D F0B0 F1B1 F2B0 F4B0 F7B0 F7B1 F7B4 F8B3
+BIDIR_LVCMOS25 F0B0 F6B0 F6B1 F7B0
+BIDIR_LVCMOS25D F0B0 F2B0 F4B0 F7B0 F8B3
+BIDIR_LVCMOS33 F0B0 F3B1 F4B1 F5B0 F5B1 F6B0 F6B1 F7B0
+BIDIR_LVCMOS33D F0B0 F0B3 F1B3 F2B0 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F9B4
+BIDIR_LVDS F0B0 F1B1 F2B0 F4B0 F7B0 F7B1 F7B4 F8B3
+BIDIR_LVTTL33 F0B0 F3B1 F4B1 F5B0 F5B1 F6B0 F6B1 F7B0
+BIDIR_MLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+BIDIR_SSTL135D_I F0B0 F0B3 F2B0 F4B0 F4B1 F7B0 F8B3
+BIDIR_SSTL135D_II F0B0 F2B0 F3B1 F4B0 F7B0 F8B3 F8B4
+BIDIR_SSTL135_I F0B0 F2B0 F3B0 F4B0 F4B1 F7B0
+BIDIR_SSTL135_II F0B0 F2B0 F3B0 F3B1 F4B0 F7B0
+BIDIR_SSTL15D_I F0B0 F0B3 F2B0 F4B0 F4B1 F7B0 F8B3
+BIDIR_SSTL15D_II F0B0 F2B0 F3B1 F4B0 F7B0 F8B3 F8B4
+BIDIR_SSTL15_I F0B0 F2B0 F3B0 F4B0 F4B1 F7B0
+BIDIR_SSTL15_II F0B0 F2B0 F3B0 F3B1 F4B0 F7B0
+BIDIR_SSTL18D_I F0B0 F2B0 F4B0 F7B0 F8B3
+BIDIR_SSTL18D_II F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+BIDIR_SSTL18_I F0B0 F2B0 F3B0 F4B0 F7B0
+BIDIR_SSTL18_II F0B0 F2B0 F2B1 F3B0 F3B1 F4B0 F4B1 F5B1 F7B0
+INPUT_BLVDS25 F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_HSUL12 F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_HSUL12D F0B0 F2B0 F4B0 F7B0
+INPUT_LVCMOS12 F0B0 F5B0 F7B0
+INPUT_LVCMOS15 F0B0 !F7B0
+INPUT_LVCMOS18 F0B0 !F7B0
+INPUT_LVCMOS18D F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_LVCMOS25 F0B0 F6B0 F6B1 F7B0
+INPUT_LVCMOS25D F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_LVCMOS33 F0B0 F5B0 F6B0 F6B1 F7B0
+INPUT_LVCMOS33D F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_LVDS F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_LVPECL33 F0B0 F2B0 F4B0 F7B0
+INPUT_LVTTL33 F0B0 F5B0 F6B0 F6B1 F7B0
+INPUT_MLVDS25 F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SLVS F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL135D_I F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL135D_II F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL135_I F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SSTL135_II F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SSTL15D_I F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL15D_II F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL15_I F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SSTL15_II F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SSTL18D_I F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL18D_II F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL18_I F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SSTL18_II F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SUBLVDS F0B0 F2B0 F4B0 F7B0 F8B3
+NONE F7B0
+OUTPUT_BLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+OUTPUT_HSUL12 F0B0 F2B0 F7B0
+OUTPUT_HSUL12D F0B0 F2B0 F7B0
+OUTPUT_LVCMOS12 F0B0 F2B0 F7B0
+OUTPUT_LVCMOS15 F0B0 F2B0 F7B0
+OUTPUT_LVCMOS18 F0B0 F2B0 F7B0
+OUTPUT_LVCMOS18D F0B0 F1B1 F2B0 F7B0 F7B1 F7B4 F8B3
+OUTPUT_LVCMOS25 F0B0 F2B0 F7B0
+OUTPUT_LVCMOS25D F0B0 F2B0 F7B0 F8B3
+OUTPUT_LVCMOS33 F0B0 F2B0 F3B1 F4B1 F5B1 F7B0
+OUTPUT_LVCMOS33D F0B0 F0B3 F1B3 F2B0 F3B1 F4B1 F5B1 F7B0 F8B3 F9B4
+OUTPUT_LVDS F0B0 F1B1 F2B0 F7B0 F7B1 F7B4 F8B3
+OUTPUT_LVDS25E F0B0 F2B0 F7B0 F8B3
+OUTPUT_LVPECL33E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+OUTPUT_LVTTL33 F0B0 F2B0 F3B1 F4B1 F5B1 F7B0
+OUTPUT_MLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+OUTPUT_SSTL135D_I F0B0 F0B3 F2B0 F4B1 F7B0 F8B3
+OUTPUT_SSTL135D_II F0B0 F2B0 F3B1 F7B0 F8B3 F8B4
+OUTPUT_SSTL135_I F0B0 F2B0 F4B1 F7B0
+OUTPUT_SSTL135_II F0B0 F2B0 F3B1 F7B0
+OUTPUT_SSTL15D_I F0B0 F0B3 F2B0 F4B1 F7B0 F8B3
+OUTPUT_SSTL15D_II F0B0 F2B0 F3B1 F7B0 F8B3 F8B4
+OUTPUT_SSTL15_I F0B0 F2B0 F4B1 F7B0
+OUTPUT_SSTL15_II F0B0 F2B0 F3B1 F7B0
+OUTPUT_SSTL18D_I F0B0 F2B0 F7B0 F8B3
+OUTPUT_SSTL18D_II F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+OUTPUT_SSTL18_I F0B0 F2B0 F7B0
+OUTPUT_SSTL18_II F0B0 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0
+
+.config_enum PIOA.DRIVE
+12 !F1B1 F2B1 !F3B1 !F4B1 !F5B1
+16 !F1B1 F2B1 F3B1 F4B1 F5B1
+4 F1B1 F2B1 F3B1 !F4B1 !F5B1
+8 !F1B1 !F2B1 F3B1 F4B1 F5B1
+
+.config_enum PIOA.HYSTERESIS OFF
+OFF !F6B1
+ON F6B1
+
+.config_enum PIOA.OPENDRAIN
+OFF F3B1 F4B1 !F4B2 F5B1
+ON !F3B1 F4B2 !F4B1 !F5B1
+
+.config_enum PIOA.PULLMODE DOWN
+DOWN !F1B0 !F2B0
+NONE !F1B0 F2B0
+UP F1B0 F2B0
+
+.config_enum PIOA.SLEWRATE SLOW
+FAST F5B2
+SLOW !F5B2
+
+.config_enum PIOB.BASE_TYPE NONE
+BIDIR_HSUL12 F0B2 F3B2 F6B3 F8B3 F9B3
+BIDIR_LVCMOS12 F1B2 F3B2 F6B3
+BIDIR_LVCMOS15 !F3B2 F6B3
+BIDIR_LVCMOS18 !F3B2 F6B3
+BIDIR_LVCMOS25 F2B2 F2B3 F3B2 F6B3
+BIDIR_LVCMOS33 F0B3 F1B2 F1B3 F2B2 F2B3 F3B2 F6B3 F9B4
+BIDIR_LVTTL33 F0B3 F1B2 F1B3 F2B2 F2B3 F3B2 F6B3 F9B4
+BIDIR_SSTL135_I F0B2 F0B3 F3B2 F6B3 F8B3 F9B3
+BIDIR_SSTL135_II F0B2 F3B2 F6B3 F8B3 F9B3 F9B4
+BIDIR_SSTL15_I F0B2 F0B3 F3B2 F6B3 F8B3 F9B3
+BIDIR_SSTL15_II F0B2 F3B2 F6B3 F8B3 F9B3 F9B4
+BIDIR_SSTL18_I F0B2 F3B2 F6B3 F8B3 F9B3
+BIDIR_SSTL18_II F0B2 F0B3 F1B3 F3B2 F6B3 F8B3 F8B4 F9B3 F9B4
+INPUT_HSUL12 F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_LVCMOS12 F1B2 F3B2 F6B3
+INPUT_LVCMOS15 !F3B2 F6B3
+INPUT_LVCMOS18 !F3B2 F6B3
+INPUT_LVCMOS25 F2B2 F2B3 F3B2 F6B3
+INPUT_LVCMOS33 F1B2 F2B2 F2B3 F3B2 F6B3
+INPUT_LVTTL33 F1B2 F2B2 F2B3 F3B2 F6B3
+INPUT_SSTL135_I F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_SSTL135_II F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_SSTL15_I F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_SSTL15_II F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_SSTL18_I F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_SSTL18_II F0B2 F3B2 F6B3 F8B3 F9B3
+NONE F3B2
+OUTPUT_HSUL12 F3B2 F6B3 F8B3
+OUTPUT_LVCMOS12 F3B2 F6B3 F8B3
+OUTPUT_LVCMOS15 F3B2 F6B3 F8B3
+OUTPUT_LVCMOS18 F3B2 F6B3 F8B3
+OUTPUT_LVCMOS25 F3B2 F6B3 F8B3
+OUTPUT_LVCMOS33 F0B3 F1B3 F3B2 F6B3 F8B3 F9B4
+OUTPUT_LVTTL33 F0B3 F1B3 F3B2 F6B3 F8B3 F9B4
+OUTPUT_SSTL135_I F0B3 F3B2 F6B3 F8B3
+OUTPUT_SSTL135_II F3B2 F6B3 F8B3 F9B4
+OUTPUT_SSTL15_I F0B3 F3B2 F6B3 F8B3
+OUTPUT_SSTL15_II F3B2 F6B3 F8B3 F9B4
+OUTPUT_SSTL18_I F3B2 F6B3 F8B3
+OUTPUT_SSTL18_II F0B3 F1B3 F3B2 F6B3 F8B3 F8B4 F9B4
+
+.config_enum PIOB.DRIVE
+12 !F0B3 !F1B3 !F7B4 F8B4 !F9B4
+16 F0B3 F1B3 !F7B4 F8B4 F9B4
+4 !F0B3 !F1B3 F7B4 F8B4 F9B4
+8 F0B3 F1B3 !F7B4 !F8B4 F9B4
+
+.config_enum PIOB.HYSTERESIS OFF
+OFF !F2B3
+ON F2B3
+
+.config_enum PIOB.OPENDRAIN
+OFF F0B3 !F0B4 F1B3 F9B4
+ON F0B4 !F0B3 !F1B3 !F9B4
+
+.config_enum PIOB.PULLMODE DOWN
+DOWN !F7B3 !F8B3
+NONE !F7B3 F8B3
+UP F7B3 F8B3
+
+.config_enum PIOB.SLEWRATE SLOW
+FAST F1B4
+SLOW !F1B4
+
+.config_enum PIOC.BASE_TYPE NONE
+BIDIR_BLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B5 F6B6 F7B6 F9B5
+BIDIR_HSUL12 F2B5 F4B5 F5B5 F6B5 F9B5
+BIDIR_HSUL12D F2B5 F4B5 F6B5 F9B5
+BIDIR_LVCMOS12 F2B5 F7B5 F9B5
+BIDIR_LVCMOS15 F2B5 !F9B5
+BIDIR_LVCMOS18 F2B5 !F9B5
+BIDIR_LVCMOS25 F2B5 F8B5 F8B6 F9B5
+BIDIR_LVCMOS25D F0B7 F2B5 F4B5 F6B5 F9B5
+BIDIR_LVCMOS33 F2B5 F5B6 F6B6 F7B5 F7B6 F8B5 F8B6 F9B5
+BIDIR_LVCMOS33D F0B7 F1B8 F2B5 F2B8 F3B8 F4B5 F5B6 F6B5 F6B6 F7B6 F9B5
+BIDIR_LVTTL33 F2B5 F5B6 F6B6 F7B5 F7B6 F8B5 F8B6 F9B5
+BIDIR_MLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B5 F6B6 F7B6 F9B5
+BIDIR_SSTL135D_I F0B7 F2B5 F2B8 F4B5 F6B5 F6B6 F9B5
+BIDIR_SSTL135D_II F0B7 F0B8 F2B5 F4B5 F5B6 F6B5 F9B5
+BIDIR_SSTL135_I F2B5 F4B5 F5B5 F6B5 F6B6 F9B5
+BIDIR_SSTL135_II F2B5 F4B5 F5B5 F5B6 F6B5 F9B5
+BIDIR_SSTL15D_I F0B7 F2B5 F2B8 F4B5 F6B5 F6B6 F9B5
+BIDIR_SSTL15D_II F0B7 F0B8 F2B5 F4B5 F5B6 F6B5 F9B5
+BIDIR_SSTL15_I F2B5 F4B5 F5B5 F6B5 F6B6 F9B5
+BIDIR_SSTL15_II F2B5 F4B5 F5B5 F5B6 F6B5 F9B5
+BIDIR_SSTL18D_I F0B7 F2B5 F4B5 F6B5 F9B5
+BIDIR_SSTL18D_II F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B5 F6B6 F7B6 F9B5
+BIDIR_SSTL18_I F2B5 F4B5 F5B5 F6B5 F9B5
+BIDIR_SSTL18_II F2B5 F4B5 F4B6 F5B5 F5B6 F6B5 F6B6 F7B6 F9B5
+INPUT_BLVDS25 F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_HSUL12 F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_HSUL12D F2B5 F4B5 F6B5 F9B5
+INPUT_LVCMOS12 F2B5 F7B5 F9B5
+INPUT_LVCMOS15 F2B5 !F9B5
+INPUT_LVCMOS18 F2B5 !F9B5
+INPUT_LVCMOS18D F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_LVCMOS25 F2B5 F8B5 F8B6 F9B5
+INPUT_LVCMOS25D F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_LVCMOS33 F2B5 F7B5 F8B5 F8B6 F9B5
+INPUT_LVCMOS33D F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_LVDS F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_LVPECL33 F2B5 F4B5 F6B5 F9B5
+INPUT_LVTTL33 F2B5 F7B5 F8B5 F8B6 F9B5
+INPUT_MLVDS25 F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SLVS F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL135D_I F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL135D_II F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL135_I F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SSTL135_II F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SSTL15D_I F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL15D_II F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL15_I F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SSTL15_II F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SSTL18D_I F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL18D_II F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL18_I F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SSTL18_II F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SUBLVDS F0B7 F2B5 F4B5 F6B5 F9B5
+NONE F9B5
+OUTPUT_BLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
+OUTPUT_HSUL12 F2B5 F4B5 F9B5
+OUTPUT_HSUL12D F2B5 F4B5 F9B5
+OUTPUT_LVCMOS12 F2B5 F4B5 F9B5
+OUTPUT_LVCMOS15 F2B5 F4B5 F9B5
+OUTPUT_LVCMOS18 F2B5 F4B5 F9B5
+OUTPUT_LVCMOS25 F2B5 F4B5 F9B5
+OUTPUT_LVCMOS25D F0B7 F2B5 F4B5 F9B5
+OUTPUT_LVCMOS33 F2B5 F4B5 F5B6 F6B6 F7B6 F9B5
+OUTPUT_LVCMOS33D F0B7 F1B8 F2B5 F2B8 F3B8 F4B5 F5B6 F6B6 F7B6 F9B5
+OUTPUT_LVDS25E F0B7 F2B5 F4B5 F9B5
+OUTPUT_LVPECL33E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
+OUTPUT_LVTTL33 F2B5 F4B5 F5B6 F6B6 F7B6 F9B5
+OUTPUT_MLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
+OUTPUT_SSTL135D_I F0B7 F2B5 F2B8 F4B5 F6B6 F9B5
+OUTPUT_SSTL135D_II F0B7 F0B8 F2B5 F4B5 F5B6 F9B5
+OUTPUT_SSTL135_I F2B5 F4B5 F6B6 F9B5
+OUTPUT_SSTL135_II F2B5 F4B5 F5B6 F9B5
+OUTPUT_SSTL15D_I F0B7 F2B5 F2B8 F4B5 F6B6 F9B5
+OUTPUT_SSTL15D_II F0B7 F0B8 F2B5 F4B5 F5B6 F9B5
+OUTPUT_SSTL15_I F2B5 F4B5 F6B6 F9B5
+OUTPUT_SSTL15_II F2B5 F4B5 F5B6 F9B5
+OUTPUT_SSTL18D_I F0B7 F2B5 F4B5 F9B5
+OUTPUT_SSTL18D_II F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
+OUTPUT_SSTL18_I F2B5 F4B5 F9B5
+OUTPUT_SSTL18_II F2B5 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
+
+.config_enum PIOC.DRIVE
+12 !F3B6 F4B6 !F5B6 !F6B6 !F7B6
+16 !F3B6 F4B6 F5B6 F6B6 F7B6
+4 F3B6 F4B6 F5B6 !F6B6 !F7B6
+8 !F3B6 !F4B6 F5B6 F6B6 F7B6
+
+.config_enum PIOC.HYSTERESIS OFF
+OFF !F8B6
+ON F8B6
+
+.config_enum PIOC.OPENDRAIN
+OFF F5B6 F6B6 !F6B7 F7B6
+ON !F5B6 F6B7 !F6B6 !F7B6
+
+.config_enum PIOC.PULLMODE DOWN
+DOWN !F3B5 !F4B5
+NONE !F3B5 F4B5
+UP F3B5 F4B5
+
+.config_enum PIOC.SLEWRATE SLOW
+FAST F7B7
+SLOW !F7B7
+
+.config_enum PIOD.BASE_TYPE NONE
+BIDIR_HSUL12 F0B7 F1B7 F2B7 F5B7 F8B8
+BIDIR_LVCMOS12 F3B7 F5B7 F8B8
+BIDIR_LVCMOS15 !F5B7 F8B8
+BIDIR_LVCMOS18 !F5B7 F8B8
+BIDIR_LVCMOS25 F4B7 F4B8 F5B7 F8B8
+BIDIR_LVCMOS33 F1B8 F2B8 F3B7 F3B8 F4B7 F4B8 F5B7 F8B8
+BIDIR_LVTTL33 F1B8 F2B8 F3B7 F3B8 F4B7 F4B8 F5B7 F8B8
+BIDIR_SSTL135_I F0B7 F1B7 F2B7 F2B8 F5B7 F8B8
+BIDIR_SSTL135_II F0B7 F1B7 F1B8 F2B7 F5B7 F8B8
+BIDIR_SSTL15_I F0B7 F1B7 F2B7 F2B8 F5B7 F8B8
+BIDIR_SSTL15_II F0B7 F1B7 F1B8 F2B7 F5B7 F8B8
+BIDIR_SSTL18_I F0B7 F1B7 F2B7 F5B7 F8B8
+BIDIR_SSTL18_II F0B7 F0B8 F1B7 F1B8 F2B7 F2B8 F3B8 F5B7 F8B8
+INPUT_HSUL12 F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_LVCMOS12 F3B7 F5B7 F8B8
+INPUT_LVCMOS15 !F5B7 F8B8
+INPUT_LVCMOS18 !F5B7 F8B8
+INPUT_LVCMOS25 F4B7 F4B8 F5B7 F8B8
+INPUT_LVCMOS33 F3B7 F4B7 F4B8 F5B7 F8B8
+INPUT_LVTTL33 F3B7 F4B7 F4B8 F5B7 F8B8
+INPUT_SSTL135_I F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_SSTL135_II F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_SSTL15_I F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_SSTL15_II F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_SSTL18_I F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_SSTL18_II F0B7 F1B7 F2B7 F5B7 F8B8
+NONE F5B7
+OUTPUT_HSUL12 F0B7 F5B7 F8B8
+OUTPUT_LVCMOS12 F0B7 F5B7 F8B8
+OUTPUT_LVCMOS15 F0B7 F5B7 F8B8
+OUTPUT_LVCMOS18 F0B7 F5B7 F8B8
+OUTPUT_LVCMOS25 F0B7 F5B7 F8B8
+OUTPUT_LVCMOS33 F0B7 F1B8 F2B8 F3B8 F5B7 F8B8
+OUTPUT_LVTTL33 F0B7 F1B8 F2B8 F3B8 F5B7 F8B8
+OUTPUT_SSTL135_I F0B7 F2B8 F5B7 F8B8
+OUTPUT_SSTL135_II F0B7 F1B8 F5B7 F8B8
+OUTPUT_SSTL15_I F0B7 F2B8 F5B7 F8B8
+OUTPUT_SSTL15_II F0B7 F1B8 F5B7 F8B8
+OUTPUT_SSTL18_I F0B7 F5B7 F8B8
+OUTPUT_SSTL18_II F0B7 F0B8 F1B8 F2B8 F3B8 F5B7 F8B8
+
+.config_enum PIOD.DRIVE
+12 F0B8 !F1B8 !F2B8 !F3B8 !F9B9
+16 F0B8 F1B8 F2B8 F3B8 !F9B9
+4 F0B8 F1B8 !F2B8 !F3B8 F9B9
+8 !F0B8 F1B8 F2B8 F3B8 !F9B9
+
+.config_enum PIOD.HYSTERESIS OFF
+OFF !F4B8
+ON F4B8
+
+.config_enum PIOD.OPENDRAIN
+OFF F1B8 F2B8 !F2B9 F3B8
+ON !F1B8 !F2B8 F2B9 !F3B8
+
+.config_enum PIOD.PULLMODE DOWN
+DOWN !F0B7 !F9B8
+NONE F0B7 !F9B8
+UP F0B7 F9B8
+
+.config_enum PIOD.SLEWRATE SLOW
+FAST F3B9
+SLOW !F3B9
+
+
+# Fixed Connections
diff --git a/ECP5/tiledata/PICR2_DQS1/bits.db b/ECP5/tiledata/PICR2_DQS1/bits.db
index 8b13789..c486cf3 100644
--- a/ECP5/tiledata/PICR2_DQS1/bits.db
+++ b/ECP5/tiledata/PICR2_DQS1/bits.db
@@ -1 +1,141 @@
+# Routing Mux Bits
+.mux N2_ECLKC
+BNK_ECLK1 F5B1
+.mux N2_ECLKD
+BNK_ECLK1 F3B6
+
+.mux N2_JDIC
+N2_INDDC_IOLOGIC F1B1
+
+.mux N2_JDID
+N2_INDDD_IOLOGIC F9B7
+
+
+# Non-Routing Configuration
+.config_enum PIOC.BASE_TYPE INPUT_LVCMOS18D
+BIDIR_BLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_HSUL12 F7B4 F8B4
+BIDIR_HSUL12D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_LVCMOS12 F7B4 F8B4
+BIDIR_LVCMOS15 F7B4 F8B4
+BIDIR_LVCMOS18 F7B4 F8B4
+BIDIR_LVCMOS25 F7B4 F8B4
+BIDIR_LVCMOS25D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_LVCMOS33 F7B4 F8B4
+BIDIR_LVCMOS33D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_LVTTL33 F7B4 F8B4
+BIDIR_MLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL135D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL135D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL135_I F7B4 F8B4
+BIDIR_SSTL135_II F7B4 F8B4
+BIDIR_SSTL15D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL15D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL15_I F7B4 F8B4
+BIDIR_SSTL15_II F7B4 F8B4
+BIDIR_SSTL18D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL18D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL18_I F7B4 F8B4
+BIDIR_SSTL18_II F7B4 F8B4
+INPUT_BLVDS25
+INPUT_HSUL12
+INPUT_HSUL12D
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS18D
+INPUT_LVCMOS25
+INPUT_LVCMOS25D
+INPUT_LVCMOS33
+INPUT_LVCMOS33D
+INPUT_LVDS
+INPUT_LVPECL33
+INPUT_LVTTL33
+INPUT_MLVDS25
+INPUT_SLVS
+INPUT_SSTL135D_I
+INPUT_SSTL135D_II
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15D_I
+INPUT_SSTL15D_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18D_I
+INPUT_SSTL18D_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+INPUT_SUBLVDS
+NONE
+OUTPUT_BLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_HSUL12 F7B4 F8B4
+OUTPUT_HSUL12D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_LVCMOS12 F7B4 F8B4
+OUTPUT_LVCMOS15 F7B4 F8B4
+OUTPUT_LVCMOS18 F7B4 F8B4
+OUTPUT_LVCMOS25 F7B4 F8B4
+OUTPUT_LVCMOS25D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_LVCMOS33 F7B4 F8B4
+OUTPUT_LVCMOS33D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_LVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_LVPECL33E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_LVTTL33 F7B4 F8B4
+OUTPUT_MLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL135D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL135D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL135_I F7B4 F8B4
+OUTPUT_SSTL135_II F7B4 F8B4
+OUTPUT_SSTL15D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL15D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL15_I F7B4 F8B4
+OUTPUT_SSTL15_II F7B4 F8B4
+OUTPUT_SSTL18D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL18D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL18_I F7B4 F8B4
+OUTPUT_SSTL18_II F7B4 F8B4
+
+.config_enum PIOD.BASE_TYPE INPUT_HSUL12
+BIDIR_HSUL12 F4B9 F5B9
+BIDIR_LVCMOS12 F4B9 F5B9
+BIDIR_LVCMOS15 F4B9 F5B9
+BIDIR_LVCMOS18 F4B9 F5B9
+BIDIR_LVCMOS25 F4B9 F5B9
+BIDIR_LVCMOS33 F4B9 F5B9
+BIDIR_LVTTL33 F4B9 F5B9
+BIDIR_SSTL135_I F4B9 F5B9
+BIDIR_SSTL135_II F4B9 F5B9
+BIDIR_SSTL15_I F4B9 F5B9
+BIDIR_SSTL15_II F4B9 F5B9
+BIDIR_SSTL18_I F4B9 F5B9
+BIDIR_SSTL18_II F4B9 F5B9
+INPUT_HSUL12
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS25
+INPUT_LVCMOS33
+INPUT_LVTTL33
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+NONE
+OUTPUT_HSUL12 F4B9 F5B9
+OUTPUT_LVCMOS12 F4B9 F5B9
+OUTPUT_LVCMOS15 F4B9 F5B9
+OUTPUT_LVCMOS18 F4B9 F5B9
+OUTPUT_LVCMOS25 F4B9 F5B9
+OUTPUT_LVCMOS33 F4B9 F5B9
+OUTPUT_LVTTL33 F4B9 F5B9
+OUTPUT_SSTL135_I F4B9 F5B9
+OUTPUT_SSTL135_II F4B9 F5B9
+OUTPUT_SSTL15_I F4B9 F5B9
+OUTPUT_SSTL15_II F4B9 F5B9
+OUTPUT_SSTL18_I F4B9 F5B9
+OUTPUT_SSTL18_II F4B9 F5B9
+
+
+# Fixed Connections
