# Routing Mux Bits
.mux N1_JDIA
N1_INDDA_SIOLOGIC F21B0


# Non-Routing Configuration
.config IOLOGICA.DELAY.DEL_VALUE 0000000
F10B0
F9B0
F8B0
F7B0
F6B0
F5B0
F4B0

.config_enum IOLOGICA.CLKIMUX 0
0 -
CLK F19B0
INV F19B0 F20B0

.config_enum IOLOGICA.CLKOMUX 0
0 -
CLK F42B0
INV F42B0 F43B0

.config_enum IOLOGICA.DELAY.OUTDEL DISABLED
DISABLED -
ENABLED F44B0

.config_enum IOLOGICA.DELAY.WAIT_FOR_EDGE DISABLED
DISABLED -
ENABLED F39B0

.config_enum IOLOGICA.GSR ENABLED
DISABLED F12B0
ENABLED -

.config_enum IOLOGICA.LSRIMUX 0
0 -
LSRMUX F22B0

.config_enum IOLOGICA.LSRMUX INV
INV -
LSR F32B0

.config_enum IOLOGICA.LSROMUX 0
0 -
LSRMUX F45B0

.config_enum IOLOGICA.MODE IREG_OREG
IDDRX1_ODDRX1 F26B0 F41B0 F64B0
IREG_OREG -
NONE -

.config_enum PIOA.BASE_TYPE INPUT_LVCMOS12
BIDIR_LVCMOS12 F54B0 F55B0
BIDIR_LVCMOS15 F54B0 F55B0
BIDIR_LVCMOS18 F54B0 F55B0
BIDIR_LVCMOS25 F54B0 F55B0
BIDIR_LVCMOS33 F54B0 F55B0
BIDIR_LVTTL33 F54B0 F55B0
INPUT_LVCMOS12 -
INPUT_LVCMOS15 -
INPUT_LVCMOS18 -
INPUT_LVCMOS25 -
INPUT_LVCMOS33 -
INPUT_LVTTL33 -
NONE -
OUTPUT_LVCMOS12 F54B0 F55B0
OUTPUT_LVCMOS15 F54B0 F55B0
OUTPUT_LVCMOS18 F54B0 F55B0
OUTPUT_LVCMOS25 F54B0 F55B0
OUTPUT_LVCMOS33 F54B0 F55B0
OUTPUT_LVTTL33 F54B0 F55B0

.config_enum PIOA.DATAMUX_ODDR PADDO
IOLDO F50B0
PADDO -


# Fixed Connections