Update to prjtrellis d4ea249e67c8e91e2d887c76785365dc3993e824 Signed-off-by: David Shah <davey1576@gmail.com>

diff --git a/ECP5/tiledata/MIB_DSP2/bits.db b/ECP5/tiledata/MIB_DSP2/bits.db
index bd087e5..0774a02 100644
--- a/ECP5/tiledata/MIB_DSP2/bits.db
+++ b/ECP5/tiledata/MIB_DSP2/bits.db

@@ -341,18 +341,34 @@
 CLK3 -
 NONE F21B0
 
+.config_enum MULT18_0.CLK0MUX CLK0
+CLK0 -
+INV F61B0
+
 .config_enum MULT18_0.CLK0_DIV ENABLED
 DISABLED F65B0
 ENABLED -
 
+.config_enum MULT18_0.CLK1MUX CLK1
+CLK1 -
+INV F62B0
+
 .config_enum MULT18_0.CLK1_DIV ENABLED
 DISABLED F66B0
 ENABLED -
 
+.config_enum MULT18_0.CLK2MUX CLK2
+CLK2 -
+INV F63B0
+
 .config_enum MULT18_0.CLK2_DIV ENABLED
 DISABLED F67B0
 ENABLED -
 
+.config_enum MULT18_0.CLK3MUX CLK3
+CLK3 -
+INV F64B0
+
 .config_enum MULT18_0.CLK3_DIV ENABLED
 DISABLED F68B0
 ENABLED -
@@ -382,18 +398,34 @@
 CLK3 -
 NONE F58B0
 
+.config_enum MULT18_1.CLK0MUX CLK0
+CLK0 -
+INV F61B0
+
 .config_enum MULT18_1.CLK0_DIV ENABLED
 DISABLED F65B0
 ENABLED -
 
+.config_enum MULT18_1.CLK1MUX CLK1
+CLK1 -
+INV F62B0
+
 .config_enum MULT18_1.CLK1_DIV ENABLED
 DISABLED F66B0
 ENABLED -
 
+.config_enum MULT18_1.CLK2MUX CLK2
+CLK2 -
+INV F63B0
+
 .config_enum MULT18_1.CLK2_DIV ENABLED
 DISABLED F67B0
 ENABLED -
 
+.config_enum MULT18_1.CLK3MUX CLK3
+CLK3 -
+INV F64B0
+
 .config_enum MULT18_1.CLK3_DIV ENABLED
 DISABLED F68B0
 ENABLED -

diff --git a/ECP5/tiledata/MIB_DSP4/bits.db b/ECP5/tiledata/MIB_DSP4/bits.db
index 0992f53..a8bbb1e 100644
--- a/ECP5/tiledata/MIB_DSP4/bits.db
+++ b/ECP5/tiledata/MIB_DSP4/bits.db

@@ -59,6 +59,54 @@
 ALU54B F34B0 F41B0
 NONE -
 
+.config_enum MULT18_0.CE0MUX INV
+CE0 F46B0
+INV -
+
+.config_enum MULT18_0.CE1MUX INV
+CE1 F47B0
+INV -
+
+.config_enum MULT18_0.CE2MUX INV
+CE2 F48B0
+INV -
+
+.config_enum MULT18_0.CE3MUX INV
+CE3 F49B0
+INV -
+
+.config_enum MULT18_0.RST0MUX INV
+INV -
+RST0 F50B0
+
+.config_enum MULT18_0.RST1MUX INV
+INV -
+RST1 F51B0
+
+.config_enum MULT18_0.RST2MUX INV
+INV -
+RST2 F54B0
+
+.config_enum MULT18_0.RST3MUX INV
+INV -
+RST3 F55B0
+
+.config_enum MULT18_1.CE0MUX INV
+CE0 F46B0
+INV -
+
+.config_enum MULT18_1.CE1MUX INV
+CE1 F47B0
+INV -
+
+.config_enum MULT18_1.CE2MUX INV
+CE2 F48B0
+INV -
+
+.config_enum MULT18_1.CE3MUX INV
+CE3 F49B0
+INV -
+
 .config_enum MULT18_1.REG_INPUTB_CLK CLK3
 CLK0 -
 CLK1 -
@@ -66,18 +114,98 @@
 CLK3 -
 NONE F34B0 F41B0
 
+.config_enum MULT18_1.RST0MUX INV
+INV -
+RST0 F50B0
+
+.config_enum MULT18_1.RST1MUX INV
+INV -
+RST1 F51B0
+
+.config_enum MULT18_1.RST2MUX INV
+INV -
+RST2 F54B0
+
+.config_enum MULT18_1.RST3MUX INV
+INV -
+RST3 F55B0
+
 .config_enum MULT18_1.SOURCEB_MODE
 B_C_DYNAMIC F32B0
 B_SHIFT F29B0
 C_SHIFT F28B0 F29B0
 HIGHSPEED F28B0 F32B0
 
+.config_enum MULT18_4.CE0MUX INV
+CE0 F58B0
+INV -
+
+.config_enum MULT18_4.CE1MUX INV
+CE1 F59B0
+INV -
+
+.config_enum MULT18_4.CE2MUX INV
+CE2 F60B0
+INV -
+
+.config_enum MULT18_4.CE3MUX INV
+CE3 F61B0
+INV -
+
+.config_enum MULT18_4.RST0MUX INV
+INV -
+RST0 F50B0
+
+.config_enum MULT18_4.RST1MUX INV
+INV -
+RST1 F51B0
+
+.config_enum MULT18_4.RST2MUX INV
+INV -
+RST2 F54B0
+
+.config_enum MULT18_4.RST3MUX INV
+INV -
+RST3 F55B0
+
 .config_enum MULT18_4.SOURCEB_MODE
 B_C_DYNAMIC F91B0
 B_SHIFT F92B0
 C_SHIFT F90B0 F92B0
 HIGHSPEED F90B0 F91B0
 
+.config_enum MULT18_5.CE0MUX INV
+CE0 F58B0
+INV -
+
+.config_enum MULT18_5.CE1MUX INV
+CE1 F59B0
+INV -
+
+.config_enum MULT18_5.CE2MUX INV
+CE2 F60B0
+INV -
+
+.config_enum MULT18_5.CE3MUX INV
+CE3 F61B0
+INV -
+
+.config_enum MULT18_5.RST0MUX INV
+INV -
+RST0 F50B0
+
+.config_enum MULT18_5.RST1MUX INV
+INV -
+RST1 F51B0
+
+.config_enum MULT18_5.RST2MUX INV
+INV -
+RST2 F54B0
+
+.config_enum MULT18_5.RST3MUX INV
+INV -
+RST3 F55B0
+
 
 # Fixed Connections
 .fixed_conn E1_JF0 JP4_MULT18

diff --git a/ECP5/tiledata/MIB_DSP7/bits.db b/ECP5/tiledata/MIB_DSP7/bits.db
index 96342eb..aecbec0 100644
--- a/ECP5/tiledata/MIB_DSP7/bits.db
+++ b/ECP5/tiledata/MIB_DSP7/bits.db

@@ -32,18 +32,34 @@
 CLK3 -
 NONE F2B0
 
+.config_enum MULT18_4.CLK0MUX CLK0
+CLK0 -
+INV F5B0
+
 .config_enum MULT18_4.CLK0_DIV ENABLED
 DISABLED F9B0
 ENABLED -
 
+.config_enum MULT18_4.CLK1MUX CLK1
+CLK1 -
+INV F6B0
+
 .config_enum MULT18_4.CLK1_DIV ENABLED
 DISABLED F10B0
 ENABLED -
 
+.config_enum MULT18_4.CLK2MUX CLK2
+CLK2 -
+INV F7B0
+
 .config_enum MULT18_4.CLK2_DIV ENABLED
 DISABLED F11B0
 ENABLED -
 
+.config_enum MULT18_4.CLK3MUX CLK3
+CLK3 -
+INV F8B0
+
 .config_enum MULT18_4.CLK3_DIV ENABLED
 DISABLED F12B0
 ENABLED -
@@ -59,18 +75,34 @@
 CLK3 -
 NONE F1B0
 
+.config_enum MULT18_5.CLK0MUX CLK0
+CLK0 -
+INV F5B0
+
 .config_enum MULT18_5.CLK0_DIV ENABLED
 DISABLED F9B0
 ENABLED -
 
+.config_enum MULT18_5.CLK1MUX CLK1
+CLK1 -
+INV F6B0
+
 .config_enum MULT18_5.CLK1_DIV ENABLED
 DISABLED F10B0
 ENABLED -
 
+.config_enum MULT18_5.CLK2MUX CLK2
+CLK2 -
+INV F7B0
+
 .config_enum MULT18_5.CLK2_DIV ENABLED
 DISABLED F11B0
 ENABLED -
 
+.config_enum MULT18_5.CLK3MUX CLK3
+CLK3 -
+INV F8B0
+
 .config_enum MULT18_5.CLK3_DIV ENABLED
 DISABLED F12B0
 ENABLED -