Update with results from prjtrellis 5199a14822d03f1067457d2f06cac823f503ebd0
diff --git a/.gitignore b/.gitignore
index bffb817..72e8ffc 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,2 +1 @@
-html
-
+*
diff --git a/ECP5/tiledata/MIB_CIB_LR/bits.db b/ECP5/tiledata/MIB_CIB_LR/bits.db
index 8b13789..c654018 100644
--- a/ECP5/tiledata/MIB_CIB_LR/bits.db
+++ b/ECP5/tiledata/MIB_CIB_LR/bits.db
@@ -1 +1,129 @@
+# Routing Mux Bits
+# Non-Routing Configuration
+.config_enum PIOC.BASE_TYPE INPUT_LVCMOS18D
+BIDIR_BLVDS25E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_HSUL12 F1B4 F2B4
+BIDIR_HSUL12D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_LVCMOS12 F1B4 F2B4
+BIDIR_LVCMOS15 F1B4 F2B4
+BIDIR_LVCMOS18 F1B4 F2B4
+BIDIR_LVCMOS25 F1B4 F2B4
+BIDIR_LVCMOS25D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_LVCMOS33 F1B4 F2B4
+BIDIR_LVCMOS33D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_LVTTL33 F1B4 F2B4
+BIDIR_MLVDS25E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_SSTL135D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_SSTL135D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_SSTL135_I F1B4 F2B4
+BIDIR_SSTL135_II F1B4 F2B4
+BIDIR_SSTL15D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_SSTL15D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_SSTL15_I F1B4 F2B4
+BIDIR_SSTL15_II F1B4 F2B4
+BIDIR_SSTL18D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_SSTL18D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_SSTL18_I F1B4 F2B4
+BIDIR_SSTL18_II F1B4 F2B4
+INPUT_BLVDS25
+INPUT_HSUL12
+INPUT_HSUL12D
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS18D
+INPUT_LVCMOS25
+INPUT_LVCMOS25D
+INPUT_LVCMOS33
+INPUT_LVCMOS33D
+INPUT_LVDS
+INPUT_LVPECL33
+INPUT_LVTTL33
+INPUT_MLVDS25
+INPUT_SLVS
+INPUT_SSTL135D_I
+INPUT_SSTL135D_II
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15D_I
+INPUT_SSTL15D_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18D_I
+INPUT_SSTL18D_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+INPUT_SUBLVDS
+NONE
+OUTPUT_BLVDS25E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_HSUL12 F1B4 F2B4
+OUTPUT_HSUL12D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_LVCMOS12 F1B4 F2B4
+OUTPUT_LVCMOS15 F1B4 F2B4
+OUTPUT_LVCMOS18 F1B4 F2B4
+OUTPUT_LVCMOS25 F1B4 F2B4
+OUTPUT_LVCMOS25D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_LVCMOS33 F1B4 F2B4
+OUTPUT_LVCMOS33D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_LVDS25E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_LVPECL33E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_LVTTL33 F1B4 F2B4
+OUTPUT_MLVDS25E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_SSTL135D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_SSTL135D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_SSTL135_I F1B4 F2B4
+OUTPUT_SSTL135_II F1B4 F2B4
+OUTPUT_SSTL15D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_SSTL15D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_SSTL15_I F1B4 F2B4
+OUTPUT_SSTL15_II F1B4 F2B4
+OUTPUT_SSTL18D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_SSTL18D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_SSTL18_I F1B4 F2B4
+OUTPUT_SSTL18_II F1B4 F2B4
+
+.config_enum PIOD.BASE_TYPE INPUT_HSUL12
+BIDIR_HSUL12 F4B9 F5B9
+BIDIR_LVCMOS12 F4B9 F5B9
+BIDIR_LVCMOS15 F4B9 F5B9
+BIDIR_LVCMOS18 F4B9 F5B9
+BIDIR_LVCMOS25 F4B9 F5B9
+BIDIR_LVCMOS33 F4B9 F5B9
+BIDIR_LVTTL33 F4B9 F5B9
+BIDIR_SSTL135_I F4B9 F5B9
+BIDIR_SSTL135_II F4B9 F5B9
+BIDIR_SSTL15_I F4B9 F5B9
+BIDIR_SSTL15_II F4B9 F5B9
+BIDIR_SSTL18_I F4B9 F5B9
+BIDIR_SSTL18_II F4B9 F5B9
+INPUT_HSUL12
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS25
+INPUT_LVCMOS33
+INPUT_LVTTL33
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+NONE
+OUTPUT_HSUL12 F4B9 F5B9
+OUTPUT_LVCMOS12 F4B9 F5B9
+OUTPUT_LVCMOS15 F4B9 F5B9
+OUTPUT_LVCMOS18 F4B9 F5B9
+OUTPUT_LVCMOS25 F4B9 F5B9
+OUTPUT_LVCMOS33 F4B9 F5B9
+OUTPUT_LVTTL33 F4B9 F5B9
+OUTPUT_SSTL135_I F4B9 F5B9
+OUTPUT_SSTL135_II F4B9 F5B9
+OUTPUT_SSTL15_I F4B9 F5B9
+OUTPUT_SSTL15_II F4B9 F5B9
+OUTPUT_SSTL18_I F4B9 F5B9
+OUTPUT_SSTL18_II F4B9 F5B9
+
+
+# Fixed Connections
diff --git a/ECP5/tiledata/MIB_CIB_LR_A/bits.db b/ECP5/tiledata/MIB_CIB_LR_A/bits.db
index 8b13789..693154a 100644
--- a/ECP5/tiledata/MIB_CIB_LR_A/bits.db
+++ b/ECP5/tiledata/MIB_CIB_LR_A/bits.db
@@ -1 +1,129 @@
+# Routing Mux Bits
+# Non-Routing Configuration
+.config_enum PIOC.BASE_TYPE INPUT_LVCMOS18D
+BIDIR_BLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_HSUL12 F7B4 F8B4
+BIDIR_HSUL12D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_LVCMOS12 F7B4 F8B4
+BIDIR_LVCMOS15 F7B4 F8B4
+BIDIR_LVCMOS18 F7B4 F8B4
+BIDIR_LVCMOS25 F7B4 F8B4
+BIDIR_LVCMOS25D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_LVCMOS33 F7B4 F8B4
+BIDIR_LVCMOS33D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_LVTTL33 F7B4 F8B4
+BIDIR_MLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL135D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL135D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL135_I F7B4 F8B4
+BIDIR_SSTL135_II F7B4 F8B4
+BIDIR_SSTL15D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL15D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL15_I F7B4 F8B4
+BIDIR_SSTL15_II F7B4 F8B4
+BIDIR_SSTL18D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL18D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL18_I F7B4 F8B4
+BIDIR_SSTL18_II F7B4 F8B4
+INPUT_BLVDS25
+INPUT_HSUL12
+INPUT_HSUL12D
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS18D
+INPUT_LVCMOS25
+INPUT_LVCMOS25D
+INPUT_LVCMOS33
+INPUT_LVCMOS33D
+INPUT_LVDS
+INPUT_LVPECL33
+INPUT_LVTTL33
+INPUT_MLVDS25
+INPUT_SLVS
+INPUT_SSTL135D_I
+INPUT_SSTL135D_II
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15D_I
+INPUT_SSTL15D_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18D_I
+INPUT_SSTL18D_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+INPUT_SUBLVDS
+NONE
+OUTPUT_BLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_HSUL12 F7B4 F8B4
+OUTPUT_HSUL12D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_LVCMOS12 F7B4 F8B4
+OUTPUT_LVCMOS15 F7B4 F8B4
+OUTPUT_LVCMOS18 F7B4 F8B4
+OUTPUT_LVCMOS25 F7B4 F8B4
+OUTPUT_LVCMOS25D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_LVCMOS33 F7B4 F8B4
+OUTPUT_LVCMOS33D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_LVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_LVPECL33E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_LVTTL33 F7B4 F8B4
+OUTPUT_MLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL135D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL135D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL135_I F7B4 F8B4
+OUTPUT_SSTL135_II F7B4 F8B4
+OUTPUT_SSTL15D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL15D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL15_I F7B4 F8B4
+OUTPUT_SSTL15_II F7B4 F8B4
+OUTPUT_SSTL18D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL18D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL18_I F7B4 F8B4
+OUTPUT_SSTL18_II F7B4 F8B4
+
+.config_enum PIOD.BASE_TYPE INPUT_HSUL12
+BIDIR_HSUL12 F4B9 F5B9
+BIDIR_LVCMOS12 F4B9 F5B9
+BIDIR_LVCMOS15 F4B9 F5B9
+BIDIR_LVCMOS18 F4B9 F5B9
+BIDIR_LVCMOS25 F4B9 F5B9
+BIDIR_LVCMOS33 F4B9 F5B9
+BIDIR_LVTTL33 F4B9 F5B9
+BIDIR_SSTL135_I F4B9 F5B9
+BIDIR_SSTL135_II F4B9 F5B9
+BIDIR_SSTL15_I F4B9 F5B9
+BIDIR_SSTL15_II F4B9 F5B9
+BIDIR_SSTL18_I F4B9 F5B9
+BIDIR_SSTL18_II F4B9 F5B9
+INPUT_HSUL12
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS25
+INPUT_LVCMOS33
+INPUT_LVTTL33
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+NONE
+OUTPUT_HSUL12 F4B9 F5B9
+OUTPUT_LVCMOS12 F4B9 F5B9
+OUTPUT_LVCMOS15 F4B9 F5B9
+OUTPUT_LVCMOS18 F4B9 F5B9
+OUTPUT_LVCMOS25 F4B9 F5B9
+OUTPUT_LVCMOS33 F4B9 F5B9
+OUTPUT_LVTTL33 F4B9 F5B9
+OUTPUT_SSTL135_I F4B9 F5B9
+OUTPUT_SSTL135_II F4B9 F5B9
+OUTPUT_SSTL15_I F4B9 F5B9
+OUTPUT_SSTL15_II F4B9 F5B9
+OUTPUT_SSTL18_I F4B9 F5B9
+OUTPUT_SSTL18_II F4B9 F5B9
+
+
+# Fixed Connections
diff --git a/ECP5/tiledata/PICL0_DQS2/bits.db b/ECP5/tiledata/PICL0_DQS2/bits.db
index 8b13789..c6bd7e3 100644
--- a/ECP5/tiledata/PICL0_DQS2/bits.db
+++ b/ECP5/tiledata/PICL0_DQS2/bits.db
@@ -1 +1,133 @@
+# Routing Mux Bits
+# Non-Routing Configuration
+.config_enum PIOA.BASE_TYPE INPUT_LVCMOS18D
+BIDIR_BLVDS25E F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+BIDIR_HSUL12 F1B4 F2B4
+BIDIR_HSUL12D F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+BIDIR_LVCMOS12 F1B4 F2B4
+BIDIR_LVCMOS15 F1B4 F2B4
+BIDIR_LVCMOS18 F1B4 F2B4
+BIDIR_LVCMOS18D F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+BIDIR_LVCMOS25 F1B4 F2B4
+BIDIR_LVCMOS25D F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+BIDIR_LVCMOS33 F1B4 F2B4
+BIDIR_LVCMOS33D F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+BIDIR_LVDS F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+BIDIR_LVTTL33 F1B4 F2B4
+BIDIR_MLVDS25E F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+BIDIR_SSTL135D_I F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+BIDIR_SSTL135D_II F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+BIDIR_SSTL135_I F1B4 F2B4
+BIDIR_SSTL135_II F1B4 F2B4
+BIDIR_SSTL15D_I F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+BIDIR_SSTL15D_II F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+BIDIR_SSTL15_I F1B4 F2B4
+BIDIR_SSTL15_II F1B4 F2B4
+BIDIR_SSTL18D_I F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+BIDIR_SSTL18D_II F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+BIDIR_SSTL18_I F1B4 F2B4
+BIDIR_SSTL18_II F1B4 F2B4
+INPUT_BLVDS25
+INPUT_HSUL12
+INPUT_HSUL12D
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS18D
+INPUT_LVCMOS25
+INPUT_LVCMOS25D
+INPUT_LVCMOS33
+INPUT_LVCMOS33D
+INPUT_LVDS
+INPUT_LVPECL33
+INPUT_LVTTL33
+INPUT_MLVDS25
+INPUT_SLVS
+INPUT_SSTL135D_I
+INPUT_SSTL135D_II
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15D_I
+INPUT_SSTL15D_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18D_I
+INPUT_SSTL18D_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+INPUT_SUBLVDS
+NONE
+OUTPUT_BLVDS25E F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+OUTPUT_HSUL12 F1B4 F2B4
+OUTPUT_HSUL12D F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+OUTPUT_LVCMOS12 F1B4 F2B4
+OUTPUT_LVCMOS15 F1B4 F2B4
+OUTPUT_LVCMOS18 F1B4 F2B4
+OUTPUT_LVCMOS18D F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+OUTPUT_LVCMOS25 F1B4 F2B4
+OUTPUT_LVCMOS25D F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+OUTPUT_LVCMOS33 F1B4 F2B4
+OUTPUT_LVCMOS33D F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+OUTPUT_LVDS F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+OUTPUT_LVDS25E F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+OUTPUT_LVPECL33E F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+OUTPUT_LVTTL33 F1B4 F2B4
+OUTPUT_MLVDS25E F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+OUTPUT_SSTL135D_I F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+OUTPUT_SSTL135D_II F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+OUTPUT_SSTL135_I F1B4 F2B4
+OUTPUT_SSTL135_II F1B4 F2B4
+OUTPUT_SSTL15D_I F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+OUTPUT_SSTL15D_II F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+OUTPUT_SSTL15_I F1B4 F2B4
+OUTPUT_SSTL15_II F1B4 F2B4
+OUTPUT_SSTL18D_I F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+OUTPUT_SSTL18D_II F1B1 F1B4 F2B4 F3B6 F3B9 F4B9
+OUTPUT_SSTL18_I F1B4 F2B4
+OUTPUT_SSTL18_II F1B4 F2B4
+
+.config_enum PIOB.BASE_TYPE INPUT_HSUL12
+BIDIR_HSUL12 F3B9 F4B9
+BIDIR_LVCMOS12 F3B9 F4B9
+BIDIR_LVCMOS15 F3B9 F4B9
+BIDIR_LVCMOS18 F3B9 F4B9
+BIDIR_LVCMOS25 F3B9 F4B9
+BIDIR_LVCMOS33 F3B9 F4B9
+BIDIR_LVTTL33 F3B9 F4B9
+BIDIR_SSTL135_I F3B9 F4B9
+BIDIR_SSTL135_II F3B9 F4B9
+BIDIR_SSTL15_I F3B9 F4B9
+BIDIR_SSTL15_II F3B9 F4B9
+BIDIR_SSTL18_I F3B9 F4B9
+BIDIR_SSTL18_II F3B9 F4B9
+INPUT_HSUL12
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS25
+INPUT_LVCMOS33
+INPUT_LVTTL33
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+NONE
+OUTPUT_HSUL12 F3B9 F4B9
+OUTPUT_LVCMOS12 F3B9 F4B9
+OUTPUT_LVCMOS15 F3B9 F4B9
+OUTPUT_LVCMOS18 F3B9 F4B9
+OUTPUT_LVCMOS25 F3B9 F4B9
+OUTPUT_LVCMOS33 F3B9 F4B9
+OUTPUT_LVTTL33 F3B9 F4B9
+OUTPUT_SSTL135_I F3B9 F4B9
+OUTPUT_SSTL135_II F3B9 F4B9
+OUTPUT_SSTL15_I F3B9 F4B9
+OUTPUT_SSTL15_II F3B9 F4B9
+OUTPUT_SSTL18_I F3B9 F4B9
+OUTPUT_SSTL18_II F3B9 F4B9
+
+
+# Fixed Connections
diff --git a/ECP5/tiledata/PICL1/bits.db b/ECP5/tiledata/PICL1/bits.db
index 1d1f155..709fb7b 100644
--- a/ECP5/tiledata/PICL1/bits.db
+++ b/ECP5/tiledata/PICL1/bits.db
@@ -87,6 +87,20 @@
OUTPUT_SSTL18_I F2B0 F7B0 F9B0
OUTPUT_SSTL18_II F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F9B0
+.config_enum PIOA.DRIVE
+12 !F4B1 !F5B1 !F6B1 F7B1 !F8B1
+16 F4B1 F5B1 F6B1 F7B1 !F8B1
+4 !F4B1 !F5B1 F6B1 F7B1 F8B1
+8 F4B1 F5B1 F6B1 !F7B1 !F8B1
+
+.config_enum PIOA.HYSTERESIS OFF
+OFF !F3B1
+ON F3B1
+
+.config_enum PIOA.OPENDRAIN
+OFF F4B1 F5B1 !F5B2 F6B1
+ON !F4B1 F5B2 !F5B1 !F6B1
+
.config_enum PIOA.PULLMODE DOWN
DOWN !F7B0 !F8B0
NONE F7B0 !F8B0
@@ -138,6 +152,20 @@
OUTPUT_SSTL18_I F1B3 F3B3 F6B2
OUTPUT_SSTL18_II F0B4 F1B3 F1B4 F3B3 F6B2 F8B3 F9B3
+.config_enum PIOB.DRIVE
+12 !F0B4 F1B4 !F2B4 !F8B3 !F9B3
+16 F0B4 F1B4 !F2B4 F8B3 F9B3
+4 F0B4 F1B4 F2B4 !F8B3 !F9B3
+8 F0B4 !F1B4 !F2B4 F8B3 F9B3
+
+.config_enum PIOB.HYSTERESIS OFF
+OFF !F7B3
+ON F7B3
+
+.config_enum PIOB.OPENDRAIN
+OFF F0B4 F8B3 F9B3 !F9B4
+ON !F0B4 !F8B3 F9B4 !F9B3
+
.config_enum PIOB.PULLMODE DOWN
DOWN !F1B3 !F2B3
NONE F1B3 !F2B3
@@ -229,6 +257,20 @@
OUTPUT_SSTL18_I F0B5 F5B5 F7B5
OUTPUT_SSTL18_II F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F7B5
+.config_enum PIOC.DRIVE
+12 !F2B6 !F3B6 !F4B6 F5B6 !F6B6
+16 F2B6 F3B6 F4B6 F5B6 !F6B6
+4 !F2B6 !F3B6 F4B6 F5B6 F6B6
+8 F2B6 F3B6 F4B6 !F5B6 !F6B6
+
+.config_enum PIOC.HYSTERESIS OFF
+OFF !F1B6
+ON F1B6
+
+.config_enum PIOC.OPENDRAIN
+OFF F2B6 F3B6 !F3B7 F4B6
+ON !F2B6 !F3B6 F3B7 !F4B6
+
.config_enum PIOC.PULLMODE DOWN
DOWN !F5B5 !F6B5
NONE F5B5 !F6B5
@@ -280,6 +322,20 @@
OUTPUT_SSTL18_I F1B8 F4B7 F9B7
OUTPUT_SSTL18_II F1B8 F4B7 F6B8 F7B8 F8B8 F9B7 F9B8
+.config_enum PIOD.DRIVE
+12 !F0B9 !F6B8 !F7B8 !F8B8 F9B8
+16 !F0B9 F6B8 F7B8 F8B8 F9B8
+4 F0B9 !F6B8 !F7B8 F8B8 F9B8
+8 !F0B9 F6B8 F7B8 F8B8 !F9B8
+
+.config_enum PIOD.HYSTERESIS OFF
+OFF !F5B8
+ON F5B8
+
+.config_enum PIOD.OPENDRAIN
+OFF F6B8 F7B8 !F7B9 F8B8
+ON !F6B8 !F7B8 F7B9 !F8B8
+
.config_enum PIOD.PULLMODE DOWN
DOWN !F0B8 !F9B7
NONE !F0B8 F9B7
diff --git a/ECP5/tiledata/PICL1_DQS0/bits.db b/ECP5/tiledata/PICL1_DQS0/bits.db
index 8b13789..bed34cf 100644
--- a/ECP5/tiledata/PICL1_DQS0/bits.db
+++ b/ECP5/tiledata/PICL1_DQS0/bits.db
@@ -1 +1,349 @@
+# Routing Mux Bits
+# Non-Routing Configuration
+.config_enum PIOA.BASE_TYPE NONE
+BIDIR_BLVDS25E F0B4 F1B3 F1B4 F2B0 F4B1 F5B0 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
+BIDIR_HSUL12 F2B0 F5B0 F6B0 F7B0 F9B0
+BIDIR_HSUL12D F2B0 F5B0 F7B0 F9B0
+BIDIR_LVCMOS12 F2B0 F4B0 F9B0
+BIDIR_LVCMOS15 !F2B0 F9B0
+BIDIR_LVCMOS18 !F2B0 F9B0
+BIDIR_LVCMOS18D F1B3 F2B0 F2B1 F2B4 F5B0 F7B0 F8B1 F9B0
+BIDIR_LVCMOS25 F2B0 F3B0 F3B1 F9B0
+BIDIR_LVCMOS25D F1B3 F2B0 F5B0 F7B0 F9B0
+BIDIR_LVCMOS33 F2B0 F3B0 F3B1 F4B0 F4B1 F5B1 F6B1 F9B0
+BIDIR_LVCMOS33D F0B4 F1B3 F2B0 F4B1 F5B0 F5B1 F6B1 F7B0 F8B3 F9B0 F9B3
+BIDIR_LVDS F1B3 F2B0 F2B1 F2B4 F5B0 F7B0 F8B1 F9B0
+BIDIR_LVTTL33 F2B0 F3B0 F3B1 F4B0 F4B1 F5B1 F6B1 F9B0
+BIDIR_MLVDS25E F0B4 F1B3 F1B4 F2B0 F4B1 F5B0 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
+BIDIR_SSTL135D_I F1B3 F2B0 F5B0 F5B1 F7B0 F9B0 F9B3
+BIDIR_SSTL135D_II F1B3 F1B4 F2B0 F5B0 F6B1 F7B0 F9B0
+BIDIR_SSTL135_I F2B0 F5B0 F5B1 F6B0 F7B0 F9B0
+BIDIR_SSTL135_II F2B0 F5B0 F6B0 F6B1 F7B0 F9B0
+BIDIR_SSTL15D_I F1B3 F2B0 F5B0 F5B1 F7B0 F9B0 F9B3
+BIDIR_SSTL15D_II F1B3 F1B4 F2B0 F5B0 F6B1 F7B0 F9B0
+BIDIR_SSTL15_I F2B0 F5B0 F5B1 F6B0 F7B0 F9B0
+BIDIR_SSTL15_II F2B0 F5B0 F6B0 F6B1 F7B0 F9B0
+BIDIR_SSTL18D_I F1B3 F2B0 F5B0 F7B0 F9B0
+BIDIR_SSTL18D_II F0B4 F1B3 F1B4 F2B0 F4B1 F5B0 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
+BIDIR_SSTL18_I F2B0 F5B0 F6B0 F7B0 F9B0
+BIDIR_SSTL18_II F2B0 F4B1 F5B0 F5B1 F6B0 F6B1 F7B0 F7B1 F9B0
+INPUT_BLVDS25 F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_HSUL12 F2B0 F5B0 F6B0 F7B0 F9B0
+INPUT_HSUL12D F2B0 F5B0 F7B0 F9B0
+INPUT_LVCMOS12 F2B0 F4B0 F9B0
+INPUT_LVCMOS15 !F2B0 F9B0
+INPUT_LVCMOS18 !F2B0 F9B0
+INPUT_LVCMOS18D F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_LVCMOS25 F2B0 F3B0 F3B1 F9B0
+INPUT_LVCMOS25D F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_LVCMOS33 F2B0 F3B0 F3B1 F4B0 F9B0
+INPUT_LVCMOS33D F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_LVDS F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_LVPECL33 F2B0 F5B0 F7B0 F9B0
+INPUT_LVTTL33 F2B0 F3B0 F3B1 F4B0 F9B0
+INPUT_MLVDS25 F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SLVS F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SSTL135D_I F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SSTL135D_II F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SSTL135_I F2B0 F5B0 F6B0 F7B0 F9B0
+INPUT_SSTL135_II F2B0 F5B0 F6B0 F7B0 F9B0
+INPUT_SSTL15D_I F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SSTL15D_II F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SSTL15_I F2B0 F5B0 F6B0 F7B0 F9B0
+INPUT_SSTL15_II F2B0 F5B0 F6B0 F7B0 F9B0
+INPUT_SSTL18D_I F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SSTL18D_II F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SSTL18_I F2B0 F5B0 F6B0 F7B0 F9B0
+INPUT_SSTL18_II F2B0 F5B0 F6B0 F7B0 F9B0
+INPUT_SUBLVDS F1B3 F2B0 F5B0 F7B0 F9B0
+NONE F2B0
+OUTPUT_BLVDS25E F0B4 F1B3 F1B4 F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
+OUTPUT_HSUL12 F2B0 F7B0 F9B0
+OUTPUT_HSUL12D F2B0 F7B0 F9B0
+OUTPUT_LVCMOS12 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS15 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS18 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS18D F1B3 F2B0 F2B1 F2B4 F7B0 F8B1 F9B0
+OUTPUT_LVCMOS25 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS25D F1B3 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS33 F2B0 F4B1 F5B1 F6B1 F7B0 F9B0
+OUTPUT_LVCMOS33D F0B4 F1B3 F2B0 F4B1 F5B1 F6B1 F7B0 F8B3 F9B0 F9B3
+OUTPUT_LVDS F1B3 F2B0 F2B1 F2B4 F7B0 F8B1 F9B0
+OUTPUT_LVDS25E F1B3 F2B0 F7B0 F9B0
+OUTPUT_LVPECL33E F0B4 F1B3 F1B4 F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
+OUTPUT_LVTTL33 F2B0 F4B1 F5B1 F6B1 F7B0 F9B0
+OUTPUT_MLVDS25E F0B4 F1B3 F1B4 F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
+OUTPUT_SSTL135D_I F1B3 F2B0 F5B1 F7B0 F9B0 F9B3
+OUTPUT_SSTL135D_II F1B3 F1B4 F2B0 F6B1 F7B0 F9B0
+OUTPUT_SSTL135_I F2B0 F5B1 F7B0 F9B0
+OUTPUT_SSTL135_II F2B0 F6B1 F7B0 F9B0
+OUTPUT_SSTL15D_I F1B3 F2B0 F5B1 F7B0 F9B0 F9B3
+OUTPUT_SSTL15D_II F1B3 F1B4 F2B0 F6B1 F7B0 F9B0
+OUTPUT_SSTL15_I F2B0 F5B1 F7B0 F9B0
+OUTPUT_SSTL15_II F2B0 F6B1 F7B0 F9B0
+OUTPUT_SSTL18D_I F1B3 F2B0 F7B0 F9B0
+OUTPUT_SSTL18D_II F0B4 F1B3 F1B4 F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
+OUTPUT_SSTL18_I F2B0 F7B0 F9B0
+OUTPUT_SSTL18_II F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F9B0
+
+.config_enum PIOA.DRIVE
+12 !F4B1 !F5B1 !F6B1 F7B1 !F8B1
+16 F4B1 F5B1 F6B1 F7B1 !F8B1
+4 !F4B1 !F5B1 F6B1 F7B1 F8B1
+8 F4B1 F5B1 F6B1 !F7B1 !F8B1
+
+.config_enum PIOA.HYSTERESIS OFF
+OFF !F3B1
+ON F3B1
+
+.config_enum PIOA.OPENDRAIN
+OFF F4B1 F5B1 !F5B2 F6B1
+ON !F4B1 !F5B1 F5B2 !F6B1
+
+.config_enum PIOA.PULLMODE DOWN
+DOWN !F7B0 !F8B0
+NONE F7B0 !F8B0
+UP F7B0 F8B0
+
+.config_enum PIOA.SLEWRATE SLOW
+FAST F4B2
+SLOW !F4B2
+
+.config_enum PIOB.BASE_TYPE NONE
+BIDIR_HSUL12 F0B3 F1B3 F3B3 F6B2 F9B2
+BIDIR_LVCMOS12 F3B3 F6B2 F8B2
+BIDIR_LVCMOS15 F3B3 !F6B2
+BIDIR_LVCMOS18 F3B3 !F6B2
+BIDIR_LVCMOS25 F3B3 F6B2 F7B2 F7B3
+BIDIR_LVCMOS33 F0B4 F3B3 F6B2 F7B2 F7B3 F8B2 F8B3 F9B3
+BIDIR_LVTTL33 F0B4 F3B3 F6B2 F7B2 F7B3 F8B2 F8B3 F9B3
+BIDIR_SSTL135_I F0B3 F1B3 F3B3 F6B2 F9B2 F9B3
+BIDIR_SSTL135_II F0B3 F0B4 F1B3 F3B3 F6B2 F9B2
+BIDIR_SSTL15_I F0B3 F1B3 F3B3 F6B2 F9B2 F9B3
+BIDIR_SSTL15_II F0B3 F0B4 F1B3 F3B3 F6B2 F9B2
+BIDIR_SSTL18_I F0B3 F1B3 F3B3 F6B2 F9B2
+BIDIR_SSTL18_II F0B3 F0B4 F1B3 F1B4 F3B3 F6B2 F8B3 F9B2 F9B3
+INPUT_HSUL12 F0B3 F1B3 F3B3 F6B2 F9B2
+INPUT_LVCMOS12 F3B3 F6B2 F8B2
+INPUT_LVCMOS15 F3B3 !F6B2
+INPUT_LVCMOS18 F3B3 !F6B2
+INPUT_LVCMOS25 F3B3 F6B2 F7B2 F7B3
+INPUT_LVCMOS33 F3B3 F6B2 F7B2 F7B3 F8B2
+INPUT_LVTTL33 F3B3 F6B2 F7B2 F7B3 F8B2
+INPUT_SSTL135_I F0B3 F1B3 F3B3 F6B2 F9B2
+INPUT_SSTL135_II F0B3 F1B3 F3B3 F6B2 F9B2
+INPUT_SSTL15_I F0B3 F1B3 F3B3 F6B2 F9B2
+INPUT_SSTL15_II F0B3 F1B3 F3B3 F6B2 F9B2
+INPUT_SSTL18_I F0B3 F1B3 F3B3 F6B2 F9B2
+INPUT_SSTL18_II F0B3 F1B3 F3B3 F6B2 F9B2
+NONE F6B2
+OUTPUT_HSUL12 F1B3 F3B3 F6B2
+OUTPUT_LVCMOS12 F1B3 F3B3 F6B2
+OUTPUT_LVCMOS15 F1B3 F3B3 F6B2
+OUTPUT_LVCMOS18 F1B3 F3B3 F6B2
+OUTPUT_LVCMOS25 F1B3 F3B3 F6B2
+OUTPUT_LVCMOS33 F0B4 F1B3 F3B3 F6B2 F8B3 F9B3
+OUTPUT_LVTTL33 F0B4 F1B3 F3B3 F6B2 F8B3 F9B3
+OUTPUT_SSTL135_I F1B3 F3B3 F6B2 F9B3
+OUTPUT_SSTL135_II F0B4 F1B3 F3B3 F6B2
+OUTPUT_SSTL15_I F1B3 F3B3 F6B2 F9B3
+OUTPUT_SSTL15_II F0B4 F1B3 F3B3 F6B2
+OUTPUT_SSTL18_I F1B3 F3B3 F6B2
+OUTPUT_SSTL18_II F0B4 F1B3 F1B4 F3B3 F6B2 F8B3 F9B3
+
+.config_enum PIOB.DRIVE
+12 !F0B4 F1B4 !F2B4 !F8B3 !F9B3
+16 F0B4 F1B4 !F2B4 F8B3 F9B3
+4 F0B4 F1B4 F2B4 !F8B3 !F9B3
+8 F0B4 !F1B4 !F2B4 F8B3 F9B3
+
+.config_enum PIOB.HYSTERESIS OFF
+OFF !F7B3
+ON F7B3
+
+.config_enum PIOB.OPENDRAIN
+OFF F0B4 F8B3 F9B3 !F9B4
+ON !F0B4 !F8B3 !F9B3 F9B4
+
+.config_enum PIOB.PULLMODE DOWN
+DOWN !F1B3 !F2B3
+NONE F1B3 !F2B3
+UP F1B3 F2B3
+
+.config_enum PIOB.SLEWRATE SLOW
+FAST F8B4
+SLOW !F8B4
+
+.config_enum PIOC.BASE_TYPE NONE
+BIDIR_BLVDS25E F0B5 F2B6 F3B5 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
+BIDIR_HSUL12 F0B5 F3B5 F4B5 F5B5 F7B5
+BIDIR_HSUL12D F0B5 F3B5 F5B5 F7B5
+BIDIR_LVCMOS12 F0B5 F2B5 F7B5
+BIDIR_LVCMOS15 !F0B5 F7B5
+BIDIR_LVCMOS18 !F0B5 F7B5
+BIDIR_LVCMOS25 F0B5 F1B5 F1B6 F7B5
+BIDIR_LVCMOS25D F0B5 F3B5 F5B5 F7B5 F9B7
+BIDIR_LVCMOS33 F0B5 F1B5 F1B6 F2B5 F2B6 F3B6 F4B6 F7B5
+BIDIR_LVCMOS33D F0B5 F2B6 F3B5 F3B6 F4B6 F5B5 F6B8 F7B5 F7B8 F8B8 F9B7
+BIDIR_LVTTL33 F0B5 F1B5 F1B6 F2B5 F2B6 F3B6 F4B6 F7B5
+BIDIR_MLVDS25E F0B5 F2B6 F3B5 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
+BIDIR_SSTL135D_I F0B5 F3B5 F3B6 F5B5 F7B5 F7B8 F9B7
+BIDIR_SSTL135D_II F0B5 F3B5 F4B6 F5B5 F7B5 F9B7 F9B8
+BIDIR_SSTL135_I F0B5 F3B5 F3B6 F4B5 F5B5 F7B5
+BIDIR_SSTL135_II F0B5 F3B5 F4B5 F4B6 F5B5 F7B5
+BIDIR_SSTL15D_I F0B5 F3B5 F3B6 F5B5 F7B5 F7B8 F9B7
+BIDIR_SSTL15D_II F0B5 F3B5 F4B6 F5B5 F7B5 F9B7 F9B8
+BIDIR_SSTL15_I F0B5 F3B5 F3B6 F4B5 F5B5 F7B5
+BIDIR_SSTL15_II F0B5 F3B5 F4B5 F4B6 F5B5 F7B5
+BIDIR_SSTL18D_I F0B5 F3B5 F5B5 F7B5 F9B7
+BIDIR_SSTL18D_II F0B5 F2B6 F3B5 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
+BIDIR_SSTL18_I F0B5 F3B5 F4B5 F5B5 F7B5
+BIDIR_SSTL18_II F0B5 F2B6 F3B5 F3B6 F4B5 F4B6 F5B5 F5B6 F7B5
+INPUT_BLVDS25 F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_HSUL12 F0B5 F3B5 F4B5 F5B5 F7B5
+INPUT_HSUL12D F0B5 F3B5 F5B5 F7B5
+INPUT_LVCMOS12 F0B5 F2B5 F7B5
+INPUT_LVCMOS15 !F0B5 F7B5
+INPUT_LVCMOS18 !F0B5 F7B5
+INPUT_LVCMOS18D F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_LVCMOS25 F0B5 F1B5 F1B6 F7B5
+INPUT_LVCMOS25D F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_LVCMOS33 F0B5 F1B5 F1B6 F2B5 F7B5
+INPUT_LVCMOS33D F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_LVDS F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_LVPECL33 F0B5 F3B5 F5B5 F7B5
+INPUT_LVTTL33 F0B5 F1B5 F1B6 F2B5 F7B5
+INPUT_MLVDS25 F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SLVS F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SSTL135D_I F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SSTL135D_II F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SSTL135_I F0B5 F3B5 F4B5 F5B5 F7B5
+INPUT_SSTL135_II F0B5 F3B5 F4B5 F5B5 F7B5
+INPUT_SSTL15D_I F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SSTL15D_II F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SSTL15_I F0B5 F3B5 F4B5 F5B5 F7B5
+INPUT_SSTL15_II F0B5 F3B5 F4B5 F5B5 F7B5
+INPUT_SSTL18D_I F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SSTL18D_II F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SSTL18_I F0B5 F3B5 F4B5 F5B5 F7B5
+INPUT_SSTL18_II F0B5 F3B5 F4B5 F5B5 F7B5
+INPUT_SUBLVDS F0B5 F3B5 F5B5 F7B5 F9B7
+NONE F0B5
+OUTPUT_BLVDS25E F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
+OUTPUT_HSUL12 F0B5 F5B5 F7B5
+OUTPUT_HSUL12D F0B5 F5B5 F7B5
+OUTPUT_LVCMOS12 F0B5 F5B5 F7B5
+OUTPUT_LVCMOS15 F0B5 F5B5 F7B5
+OUTPUT_LVCMOS18 F0B5 F5B5 F7B5
+OUTPUT_LVCMOS25 F0B5 F5B5 F7B5
+OUTPUT_LVCMOS25D F0B5 F5B5 F7B5 F9B7
+OUTPUT_LVCMOS33 F0B5 F2B6 F3B6 F4B6 F5B5 F7B5
+OUTPUT_LVCMOS33D F0B5 F2B6 F3B6 F4B6 F5B5 F6B8 F7B5 F7B8 F8B8 F9B7
+OUTPUT_LVDS25E F0B5 F5B5 F7B5 F9B7
+OUTPUT_LVPECL33E F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
+OUTPUT_LVTTL33 F0B5 F2B6 F3B6 F4B6 F5B5 F7B5
+OUTPUT_MLVDS25E F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
+OUTPUT_SSTL135D_I F0B5 F3B6 F5B5 F7B5 F7B8 F9B7
+OUTPUT_SSTL135D_II F0B5 F4B6 F5B5 F7B5 F9B7 F9B8
+OUTPUT_SSTL135_I F0B5 F3B6 F5B5 F7B5
+OUTPUT_SSTL135_II F0B5 F4B6 F5B5 F7B5
+OUTPUT_SSTL15D_I F0B5 F3B6 F5B5 F7B5 F7B8 F9B7
+OUTPUT_SSTL15D_II F0B5 F4B6 F5B5 F7B5 F9B7 F9B8
+OUTPUT_SSTL15_I F0B5 F3B6 F5B5 F7B5
+OUTPUT_SSTL15_II F0B5 F4B6 F5B5 F7B5
+OUTPUT_SSTL18D_I F0B5 F5B5 F7B5 F9B7
+OUTPUT_SSTL18D_II F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
+OUTPUT_SSTL18_I F0B5 F5B5 F7B5
+OUTPUT_SSTL18_II F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F7B5
+
+.config_enum PIOC.DRIVE
+12 !F2B6 !F3B6 !F4B6 F5B6 !F6B6
+16 F2B6 F3B6 F4B6 F5B6 !F6B6
+4 !F2B6 !F3B6 F4B6 F5B6 F6B6
+8 F2B6 F3B6 F4B6 !F5B6 !F6B6
+
+.config_enum PIOC.HYSTERESIS OFF
+OFF !F1B6
+ON F1B6
+
+.config_enum PIOC.OPENDRAIN
+OFF F2B6 F3B6 !F3B7 F4B6
+ON !F2B6 F3B7 !F3B6 !F4B6
+
+.config_enum PIOC.PULLMODE DOWN
+DOWN !F5B5 !F6B5
+NONE F5B5 !F6B5
+UP F5B5 F6B5
+
+.config_enum PIOC.SLEWRATE SLOW
+FAST F2B7
+SLOW !F2B7
+
+.config_enum PIOD.BASE_TYPE NONE
+BIDIR_HSUL12 F1B8 F4B7 F7B7 F8B7 F9B7
+BIDIR_LVCMOS12 F1B8 F4B7 F6B7
+BIDIR_LVCMOS15 F1B8 !F4B7
+BIDIR_LVCMOS18 F1B8 !F4B7
+BIDIR_LVCMOS25 F1B8 F4B7 F5B7 F5B8
+BIDIR_LVCMOS33 F1B8 F4B7 F5B7 F5B8 F6B7 F6B8 F7B8 F8B8
+BIDIR_LVTTL33 F1B8 F4B7 F5B7 F5B8 F6B7 F6B8 F7B8 F8B8
+BIDIR_SSTL135_I F1B8 F4B7 F7B7 F7B8 F8B7 F9B7
+BIDIR_SSTL135_II F1B8 F4B7 F7B7 F8B7 F8B8 F9B7
+BIDIR_SSTL15_I F1B8 F4B7 F7B7 F7B8 F8B7 F9B7
+BIDIR_SSTL15_II F1B8 F4B7 F7B7 F8B7 F8B8 F9B7
+BIDIR_SSTL18_I F1B8 F4B7 F7B7 F8B7 F9B7
+BIDIR_SSTL18_II F1B8 F4B7 F6B8 F7B7 F7B8 F8B7 F8B8 F9B7 F9B8
+INPUT_HSUL12 F1B8 F4B7 F7B7 F8B7 F9B7
+INPUT_LVCMOS12 F1B8 F4B7 F6B7
+INPUT_LVCMOS15 F1B8 !F4B7
+INPUT_LVCMOS18 F1B8 !F4B7
+INPUT_LVCMOS25 F1B8 F4B7 F5B7 F5B8
+INPUT_LVCMOS33 F1B8 F4B7 F5B7 F5B8 F6B7
+INPUT_LVTTL33 F1B8 F4B7 F5B7 F5B8 F6B7
+INPUT_SSTL135_I F1B8 F4B7 F7B7 F8B7 F9B7
+INPUT_SSTL135_II F1B8 F4B7 F7B7 F8B7 F9B7
+INPUT_SSTL15_I F1B8 F4B7 F7B7 F8B7 F9B7
+INPUT_SSTL15_II F1B8 F4B7 F7B7 F8B7 F9B7
+INPUT_SSTL18_I F1B8 F4B7 F7B7 F8B7 F9B7
+INPUT_SSTL18_II F1B8 F4B7 F7B7 F8B7 F9B7
+NONE F4B7
+OUTPUT_HSUL12 F1B8 F4B7 F9B7
+OUTPUT_LVCMOS12 F1B8 F4B7 F9B7
+OUTPUT_LVCMOS15 F1B8 F4B7 F9B7
+OUTPUT_LVCMOS18 F1B8 F4B7 F9B7
+OUTPUT_LVCMOS25 F1B8 F4B7 F9B7
+OUTPUT_LVCMOS33 F1B8 F4B7 F6B8 F7B8 F8B8 F9B7
+OUTPUT_LVTTL33 F1B8 F4B7 F6B8 F7B8 F8B8 F9B7
+OUTPUT_SSTL135_I F1B8 F4B7 F7B8 F9B7
+OUTPUT_SSTL135_II F1B8 F4B7 F8B8 F9B7
+OUTPUT_SSTL15_I F1B8 F4B7 F7B8 F9B7
+OUTPUT_SSTL15_II F1B8 F4B7 F8B8 F9B7
+OUTPUT_SSTL18_I F1B8 F4B7 F9B7
+OUTPUT_SSTL18_II F1B8 F4B7 F6B8 F7B8 F8B8 F9B7 F9B8
+
+.config_enum PIOD.DRIVE
+12 !F0B9 !F6B8 !F7B8 !F8B8 F9B8
+16 !F0B9 F6B8 F7B8 F8B8 F9B8
+4 F0B9 !F6B8 !F7B8 F8B8 F9B8
+8 !F0B9 F6B8 F7B8 F8B8 !F9B8
+
+.config_enum PIOD.HYSTERESIS OFF
+OFF !F5B8
+ON F5B8
+
+.config_enum PIOD.OPENDRAIN
+OFF F6B8 F7B8 !F7B9 F8B8
+ON !F6B8 F7B9 !F7B8 !F8B8
+
+.config_enum PIOD.PULLMODE DOWN
+DOWN !F0B8 !F9B7
+NONE !F0B8 F9B7
+UP F0B8 F9B7
+
+.config_enum PIOD.SLEWRATE SLOW
+FAST F6B9
+SLOW !F6B9
+
+
+# Fixed Connections
diff --git a/ECP5/tiledata/PICL1_DQS3/bits.db b/ECP5/tiledata/PICL1_DQS3/bits.db
index 8b13789..f134d0c 100644
--- a/ECP5/tiledata/PICL1_DQS3/bits.db
+++ b/ECP5/tiledata/PICL1_DQS3/bits.db
@@ -1 +1,349 @@
+# Routing Mux Bits
+# Non-Routing Configuration
+.config_enum PIOA.BASE_TYPE NONE
+BIDIR_BLVDS25E F0B4 F1B3 F1B4 F2B0 F4B1 F5B0 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
+BIDIR_HSUL12 F2B0 F5B0 F6B0 F7B0 F9B0
+BIDIR_HSUL12D F2B0 F5B0 F7B0 F9B0
+BIDIR_LVCMOS12 F2B0 F4B0 F9B0
+BIDIR_LVCMOS15 !F2B0 F9B0
+BIDIR_LVCMOS18 !F2B0 F9B0
+BIDIR_LVCMOS18D F1B3 F2B0 F2B1 F2B4 F5B0 F7B0 F8B1 F9B0
+BIDIR_LVCMOS25 F2B0 F3B0 F3B1 F9B0
+BIDIR_LVCMOS25D F1B3 F2B0 F5B0 F7B0 F9B0
+BIDIR_LVCMOS33 F2B0 F3B0 F3B1 F4B0 F4B1 F5B1 F6B1 F9B0
+BIDIR_LVCMOS33D F0B4 F1B3 F2B0 F4B1 F5B0 F5B1 F6B1 F7B0 F8B3 F9B0 F9B3
+BIDIR_LVDS F1B3 F2B0 F2B1 F2B4 F5B0 F7B0 F8B1 F9B0
+BIDIR_LVTTL33 F2B0 F3B0 F3B1 F4B0 F4B1 F5B1 F6B1 F9B0
+BIDIR_MLVDS25E F0B4 F1B3 F1B4 F2B0 F4B1 F5B0 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
+BIDIR_SSTL135D_I F1B3 F2B0 F5B0 F5B1 F7B0 F9B0 F9B3
+BIDIR_SSTL135D_II F1B3 F1B4 F2B0 F5B0 F6B1 F7B0 F9B0
+BIDIR_SSTL135_I F2B0 F5B0 F5B1 F6B0 F7B0 F9B0
+BIDIR_SSTL135_II F2B0 F5B0 F6B0 F6B1 F7B0 F9B0
+BIDIR_SSTL15D_I F1B3 F2B0 F5B0 F5B1 F7B0 F9B0 F9B3
+BIDIR_SSTL15D_II F1B3 F1B4 F2B0 F5B0 F6B1 F7B0 F9B0
+BIDIR_SSTL15_I F2B0 F5B0 F5B1 F6B0 F7B0 F9B0
+BIDIR_SSTL15_II F2B0 F5B0 F6B0 F6B1 F7B0 F9B0
+BIDIR_SSTL18D_I F1B3 F2B0 F5B0 F7B0 F9B0
+BIDIR_SSTL18D_II F0B4 F1B3 F1B4 F2B0 F4B1 F5B0 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
+BIDIR_SSTL18_I F2B0 F5B0 F6B0 F7B0 F9B0
+BIDIR_SSTL18_II F2B0 F4B1 F5B0 F5B1 F6B0 F6B1 F7B0 F7B1 F9B0
+INPUT_BLVDS25 F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_HSUL12 F2B0 F5B0 F6B0 F7B0 F9B0
+INPUT_HSUL12D F2B0 F5B0 F7B0 F9B0
+INPUT_LVCMOS12 F2B0 F4B0 F9B0
+INPUT_LVCMOS15 !F2B0 F9B0
+INPUT_LVCMOS18 !F2B0 F9B0
+INPUT_LVCMOS18D F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_LVCMOS25 F2B0 F3B0 F3B1 F9B0
+INPUT_LVCMOS25D F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_LVCMOS33 F2B0 F3B0 F3B1 F4B0 F9B0
+INPUT_LVCMOS33D F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_LVDS F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_LVPECL33 F2B0 F5B0 F7B0 F9B0
+INPUT_LVTTL33 F2B0 F3B0 F3B1 F4B0 F9B0
+INPUT_MLVDS25 F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SLVS F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SSTL135D_I F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SSTL135D_II F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SSTL135_I F2B0 F5B0 F6B0 F7B0 F9B0
+INPUT_SSTL135_II F2B0 F5B0 F6B0 F7B0 F9B0
+INPUT_SSTL15D_I F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SSTL15D_II F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SSTL15_I F2B0 F5B0 F6B0 F7B0 F9B0
+INPUT_SSTL15_II F2B0 F5B0 F6B0 F7B0 F9B0
+INPUT_SSTL18D_I F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SSTL18D_II F1B3 F2B0 F5B0 F7B0 F9B0
+INPUT_SSTL18_I F2B0 F5B0 F6B0 F7B0 F9B0
+INPUT_SSTL18_II F2B0 F5B0 F6B0 F7B0 F9B0
+INPUT_SUBLVDS F1B3 F2B0 F5B0 F7B0 F9B0
+NONE F2B0
+OUTPUT_BLVDS25E F0B4 F1B3 F1B4 F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
+OUTPUT_HSUL12 F2B0 F7B0 F9B0
+OUTPUT_HSUL12D F2B0 F7B0 F9B0
+OUTPUT_LVCMOS12 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS15 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS18 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS18D F1B3 F2B0 F2B1 F2B4 F7B0 F8B1 F9B0
+OUTPUT_LVCMOS25 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS25D F1B3 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS33 F2B0 F4B1 F5B1 F6B1 F7B0 F9B0
+OUTPUT_LVCMOS33D F0B4 F1B3 F2B0 F4B1 F5B1 F6B1 F7B0 F8B3 F9B0 F9B3
+OUTPUT_LVDS F1B3 F2B0 F2B1 F2B4 F7B0 F8B1 F9B0
+OUTPUT_LVDS25E F1B3 F2B0 F7B0 F9B0
+OUTPUT_LVPECL33E F0B4 F1B3 F1B4 F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
+OUTPUT_LVTTL33 F2B0 F4B1 F5B1 F6B1 F7B0 F9B0
+OUTPUT_MLVDS25E F0B4 F1B3 F1B4 F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
+OUTPUT_SSTL135D_I F1B3 F2B0 F5B1 F7B0 F9B0 F9B3
+OUTPUT_SSTL135D_II F1B3 F1B4 F2B0 F6B1 F7B0 F9B0
+OUTPUT_SSTL135_I F2B0 F5B1 F7B0 F9B0
+OUTPUT_SSTL135_II F2B0 F6B1 F7B0 F9B0
+OUTPUT_SSTL15D_I F1B3 F2B0 F5B1 F7B0 F9B0 F9B3
+OUTPUT_SSTL15D_II F1B3 F1B4 F2B0 F6B1 F7B0 F9B0
+OUTPUT_SSTL15_I F2B0 F5B1 F7B0 F9B0
+OUTPUT_SSTL15_II F2B0 F6B1 F7B0 F9B0
+OUTPUT_SSTL18D_I F1B3 F2B0 F7B0 F9B0
+OUTPUT_SSTL18D_II F0B4 F1B3 F1B4 F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
+OUTPUT_SSTL18_I F2B0 F7B0 F9B0
+OUTPUT_SSTL18_II F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F9B0
+
+.config_enum PIOA.DRIVE
+12 !F4B1 !F5B1 !F6B1 F7B1 !F8B1
+16 F4B1 F5B1 F6B1 F7B1 !F8B1
+4 !F4B1 !F5B1 F6B1 F7B1 F8B1
+8 F4B1 F5B1 F6B1 !F7B1 !F8B1
+
+.config_enum PIOA.HYSTERESIS OFF
+OFF !F3B1
+ON F3B1
+
+.config_enum PIOA.OPENDRAIN
+OFF F4B1 F5B1 !F5B2 F6B1
+ON !F4B1 !F5B1 F5B2 !F6B1
+
+.config_enum PIOA.PULLMODE DOWN
+DOWN !F7B0 !F8B0
+NONE F7B0 !F8B0
+UP F7B0 F8B0
+
+.config_enum PIOA.SLEWRATE SLOW
+FAST F4B2
+SLOW !F4B2
+
+.config_enum PIOB.BASE_TYPE NONE
+BIDIR_HSUL12 F0B3 F1B3 F3B3 F6B2 F9B2
+BIDIR_LVCMOS12 F3B3 F6B2 F8B2
+BIDIR_LVCMOS15 F3B3 !F6B2
+BIDIR_LVCMOS18 F3B3 !F6B2
+BIDIR_LVCMOS25 F3B3 F6B2 F7B2 F7B3
+BIDIR_LVCMOS33 F0B4 F3B3 F6B2 F7B2 F7B3 F8B2 F8B3 F9B3
+BIDIR_LVTTL33 F0B4 F3B3 F6B2 F7B2 F7B3 F8B2 F8B3 F9B3
+BIDIR_SSTL135_I F0B3 F1B3 F3B3 F6B2 F9B2 F9B3
+BIDIR_SSTL135_II F0B3 F0B4 F1B3 F3B3 F6B2 F9B2
+BIDIR_SSTL15_I F0B3 F1B3 F3B3 F6B2 F9B2 F9B3
+BIDIR_SSTL15_II F0B3 F0B4 F1B3 F3B3 F6B2 F9B2
+BIDIR_SSTL18_I F0B3 F1B3 F3B3 F6B2 F9B2
+BIDIR_SSTL18_II F0B3 F0B4 F1B3 F1B4 F3B3 F6B2 F8B3 F9B2 F9B3
+INPUT_HSUL12 F0B3 F1B3 F3B3 F6B2 F9B2
+INPUT_LVCMOS12 F3B3 F6B2 F8B2
+INPUT_LVCMOS15 F3B3 !F6B2
+INPUT_LVCMOS18 F3B3 !F6B2
+INPUT_LVCMOS25 F3B3 F6B2 F7B2 F7B3
+INPUT_LVCMOS33 F3B3 F6B2 F7B2 F7B3 F8B2
+INPUT_LVTTL33 F3B3 F6B2 F7B2 F7B3 F8B2
+INPUT_SSTL135_I F0B3 F1B3 F3B3 F6B2 F9B2
+INPUT_SSTL135_II F0B3 F1B3 F3B3 F6B2 F9B2
+INPUT_SSTL15_I F0B3 F1B3 F3B3 F6B2 F9B2
+INPUT_SSTL15_II F0B3 F1B3 F3B3 F6B2 F9B2
+INPUT_SSTL18_I F0B3 F1B3 F3B3 F6B2 F9B2
+INPUT_SSTL18_II F0B3 F1B3 F3B3 F6B2 F9B2
+NONE F6B2
+OUTPUT_HSUL12 F1B3 F3B3 F6B2
+OUTPUT_LVCMOS12 F1B3 F3B3 F6B2
+OUTPUT_LVCMOS15 F1B3 F3B3 F6B2
+OUTPUT_LVCMOS18 F1B3 F3B3 F6B2
+OUTPUT_LVCMOS25 F1B3 F3B3 F6B2
+OUTPUT_LVCMOS33 F0B4 F1B3 F3B3 F6B2 F8B3 F9B3
+OUTPUT_LVTTL33 F0B4 F1B3 F3B3 F6B2 F8B3 F9B3
+OUTPUT_SSTL135_I F1B3 F3B3 F6B2 F9B3
+OUTPUT_SSTL135_II F0B4 F1B3 F3B3 F6B2
+OUTPUT_SSTL15_I F1B3 F3B3 F6B2 F9B3
+OUTPUT_SSTL15_II F0B4 F1B3 F3B3 F6B2
+OUTPUT_SSTL18_I F1B3 F3B3 F6B2
+OUTPUT_SSTL18_II F0B4 F1B3 F1B4 F3B3 F6B2 F8B3 F9B3
+
+.config_enum PIOB.DRIVE
+12 !F0B4 F1B4 !F2B4 !F8B3 !F9B3
+16 F0B4 F1B4 !F2B4 F8B3 F9B3
+4 F0B4 F1B4 F2B4 !F8B3 !F9B3
+8 F0B4 !F1B4 !F2B4 F8B3 F9B3
+
+.config_enum PIOB.HYSTERESIS OFF
+OFF !F7B3
+ON F7B3
+
+.config_enum PIOB.OPENDRAIN
+OFF F0B4 F8B3 F9B3 !F9B4
+ON !F0B4 !F8B3 F9B4 !F9B3
+
+.config_enum PIOB.PULLMODE DOWN
+DOWN !F1B3 !F2B3
+NONE F1B3 !F2B3
+UP F1B3 F2B3
+
+.config_enum PIOB.SLEWRATE SLOW
+FAST F8B4
+SLOW !F8B4
+
+.config_enum PIOC.BASE_TYPE NONE
+BIDIR_BLVDS25E F0B5 F2B6 F3B5 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
+BIDIR_HSUL12 F0B5 F3B5 F4B5 F5B5 F7B5
+BIDIR_HSUL12D F0B5 F3B5 F5B5 F7B5
+BIDIR_LVCMOS12 F0B5 F2B5 F7B5
+BIDIR_LVCMOS15 !F0B5 F7B5
+BIDIR_LVCMOS18 !F0B5 F7B5
+BIDIR_LVCMOS25 F0B5 F1B5 F1B6 F7B5
+BIDIR_LVCMOS25D F0B5 F3B5 F5B5 F7B5 F9B7
+BIDIR_LVCMOS33 F0B5 F1B5 F1B6 F2B5 F2B6 F3B6 F4B6 F7B5
+BIDIR_LVCMOS33D F0B5 F2B6 F3B5 F3B6 F4B6 F5B5 F6B8 F7B5 F7B8 F8B8 F9B7
+BIDIR_LVTTL33 F0B5 F1B5 F1B6 F2B5 F2B6 F3B6 F4B6 F7B5
+BIDIR_MLVDS25E F0B5 F2B6 F3B5 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
+BIDIR_SSTL135D_I F0B5 F3B5 F3B6 F5B5 F7B5 F7B8 F9B7
+BIDIR_SSTL135D_II F0B5 F3B5 F4B6 F5B5 F7B5 F9B7 F9B8
+BIDIR_SSTL135_I F0B5 F3B5 F3B6 F4B5 F5B5 F7B5
+BIDIR_SSTL135_II F0B5 F3B5 F4B5 F4B6 F5B5 F7B5
+BIDIR_SSTL15D_I F0B5 F3B5 F3B6 F5B5 F7B5 F7B8 F9B7
+BIDIR_SSTL15D_II F0B5 F3B5 F4B6 F5B5 F7B5 F9B7 F9B8
+BIDIR_SSTL15_I F0B5 F3B5 F3B6 F4B5 F5B5 F7B5
+BIDIR_SSTL15_II F0B5 F3B5 F4B5 F4B6 F5B5 F7B5
+BIDIR_SSTL18D_I F0B5 F3B5 F5B5 F7B5 F9B7
+BIDIR_SSTL18D_II F0B5 F2B6 F3B5 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
+BIDIR_SSTL18_I F0B5 F3B5 F4B5 F5B5 F7B5
+BIDIR_SSTL18_II F0B5 F2B6 F3B5 F3B6 F4B5 F4B6 F5B5 F5B6 F7B5
+INPUT_BLVDS25 F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_HSUL12 F0B5 F3B5 F4B5 F5B5 F7B5
+INPUT_HSUL12D F0B5 F3B5 F5B5 F7B5
+INPUT_LVCMOS12 F0B5 F2B5 F7B5
+INPUT_LVCMOS15 !F0B5 F7B5
+INPUT_LVCMOS18 !F0B5 F7B5
+INPUT_LVCMOS18D F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_LVCMOS25 F0B5 F1B5 F1B6 F7B5
+INPUT_LVCMOS25D F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_LVCMOS33 F0B5 F1B5 F1B6 F2B5 F7B5
+INPUT_LVCMOS33D F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_LVDS F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_LVPECL33 F0B5 F3B5 F5B5 F7B5
+INPUT_LVTTL33 F0B5 F1B5 F1B6 F2B5 F7B5
+INPUT_MLVDS25 F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SLVS F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SSTL135D_I F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SSTL135D_II F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SSTL135_I F0B5 F3B5 F4B5 F5B5 F7B5
+INPUT_SSTL135_II F0B5 F3B5 F4B5 F5B5 F7B5
+INPUT_SSTL15D_I F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SSTL15D_II F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SSTL15_I F0B5 F3B5 F4B5 F5B5 F7B5
+INPUT_SSTL15_II F0B5 F3B5 F4B5 F5B5 F7B5
+INPUT_SSTL18D_I F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SSTL18D_II F0B5 F3B5 F5B5 F7B5 F9B7
+INPUT_SSTL18_I F0B5 F3B5 F4B5 F5B5 F7B5
+INPUT_SSTL18_II F0B5 F3B5 F4B5 F5B5 F7B5
+INPUT_SUBLVDS F0B5 F3B5 F5B5 F7B5 F9B7
+NONE F0B5
+OUTPUT_BLVDS25E F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
+OUTPUT_HSUL12 F0B5 F5B5 F7B5
+OUTPUT_HSUL12D F0B5 F5B5 F7B5
+OUTPUT_LVCMOS12 F0B5 F5B5 F7B5
+OUTPUT_LVCMOS15 F0B5 F5B5 F7B5
+OUTPUT_LVCMOS18 F0B5 F5B5 F7B5
+OUTPUT_LVCMOS25 F0B5 F5B5 F7B5
+OUTPUT_LVCMOS25D F0B5 F5B5 F7B5 F9B7
+OUTPUT_LVCMOS33 F0B5 F2B6 F3B6 F4B6 F5B5 F7B5
+OUTPUT_LVCMOS33D F0B5 F2B6 F3B6 F4B6 F5B5 F6B8 F7B5 F7B8 F8B8 F9B7
+OUTPUT_LVDS25E F0B5 F5B5 F7B5 F9B7
+OUTPUT_LVPECL33E F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
+OUTPUT_LVTTL33 F0B5 F2B6 F3B6 F4B6 F5B5 F7B5
+OUTPUT_MLVDS25E F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
+OUTPUT_SSTL135D_I F0B5 F3B6 F5B5 F7B5 F7B8 F9B7
+OUTPUT_SSTL135D_II F0B5 F4B6 F5B5 F7B5 F9B7 F9B8
+OUTPUT_SSTL135_I F0B5 F3B6 F5B5 F7B5
+OUTPUT_SSTL135_II F0B5 F4B6 F5B5 F7B5
+OUTPUT_SSTL15D_I F0B5 F3B6 F5B5 F7B5 F7B8 F9B7
+OUTPUT_SSTL15D_II F0B5 F4B6 F5B5 F7B5 F9B7 F9B8
+OUTPUT_SSTL15_I F0B5 F3B6 F5B5 F7B5
+OUTPUT_SSTL15_II F0B5 F4B6 F5B5 F7B5
+OUTPUT_SSTL18D_I F0B5 F5B5 F7B5 F9B7
+OUTPUT_SSTL18D_II F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
+OUTPUT_SSTL18_I F0B5 F5B5 F7B5
+OUTPUT_SSTL18_II F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F7B5
+
+.config_enum PIOC.DRIVE
+12 !F2B6 !F3B6 !F4B6 F5B6 !F6B6
+16 F2B6 F3B6 F4B6 F5B6 !F6B6
+4 !F2B6 !F3B6 F4B6 F5B6 F6B6
+8 F2B6 F3B6 F4B6 !F5B6 !F6B6
+
+.config_enum PIOC.HYSTERESIS OFF
+OFF !F1B6
+ON F1B6
+
+.config_enum PIOC.OPENDRAIN
+OFF F2B6 F3B6 !F3B7 F4B6
+ON !F2B6 !F3B6 F3B7 !F4B6
+
+.config_enum PIOC.PULLMODE DOWN
+DOWN !F5B5 !F6B5
+NONE F5B5 !F6B5
+UP F5B5 F6B5
+
+.config_enum PIOC.SLEWRATE SLOW
+FAST F2B7
+SLOW !F2B7
+
+.config_enum PIOD.BASE_TYPE NONE
+BIDIR_HSUL12 F1B8 F4B7 F7B7 F8B7 F9B7
+BIDIR_LVCMOS12 F1B8 F4B7 F6B7
+BIDIR_LVCMOS15 F1B8 !F4B7
+BIDIR_LVCMOS18 F1B8 !F4B7
+BIDIR_LVCMOS25 F1B8 F4B7 F5B7 F5B8
+BIDIR_LVCMOS33 F1B8 F4B7 F5B7 F5B8 F6B7 F6B8 F7B8 F8B8
+BIDIR_LVTTL33 F1B8 F4B7 F5B7 F5B8 F6B7 F6B8 F7B8 F8B8
+BIDIR_SSTL135_I F1B8 F4B7 F7B7 F7B8 F8B7 F9B7
+BIDIR_SSTL135_II F1B8 F4B7 F7B7 F8B7 F8B8 F9B7
+BIDIR_SSTL15_I F1B8 F4B7 F7B7 F7B8 F8B7 F9B7
+BIDIR_SSTL15_II F1B8 F4B7 F7B7 F8B7 F8B8 F9B7
+BIDIR_SSTL18_I F1B8 F4B7 F7B7 F8B7 F9B7
+BIDIR_SSTL18_II F1B8 F4B7 F6B8 F7B7 F7B8 F8B7 F8B8 F9B7 F9B8
+INPUT_HSUL12 F1B8 F4B7 F7B7 F8B7 F9B7
+INPUT_LVCMOS12 F1B8 F4B7 F6B7
+INPUT_LVCMOS15 F1B8 !F4B7
+INPUT_LVCMOS18 F1B8 !F4B7
+INPUT_LVCMOS25 F1B8 F4B7 F5B7 F5B8
+INPUT_LVCMOS33 F1B8 F4B7 F5B7 F5B8 F6B7
+INPUT_LVTTL33 F1B8 F4B7 F5B7 F5B8 F6B7
+INPUT_SSTL135_I F1B8 F4B7 F7B7 F8B7 F9B7
+INPUT_SSTL135_II F1B8 F4B7 F7B7 F8B7 F9B7
+INPUT_SSTL15_I F1B8 F4B7 F7B7 F8B7 F9B7
+INPUT_SSTL15_II F1B8 F4B7 F7B7 F8B7 F9B7
+INPUT_SSTL18_I F1B8 F4B7 F7B7 F8B7 F9B7
+INPUT_SSTL18_II F1B8 F4B7 F7B7 F8B7 F9B7
+NONE F4B7
+OUTPUT_HSUL12 F1B8 F4B7 F9B7
+OUTPUT_LVCMOS12 F1B8 F4B7 F9B7
+OUTPUT_LVCMOS15 F1B8 F4B7 F9B7
+OUTPUT_LVCMOS18 F1B8 F4B7 F9B7
+OUTPUT_LVCMOS25 F1B8 F4B7 F9B7
+OUTPUT_LVCMOS33 F1B8 F4B7 F6B8 F7B8 F8B8 F9B7
+OUTPUT_LVTTL33 F1B8 F4B7 F6B8 F7B8 F8B8 F9B7
+OUTPUT_SSTL135_I F1B8 F4B7 F7B8 F9B7
+OUTPUT_SSTL135_II F1B8 F4B7 F8B8 F9B7
+OUTPUT_SSTL15_I F1B8 F4B7 F7B8 F9B7
+OUTPUT_SSTL15_II F1B8 F4B7 F8B8 F9B7
+OUTPUT_SSTL18_I F1B8 F4B7 F9B7
+OUTPUT_SSTL18_II F1B8 F4B7 F6B8 F7B8 F8B8 F9B7 F9B8
+
+.config_enum PIOD.DRIVE
+12 !F0B9 !F6B8 !F7B8 !F8B8 F9B8
+16 !F0B9 F6B8 F7B8 F8B8 F9B8
+4 F0B9 !F6B8 !F7B8 F8B8 F9B8
+8 !F0B9 F6B8 F7B8 F8B8 !F9B8
+
+.config_enum PIOD.HYSTERESIS OFF
+OFF !F5B8
+ON F5B8
+
+.config_enum PIOD.OPENDRAIN
+OFF F6B8 F7B8 !F7B9 F8B8
+ON !F6B8 !F7B8 F7B9 !F8B8
+
+.config_enum PIOD.PULLMODE DOWN
+DOWN !F0B8 !F9B7
+NONE !F0B8 F9B7
+UP F0B8 F9B7
+
+.config_enum PIOD.SLEWRATE SLOW
+FAST F6B9
+SLOW !F6B9
+
+
+# Fixed Connections
diff --git a/ECP5/tiledata/PICL2_DQS1/bits.db b/ECP5/tiledata/PICL2_DQS1/bits.db
index 8b13789..c654018 100644
--- a/ECP5/tiledata/PICL2_DQS1/bits.db
+++ b/ECP5/tiledata/PICL2_DQS1/bits.db
@@ -1 +1,129 @@
+# Routing Mux Bits
+# Non-Routing Configuration
+.config_enum PIOC.BASE_TYPE INPUT_LVCMOS18D
+BIDIR_BLVDS25E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_HSUL12 F1B4 F2B4
+BIDIR_HSUL12D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_LVCMOS12 F1B4 F2B4
+BIDIR_LVCMOS15 F1B4 F2B4
+BIDIR_LVCMOS18 F1B4 F2B4
+BIDIR_LVCMOS25 F1B4 F2B4
+BIDIR_LVCMOS25D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_LVCMOS33 F1B4 F2B4
+BIDIR_LVCMOS33D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_LVTTL33 F1B4 F2B4
+BIDIR_MLVDS25E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_SSTL135D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_SSTL135D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_SSTL135_I F1B4 F2B4
+BIDIR_SSTL135_II F1B4 F2B4
+BIDIR_SSTL15D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_SSTL15D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_SSTL15_I F1B4 F2B4
+BIDIR_SSTL15_II F1B4 F2B4
+BIDIR_SSTL18D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_SSTL18D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+BIDIR_SSTL18_I F1B4 F2B4
+BIDIR_SSTL18_II F1B4 F2B4
+INPUT_BLVDS25
+INPUT_HSUL12
+INPUT_HSUL12D
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS18D
+INPUT_LVCMOS25
+INPUT_LVCMOS25D
+INPUT_LVCMOS33
+INPUT_LVCMOS33D
+INPUT_LVDS
+INPUT_LVPECL33
+INPUT_LVTTL33
+INPUT_MLVDS25
+INPUT_SLVS
+INPUT_SSTL135D_I
+INPUT_SSTL135D_II
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15D_I
+INPUT_SSTL15D_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18D_I
+INPUT_SSTL18D_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+INPUT_SUBLVDS
+NONE
+OUTPUT_BLVDS25E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_HSUL12 F1B4 F2B4
+OUTPUT_HSUL12D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_LVCMOS12 F1B4 F2B4
+OUTPUT_LVCMOS15 F1B4 F2B4
+OUTPUT_LVCMOS18 F1B4 F2B4
+OUTPUT_LVCMOS25 F1B4 F2B4
+OUTPUT_LVCMOS25D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_LVCMOS33 F1B4 F2B4
+OUTPUT_LVCMOS33D F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_LVDS25E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_LVPECL33E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_LVTTL33 F1B4 F2B4
+OUTPUT_MLVDS25E F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_SSTL135D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_SSTL135D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_SSTL135_I F1B4 F2B4
+OUTPUT_SSTL135_II F1B4 F2B4
+OUTPUT_SSTL15D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_SSTL15D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_SSTL15_I F1B4 F2B4
+OUTPUT_SSTL15_II F1B4 F2B4
+OUTPUT_SSTL18D_I F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_SSTL18D_II F1B1 F1B4 F2B4 F3B6 F4B9 F5B9
+OUTPUT_SSTL18_I F1B4 F2B4
+OUTPUT_SSTL18_II F1B4 F2B4
+
+.config_enum PIOD.BASE_TYPE INPUT_HSUL12
+BIDIR_HSUL12 F4B9 F5B9
+BIDIR_LVCMOS12 F4B9 F5B9
+BIDIR_LVCMOS15 F4B9 F5B9
+BIDIR_LVCMOS18 F4B9 F5B9
+BIDIR_LVCMOS25 F4B9 F5B9
+BIDIR_LVCMOS33 F4B9 F5B9
+BIDIR_LVTTL33 F4B9 F5B9
+BIDIR_SSTL135_I F4B9 F5B9
+BIDIR_SSTL135_II F4B9 F5B9
+BIDIR_SSTL15_I F4B9 F5B9
+BIDIR_SSTL15_II F4B9 F5B9
+BIDIR_SSTL18_I F4B9 F5B9
+BIDIR_SSTL18_II F4B9 F5B9
+INPUT_HSUL12
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS25
+INPUT_LVCMOS33
+INPUT_LVTTL33
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+NONE
+OUTPUT_HSUL12 F4B9 F5B9
+OUTPUT_LVCMOS12 F4B9 F5B9
+OUTPUT_LVCMOS15 F4B9 F5B9
+OUTPUT_LVCMOS18 F4B9 F5B9
+OUTPUT_LVCMOS25 F4B9 F5B9
+OUTPUT_LVCMOS33 F4B9 F5B9
+OUTPUT_LVTTL33 F4B9 F5B9
+OUTPUT_SSTL135_I F4B9 F5B9
+OUTPUT_SSTL135_II F4B9 F5B9
+OUTPUT_SSTL15_I F4B9 F5B9
+OUTPUT_SSTL15_II F4B9 F5B9
+OUTPUT_SSTL18_I F4B9 F5B9
+OUTPUT_SSTL18_II F4B9 F5B9
+
+
+# Fixed Connections
diff --git a/ECP5/tiledata/PICR0/bits.db b/ECP5/tiledata/PICR0/bits.db
index 8b13789..4ac1402 100644
--- a/ECP5/tiledata/PICR0/bits.db
+++ b/ECP5/tiledata/PICR0/bits.db
@@ -1 +1,133 @@
+# Routing Mux Bits
+# Non-Routing Configuration
+.config_enum PIOA.BASE_TYPE INPUT_LVCMOS18D
+BIDIR_BLVDS25E F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_HSUL12 F7B4 F8B4
+BIDIR_HSUL12D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_LVCMOS12 F7B4 F8B4
+BIDIR_LVCMOS15 F7B4 F8B4
+BIDIR_LVCMOS18 F7B4 F8B4
+BIDIR_LVCMOS18D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_LVCMOS25 F7B4 F8B4
+BIDIR_LVCMOS25D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_LVCMOS33 F7B4 F8B4
+BIDIR_LVCMOS33D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_LVDS F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_LVTTL33 F7B4 F8B4
+BIDIR_MLVDS25E F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_SSTL135D_I F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_SSTL135D_II F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_SSTL135_I F7B4 F8B4
+BIDIR_SSTL135_II F7B4 F8B4
+BIDIR_SSTL15D_I F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_SSTL15D_II F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_SSTL15_I F7B4 F8B4
+BIDIR_SSTL15_II F7B4 F8B4
+BIDIR_SSTL18D_I F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_SSTL18D_II F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+BIDIR_SSTL18_I F7B4 F8B4
+BIDIR_SSTL18_II F7B4 F8B4
+INPUT_BLVDS25
+INPUT_HSUL12
+INPUT_HSUL12D
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS18D
+INPUT_LVCMOS25
+INPUT_LVCMOS25D
+INPUT_LVCMOS33
+INPUT_LVCMOS33D
+INPUT_LVDS
+INPUT_LVPECL33
+INPUT_LVTTL33
+INPUT_MLVDS25
+INPUT_SLVS
+INPUT_SSTL135D_I
+INPUT_SSTL135D_II
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15D_I
+INPUT_SSTL15D_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18D_I
+INPUT_SSTL18D_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+INPUT_SUBLVDS
+NONE
+OUTPUT_BLVDS25E F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_HSUL12 F7B4 F8B4
+OUTPUT_HSUL12D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_LVCMOS12 F7B4 F8B4
+OUTPUT_LVCMOS15 F7B4 F8B4
+OUTPUT_LVCMOS18 F7B4 F8B4
+OUTPUT_LVCMOS18D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_LVCMOS25 F7B4 F8B4
+OUTPUT_LVCMOS25D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_LVCMOS33 F7B4 F8B4
+OUTPUT_LVCMOS33D F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_LVDS F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_LVDS25E F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_LVPECL33E F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_LVTTL33 F7B4 F8B4
+OUTPUT_MLVDS25E F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_SSTL135D_I F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_SSTL135D_II F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_SSTL135_I F7B4 F8B4
+OUTPUT_SSTL135_II F7B4 F8B4
+OUTPUT_SSTL15D_I F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_SSTL15D_II F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_SSTL15_I F7B4 F8B4
+OUTPUT_SSTL15_II F7B4 F8B4
+OUTPUT_SSTL18D_I F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_SSTL18D_II F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
+OUTPUT_SSTL18_I F7B4 F8B4
+OUTPUT_SSTL18_II F7B4 F8B4
+
+.config_enum PIOB.BASE_TYPE INPUT_HSUL12
+BIDIR_HSUL12 F5B9 F6B9
+BIDIR_LVCMOS12 F5B9 F6B9
+BIDIR_LVCMOS15 F5B9 F6B9
+BIDIR_LVCMOS18 F5B9 F6B9
+BIDIR_LVCMOS25 F5B9 F6B9
+BIDIR_LVCMOS33 F5B9 F6B9
+BIDIR_LVTTL33 F5B9 F6B9
+BIDIR_SSTL135_I F5B9 F6B9
+BIDIR_SSTL135_II F5B9 F6B9
+BIDIR_SSTL15_I F5B9 F6B9
+BIDIR_SSTL15_II F5B9 F6B9
+BIDIR_SSTL18_I F5B9 F6B9
+BIDIR_SSTL18_II F5B9 F6B9
+INPUT_HSUL12
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS25
+INPUT_LVCMOS33
+INPUT_LVTTL33
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+NONE
+OUTPUT_HSUL12 F5B9 F6B9
+OUTPUT_LVCMOS12 F5B9 F6B9
+OUTPUT_LVCMOS15 F5B9 F6B9
+OUTPUT_LVCMOS18 F5B9 F6B9
+OUTPUT_LVCMOS25 F5B9 F6B9
+OUTPUT_LVCMOS33 F5B9 F6B9
+OUTPUT_LVTTL33 F5B9 F6B9
+OUTPUT_SSTL135_I F5B9 F6B9
+OUTPUT_SSTL135_II F5B9 F6B9
+OUTPUT_SSTL15_I F5B9 F6B9
+OUTPUT_SSTL15_II F5B9 F6B9
+OUTPUT_SSTL18_I F5B9 F6B9
+OUTPUT_SSTL18_II F5B9 F6B9
+
+
+# Fixed Connections
diff --git a/ECP5/tiledata/PICR1/bits.db b/ECP5/tiledata/PICR1/bits.db
index 8b13789..ca91418 100644
--- a/ECP5/tiledata/PICR1/bits.db
+++ b/ECP5/tiledata/PICR1/bits.db
@@ -1 +1,349 @@
+# Routing Mux Bits
+# Non-Routing Configuration
+.config_enum PIOA.BASE_TYPE NONE
+BIDIR_BLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+BIDIR_HSUL12 F0B0 F2B0 F3B0 F4B0 F7B0
+BIDIR_HSUL12D F0B0 F2B0 F4B0 F7B0
+BIDIR_LVCMOS12 F0B0 F5B0 F7B0
+BIDIR_LVCMOS15 F0B0 !F7B0
+BIDIR_LVCMOS18 F0B0 !F7B0
+BIDIR_LVCMOS18D F0B0 F1B1 F2B0 F4B0 F7B0 F7B1 F7B4 F8B3
+BIDIR_LVCMOS25 F0B0 F6B0 F6B1 F7B0
+BIDIR_LVCMOS25D F0B0 F2B0 F4B0 F7B0 F8B3
+BIDIR_LVCMOS33 F0B0 F3B1 F4B1 F5B0 F5B1 F6B0 F6B1 F7B0
+BIDIR_LVCMOS33D F0B0 F0B3 F1B3 F2B0 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F9B4
+BIDIR_LVDS F0B0 F1B1 F2B0 F4B0 F7B0 F7B1 F7B4 F8B3
+BIDIR_LVTTL33 F0B0 F3B1 F4B1 F5B0 F5B1 F6B0 F6B1 F7B0
+BIDIR_MLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+BIDIR_SSTL135D_I F0B0 F0B3 F2B0 F4B0 F4B1 F7B0 F8B3
+BIDIR_SSTL135D_II F0B0 F2B0 F3B1 F4B0 F7B0 F8B3 F8B4
+BIDIR_SSTL135_I F0B0 F2B0 F3B0 F4B0 F4B1 F7B0
+BIDIR_SSTL135_II F0B0 F2B0 F3B0 F3B1 F4B0 F7B0
+BIDIR_SSTL15D_I F0B0 F0B3 F2B0 F4B0 F4B1 F7B0 F8B3
+BIDIR_SSTL15D_II F0B0 F2B0 F3B1 F4B0 F7B0 F8B3 F8B4
+BIDIR_SSTL15_I F0B0 F2B0 F3B0 F4B0 F4B1 F7B0
+BIDIR_SSTL15_II F0B0 F2B0 F3B0 F3B1 F4B0 F7B0
+BIDIR_SSTL18D_I F0B0 F2B0 F4B0 F7B0 F8B3
+BIDIR_SSTL18D_II F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+BIDIR_SSTL18_I F0B0 F2B0 F3B0 F4B0 F7B0
+BIDIR_SSTL18_II F0B0 F2B0 F2B1 F3B0 F3B1 F4B0 F4B1 F5B1 F7B0
+INPUT_BLVDS25 F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_HSUL12 F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_HSUL12D F0B0 F2B0 F4B0 F7B0
+INPUT_LVCMOS12 F0B0 F5B0 F7B0
+INPUT_LVCMOS15 F0B0 !F7B0
+INPUT_LVCMOS18 F0B0 !F7B0
+INPUT_LVCMOS18D F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_LVCMOS25 F0B0 F6B0 F6B1 F7B0
+INPUT_LVCMOS25D F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_LVCMOS33 F0B0 F5B0 F6B0 F6B1 F7B0
+INPUT_LVCMOS33D F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_LVDS F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_LVPECL33 F0B0 F2B0 F4B0 F7B0
+INPUT_LVTTL33 F0B0 F5B0 F6B0 F6B1 F7B0
+INPUT_MLVDS25 F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SLVS F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL135D_I F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL135D_II F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL135_I F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SSTL135_II F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SSTL15D_I F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL15D_II F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL15_I F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SSTL15_II F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SSTL18D_I F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL18D_II F0B0 F2B0 F4B0 F7B0 F8B3
+INPUT_SSTL18_I F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SSTL18_II F0B0 F2B0 F3B0 F4B0 F7B0
+INPUT_SUBLVDS F0B0 F2B0 F4B0 F7B0 F8B3
+NONE F7B0
+OUTPUT_BLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+OUTPUT_HSUL12 F0B0 F2B0 F7B0
+OUTPUT_HSUL12D F0B0 F2B0 F7B0
+OUTPUT_LVCMOS12 F0B0 F2B0 F7B0
+OUTPUT_LVCMOS15 F0B0 F2B0 F7B0
+OUTPUT_LVCMOS18 F0B0 F2B0 F7B0
+OUTPUT_LVCMOS18D F0B0 F1B1 F2B0 F7B0 F7B1 F7B4 F8B3
+OUTPUT_LVCMOS25 F0B0 F2B0 F7B0
+OUTPUT_LVCMOS25D F0B0 F2B0 F7B0 F8B3
+OUTPUT_LVCMOS33 F0B0 F2B0 F3B1 F4B1 F5B1 F7B0
+OUTPUT_LVCMOS33D F0B0 F0B3 F1B3 F2B0 F3B1 F4B1 F5B1 F7B0 F8B3 F9B4
+OUTPUT_LVDS F0B0 F1B1 F2B0 F7B0 F7B1 F7B4 F8B3
+OUTPUT_LVDS25E F0B0 F2B0 F7B0 F8B3
+OUTPUT_LVPECL33E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+OUTPUT_LVTTL33 F0B0 F2B0 F3B1 F4B1 F5B1 F7B0
+OUTPUT_MLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+OUTPUT_SSTL135D_I F0B0 F0B3 F2B0 F4B1 F7B0 F8B3
+OUTPUT_SSTL135D_II F0B0 F2B0 F3B1 F7B0 F8B3 F8B4
+OUTPUT_SSTL135_I F0B0 F2B0 F4B1 F7B0
+OUTPUT_SSTL135_II F0B0 F2B0 F3B1 F7B0
+OUTPUT_SSTL15D_I F0B0 F0B3 F2B0 F4B1 F7B0 F8B3
+OUTPUT_SSTL15D_II F0B0 F2B0 F3B1 F7B0 F8B3 F8B4
+OUTPUT_SSTL15_I F0B0 F2B0 F4B1 F7B0
+OUTPUT_SSTL15_II F0B0 F2B0 F3B1 F7B0
+OUTPUT_SSTL18D_I F0B0 F2B0 F7B0 F8B3
+OUTPUT_SSTL18D_II F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
+OUTPUT_SSTL18_I F0B0 F2B0 F7B0
+OUTPUT_SSTL18_II F0B0 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0
+
+.config_enum PIOA.DRIVE
+12 !F1B1 F2B1 !F3B1 !F4B1 !F5B1
+16 !F1B1 F2B1 F3B1 F4B1 F5B1
+4 F1B1 F2B1 F3B1 !F4B1 !F5B1
+8 !F1B1 !F2B1 F3B1 F4B1 F5B1
+
+.config_enum PIOA.HYSTERESIS OFF
+OFF !F6B1
+ON F6B1
+
+.config_enum PIOA.OPENDRAIN
+OFF F3B1 F4B1 !F4B2 F5B1
+ON !F3B1 !F4B1 F4B2 !F5B1
+
+.config_enum PIOA.PULLMODE DOWN
+DOWN !F1B0 !F2B0
+NONE !F1B0 F2B0
+UP F1B0 F2B0
+
+.config_enum PIOA.SLEWRATE SLOW
+FAST F5B2
+SLOW !F5B2
+
+.config_enum PIOB.BASE_TYPE NONE
+BIDIR_HSUL12 F0B2 F3B2 F6B3 F8B3 F9B3
+BIDIR_LVCMOS12 F1B2 F3B2 F6B3
+BIDIR_LVCMOS15 !F3B2 F6B3
+BIDIR_LVCMOS18 !F3B2 F6B3
+BIDIR_LVCMOS25 F2B2 F2B3 F3B2 F6B3
+BIDIR_LVCMOS33 F0B3 F1B2 F1B3 F2B2 F2B3 F3B2 F6B3 F9B4
+BIDIR_LVTTL33 F0B3 F1B2 F1B3 F2B2 F2B3 F3B2 F6B3 F9B4
+BIDIR_SSTL135_I F0B2 F0B3 F3B2 F6B3 F8B3 F9B3
+BIDIR_SSTL135_II F0B2 F3B2 F6B3 F8B3 F9B3 F9B4
+BIDIR_SSTL15_I F0B2 F0B3 F3B2 F6B3 F8B3 F9B3
+BIDIR_SSTL15_II F0B2 F3B2 F6B3 F8B3 F9B3 F9B4
+BIDIR_SSTL18_I F0B2 F3B2 F6B3 F8B3 F9B3
+BIDIR_SSTL18_II F0B2 F0B3 F1B3 F3B2 F6B3 F8B3 F8B4 F9B3 F9B4
+INPUT_HSUL12 F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_LVCMOS12 F1B2 F3B2 F6B3
+INPUT_LVCMOS15 !F3B2 F6B3
+INPUT_LVCMOS18 !F3B2 F6B3
+INPUT_LVCMOS25 F2B2 F2B3 F3B2 F6B3
+INPUT_LVCMOS33 F1B2 F2B2 F2B3 F3B2 F6B3
+INPUT_LVTTL33 F1B2 F2B2 F2B3 F3B2 F6B3
+INPUT_SSTL135_I F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_SSTL135_II F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_SSTL15_I F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_SSTL15_II F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_SSTL18_I F0B2 F3B2 F6B3 F8B3 F9B3
+INPUT_SSTL18_II F0B2 F3B2 F6B3 F8B3 F9B3
+NONE F3B2
+OUTPUT_HSUL12 F3B2 F6B3 F8B3
+OUTPUT_LVCMOS12 F3B2 F6B3 F8B3
+OUTPUT_LVCMOS15 F3B2 F6B3 F8B3
+OUTPUT_LVCMOS18 F3B2 F6B3 F8B3
+OUTPUT_LVCMOS25 F3B2 F6B3 F8B3
+OUTPUT_LVCMOS33 F0B3 F1B3 F3B2 F6B3 F8B3 F9B4
+OUTPUT_LVTTL33 F0B3 F1B3 F3B2 F6B3 F8B3 F9B4
+OUTPUT_SSTL135_I F0B3 F3B2 F6B3 F8B3
+OUTPUT_SSTL135_II F3B2 F6B3 F8B3 F9B4
+OUTPUT_SSTL15_I F0B3 F3B2 F6B3 F8B3
+OUTPUT_SSTL15_II F3B2 F6B3 F8B3 F9B4
+OUTPUT_SSTL18_I F3B2 F6B3 F8B3
+OUTPUT_SSTL18_II F0B3 F1B3 F3B2 F6B3 F8B3 F8B4 F9B4
+
+.config_enum PIOB.DRIVE
+12 !F0B3 !F1B3 !F7B4 F8B4 !F9B4
+16 F0B3 F1B3 !F7B4 F8B4 F9B4
+4 !F0B3 !F1B3 F7B4 F8B4 F9B4
+8 F0B3 F1B3 !F7B4 !F8B4 F9B4
+
+.config_enum PIOB.HYSTERESIS OFF
+OFF !F2B3
+ON F2B3
+
+.config_enum PIOB.OPENDRAIN
+OFF F0B3 !F0B4 F1B3 F9B4
+ON !F0B3 F0B4 !F1B3 !F9B4
+
+.config_enum PIOB.PULLMODE DOWN
+DOWN !F7B3 !F8B3
+NONE !F7B3 F8B3
+UP F7B3 F8B3
+
+.config_enum PIOB.SLEWRATE SLOW
+FAST F1B4
+SLOW !F1B4
+
+.config_enum PIOC.BASE_TYPE NONE
+BIDIR_BLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B5 F6B6 F7B6 F9B5
+BIDIR_HSUL12 F2B5 F4B5 F5B5 F6B5 F9B5
+BIDIR_HSUL12D F2B5 F4B5 F6B5 F9B5
+BIDIR_LVCMOS12 F2B5 F7B5 F9B5
+BIDIR_LVCMOS15 F2B5 !F9B5
+BIDIR_LVCMOS18 F2B5 !F9B5
+BIDIR_LVCMOS25 F2B5 F8B5 F8B6 F9B5
+BIDIR_LVCMOS25D F0B7 F2B5 F4B5 F6B5 F9B5
+BIDIR_LVCMOS33 F2B5 F5B6 F6B6 F7B5 F7B6 F8B5 F8B6 F9B5
+BIDIR_LVCMOS33D F0B7 F1B8 F2B5 F2B8 F3B8 F4B5 F5B6 F6B5 F6B6 F7B6 F9B5
+BIDIR_LVTTL33 F2B5 F5B6 F6B6 F7B5 F7B6 F8B5 F8B6 F9B5
+BIDIR_MLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B5 F6B6 F7B6 F9B5
+BIDIR_SSTL135D_I F0B7 F2B5 F2B8 F4B5 F6B5 F6B6 F9B5
+BIDIR_SSTL135D_II F0B7 F0B8 F2B5 F4B5 F5B6 F6B5 F9B5
+BIDIR_SSTL135_I F2B5 F4B5 F5B5 F6B5 F6B6 F9B5
+BIDIR_SSTL135_II F2B5 F4B5 F5B5 F5B6 F6B5 F9B5
+BIDIR_SSTL15D_I F0B7 F2B5 F2B8 F4B5 F6B5 F6B6 F9B5
+BIDIR_SSTL15D_II F0B7 F0B8 F2B5 F4B5 F5B6 F6B5 F9B5
+BIDIR_SSTL15_I F2B5 F4B5 F5B5 F6B5 F6B6 F9B5
+BIDIR_SSTL15_II F2B5 F4B5 F5B5 F5B6 F6B5 F9B5
+BIDIR_SSTL18D_I F0B7 F2B5 F4B5 F6B5 F9B5
+BIDIR_SSTL18D_II F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B5 F6B6 F7B6 F9B5
+BIDIR_SSTL18_I F2B5 F4B5 F5B5 F6B5 F9B5
+BIDIR_SSTL18_II F2B5 F4B5 F4B6 F5B5 F5B6 F6B5 F6B6 F7B6 F9B5
+INPUT_BLVDS25 F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_HSUL12 F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_HSUL12D F2B5 F4B5 F6B5 F9B5
+INPUT_LVCMOS12 F2B5 F7B5 F9B5
+INPUT_LVCMOS15 F2B5 !F9B5
+INPUT_LVCMOS18 F2B5 !F9B5
+INPUT_LVCMOS18D F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_LVCMOS25 F2B5 F8B5 F8B6 F9B5
+INPUT_LVCMOS25D F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_LVCMOS33 F2B5 F7B5 F8B5 F8B6 F9B5
+INPUT_LVCMOS33D F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_LVDS F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_LVPECL33 F2B5 F4B5 F6B5 F9B5
+INPUT_LVTTL33 F2B5 F7B5 F8B5 F8B6 F9B5
+INPUT_MLVDS25 F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SLVS F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL135D_I F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL135D_II F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL135_I F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SSTL135_II F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SSTL15D_I F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL15D_II F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL15_I F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SSTL15_II F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SSTL18D_I F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL18D_II F0B7 F2B5 F4B5 F6B5 F9B5
+INPUT_SSTL18_I F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SSTL18_II F2B5 F4B5 F5B5 F6B5 F9B5
+INPUT_SUBLVDS F0B7 F2B5 F4B5 F6B5 F9B5
+NONE F9B5
+OUTPUT_BLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
+OUTPUT_HSUL12 F2B5 F4B5 F9B5
+OUTPUT_HSUL12D F2B5 F4B5 F9B5
+OUTPUT_LVCMOS12 F2B5 F4B5 F9B5
+OUTPUT_LVCMOS15 F2B5 F4B5 F9B5
+OUTPUT_LVCMOS18 F2B5 F4B5 F9B5
+OUTPUT_LVCMOS25 F2B5 F4B5 F9B5
+OUTPUT_LVCMOS25D F0B7 F2B5 F4B5 F9B5
+OUTPUT_LVCMOS33 F2B5 F4B5 F5B6 F6B6 F7B6 F9B5
+OUTPUT_LVCMOS33D F0B7 F1B8 F2B5 F2B8 F3B8 F4B5 F5B6 F6B6 F7B6 F9B5
+OUTPUT_LVDS25E F0B7 F2B5 F4B5 F9B5
+OUTPUT_LVPECL33E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
+OUTPUT_LVTTL33 F2B5 F4B5 F5B6 F6B6 F7B6 F9B5
+OUTPUT_MLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
+OUTPUT_SSTL135D_I F0B7 F2B5 F2B8 F4B5 F6B6 F9B5
+OUTPUT_SSTL135D_II F0B7 F0B8 F2B5 F4B5 F5B6 F9B5
+OUTPUT_SSTL135_I F2B5 F4B5 F6B6 F9B5
+OUTPUT_SSTL135_II F2B5 F4B5 F5B6 F9B5
+OUTPUT_SSTL15D_I F0B7 F2B5 F2B8 F4B5 F6B6 F9B5
+OUTPUT_SSTL15D_II F0B7 F0B8 F2B5 F4B5 F5B6 F9B5
+OUTPUT_SSTL15_I F2B5 F4B5 F6B6 F9B5
+OUTPUT_SSTL15_II F2B5 F4B5 F5B6 F9B5
+OUTPUT_SSTL18D_I F0B7 F2B5 F4B5 F9B5
+OUTPUT_SSTL18D_II F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
+OUTPUT_SSTL18_I F2B5 F4B5 F9B5
+OUTPUT_SSTL18_II F2B5 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
+
+.config_enum PIOC.DRIVE
+12 !F3B6 F4B6 !F5B6 !F6B6 !F7B6
+16 !F3B6 F4B6 F5B6 F6B6 F7B6
+4 F3B6 F4B6 F5B6 !F6B6 !F7B6
+8 !F3B6 !F4B6 F5B6 F6B6 F7B6
+
+.config_enum PIOC.HYSTERESIS OFF
+OFF !F8B6
+ON F8B6
+
+.config_enum PIOC.OPENDRAIN
+OFF F5B6 F6B6 !F6B7 F7B6
+ON !F5B6 !F6B6 F6B7 !F7B6
+
+.config_enum PIOC.PULLMODE DOWN
+DOWN !F3B5 !F4B5
+NONE !F3B5 F4B5
+UP F3B5 F4B5
+
+.config_enum PIOC.SLEWRATE SLOW
+FAST F7B7
+SLOW !F7B7
+
+.config_enum PIOD.BASE_TYPE NONE
+BIDIR_HSUL12 F0B7 F1B7 F2B7 F5B7 F8B8
+BIDIR_LVCMOS12 F3B7 F5B7 F8B8
+BIDIR_LVCMOS15 !F5B7 F8B8
+BIDIR_LVCMOS18 !F5B7 F8B8
+BIDIR_LVCMOS25 F4B7 F4B8 F5B7 F8B8
+BIDIR_LVCMOS33 F1B8 F2B8 F3B7 F3B8 F4B7 F4B8 F5B7 F8B8
+BIDIR_LVTTL33 F1B8 F2B8 F3B7 F3B8 F4B7 F4B8 F5B7 F8B8
+BIDIR_SSTL135_I F0B7 F1B7 F2B7 F2B8 F5B7 F8B8
+BIDIR_SSTL135_II F0B7 F1B7 F1B8 F2B7 F5B7 F8B8
+BIDIR_SSTL15_I F0B7 F1B7 F2B7 F2B8 F5B7 F8B8
+BIDIR_SSTL15_II F0B7 F1B7 F1B8 F2B7 F5B7 F8B8
+BIDIR_SSTL18_I F0B7 F1B7 F2B7 F5B7 F8B8
+BIDIR_SSTL18_II F0B7 F0B8 F1B7 F1B8 F2B7 F2B8 F3B8 F5B7 F8B8
+INPUT_HSUL12 F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_LVCMOS12 F3B7 F5B7 F8B8
+INPUT_LVCMOS15 !F5B7 F8B8
+INPUT_LVCMOS18 !F5B7 F8B8
+INPUT_LVCMOS25 F4B7 F4B8 F5B7 F8B8
+INPUT_LVCMOS33 F3B7 F4B7 F4B8 F5B7 F8B8
+INPUT_LVTTL33 F3B7 F4B7 F4B8 F5B7 F8B8
+INPUT_SSTL135_I F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_SSTL135_II F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_SSTL15_I F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_SSTL15_II F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_SSTL18_I F0B7 F1B7 F2B7 F5B7 F8B8
+INPUT_SSTL18_II F0B7 F1B7 F2B7 F5B7 F8B8
+NONE F5B7
+OUTPUT_HSUL12 F0B7 F5B7 F8B8
+OUTPUT_LVCMOS12 F0B7 F5B7 F8B8
+OUTPUT_LVCMOS15 F0B7 F5B7 F8B8
+OUTPUT_LVCMOS18 F0B7 F5B7 F8B8
+OUTPUT_LVCMOS25 F0B7 F5B7 F8B8
+OUTPUT_LVCMOS33 F0B7 F1B8 F2B8 F3B8 F5B7 F8B8
+OUTPUT_LVTTL33 F0B7 F1B8 F2B8 F3B8 F5B7 F8B8
+OUTPUT_SSTL135_I F0B7 F2B8 F5B7 F8B8
+OUTPUT_SSTL135_II F0B7 F1B8 F5B7 F8B8
+OUTPUT_SSTL15_I F0B7 F2B8 F5B7 F8B8
+OUTPUT_SSTL15_II F0B7 F1B8 F5B7 F8B8
+OUTPUT_SSTL18_I F0B7 F5B7 F8B8
+OUTPUT_SSTL18_II F0B7 F0B8 F1B8 F2B8 F3B8 F5B7 F8B8
+
+.config_enum PIOD.DRIVE
+12 F0B8 !F1B8 !F2B8 !F3B8 !F9B9
+16 F0B8 F1B8 F2B8 F3B8 !F9B9
+4 F0B8 F1B8 !F2B8 !F3B8 F9B9
+8 !F0B8 F1B8 F2B8 F3B8 !F9B9
+
+.config_enum PIOD.HYSTERESIS OFF
+OFF !F4B8
+ON F4B8
+
+.config_enum PIOD.OPENDRAIN
+OFF F1B8 F2B8 !F2B9 F3B8
+ON !F1B8 F2B9 !F2B8 !F3B8
+
+.config_enum PIOD.PULLMODE DOWN
+DOWN !F0B7 !F9B8
+NONE F0B7 !F9B8
+UP F0B7 F9B8
+
+.config_enum PIOD.SLEWRATE SLOW
+FAST F3B9
+SLOW !F3B9
+
+
+# Fixed Connections
diff --git a/ECP5/tiledata/PICR2/bits.db b/ECP5/tiledata/PICR2/bits.db
index 8b13789..693154a 100644
--- a/ECP5/tiledata/PICR2/bits.db
+++ b/ECP5/tiledata/PICR2/bits.db
@@ -1 +1,129 @@
+# Routing Mux Bits
+# Non-Routing Configuration
+.config_enum PIOC.BASE_TYPE INPUT_LVCMOS18D
+BIDIR_BLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_HSUL12 F7B4 F8B4
+BIDIR_HSUL12D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_LVCMOS12 F7B4 F8B4
+BIDIR_LVCMOS15 F7B4 F8B4
+BIDIR_LVCMOS18 F7B4 F8B4
+BIDIR_LVCMOS25 F7B4 F8B4
+BIDIR_LVCMOS25D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_LVCMOS33 F7B4 F8B4
+BIDIR_LVCMOS33D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_LVTTL33 F7B4 F8B4
+BIDIR_MLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL135D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL135D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL135_I F7B4 F8B4
+BIDIR_SSTL135_II F7B4 F8B4
+BIDIR_SSTL15D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL15D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL15_I F7B4 F8B4
+BIDIR_SSTL15_II F7B4 F8B4
+BIDIR_SSTL18D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL18D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+BIDIR_SSTL18_I F7B4 F8B4
+BIDIR_SSTL18_II F7B4 F8B4
+INPUT_BLVDS25
+INPUT_HSUL12
+INPUT_HSUL12D
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS18D
+INPUT_LVCMOS25
+INPUT_LVCMOS25D
+INPUT_LVCMOS33
+INPUT_LVCMOS33D
+INPUT_LVDS
+INPUT_LVPECL33
+INPUT_LVTTL33
+INPUT_MLVDS25
+INPUT_SLVS
+INPUT_SSTL135D_I
+INPUT_SSTL135D_II
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15D_I
+INPUT_SSTL15D_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18D_I
+INPUT_SSTL18D_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+INPUT_SUBLVDS
+NONE
+OUTPUT_BLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_HSUL12 F7B4 F8B4
+OUTPUT_HSUL12D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_LVCMOS12 F7B4 F8B4
+OUTPUT_LVCMOS15 F7B4 F8B4
+OUTPUT_LVCMOS18 F7B4 F8B4
+OUTPUT_LVCMOS25 F7B4 F8B4
+OUTPUT_LVCMOS25D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_LVCMOS33 F7B4 F8B4
+OUTPUT_LVCMOS33D F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_LVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_LVPECL33E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_LVTTL33 F7B4 F8B4
+OUTPUT_MLVDS25E F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL135D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL135D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL135_I F7B4 F8B4
+OUTPUT_SSTL135_II F7B4 F8B4
+OUTPUT_SSTL15D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL15D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL15_I F7B4 F8B4
+OUTPUT_SSTL15_II F7B4 F8B4
+OUTPUT_SSTL18D_I F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL18D_II F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
+OUTPUT_SSTL18_I F7B4 F8B4
+OUTPUT_SSTL18_II F7B4 F8B4
+
+.config_enum PIOD.BASE_TYPE INPUT_HSUL12
+BIDIR_HSUL12 F4B9 F5B9
+BIDIR_LVCMOS12 F4B9 F5B9
+BIDIR_LVCMOS15 F4B9 F5B9
+BIDIR_LVCMOS18 F4B9 F5B9
+BIDIR_LVCMOS25 F4B9 F5B9
+BIDIR_LVCMOS33 F4B9 F5B9
+BIDIR_LVTTL33 F4B9 F5B9
+BIDIR_SSTL135_I F4B9 F5B9
+BIDIR_SSTL135_II F4B9 F5B9
+BIDIR_SSTL15_I F4B9 F5B9
+BIDIR_SSTL15_II F4B9 F5B9
+BIDIR_SSTL18_I F4B9 F5B9
+BIDIR_SSTL18_II F4B9 F5B9
+INPUT_HSUL12
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS25
+INPUT_LVCMOS33
+INPUT_LVTTL33
+INPUT_SSTL135_I
+INPUT_SSTL135_II
+INPUT_SSTL15_I
+INPUT_SSTL15_II
+INPUT_SSTL18_I
+INPUT_SSTL18_II
+NONE
+OUTPUT_HSUL12 F4B9 F5B9
+OUTPUT_LVCMOS12 F4B9 F5B9
+OUTPUT_LVCMOS15 F4B9 F5B9
+OUTPUT_LVCMOS18 F4B9 F5B9
+OUTPUT_LVCMOS25 F4B9 F5B9
+OUTPUT_LVCMOS33 F4B9 F5B9
+OUTPUT_LVTTL33 F4B9 F5B9
+OUTPUT_SSTL135_I F4B9 F5B9
+OUTPUT_SSTL135_II F4B9 F5B9
+OUTPUT_SSTL15_I F4B9 F5B9
+OUTPUT_SSTL15_II F4B9 F5B9
+OUTPUT_SSTL18_I F4B9 F5B9
+OUTPUT_SSTL18_II F4B9 F5B9
+
+
+# Fixed Connections
diff --git a/ECP5/tiledata/PICT0/bits.db b/ECP5/tiledata/PICT0/bits.db
index 8b13789..61eb765 100644
--- a/ECP5/tiledata/PICT0/bits.db
+++ b/ECP5/tiledata/PICT0/bits.db
@@ -1 +1,26 @@
+# Routing Mux Bits
+# Non-Routing Configuration
+.config_enum PIOA.BASE_TYPE INPUT_LVCMOS12
+BIDIR_LVCMOS12 F54B0 F55B0
+BIDIR_LVCMOS15 F54B0 F55B0
+BIDIR_LVCMOS18 F54B0 F55B0
+BIDIR_LVCMOS25 F54B0 F55B0
+BIDIR_LVCMOS33 F54B0 F55B0
+BIDIR_LVTTL33 F54B0 F55B0
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS25
+INPUT_LVCMOS33
+INPUT_LVTTL33
+NONE
+OUTPUT_LVCMOS12 F54B0 F55B0
+OUTPUT_LVCMOS15 F54B0 F55B0
+OUTPUT_LVCMOS18 F54B0 F55B0
+OUTPUT_LVCMOS25 F54B0 F55B0
+OUTPUT_LVCMOS33 F54B0 F55B0
+OUTPUT_LVTTL33 F54B0 F55B0
+
+
+# Fixed Connections
diff --git a/ECP5/tiledata/PICT1/bits.db b/ECP5/tiledata/PICT1/bits.db
index 8b13789..75206a1 100644
--- a/ECP5/tiledata/PICT1/bits.db
+++ b/ECP5/tiledata/PICT1/bits.db
@@ -1 +1,26 @@
+# Routing Mux Bits
+# Non-Routing Configuration
+.config_enum PIOB.BASE_TYPE INPUT_LVCMOS12
+BIDIR_LVCMOS12 F54B0 F55B0
+BIDIR_LVCMOS15 F54B0 F55B0
+BIDIR_LVCMOS18 F54B0 F55B0
+BIDIR_LVCMOS25 F54B0 F55B0
+BIDIR_LVCMOS33 F54B0 F55B0
+BIDIR_LVTTL33 F54B0 F55B0
+INPUT_LVCMOS12
+INPUT_LVCMOS15
+INPUT_LVCMOS18
+INPUT_LVCMOS25
+INPUT_LVCMOS33
+INPUT_LVTTL33
+NONE
+OUTPUT_LVCMOS12 F54B0 F55B0
+OUTPUT_LVCMOS15 F54B0 F55B0
+OUTPUT_LVCMOS18 F54B0 F55B0
+OUTPUT_LVCMOS25 F54B0 F55B0
+OUTPUT_LVCMOS33 F54B0 F55B0
+OUTPUT_LVTTL33 F54B0 F55B0
+
+
+# Fixed Connections
diff --git a/ECP5/tiledata/PIOT0/bits.db b/ECP5/tiledata/PIOT0/bits.db
index 8b13789..f75b14a 100644
--- a/ECP5/tiledata/PIOT0/bits.db
+++ b/ECP5/tiledata/PIOT0/bits.db
@@ -1 +1,49 @@
+# Routing Mux Bits
+# Non-Routing Configuration
+.config_enum PIOA.BASE_TYPE NONE
+BIDIR_LVCMOS12 F2B0 F4B0 F9B0
+BIDIR_LVCMOS15 !F2B0 F9B0
+BIDIR_LVCMOS18 !F2B0 F9B0
+BIDIR_LVCMOS25 F2B0 F3B0 F9B0 F14B0
+BIDIR_LVCMOS33 F2B0 F3B0 F4B0 F9B0 F14B0 F15B0 F16B0 F17B0
+BIDIR_LVTTL33 F2B0 F3B0 F4B0 F9B0 F14B0 F15B0 F16B0 F17B0
+INPUT_LVCMOS12 F2B0 F4B0 F9B0
+INPUT_LVCMOS15 !F2B0 F9B0
+INPUT_LVCMOS18 !F2B0 F9B0
+INPUT_LVCMOS25 F2B0 F3B0 F9B0 F14B0
+INPUT_LVCMOS33 F2B0 F3B0 F4B0 F9B0 F14B0
+INPUT_LVTTL33 F2B0 F3B0 F4B0 F9B0 F14B0
+NONE F2B0
+OUTPUT_LVCMOS12 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS15 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS18 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS25 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS33 F2B0 F7B0 F9B0 F15B0 F16B0 F17B0
+OUTPUT_LVTTL33 F2B0 F7B0 F9B0 F15B0 F16B0 F17B0
+
+.config_enum PIOA.DRIVE
+12 !F15B0 !F16B0 !F17B0 F18B0 !F19B0
+16 F15B0 F16B0 F17B0 F18B0 !F19B0
+4 !F15B0 !F16B0 F17B0 F18B0 F19B0
+8 F15B0 F16B0 F17B0 !F18B0 !F19B0
+
+.config_enum PIOA.HYSTERESIS OFF
+OFF !F14B0
+ON F14B0
+
+.config_enum PIOA.OPENDRAIN
+OFF F9B0 F15B0 F16B0 F17B0 !F26B0
+ON !F9B0 !F15B0 !F16B0 !F17B0 F26B0
+
+.config_enum PIOA.PULLMODE DOWN
+DOWN !F7B0 !F8B0
+NONE F7B0 !F8B0
+UP F7B0 F8B0
+
+.config_enum PIOA.SLEWRATE SLOW
+FAST F25B0
+SLOW !F25B0
+
+
+# Fixed Connections
diff --git a/ECP5/tiledata/PIOT1/bits.db b/ECP5/tiledata/PIOT1/bits.db
index 8b13789..c923a67 100644
--- a/ECP5/tiledata/PIOT1/bits.db
+++ b/ECP5/tiledata/PIOT1/bits.db
@@ -1 +1,49 @@
+# Routing Mux Bits
+# Non-Routing Configuration
+.config_enum PIOB.BASE_TYPE NONE
+BIDIR_LVCMOS12 F2B0 F4B0 F9B0
+BIDIR_LVCMOS15 !F2B0 F9B0
+BIDIR_LVCMOS18 !F2B0 F9B0
+BIDIR_LVCMOS25 F2B0 F3B0 F9B0 F14B0
+BIDIR_LVCMOS33 F2B0 F3B0 F4B0 F9B0 F14B0 F15B0 F16B0 F17B0
+BIDIR_LVTTL33 F2B0 F3B0 F4B0 F9B0 F14B0 F15B0 F16B0 F17B0
+INPUT_LVCMOS12 F2B0 F4B0 F9B0
+INPUT_LVCMOS15 !F2B0 F9B0
+INPUT_LVCMOS18 !F2B0 F9B0
+INPUT_LVCMOS25 F2B0 F3B0 F9B0 F14B0
+INPUT_LVCMOS33 F2B0 F3B0 F4B0 F9B0 F14B0
+INPUT_LVTTL33 F2B0 F3B0 F4B0 F9B0 F14B0
+NONE F2B0
+OUTPUT_LVCMOS12 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS15 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS18 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS25 F2B0 F7B0 F9B0
+OUTPUT_LVCMOS33 F2B0 F7B0 F9B0 F15B0 F16B0 F17B0
+OUTPUT_LVTTL33 F2B0 F7B0 F9B0 F15B0 F16B0 F17B0
+
+.config_enum PIOB.DRIVE
+12 !F15B0 !F16B0 !F17B0 F18B0 !F19B0
+16 F15B0 F16B0 F17B0 F18B0 !F19B0
+4 !F15B0 !F16B0 F17B0 F18B0 F19B0
+8 F15B0 F16B0 F17B0 !F18B0 !F19B0
+
+.config_enum PIOB.HYSTERESIS OFF
+OFF !F14B0
+ON F14B0
+
+.config_enum PIOB.OPENDRAIN
+OFF F9B0 F15B0 F16B0 F17B0 !F26B0
+ON !F9B0 !F15B0 !F16B0 !F17B0 F26B0
+
+.config_enum PIOB.PULLMODE DOWN
+DOWN !F7B0 !F8B0
+NONE F7B0 !F8B0
+UP F7B0 F8B0
+
+.config_enum PIOB.SLEWRATE SLOW
+FAST F25B0
+SLOW !F25B0
+
+
+# Fixed Connections
