Update to prjtrellis c9fa7c2b45bfa1c6d3dfddfd59a5ba22be7b99d9

ECP5/tiledata/BANKREF0/bits.db

diff --git a/ECP5/tiledata/BANKREF0/bits.db b/ECP5/tiledata/BANKREF0/bits.db
index 8b13789..a72d430 100644
--- a/ECP5/tiledata/BANKREF0/bits.db
+++ b/ECP5/tiledata/BANKREF0/bits.db
@@ -1 +1,13 @@
+# Routing Mux Bits
 
+# Non-Routing Configuration
+.config_enum BANK.VCCIO NONE
+1V2 !F3B0 !F16B0 !F17B0 !F18B0
+1V5 !F3B0 !F16B0 !F17B0 !F18B0
+1V8 F3B0 F16B0 !F17B0 !F18B0
+2V5 !F3B0 !F16B0 F17B0 !F18B0
+3V3 !F3B0 !F16B0 !F17B0 F18B0
+NONE !F3B0 !F16B0 !F17B0 !F18B0
+
+
+# Fixed Connections

ECP5/tiledata/BANKREF1/bits.db

diff --git a/ECP5/tiledata/BANKREF1/bits.db b/ECP5/tiledata/BANKREF1/bits.db
index 8b13789..a72d430 100644
--- a/ECP5/tiledata/BANKREF1/bits.db
+++ b/ECP5/tiledata/BANKREF1/bits.db
@@ -1 +1,13 @@
+# Routing Mux Bits
 
+# Non-Routing Configuration
+.config_enum BANK.VCCIO NONE
+1V2 !F3B0 !F16B0 !F17B0 !F18B0
+1V5 !F3B0 !F16B0 !F17B0 !F18B0
+1V8 F3B0 F16B0 !F17B0 !F18B0
+2V5 !F3B0 !F16B0 F17B0 !F18B0
+3V3 !F3B0 !F16B0 !F17B0 F18B0
+NONE !F3B0 !F16B0 !F17B0 !F18B0
+
+
+# Fixed Connections

ECP5/tiledata/BANKREF2/bits.db

diff --git a/ECP5/tiledata/BANKREF2/bits.db b/ECP5/tiledata/BANKREF2/bits.db
index 8b13789..bea493a 100644
--- a/ECP5/tiledata/BANKREF2/bits.db
+++ b/ECP5/tiledata/BANKREF2/bits.db
@@ -1 +1,25 @@
+# Routing Mux Bits
 
+# Non-Routing Configuration
+.config_enum BANK.DIFF_REF OFF
+OFF !F4B0
+ON F4B0
+
+.config_enum BANK.LVDSO OFF
+OFF !F3B0
+ON F3B0
+
+.config_enum BANK.VCCIO NONE
+1V2 !F1B1 !F2B1 !F3B1 !F6B0
+1V5 !F1B1 !F2B1 !F3B1 !F6B0
+1V8 !F1B1 !F2B1 F3B1 F6B0
+2V5 !F1B1 F2B1 !F3B1 !F6B0
+3V3 F1B1 !F2B1 !F3B1 !F6B0
+NONE !F1B1 !F2B1 !F3B1 !F6B0
+
+.config_enum BANK.VREF OFF
+OFF !F7B0
+ON F7B0
+
+
+# Fixed Connections

ECP5/tiledata/BANKREF2A/bits.db

diff --git a/ECP5/tiledata/BANKREF2A/bits.db b/ECP5/tiledata/BANKREF2A/bits.db
index 8b13789..4d0763a 100644
--- a/ECP5/tiledata/BANKREF2A/bits.db
+++ b/ECP5/tiledata/BANKREF2A/bits.db
@@ -1 +1,25 @@
+# Routing Mux Bits
 
+# Non-Routing Configuration
+.config_enum BANK.DIFF_REF OFF
+OFF !F4B0
+ON F4B0
+
+.config_enum BANK.LVDSO OFF
+OFF !F3B0
+ON F3B0
+
+.config_enum BANK.VCCIO NONE
+1V2 !F1B1 !F2B1 !F3B1 !F8B2
+1V5 !F1B1 !F2B1 !F3B1 !F8B2
+1V8 !F1B1 !F2B1 F3B1 F8B2
+2V5 !F1B1 F2B1 !F3B1 !F8B2
+3V3 F1B1 !F2B1 !F3B1 !F8B2
+NONE !F1B1 !F2B1 !F3B1 !F8B2
+
+.config_enum BANK.VREF OFF
+OFF !F9B2
+ON F9B2
+
+
+# Fixed Connections

ECP5/tiledata/BANKREF3/bits.db

diff --git a/ECP5/tiledata/BANKREF3/bits.db b/ECP5/tiledata/BANKREF3/bits.db
index 8b13789..5340b09 100644
--- a/ECP5/tiledata/BANKREF3/bits.db
+++ b/ECP5/tiledata/BANKREF3/bits.db
@@ -1 +1,25 @@
+# Routing Mux Bits
 
+# Non-Routing Configuration
+.config_enum BANK.DIFF_REF OFF
+OFF !F5B1
+ON F5B1
+
+.config_enum BANK.LVDSO OFF
+OFF !F6B1
+ON F6B1
+
+.config_enum BANK.VCCIO NONE
+1V2 !F3B1 !F16B1 !F17B1 !F18B1
+1V5 !F3B1 !F16B1 !F17B1 !F18B1
+1V8 F3B1 F16B1 !F17B1 !F18B1
+2V5 !F3B1 !F16B1 F17B1 !F18B1
+3V3 !F3B1 !F16B1 !F17B1 F18B1
+NONE !F3B1 !F16B1 !F17B1 !F18B1
+
+.config_enum BANK.VREF OFF
+OFF !F2B1
+ON F2B1
+
+
+# Fixed Connections

ECP5/tiledata/BANKREF4/bits.db

diff --git a/ECP5/tiledata/BANKREF4/bits.db b/ECP5/tiledata/BANKREF4/bits.db
index 8b13789..a72d430 100644
--- a/ECP5/tiledata/BANKREF4/bits.db
+++ b/ECP5/tiledata/BANKREF4/bits.db
@@ -1 +1,13 @@
+# Routing Mux Bits
 
+# Non-Routing Configuration
+.config_enum BANK.VCCIO NONE
+1V2 !F3B0 !F16B0 !F17B0 !F18B0
+1V5 !F3B0 !F16B0 !F17B0 !F18B0
+1V8 F3B0 F16B0 !F17B0 !F18B0
+2V5 !F3B0 !F16B0 F17B0 !F18B0
+3V3 !F3B0 !F16B0 !F17B0 F18B0
+NONE !F3B0 !F16B0 !F17B0 !F18B0
+
+
+# Fixed Connections

ECP5/tiledata/BANKREF6/bits.db

diff --git a/ECP5/tiledata/BANKREF6/bits.db b/ECP5/tiledata/BANKREF6/bits.db
index 8b13789..5340b09 100644
--- a/ECP5/tiledata/BANKREF6/bits.db
+++ b/ECP5/tiledata/BANKREF6/bits.db
@@ -1 +1,25 @@
+# Routing Mux Bits
 
+# Non-Routing Configuration
+.config_enum BANK.DIFF_REF OFF
+OFF !F5B1
+ON F5B1
+
+.config_enum BANK.LVDSO OFF
+OFF !F6B1
+ON F6B1
+
+.config_enum BANK.VCCIO NONE
+1V2 !F3B1 !F16B1 !F17B1 !F18B1
+1V5 !F3B1 !F16B1 !F17B1 !F18B1
+1V8 F3B1 F16B1 !F17B1 !F18B1
+2V5 !F3B1 !F16B1 F17B1 !F18B1
+3V3 !F3B1 !F16B1 !F17B1 F18B1
+NONE !F3B1 !F16B1 !F17B1 !F18B1
+
+.config_enum BANK.VREF OFF
+OFF !F2B1
+ON F2B1
+
+
+# Fixed Connections

ECP5/tiledata/BANKREF7/bits.db

diff --git a/ECP5/tiledata/BANKREF7/bits.db b/ECP5/tiledata/BANKREF7/bits.db
index 8b13789..4ba3649 100644
--- a/ECP5/tiledata/BANKREF7/bits.db
+++ b/ECP5/tiledata/BANKREF7/bits.db
@@ -1 +1,25 @@
+# Routing Mux Bits
 
+# Non-Routing Configuration
+.config_enum BANK.DIFF_REF OFF
+OFF !F5B0
+ON F5B0
+
+.config_enum BANK.LVDSO OFF
+OFF !F6B0
+ON F6B0
+
+.config_enum BANK.VCCIO NONE
+1V2 !F3B0 !F6B1 !F7B1 !F8B1
+1V5 !F3B0 !F6B1 !F7B1 !F8B1
+1V8 F3B0 F6B1 !F7B1 !F8B1
+2V5 !F3B0 !F6B1 F7B1 !F8B1
+3V3 !F3B0 !F6B1 !F7B1 F8B1
+NONE !F3B0 !F6B1 !F7B1 !F8B1
+
+.config_enum BANK.VREF OFF
+OFF !F2B0
+ON F2B0
+
+
+# Fixed Connections

ECP5/tiledata/BANKREF7A/bits.db

diff --git a/ECP5/tiledata/BANKREF7A/bits.db b/ECP5/tiledata/BANKREF7A/bits.db
index 8b13789..4ba3649 100644
--- a/ECP5/tiledata/BANKREF7A/bits.db
+++ b/ECP5/tiledata/BANKREF7A/bits.db
@@ -1 +1,25 @@
+# Routing Mux Bits
 
+# Non-Routing Configuration
+.config_enum BANK.DIFF_REF OFF
+OFF !F5B0
+ON F5B0
+
+.config_enum BANK.LVDSO OFF
+OFF !F6B0
+ON F6B0
+
+.config_enum BANK.VCCIO NONE
+1V2 !F3B0 !F6B1 !F7B1 !F8B1
+1V5 !F3B0 !F6B1 !F7B1 !F8B1
+1V8 F3B0 F6B1 !F7B1 !F8B1
+2V5 !F3B0 !F6B1 F7B1 !F8B1
+3V3 !F3B0 !F6B1 !F7B1 F8B1
+NONE !F3B0 !F6B1 !F7B1 !F8B1
+
+.config_enum BANK.VREF OFF
+OFF !F2B0
+ON F2B0
+
+
+# Fixed Connections