commit a77a960b236446fe344afca6b8185bae107ec76c
author David Shah <dave@ds0.me> Wed Nov 14 14:43:56 2018 +0000
committer David Shah <dave@ds0.me> Wed Nov 14 14:43:56 2018 +0000
tree cd6602f8ad8bc2f5cf5539c30899118ca6951f01
parent 2c1f036fb8b1f3264236b6b746ea1019fee0f9d8

Update to prjtrellis bb1ec0172a4de5728510f0f91fe16f273673101d

Signed-off-by: David Shah <dave@ds0.me>

ECP5/tiledata/PLL0_LL/bits.db

diff --git a/ECP5/tiledata/PLL0_LL/bits.db b/ECP5/tiledata/PLL0_LL/bits.db
index 4c0b772..7d178b2 100644
--- a/ECP5/tiledata/PLL0_LL/bits.db
+++ b/ECP5/tiledata/PLL0_LL/bits.db
@@ -272,8 +272,6 @@
 
 .fixed_conn N1_JPLLWAKESYNC_PLL N1_JC2
 
-.fixed_conn N1_JQ0 N1_JREFCLK_PLL
-
 .fixed_conn N1_JQ2 N1_JLOCK_PLL
 
 .fixed_conn N1_JQ4 N1_JINTLOCK_PLL

ECP5/tiledata/PLL0_LR/bits.db

diff --git a/ECP5/tiledata/PLL0_LR/bits.db b/ECP5/tiledata/PLL0_LR/bits.db
index 7a6ca21..27060e6 100644
--- a/ECP5/tiledata/PLL0_LR/bits.db
+++ b/ECP5/tiledata/PLL0_LR/bits.db
@@ -272,8 +272,6 @@
 
 .fixed_conn N1_JPLLWAKESYNC_PLL N1_JC2
 
-.fixed_conn N1_JQ0 N1_JREFCLK_PLL
-
 .fixed_conn N1_JQ2 N1_JLOCK_PLL
 
 .fixed_conn N1_JQ4 N1_JINTLOCK_PLL

ECP5/tiledata/PLL0_UL/bits.db

diff --git a/ECP5/tiledata/PLL0_UL/bits.db b/ECP5/tiledata/PLL0_UL/bits.db
index 3c4fc54..5e956b4 100644
--- a/ECP5/tiledata/PLL0_UL/bits.db
+++ b/ECP5/tiledata/PLL0_UL/bits.db
@@ -266,8 +266,6 @@
 
 .fixed_conn E1_JPLLWAKESYNC_PLL E1_JC2
 
-.fixed_conn E1_JQ0 E1_JREFCLK_PLL
-
 .fixed_conn E1_JQ2 E1_JLOCK_PLL
 
 .fixed_conn E1_JQ4 E1_JINTLOCK_PLL

ECP5/tiledata/PLL0_UR/bits.db

diff --git a/ECP5/tiledata/PLL0_UR/bits.db b/ECP5/tiledata/PLL0_UR/bits.db
index 5e650dd..01322c7 100644
--- a/ECP5/tiledata/PLL0_UR/bits.db
+++ b/ECP5/tiledata/PLL0_UR/bits.db
@@ -274,8 +274,6 @@
 
 .fixed_conn W1_JPLLWAKESYNC_PLL W1_JC2
 
-.fixed_conn W1_JQ0 W1_JREFCLK_PLL
-
 .fixed_conn W1_JQ2 W1_JLOCK_PLL
 
 .fixed_conn W1_JQ4 W1_JINTLOCK_PLL