commit d9603500f4a4df5b643c790d0e44bf7c67b755d0
author David Shah <dave@ds0.me> Sun Jan 20 15:05:44 2019 +0000
committer David Shah <dave@ds0.me> Sun Jan 20 15:05:44 2019 +0000
tree 762e5ace35279045e29e81fdb0ea36f63cbf112f
parent 7cc6ef16877c880ded8c65c0fcfd07dff02f49c5

Add LSRMODE

Signed-off-by: David Shah <dave@ds0.me>

ECP5/tiledata/PLC2/bits.db

diff --git a/ECP5/tiledata/PLC2/bits.db b/ECP5/tiledata/PLC2/bits.db
index 26d6c0f..7413acb 100644
--- a/ECP5/tiledata/PLC2/bits.db
+++ b/ECP5/tiledata/PLC2/bits.db
@@ -2730,6 +2730,10 @@
 DPRAM F50B11
 LOGIC -
 
+.config_enum SLICEA.REG0.LSRMODE LSR
+LSR !F3B11
+PRLD F3B11
+
 .config_enum SLICEA.REG0.REGSET SET
 RESET F2B11
 SET !F2B11
@@ -2738,6 +2742,10 @@
 0 F4B11
 1 !F4B11
 
+.config_enum SLICEA.REG1.LSRMODE LSR
+LSR !F6B11
+PRLD F6B11
+
 .config_enum SLICEA.REG1.REGSET SET
 RESET F5B11
 SET !F5B11
@@ -2815,6 +2823,10 @@
 DPRAM F50B11
 LOGIC -
 
+.config_enum SLICEB.REG0.LSRMODE LSR
+LSR !F48B11
+PRLD F48B11
+
 .config_enum SLICEB.REG0.REGSET SET
 RESET F49B11
 SET !F49B11
@@ -2823,6 +2835,10 @@
 0 F47B11
 1 !F47B11
 
+.config_enum SLICEB.REG1.LSRMODE LSR
+LSR !F45B11
+PRLD F45B11
+
 .config_enum SLICEB.REG1.REGSET SET
 RESET F46B11
 SET !F46B11
@@ -2894,6 +2910,10 @@
 LOGIC -
 RAMW F50B11
 
+.config_enum SLICEC.REG0.LSRMODE LSR
+LSR !F57B11
+PRLD F57B11
+
 .config_enum SLICEC.REG0.REGSET SET
 RESET F56B11
 SET !F56B11
@@ -2902,6 +2922,10 @@
 0 F58B11
 1 !F58B11
 
+.config_enum SLICEC.REG1.LSRMODE LSR
+LSR !F60B11
+PRLD F60B11
+
 .config_enum SLICEC.REG1.REGSET SET
 RESET F59B11
 SET !F59B11
@@ -2972,6 +2996,10 @@
 CCU2 F96B10 F96B11
 LOGIC -
 
+.config_enum SLICED.REG0.LSRMODE LSR
+LSR !F102B11
+PRLD F102B11
+
 .config_enum SLICED.REG0.REGSET SET
 RESET F103B11
 SET !F103B11
@@ -2980,6 +3008,10 @@
 0 F101B11
 1 !F101B11
 
+.config_enum SLICED.REG1.LSRMODE LSR
+LSR !F99B11
+PRLD F99B11
+
 .config_enum SLICED.REG1.REGSET SET
 RESET F100B11
 SET !F100B11