# Routing Mux Bits

# Non-Routing Configuration
.config_enum PIOA.BASE_TYPE NONE
BIDIR_BLVDS25E F0B4 F1B3 F1B4 F2B0 F4B1 F5B0 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
BIDIR_HSUL12 F2B0 F5B0 F6B0 F7B0 F9B0
BIDIR_HSUL12D F2B0 F5B0 F7B0 F9B0
BIDIR_LVCMOS12 F2B0 F4B0 F9B0
BIDIR_LVCMOS15 !F2B0 F9B0
BIDIR_LVCMOS18 !F2B0 F9B0
BIDIR_LVCMOS18D F1B3 F2B0 F2B1 F2B4 F5B0 F7B0 F8B1 F9B0
BIDIR_LVCMOS25 F2B0 F3B0 F3B1 F9B0
BIDIR_LVCMOS25D F1B3 F2B0 F5B0 F7B0 F9B0
BIDIR_LVCMOS33 F2B0 F3B0 F3B1 F4B0 F4B1 F5B1 F6B1 F9B0
BIDIR_LVCMOS33D F0B4 F1B3 F2B0 F4B1 F5B0 F5B1 F6B1 F7B0 F8B3 F9B0 F9B3
BIDIR_LVDS F1B3 F2B0 F2B1 F2B4 F5B0 F7B0 F8B1 F9B0
BIDIR_LVTTL33 F2B0 F3B0 F3B1 F4B0 F4B1 F5B1 F6B1 F9B0
BIDIR_MLVDS25E F0B4 F1B3 F1B4 F2B0 F4B1 F5B0 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
BIDIR_SSTL135D_I F1B3 F2B0 F5B0 F5B1 F7B0 F9B0 F9B3
BIDIR_SSTL135D_II F1B3 F1B4 F2B0 F5B0 F6B1 F7B0 F9B0
BIDIR_SSTL135_I F2B0 F5B0 F5B1 F6B0 F7B0 F9B0
BIDIR_SSTL135_II F2B0 F5B0 F6B0 F6B1 F7B0 F9B0
BIDIR_SSTL15D_I F1B3 F2B0 F5B0 F5B1 F7B0 F9B0 F9B3
BIDIR_SSTL15D_II F1B3 F1B4 F2B0 F5B0 F6B1 F7B0 F9B0
BIDIR_SSTL15_I F2B0 F5B0 F5B1 F6B0 F7B0 F9B0
BIDIR_SSTL15_II F2B0 F5B0 F6B0 F6B1 F7B0 F9B0
BIDIR_SSTL18D_I F1B3 F2B0 F5B0 F7B0 F9B0
BIDIR_SSTL18D_II F0B4 F1B3 F1B4 F2B0 F4B1 F5B0 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
BIDIR_SSTL18_I F2B0 F5B0 F6B0 F7B0 F9B0
BIDIR_SSTL18_II F2B0 F4B1 F5B0 F5B1 F6B0 F6B1 F7B0 F7B1 F9B0
INPUT_BLVDS25 F1B3 F2B0 F5B0 F7B0 F9B0
INPUT_HSUL12 F2B0 F5B0 F6B0 F7B0 F9B0
INPUT_HSUL12D F2B0 F5B0 F7B0 F9B0
INPUT_LVCMOS12 F2B0 F4B0 F9B0
INPUT_LVCMOS15 !F2B0 F9B0
INPUT_LVCMOS18 !F2B0 F9B0
INPUT_LVCMOS18D F1B3 F2B0 F5B0 F7B0 F9B0
INPUT_LVCMOS25 F2B0 F3B0 F3B1 F9B0
INPUT_LVCMOS25D F1B3 F2B0 F5B0 F7B0 F9B0
INPUT_LVCMOS33 F2B0 F3B0 F3B1 F4B0 F9B0
INPUT_LVCMOS33D F1B3 F2B0 F5B0 F7B0 F9B0
INPUT_LVDS F1B3 F2B0 F5B0 F7B0 F9B0
INPUT_LVPECL33 F2B0 F5B0 F7B0 F9B0
INPUT_LVTTL33 F2B0 F3B0 F3B1 F4B0 F9B0
INPUT_MLVDS25 F1B3 F2B0 F5B0 F7B0 F9B0
INPUT_SLVS F1B3 F2B0 F5B0 F7B0 F9B0
INPUT_SSTL135D_I F1B3 F2B0 F5B0 F7B0 F9B0
INPUT_SSTL135D_II F1B3 F2B0 F5B0 F7B0 F9B0
INPUT_SSTL135_I F2B0 F5B0 F6B0 F7B0 F9B0
INPUT_SSTL135_II F2B0 F5B0 F6B0 F7B0 F9B0
INPUT_SSTL15D_I F1B3 F2B0 F5B0 F7B0 F9B0
INPUT_SSTL15D_II F1B3 F2B0 F5B0 F7B0 F9B0
INPUT_SSTL15_I F2B0 F5B0 F6B0 F7B0 F9B0
INPUT_SSTL15_II F2B0 F5B0 F6B0 F7B0 F9B0
INPUT_SSTL18D_I F1B3 F2B0 F5B0 F7B0 F9B0
INPUT_SSTL18D_II F1B3 F2B0 F5B0 F7B0 F9B0
INPUT_SSTL18_I F2B0 F5B0 F6B0 F7B0 F9B0
INPUT_SSTL18_II F2B0 F5B0 F6B0 F7B0 F9B0
INPUT_SUBLVDS F1B3 F2B0 F5B0 F7B0 F9B0
NONE F2B0
OUTPUT_BLVDS25E F0B4 F1B3 F1B4 F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
OUTPUT_HSUL12 F2B0 F7B0 F9B0
OUTPUT_HSUL12D F2B0 F7B0 F9B0
OUTPUT_LVCMOS12 F2B0 F7B0 F9B0
OUTPUT_LVCMOS15 F2B0 F7B0 F9B0
OUTPUT_LVCMOS18 F2B0 F7B0 F9B0
OUTPUT_LVCMOS18D F1B3 F2B0 F2B1 F2B4 F7B0 F8B1 F9B0
OUTPUT_LVCMOS25 F2B0 F7B0 F9B0
OUTPUT_LVCMOS25D F1B3 F2B0 F7B0 F9B0
OUTPUT_LVCMOS33 F2B0 F4B1 F5B1 F6B1 F7B0 F9B0
OUTPUT_LVCMOS33D F0B4 F1B3 F2B0 F4B1 F5B1 F6B1 F7B0 F8B3 F9B0 F9B3
OUTPUT_LVDS F1B3 F2B0 F2B1 F2B4 F7B0 F8B1 F9B0
OUTPUT_LVDS25E F1B3 F2B0 F7B0 F9B0
OUTPUT_LVPECL33E F0B4 F1B3 F1B4 F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
OUTPUT_LVTTL33 F2B0 F4B1 F5B1 F6B1 F7B0 F9B0
OUTPUT_MLVDS25E F0B4 F1B3 F1B4 F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
OUTPUT_SSTL135D_I F1B3 F2B0 F5B1 F7B0 F9B0 F9B3
OUTPUT_SSTL135D_II F1B3 F1B4 F2B0 F6B1 F7B0 F9B0
OUTPUT_SSTL135_I F2B0 F5B1 F7B0 F9B0
OUTPUT_SSTL135_II F2B0 F6B1 F7B0 F9B0
OUTPUT_SSTL15D_I F1B3 F2B0 F5B1 F7B0 F9B0 F9B3
OUTPUT_SSTL15D_II F1B3 F1B4 F2B0 F6B1 F7B0 F9B0
OUTPUT_SSTL15_I F2B0 F5B1 F7B0 F9B0
OUTPUT_SSTL15_II F2B0 F6B1 F7B0 F9B0
OUTPUT_SSTL18D_I F1B3 F2B0 F7B0 F9B0
OUTPUT_SSTL18D_II F0B4 F1B3 F1B4 F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F8B3 F9B0 F9B3
OUTPUT_SSTL18_I F2B0 F7B0 F9B0
OUTPUT_SSTL18_II F2B0 F4B1 F5B1 F6B1 F7B0 F7B1 F9B0

.config_enum PIOA.DRIVE
12 !F4B1 !F5B1 !F6B1 F7B1 !F8B1
16 F4B1 F5B1 F6B1 F7B1 !F8B1
4 !F4B1 !F5B1 F6B1 F7B1 F8B1
8 F4B1 F5B1 F6B1 !F7B1 !F8B1

.config_enum PIOA.HYSTERESIS OFF
OFF !F3B1
ON F3B1

.config_enum PIOA.OPENDRAIN
OFF F4B1 F5B1 !F5B2 F6B1
ON !F4B1 !F5B1 F5B2 !F6B1

.config_enum PIOA.PULLMODE DOWN
DOWN !F7B0 !F8B0
NONE F7B0 !F8B0
UP F7B0 F8B0

.config_enum PIOA.SLEWRATE SLOW
FAST F4B2
SLOW !F4B2

.config_enum PIOB.BASE_TYPE NONE
BIDIR_HSUL12 F0B3 F1B3 F3B3 F6B2 F9B2
BIDIR_LVCMOS12 F3B3 F6B2 F8B2
BIDIR_LVCMOS15 F3B3 !F6B2
BIDIR_LVCMOS18 F3B3 !F6B2
BIDIR_LVCMOS25 F3B3 F6B2 F7B2 F7B3
BIDIR_LVCMOS33 F0B4 F3B3 F6B2 F7B2 F7B3 F8B2 F8B3 F9B3
BIDIR_LVTTL33 F0B4 F3B3 F6B2 F7B2 F7B3 F8B2 F8B3 F9B3
BIDIR_SSTL135_I F0B3 F1B3 F3B3 F6B2 F9B2 F9B3
BIDIR_SSTL135_II F0B3 F0B4 F1B3 F3B3 F6B2 F9B2
BIDIR_SSTL15_I F0B3 F1B3 F3B3 F6B2 F9B2 F9B3
BIDIR_SSTL15_II F0B3 F0B4 F1B3 F3B3 F6B2 F9B2
BIDIR_SSTL18_I F0B3 F1B3 F3B3 F6B2 F9B2
BIDIR_SSTL18_II F0B3 F0B4 F1B3 F1B4 F3B3 F6B2 F8B3 F9B2 F9B3
INPUT_HSUL12 F0B3 F1B3 F3B3 F6B2 F9B2
INPUT_LVCMOS12 F3B3 F6B2 F8B2
INPUT_LVCMOS15 F3B3 !F6B2
INPUT_LVCMOS18 F3B3 !F6B2
INPUT_LVCMOS25 F3B3 F6B2 F7B2 F7B3
INPUT_LVCMOS33 F3B3 F6B2 F7B2 F7B3 F8B2
INPUT_LVTTL33 F3B3 F6B2 F7B2 F7B3 F8B2
INPUT_SSTL135_I F0B3 F1B3 F3B3 F6B2 F9B2
INPUT_SSTL135_II F0B3 F1B3 F3B3 F6B2 F9B2
INPUT_SSTL15_I F0B3 F1B3 F3B3 F6B2 F9B2
INPUT_SSTL15_II F0B3 F1B3 F3B3 F6B2 F9B2
INPUT_SSTL18_I F0B3 F1B3 F3B3 F6B2 F9B2
INPUT_SSTL18_II F0B3 F1B3 F3B3 F6B2 F9B2
NONE F6B2
OUTPUT_HSUL12 F1B3 F3B3 F6B2
OUTPUT_LVCMOS12 F1B3 F3B3 F6B2
OUTPUT_LVCMOS15 F1B3 F3B3 F6B2
OUTPUT_LVCMOS18 F1B3 F3B3 F6B2
OUTPUT_LVCMOS25 F1B3 F3B3 F6B2
OUTPUT_LVCMOS33 F0B4 F1B3 F3B3 F6B2 F8B3 F9B3
OUTPUT_LVTTL33 F0B4 F1B3 F3B3 F6B2 F8B3 F9B3
OUTPUT_SSTL135_I F1B3 F3B3 F6B2 F9B3
OUTPUT_SSTL135_II F0B4 F1B3 F3B3 F6B2
OUTPUT_SSTL15_I F1B3 F3B3 F6B2 F9B3
OUTPUT_SSTL15_II F0B4 F1B3 F3B3 F6B2
OUTPUT_SSTL18_I F1B3 F3B3 F6B2
OUTPUT_SSTL18_II F0B4 F1B3 F1B4 F3B3 F6B2 F8B3 F9B3

.config_enum PIOB.DRIVE
12 !F0B4 F1B4 !F2B4 !F8B3 !F9B3
16 F0B4 F1B4 !F2B4 F8B3 F9B3
4 F0B4 F1B4 F2B4 !F8B3 !F9B3
8 F0B4 !F1B4 !F2B4 F8B3 F9B3

.config_enum PIOB.HYSTERESIS OFF
OFF !F7B3
ON F7B3

.config_enum PIOB.OPENDRAIN
OFF F0B4 F8B3 F9B3 !F9B4
ON !F0B4 !F8B3 !F9B3 F9B4

.config_enum PIOB.PULLMODE DOWN
DOWN !F1B3 !F2B3
NONE F1B3 !F2B3
UP F1B3 F2B3

.config_enum PIOB.SLEWRATE SLOW
FAST F8B4
SLOW !F8B4

.config_enum PIOC.BASE_TYPE NONE
BIDIR_BLVDS25E F0B5 F2B6 F3B5 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
BIDIR_HSUL12 F0B5 F3B5 F4B5 F5B5 F7B5
BIDIR_HSUL12D F0B5 F3B5 F5B5 F7B5
BIDIR_LVCMOS12 F0B5 F2B5 F7B5
BIDIR_LVCMOS15 !F0B5 F7B5
BIDIR_LVCMOS18 !F0B5 F7B5
BIDIR_LVCMOS25 F0B5 F1B5 F1B6 F7B5
BIDIR_LVCMOS25D F0B5 F3B5 F5B5 F7B5 F9B7
BIDIR_LVCMOS33 F0B5 F1B5 F1B6 F2B5 F2B6 F3B6 F4B6 F7B5
BIDIR_LVCMOS33D F0B5 F2B6 F3B5 F3B6 F4B6 F5B5 F6B8 F7B5 F7B8 F8B8 F9B7
BIDIR_LVTTL33 F0B5 F1B5 F1B6 F2B5 F2B6 F3B6 F4B6 F7B5
BIDIR_MLVDS25E F0B5 F2B6 F3B5 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
BIDIR_SSTL135D_I F0B5 F3B5 F3B6 F5B5 F7B5 F7B8 F9B7
BIDIR_SSTL135D_II F0B5 F3B5 F4B6 F5B5 F7B5 F9B7 F9B8
BIDIR_SSTL135_I F0B5 F3B5 F3B6 F4B5 F5B5 F7B5
BIDIR_SSTL135_II F0B5 F3B5 F4B5 F4B6 F5B5 F7B5
BIDIR_SSTL15D_I F0B5 F3B5 F3B6 F5B5 F7B5 F7B8 F9B7
BIDIR_SSTL15D_II F0B5 F3B5 F4B6 F5B5 F7B5 F9B7 F9B8
BIDIR_SSTL15_I F0B5 F3B5 F3B6 F4B5 F5B5 F7B5
BIDIR_SSTL15_II F0B5 F3B5 F4B5 F4B6 F5B5 F7B5
BIDIR_SSTL18D_I F0B5 F3B5 F5B5 F7B5 F9B7
BIDIR_SSTL18D_II F0B5 F2B6 F3B5 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
BIDIR_SSTL18_I F0B5 F3B5 F4B5 F5B5 F7B5
BIDIR_SSTL18_II F0B5 F2B6 F3B5 F3B6 F4B5 F4B6 F5B5 F5B6 F7B5
INPUT_BLVDS25 F0B5 F3B5 F5B5 F7B5 F9B7
INPUT_HSUL12 F0B5 F3B5 F4B5 F5B5 F7B5
INPUT_HSUL12D F0B5 F3B5 F5B5 F7B5
INPUT_LVCMOS12 F0B5 F2B5 F7B5
INPUT_LVCMOS15 !F0B5 F7B5
INPUT_LVCMOS18 !F0B5 F7B5
INPUT_LVCMOS18D F0B5 F3B5 F5B5 F7B5 F9B7
INPUT_LVCMOS25 F0B5 F1B5 F1B6 F7B5
INPUT_LVCMOS25D F0B5 F3B5 F5B5 F7B5 F9B7
INPUT_LVCMOS33 F0B5 F1B5 F1B6 F2B5 F7B5
INPUT_LVCMOS33D F0B5 F3B5 F5B5 F7B5 F9B7
INPUT_LVDS F0B5 F3B5 F5B5 F7B5 F9B7
INPUT_LVPECL33 F0B5 F3B5 F5B5 F7B5
INPUT_LVTTL33 F0B5 F1B5 F1B6 F2B5 F7B5
INPUT_MLVDS25 F0B5 F3B5 F5B5 F7B5 F9B7
INPUT_SLVS F0B5 F3B5 F5B5 F7B5 F9B7
INPUT_SSTL135D_I F0B5 F3B5 F5B5 F7B5 F9B7
INPUT_SSTL135D_II F0B5 F3B5 F5B5 F7B5 F9B7
INPUT_SSTL135_I F0B5 F3B5 F4B5 F5B5 F7B5
INPUT_SSTL135_II F0B5 F3B5 F4B5 F5B5 F7B5
INPUT_SSTL15D_I F0B5 F3B5 F5B5 F7B5 F9B7
INPUT_SSTL15D_II F0B5 F3B5 F5B5 F7B5 F9B7
INPUT_SSTL15_I F0B5 F3B5 F4B5 F5B5 F7B5
INPUT_SSTL15_II F0B5 F3B5 F4B5 F5B5 F7B5
INPUT_SSTL18D_I F0B5 F3B5 F5B5 F7B5 F9B7
INPUT_SSTL18D_II F0B5 F3B5 F5B5 F7B5 F9B7
INPUT_SSTL18_I F0B5 F3B5 F4B5 F5B5 F7B5
INPUT_SSTL18_II F0B5 F3B5 F4B5 F5B5 F7B5
INPUT_SUBLVDS F0B5 F3B5 F5B5 F7B5 F9B7
NONE F0B5
OUTPUT_BLVDS25E F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
OUTPUT_HSUL12 F0B5 F5B5 F7B5
OUTPUT_HSUL12D F0B5 F5B5 F7B5
OUTPUT_LVCMOS12 F0B5 F5B5 F7B5
OUTPUT_LVCMOS15 F0B5 F5B5 F7B5
OUTPUT_LVCMOS18 F0B5 F5B5 F7B5
OUTPUT_LVCMOS25 F0B5 F5B5 F7B5
OUTPUT_LVCMOS25D F0B5 F5B5 F7B5 F9B7
OUTPUT_LVCMOS33 F0B5 F2B6 F3B6 F4B6 F5B5 F7B5
OUTPUT_LVCMOS33D F0B5 F2B6 F3B6 F4B6 F5B5 F6B8 F7B5 F7B8 F8B8 F9B7
OUTPUT_LVDS25E F0B5 F5B5 F7B5 F9B7
OUTPUT_LVPECL33E F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
OUTPUT_LVTTL33 F0B5 F2B6 F3B6 F4B6 F5B5 F7B5
OUTPUT_MLVDS25E F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
OUTPUT_SSTL135D_I F0B5 F3B6 F5B5 F7B5 F7B8 F9B7
OUTPUT_SSTL135D_II F0B5 F4B6 F5B5 F7B5 F9B7 F9B8
OUTPUT_SSTL135_I F0B5 F3B6 F5B5 F7B5
OUTPUT_SSTL135_II F0B5 F4B6 F5B5 F7B5
OUTPUT_SSTL15D_I F0B5 F3B6 F5B5 F7B5 F7B8 F9B7
OUTPUT_SSTL15D_II F0B5 F4B6 F5B5 F7B5 F9B7 F9B8
OUTPUT_SSTL15_I F0B5 F3B6 F5B5 F7B5
OUTPUT_SSTL15_II F0B5 F4B6 F5B5 F7B5
OUTPUT_SSTL18D_I F0B5 F5B5 F7B5 F9B7
OUTPUT_SSTL18D_II F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F6B8 F7B5 F7B8 F8B8 F9B7 F9B8
OUTPUT_SSTL18_I F0B5 F5B5 F7B5
OUTPUT_SSTL18_II F0B5 F2B6 F3B6 F4B6 F5B5 F5B6 F7B5

.config_enum PIOC.DRIVE
12 !F2B6 !F3B6 !F4B6 F5B6 !F6B6
16 F2B6 F3B6 F4B6 F5B6 !F6B6
4 !F2B6 !F3B6 F4B6 F5B6 F6B6
8 F2B6 F3B6 F4B6 !F5B6 !F6B6

.config_enum PIOC.HYSTERESIS OFF
OFF !F1B6
ON F1B6

.config_enum PIOC.OPENDRAIN
OFF F2B6 F3B6 !F3B7 F4B6
ON !F2B6 !F3B6 F3B7 !F4B6

.config_enum PIOC.PULLMODE DOWN
DOWN !F5B5 !F6B5
NONE F5B5 !F6B5
UP F5B5 F6B5

.config_enum PIOC.SLEWRATE SLOW
FAST F2B7
SLOW !F2B7

.config_enum PIOD.BASE_TYPE NONE
BIDIR_HSUL12 F1B8 F4B7 F7B7 F8B7 F9B7
BIDIR_LVCMOS12 F1B8 F4B7 F6B7
BIDIR_LVCMOS15 F1B8 !F4B7
BIDIR_LVCMOS18 F1B8 !F4B7
BIDIR_LVCMOS25 F1B8 F4B7 F5B7 F5B8
BIDIR_LVCMOS33 F1B8 F4B7 F5B7 F5B8 F6B7 F6B8 F7B8 F8B8
BIDIR_LVTTL33 F1B8 F4B7 F5B7 F5B8 F6B7 F6B8 F7B8 F8B8
BIDIR_SSTL135_I F1B8 F4B7 F7B7 F7B8 F8B7 F9B7
BIDIR_SSTL135_II F1B8 F4B7 F7B7 F8B7 F8B8 F9B7
BIDIR_SSTL15_I F1B8 F4B7 F7B7 F7B8 F8B7 F9B7
BIDIR_SSTL15_II F1B8 F4B7 F7B7 F8B7 F8B8 F9B7
BIDIR_SSTL18_I F1B8 F4B7 F7B7 F8B7 F9B7
BIDIR_SSTL18_II F1B8 F4B7 F6B8 F7B7 F7B8 F8B7 F8B8 F9B7 F9B8
INPUT_HSUL12 F1B8 F4B7 F7B7 F8B7 F9B7
INPUT_LVCMOS12 F1B8 F4B7 F6B7
INPUT_LVCMOS15 F1B8 !F4B7
INPUT_LVCMOS18 F1B8 !F4B7
INPUT_LVCMOS25 F1B8 F4B7 F5B7 F5B8
INPUT_LVCMOS33 F1B8 F4B7 F5B7 F5B8 F6B7
INPUT_LVTTL33 F1B8 F4B7 F5B7 F5B8 F6B7
INPUT_SSTL135_I F1B8 F4B7 F7B7 F8B7 F9B7
INPUT_SSTL135_II F1B8 F4B7 F7B7 F8B7 F9B7
INPUT_SSTL15_I F1B8 F4B7 F7B7 F8B7 F9B7
INPUT_SSTL15_II F1B8 F4B7 F7B7 F8B7 F9B7
INPUT_SSTL18_I F1B8 F4B7 F7B7 F8B7 F9B7
INPUT_SSTL18_II F1B8 F4B7 F7B7 F8B7 F9B7
NONE F4B7
OUTPUT_HSUL12 F1B8 F4B7 F9B7
OUTPUT_LVCMOS12 F1B8 F4B7 F9B7
OUTPUT_LVCMOS15 F1B8 F4B7 F9B7
OUTPUT_LVCMOS18 F1B8 F4B7 F9B7
OUTPUT_LVCMOS25 F1B8 F4B7 F9B7
OUTPUT_LVCMOS33 F1B8 F4B7 F6B8 F7B8 F8B8 F9B7
OUTPUT_LVTTL33 F1B8 F4B7 F6B8 F7B8 F8B8 F9B7
OUTPUT_SSTL135_I F1B8 F4B7 F7B8 F9B7
OUTPUT_SSTL135_II F1B8 F4B7 F8B8 F9B7
OUTPUT_SSTL15_I F1B8 F4B7 F7B8 F9B7
OUTPUT_SSTL15_II F1B8 F4B7 F8B8 F9B7
OUTPUT_SSTL18_I F1B8 F4B7 F9B7
OUTPUT_SSTL18_II F1B8 F4B7 F6B8 F7B8 F8B8 F9B7 F9B8

.config_enum PIOD.DRIVE
12 !F0B9 !F6B8 !F7B8 !F8B8 F9B8
16 !F0B9 F6B8 F7B8 F8B8 F9B8
4 F0B9 !F6B8 !F7B8 F8B8 F9B8
8 !F0B9 F6B8 F7B8 F8B8 !F9B8

.config_enum PIOD.HYSTERESIS OFF
OFF !F5B8
ON F5B8

.config_enum PIOD.OPENDRAIN
OFF F6B8 F7B8 !F7B9 F8B8
ON !F6B8 !F7B8 F7B9 !F8B8

.config_enum PIOD.PULLMODE DOWN
DOWN !F0B8 !F9B7
NONE !F0B8 F9B7
UP F0B8 F9B7

.config_enum PIOD.SLEWRATE SLOW
FAST F6B9
SLOW !F6B9


# Fixed Connections