# Routing Mux Bits

# Non-Routing Configuration
.config_enum PIOA.BASE_TYPE NONE
BIDIR_BLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
BIDIR_HSUL12 F0B0 F2B0 F3B0 F4B0 F7B0
BIDIR_HSUL12D F0B0 F2B0 F4B0 F7B0
BIDIR_LVCMOS12 F0B0 F5B0 F7B0
BIDIR_LVCMOS15 F0B0 !F7B0
BIDIR_LVCMOS18 F0B0 !F7B0
BIDIR_LVCMOS18D F0B0 F1B1 F2B0 F4B0 F7B0 F7B1 F7B4 F8B3
BIDIR_LVCMOS25 F0B0 F6B0 F6B1 F7B0
BIDIR_LVCMOS25D F0B0 F2B0 F4B0 F7B0 F8B3
BIDIR_LVCMOS33 F0B0 F3B1 F4B1 F5B0 F5B1 F6B0 F6B1 F7B0
BIDIR_LVCMOS33D F0B0 F0B3 F1B3 F2B0 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F9B4
BIDIR_LVDS F0B0 F1B1 F2B0 F4B0 F7B0 F7B1 F7B4 F8B3
BIDIR_LVTTL33 F0B0 F3B1 F4B1 F5B0 F5B1 F6B0 F6B1 F7B0
BIDIR_MLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
BIDIR_SSTL135D_I F0B0 F0B3 F2B0 F4B0 F4B1 F7B0 F8B3
BIDIR_SSTL135D_II F0B0 F2B0 F3B1 F4B0 F7B0 F8B3 F8B4
BIDIR_SSTL135_I F0B0 F2B0 F3B0 F4B0 F4B1 F7B0
BIDIR_SSTL135_II F0B0 F2B0 F3B0 F3B1 F4B0 F7B0
BIDIR_SSTL15D_I F0B0 F0B3 F2B0 F4B0 F4B1 F7B0 F8B3
BIDIR_SSTL15D_II F0B0 F2B0 F3B1 F4B0 F7B0 F8B3 F8B4
BIDIR_SSTL15_I F0B0 F2B0 F3B0 F4B0 F4B1 F7B0
BIDIR_SSTL15_II F0B0 F2B0 F3B0 F3B1 F4B0 F7B0
BIDIR_SSTL18D_I F0B0 F2B0 F4B0 F7B0 F8B3
BIDIR_SSTL18D_II F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B0 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
BIDIR_SSTL18_I F0B0 F2B0 F3B0 F4B0 F7B0
BIDIR_SSTL18_II F0B0 F2B0 F2B1 F3B0 F3B1 F4B0 F4B1 F5B1 F7B0
INPUT_BLVDS25 F0B0 F2B0 F4B0 F7B0 F8B3
INPUT_HSUL12 F0B0 F2B0 F3B0 F4B0 F7B0
INPUT_HSUL12D F0B0 F2B0 F4B0 F7B0
INPUT_LVCMOS12 F0B0 F5B0 F7B0
INPUT_LVCMOS15 F0B0 !F7B0
INPUT_LVCMOS18 F0B0 !F7B0
INPUT_LVCMOS18D F0B0 F2B0 F4B0 F7B0 F8B3
INPUT_LVCMOS25 F0B0 F6B0 F6B1 F7B0
INPUT_LVCMOS25D F0B0 F2B0 F4B0 F7B0 F8B3
INPUT_LVCMOS33 F0B0 F5B0 F6B0 F6B1 F7B0
INPUT_LVCMOS33D F0B0 F2B0 F4B0 F7B0 F8B3
INPUT_LVDS F0B0 F2B0 F4B0 F7B0 F8B3
INPUT_LVPECL33 F0B0 F2B0 F4B0 F7B0
INPUT_LVTTL33 F0B0 F5B0 F6B0 F6B1 F7B0
INPUT_MLVDS25 F0B0 F2B0 F4B0 F7B0 F8B3
INPUT_SLVS F0B0 F2B0 F4B0 F7B0 F8B3
INPUT_SSTL135D_I F0B0 F2B0 F4B0 F7B0 F8B3
INPUT_SSTL135D_II F0B0 F2B0 F4B0 F7B0 F8B3
INPUT_SSTL135_I F0B0 F2B0 F3B0 F4B0 F7B0
INPUT_SSTL135_II F0B0 F2B0 F3B0 F4B0 F7B0
INPUT_SSTL15D_I F0B0 F2B0 F4B0 F7B0 F8B3
INPUT_SSTL15D_II F0B0 F2B0 F4B0 F7B0 F8B3
INPUT_SSTL15_I F0B0 F2B0 F3B0 F4B0 F7B0
INPUT_SSTL15_II F0B0 F2B0 F3B0 F4B0 F7B0
INPUT_SSTL18D_I F0B0 F2B0 F4B0 F7B0 F8B3
INPUT_SSTL18D_II F0B0 F2B0 F4B0 F7B0 F8B3
INPUT_SSTL18_I F0B0 F2B0 F3B0 F4B0 F7B0
INPUT_SSTL18_II F0B0 F2B0 F3B0 F4B0 F7B0
INPUT_SUBLVDS F0B0 F2B0 F4B0 F7B0 F8B3
NONE F7B0
OUTPUT_BLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
OUTPUT_HSUL12 F0B0 F2B0 F7B0
OUTPUT_HSUL12D F0B0 F2B0 F7B0
OUTPUT_LVCMOS12 F0B0 F2B0 F7B0
OUTPUT_LVCMOS15 F0B0 F2B0 F7B0
OUTPUT_LVCMOS18 F0B0 F2B0 F7B0
OUTPUT_LVCMOS18D F0B0 F1B1 F2B0 F7B0 F7B1 F7B4 F8B3
OUTPUT_LVCMOS25 F0B0 F2B0 F7B0
OUTPUT_LVCMOS25D F0B0 F2B0 F7B0 F8B3
OUTPUT_LVCMOS33 F0B0 F2B0 F3B1 F4B1 F5B1 F7B0
OUTPUT_LVCMOS33D F0B0 F0B3 F1B3 F2B0 F3B1 F4B1 F5B1 F7B0 F8B3 F9B4
OUTPUT_LVDS F0B0 F1B1 F2B0 F7B0 F7B1 F7B4 F8B3
OUTPUT_LVDS25E F0B0 F2B0 F7B0 F8B3
OUTPUT_LVPECL33E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
OUTPUT_LVTTL33 F0B0 F2B0 F3B1 F4B1 F5B1 F7B0
OUTPUT_MLVDS25E F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
OUTPUT_SSTL135D_I F0B0 F0B3 F2B0 F4B1 F7B0 F8B3
OUTPUT_SSTL135D_II F0B0 F2B0 F3B1 F7B0 F8B3 F8B4
OUTPUT_SSTL135_I F0B0 F2B0 F4B1 F7B0
OUTPUT_SSTL135_II F0B0 F2B0 F3B1 F7B0
OUTPUT_SSTL15D_I F0B0 F0B3 F2B0 F4B1 F7B0 F8B3
OUTPUT_SSTL15D_II F0B0 F2B0 F3B1 F7B0 F8B3 F8B4
OUTPUT_SSTL15_I F0B0 F2B0 F4B1 F7B0
OUTPUT_SSTL15_II F0B0 F2B0 F3B1 F7B0
OUTPUT_SSTL18D_I F0B0 F2B0 F7B0 F8B3
OUTPUT_SSTL18D_II F0B0 F0B3 F1B3 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0 F8B3 F8B4 F9B4
OUTPUT_SSTL18_I F0B0 F2B0 F7B0
OUTPUT_SSTL18_II F0B0 F2B0 F2B1 F3B1 F4B1 F5B1 F7B0

.config_enum PIOA.DRIVE
12 !F1B1 F2B1 !F3B1 !F4B1 !F5B1
16 !F1B1 F2B1 F3B1 F4B1 F5B1
4 F1B1 F2B1 F3B1 !F4B1 !F5B1
8 !F1B1 !F2B1 F3B1 F4B1 F5B1

.config_enum PIOA.HYSTERESIS OFF
OFF !F6B1
ON F6B1

.config_enum PIOA.OPENDRAIN
OFF F3B1 F4B1 !F4B2 F5B1
ON !F3B1 !F4B1 F4B2 !F5B1

.config_enum PIOA.PULLMODE DOWN
DOWN !F1B0 !F2B0
NONE !F1B0 F2B0
UP F1B0 F2B0

.config_enum PIOA.SLEWRATE SLOW
FAST F5B2
SLOW !F5B2

.config_enum PIOB.BASE_TYPE NONE
BIDIR_HSUL12 F0B2 F3B2 F6B3 F8B3 F9B3
BIDIR_LVCMOS12 F1B2 F3B2 F6B3
BIDIR_LVCMOS15 !F3B2 F6B3
BIDIR_LVCMOS18 !F3B2 F6B3
BIDIR_LVCMOS25 F2B2 F2B3 F3B2 F6B3
BIDIR_LVCMOS33 F0B3 F1B2 F1B3 F2B2 F2B3 F3B2 F6B3 F9B4
BIDIR_LVTTL33 F0B3 F1B2 F1B3 F2B2 F2B3 F3B2 F6B3 F9B4
BIDIR_SSTL135_I F0B2 F0B3 F3B2 F6B3 F8B3 F9B3
BIDIR_SSTL135_II F0B2 F3B2 F6B3 F8B3 F9B3 F9B4
BIDIR_SSTL15_I F0B2 F0B3 F3B2 F6B3 F8B3 F9B3
BIDIR_SSTL15_II F0B2 F3B2 F6B3 F8B3 F9B3 F9B4
BIDIR_SSTL18_I F0B2 F3B2 F6B3 F8B3 F9B3
BIDIR_SSTL18_II F0B2 F0B3 F1B3 F3B2 F6B3 F8B3 F8B4 F9B3 F9B4
INPUT_HSUL12 F0B2 F3B2 F6B3 F8B3 F9B3
INPUT_LVCMOS12 F1B2 F3B2 F6B3
INPUT_LVCMOS15 !F3B2 F6B3
INPUT_LVCMOS18 !F3B2 F6B3
INPUT_LVCMOS25 F2B2 F2B3 F3B2 F6B3
INPUT_LVCMOS33 F1B2 F2B2 F2B3 F3B2 F6B3
INPUT_LVTTL33 F1B2 F2B2 F2B3 F3B2 F6B3
INPUT_SSTL135_I F0B2 F3B2 F6B3 F8B3 F9B3
INPUT_SSTL135_II F0B2 F3B2 F6B3 F8B3 F9B3
INPUT_SSTL15_I F0B2 F3B2 F6B3 F8B3 F9B3
INPUT_SSTL15_II F0B2 F3B2 F6B3 F8B3 F9B3
INPUT_SSTL18_I F0B2 F3B2 F6B3 F8B3 F9B3
INPUT_SSTL18_II F0B2 F3B2 F6B3 F8B3 F9B3
NONE F3B2
OUTPUT_HSUL12 F3B2 F6B3 F8B3
OUTPUT_LVCMOS12 F3B2 F6B3 F8B3
OUTPUT_LVCMOS15 F3B2 F6B3 F8B3
OUTPUT_LVCMOS18 F3B2 F6B3 F8B3
OUTPUT_LVCMOS25 F3B2 F6B3 F8B3
OUTPUT_LVCMOS33 F0B3 F1B3 F3B2 F6B3 F8B3 F9B4
OUTPUT_LVTTL33 F0B3 F1B3 F3B2 F6B3 F8B3 F9B4
OUTPUT_SSTL135_I F0B3 F3B2 F6B3 F8B3
OUTPUT_SSTL135_II F3B2 F6B3 F8B3 F9B4
OUTPUT_SSTL15_I F0B3 F3B2 F6B3 F8B3
OUTPUT_SSTL15_II F3B2 F6B3 F8B3 F9B4
OUTPUT_SSTL18_I F3B2 F6B3 F8B3
OUTPUT_SSTL18_II F0B3 F1B3 F3B2 F6B3 F8B3 F8B4 F9B4

.config_enum PIOB.DRIVE
12 !F0B3 !F1B3 !F7B4 F8B4 !F9B4
16 F0B3 F1B3 !F7B4 F8B4 F9B4
4 !F0B3 !F1B3 F7B4 F8B4 F9B4
8 F0B3 F1B3 !F7B4 !F8B4 F9B4

.config_enum PIOB.HYSTERESIS OFF
OFF !F2B3
ON F2B3

.config_enum PIOB.OPENDRAIN
OFF F0B3 !F0B4 F1B3 F9B4
ON !F0B3 F0B4 !F1B3 !F9B4

.config_enum PIOB.PULLMODE DOWN
DOWN !F7B3 !F8B3
NONE !F7B3 F8B3
UP F7B3 F8B3

.config_enum PIOB.SLEWRATE SLOW
FAST F1B4
SLOW !F1B4

.config_enum PIOC.BASE_TYPE NONE
BIDIR_BLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B5 F6B6 F7B6 F9B5
BIDIR_HSUL12 F2B5 F4B5 F5B5 F6B5 F9B5
BIDIR_HSUL12D F2B5 F4B5 F6B5 F9B5
BIDIR_LVCMOS12 F2B5 F7B5 F9B5
BIDIR_LVCMOS15 F2B5 !F9B5
BIDIR_LVCMOS18 F2B5 !F9B5
BIDIR_LVCMOS25 F2B5 F8B5 F8B6 F9B5
BIDIR_LVCMOS25D F0B7 F2B5 F4B5 F6B5 F9B5
BIDIR_LVCMOS33 F2B5 F5B6 F6B6 F7B5 F7B6 F8B5 F8B6 F9B5
BIDIR_LVCMOS33D F0B7 F1B8 F2B5 F2B8 F3B8 F4B5 F5B6 F6B5 F6B6 F7B6 F9B5
BIDIR_LVTTL33 F2B5 F5B6 F6B6 F7B5 F7B6 F8B5 F8B6 F9B5
BIDIR_MLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B5 F6B6 F7B6 F9B5
BIDIR_SSTL135D_I F0B7 F2B5 F2B8 F4B5 F6B5 F6B6 F9B5
BIDIR_SSTL135D_II F0B7 F0B8 F2B5 F4B5 F5B6 F6B5 F9B5
BIDIR_SSTL135_I F2B5 F4B5 F5B5 F6B5 F6B6 F9B5
BIDIR_SSTL135_II F2B5 F4B5 F5B5 F5B6 F6B5 F9B5
BIDIR_SSTL15D_I F0B7 F2B5 F2B8 F4B5 F6B5 F6B6 F9B5
BIDIR_SSTL15D_II F0B7 F0B8 F2B5 F4B5 F5B6 F6B5 F9B5
BIDIR_SSTL15_I F2B5 F4B5 F5B5 F6B5 F6B6 F9B5
BIDIR_SSTL15_II F2B5 F4B5 F5B5 F5B6 F6B5 F9B5
BIDIR_SSTL18D_I F0B7 F2B5 F4B5 F6B5 F9B5
BIDIR_SSTL18D_II F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B5 F6B6 F7B6 F9B5
BIDIR_SSTL18_I F2B5 F4B5 F5B5 F6B5 F9B5
BIDIR_SSTL18_II F2B5 F4B5 F4B6 F5B5 F5B6 F6B5 F6B6 F7B6 F9B5
INPUT_BLVDS25 F0B7 F2B5 F4B5 F6B5 F9B5
INPUT_HSUL12 F2B5 F4B5 F5B5 F6B5 F9B5
INPUT_HSUL12D F2B5 F4B5 F6B5 F9B5
INPUT_LVCMOS12 F2B5 F7B5 F9B5
INPUT_LVCMOS15 F2B5 !F9B5
INPUT_LVCMOS18 F2B5 !F9B5
INPUT_LVCMOS18D F0B7 F2B5 F4B5 F6B5 F9B5
INPUT_LVCMOS25 F2B5 F8B5 F8B6 F9B5
INPUT_LVCMOS25D F0B7 F2B5 F4B5 F6B5 F9B5
INPUT_LVCMOS33 F2B5 F7B5 F8B5 F8B6 F9B5
INPUT_LVCMOS33D F0B7 F2B5 F4B5 F6B5 F9B5
INPUT_LVDS F0B7 F2B5 F4B5 F6B5 F9B5
INPUT_LVPECL33 F2B5 F4B5 F6B5 F9B5
INPUT_LVTTL33 F2B5 F7B5 F8B5 F8B6 F9B5
INPUT_MLVDS25 F0B7 F2B5 F4B5 F6B5 F9B5
INPUT_SLVS F0B7 F2B5 F4B5 F6B5 F9B5
INPUT_SSTL135D_I F0B7 F2B5 F4B5 F6B5 F9B5
INPUT_SSTL135D_II F0B7 F2B5 F4B5 F6B5 F9B5
INPUT_SSTL135_I F2B5 F4B5 F5B5 F6B5 F9B5
INPUT_SSTL135_II F2B5 F4B5 F5B5 F6B5 F9B5
INPUT_SSTL15D_I F0B7 F2B5 F4B5 F6B5 F9B5
INPUT_SSTL15D_II F0B7 F2B5 F4B5 F6B5 F9B5
INPUT_SSTL15_I F2B5 F4B5 F5B5 F6B5 F9B5
INPUT_SSTL15_II F2B5 F4B5 F5B5 F6B5 F9B5
INPUT_SSTL18D_I F0B7 F2B5 F4B5 F6B5 F9B5
INPUT_SSTL18D_II F0B7 F2B5 F4B5 F6B5 F9B5
INPUT_SSTL18_I F2B5 F4B5 F5B5 F6B5 F9B5
INPUT_SSTL18_II F2B5 F4B5 F5B5 F6B5 F9B5
INPUT_SUBLVDS F0B7 F2B5 F4B5 F6B5 F9B5
NONE F9B5
OUTPUT_BLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
OUTPUT_HSUL12 F2B5 F4B5 F9B5
OUTPUT_HSUL12D F2B5 F4B5 F9B5
OUTPUT_LVCMOS12 F2B5 F4B5 F9B5
OUTPUT_LVCMOS15 F2B5 F4B5 F9B5
OUTPUT_LVCMOS18 F2B5 F4B5 F9B5
OUTPUT_LVCMOS25 F2B5 F4B5 F9B5
OUTPUT_LVCMOS25D F0B7 F2B5 F4B5 F9B5
OUTPUT_LVCMOS33 F2B5 F4B5 F5B6 F6B6 F7B6 F9B5
OUTPUT_LVCMOS33D F0B7 F1B8 F2B5 F2B8 F3B8 F4B5 F5B6 F6B6 F7B6 F9B5
OUTPUT_LVDS25E F0B7 F2B5 F4B5 F9B5
OUTPUT_LVPECL33E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
OUTPUT_LVTTL33 F2B5 F4B5 F5B6 F6B6 F7B6 F9B5
OUTPUT_MLVDS25E F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
OUTPUT_SSTL135D_I F0B7 F2B5 F2B8 F4B5 F6B6 F9B5
OUTPUT_SSTL135D_II F0B7 F0B8 F2B5 F4B5 F5B6 F9B5
OUTPUT_SSTL135_I F2B5 F4B5 F6B6 F9B5
OUTPUT_SSTL135_II F2B5 F4B5 F5B6 F9B5
OUTPUT_SSTL15D_I F0B7 F2B5 F2B8 F4B5 F6B6 F9B5
OUTPUT_SSTL15D_II F0B7 F0B8 F2B5 F4B5 F5B6 F9B5
OUTPUT_SSTL15_I F2B5 F4B5 F6B6 F9B5
OUTPUT_SSTL15_II F2B5 F4B5 F5B6 F9B5
OUTPUT_SSTL18D_I F0B7 F2B5 F4B5 F9B5
OUTPUT_SSTL18D_II F0B7 F0B8 F1B8 F2B5 F2B8 F3B8 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5
OUTPUT_SSTL18_I F2B5 F4B5 F9B5
OUTPUT_SSTL18_II F2B5 F4B5 F4B6 F5B6 F6B6 F7B6 F9B5

.config_enum PIOC.DRIVE
12 !F3B6 F4B6 !F5B6 !F6B6 !F7B6
16 !F3B6 F4B6 F5B6 F6B6 F7B6
4 F3B6 F4B6 F5B6 !F6B6 !F7B6
8 !F3B6 !F4B6 F5B6 F6B6 F7B6

.config_enum PIOC.HYSTERESIS OFF
OFF !F8B6
ON F8B6

.config_enum PIOC.OPENDRAIN
OFF F5B6 F6B6 !F6B7 F7B6
ON !F5B6 !F6B6 F6B7 !F7B6

.config_enum PIOC.PULLMODE DOWN
DOWN !F3B5 !F4B5
NONE !F3B5 F4B5
UP F3B5 F4B5

.config_enum PIOC.SLEWRATE SLOW
FAST F7B7
SLOW !F7B7

.config_enum PIOD.BASE_TYPE NONE
BIDIR_HSUL12 F0B7 F1B7 F2B7 F5B7 F8B8
BIDIR_LVCMOS12 F3B7 F5B7 F8B8
BIDIR_LVCMOS15 !F5B7 F8B8
BIDIR_LVCMOS18 !F5B7 F8B8
BIDIR_LVCMOS25 F4B7 F4B8 F5B7 F8B8
BIDIR_LVCMOS33 F1B8 F2B8 F3B7 F3B8 F4B7 F4B8 F5B7 F8B8
BIDIR_LVTTL33 F1B8 F2B8 F3B7 F3B8 F4B7 F4B8 F5B7 F8B8
BIDIR_SSTL135_I F0B7 F1B7 F2B7 F2B8 F5B7 F8B8
BIDIR_SSTL135_II F0B7 F1B7 F1B8 F2B7 F5B7 F8B8
BIDIR_SSTL15_I F0B7 F1B7 F2B7 F2B8 F5B7 F8B8
BIDIR_SSTL15_II F0B7 F1B7 F1B8 F2B7 F5B7 F8B8
BIDIR_SSTL18_I F0B7 F1B7 F2B7 F5B7 F8B8
BIDIR_SSTL18_II F0B7 F0B8 F1B7 F1B8 F2B7 F2B8 F3B8 F5B7 F8B8
INPUT_HSUL12 F0B7 F1B7 F2B7 F5B7 F8B8
INPUT_LVCMOS12 F3B7 F5B7 F8B8
INPUT_LVCMOS15 !F5B7 F8B8
INPUT_LVCMOS18 !F5B7 F8B8
INPUT_LVCMOS25 F4B7 F4B8 F5B7 F8B8
INPUT_LVCMOS33 F3B7 F4B7 F4B8 F5B7 F8B8
INPUT_LVTTL33 F3B7 F4B7 F4B8 F5B7 F8B8
INPUT_SSTL135_I F0B7 F1B7 F2B7 F5B7 F8B8
INPUT_SSTL135_II F0B7 F1B7 F2B7 F5B7 F8B8
INPUT_SSTL15_I F0B7 F1B7 F2B7 F5B7 F8B8
INPUT_SSTL15_II F0B7 F1B7 F2B7 F5B7 F8B8
INPUT_SSTL18_I F0B7 F1B7 F2B7 F5B7 F8B8
INPUT_SSTL18_II F0B7 F1B7 F2B7 F5B7 F8B8
NONE F5B7
OUTPUT_HSUL12 F0B7 F5B7 F8B8
OUTPUT_LVCMOS12 F0B7 F5B7 F8B8
OUTPUT_LVCMOS15 F0B7 F5B7 F8B8
OUTPUT_LVCMOS18 F0B7 F5B7 F8B8
OUTPUT_LVCMOS25 F0B7 F5B7 F8B8
OUTPUT_LVCMOS33 F0B7 F1B8 F2B8 F3B8 F5B7 F8B8
OUTPUT_LVTTL33 F0B7 F1B8 F2B8 F3B8 F5B7 F8B8
OUTPUT_SSTL135_I F0B7 F2B8 F5B7 F8B8
OUTPUT_SSTL135_II F0B7 F1B8 F5B7 F8B8
OUTPUT_SSTL15_I F0B7 F2B8 F5B7 F8B8
OUTPUT_SSTL15_II F0B7 F1B8 F5B7 F8B8
OUTPUT_SSTL18_I F0B7 F5B7 F8B8
OUTPUT_SSTL18_II F0B7 F0B8 F1B8 F2B8 F3B8 F5B7 F8B8

.config_enum PIOD.DRIVE
12 F0B8 !F1B8 !F2B8 !F3B8 !F9B9
16 F0B8 F1B8 F2B8 F3B8 !F9B9
4 F0B8 F1B8 !F2B8 !F3B8 F9B9
8 !F0B8 F1B8 F2B8 F3B8 !F9B9

.config_enum PIOD.HYSTERESIS OFF
OFF !F4B8
ON F4B8

.config_enum PIOD.OPENDRAIN
OFF F1B8 F2B8 !F2B9 F3B8
ON !F1B8 !F2B8 F2B9 !F3B8

.config_enum PIOD.PULLMODE DOWN
DOWN !F0B7 !F9B8
NONE F0B7 !F9B8
UP F0B7 F9B8

.config_enum PIOD.SLEWRATE SLOW
FAST F3B9
SLOW !F3B9


# Fixed Connections