commit 1b5140cdbd8dec5941c92544d871293a21cbbe38
author gatecat <gatecat@ds0.me> Sat Jun 26 09:43:59 2021 +0100
committer GitHub <noreply@github.com> Sat Jun 26 09:43:59 2021 +0100
tree 63c708b0e319514706a49170808a349909c3669b
parent d7582c4a45afff1afe2a171c8020658a4450024c
parent 663ec874a4d25b09d831f3c71fa8ebeae82a5342

Merge pull request #168 from nneonneo/master

Add a tool for automatic bitstream -> Verilog conversion

diamond.sh

diff --git a/diamond.sh b/diamond.sh
index 6a69b2e..d54ee31 100755
--- a/diamond.sh
+++ b/diamond.sh
@@ -58,7 +58,7 @@
 else
 	export LD_LIBRARY_PATH="${bindir}:${fpgabindir}"
 fi
-export LM_LICENSE_FILE="${diamonddir}/license/license.dat"
+export LM_LICENSE_FILE="${LM_LICENSE_FILE:=${diamonddir}/license/license.dat}"
 
 set -ex
 if [[ $2 == *.ncl ]]

diamond_tcl.sh

diff --git a/diamond_tcl.sh b/diamond_tcl.sh
index 0bbb4f6..36db79e 100755
--- a/diamond_tcl.sh
+++ b/diamond_tcl.sh
@@ -41,7 +41,7 @@
 else
 	export LD_LIBRARY_PATH="${bindir}:${fpgabindir}"
 fi
-export LM_LICENSE_FILE="${diamonddir}/license/license.dat"
+export LM_LICENSE_FILE="${LM_LICENSE_FILE:=${diamonddir}/license/license.dat}"
 
 if $WINDOWS; then
     $FOUNDRY/userware/NT/bin/nt64/ispTcl $1

libtrellis/src/PyTrellis.cpp

diff --git a/libtrellis/src/PyTrellis.cpp b/libtrellis/src/PyTrellis.cpp
index 38ea056..ef4bbed 100644
--- a/libtrellis/src/PyTrellis.cpp
+++ b/libtrellis/src/PyTrellis.cpp
@@ -250,6 +250,7 @@
 
     // From BitDatabase.cpp
     class_<ConfigBit>(m, "ConfigBit")
+            .def(init<>())
             .def_readwrite("frame", &ConfigBit::frame)
             .def_readwrite("bit", &ConfigBit::bit)
             .def_readwrite("inv", &ConfigBit::inv);
@@ -263,6 +264,7 @@
         }, py::keep_alive<0, 1>()); /* Keep vector alive while iterator is used */
 
     class_<BitGroup>(m, "BitGroup")
+            .def(init<>())
             .def(init<const CRAMDelta &>())
             .def_readwrite("bits", &BitGroup::bits)
             .def("match", &BitGroup::match)
@@ -273,6 +275,7 @@
     py::bind_vector<vector<BitGroup>>(m, "BitGroupVector");
 
     class_<ArcData>(m, "ArcData")
+            .def(init<>())
             .def_readwrite("source", &ArcData::source)
             .def_readwrite("sink", &ArcData::sink)
             .def_readwrite("bits", &ArcData::bits);
@@ -287,6 +290,7 @@
             .def("set_driver", &MuxBits::set_driver);
 
     class_<WordSettingBits>(m, "WordSettingBits")
+            .def(init<>())
             .def_readwrite("name", &WordSettingBits::name)
             .def_readwrite("bits", &WordSettingBits::bits)
             .def_readwrite("defval", &WordSettingBits::defval)
@@ -296,6 +300,7 @@
     py::bind_map<map<string, BitGroup>>(m, "BitGroupMap");
 
     class_<EnumSettingBits>(m, "EnumSettingBits")
+            .def(init<>())
             .def_readwrite("name", &EnumSettingBits::name)
             .def_readwrite("options", &EnumSettingBits::options)
             .def("get_options", &EnumSettingBits::get_options)
@@ -356,6 +361,7 @@
     py::bind_vector<vector<ConfigUnknown>>(m, "ConfigUnknownVector");
 
     class_<TileConfig>(m, "TileConfig")
+            .def(init<>())
             .def_readwrite("carcs", &TileConfig::carcs)
             .def_readwrite("cwords", &TileConfig::cwords)
             .def_readwrite("cenums", &TileConfig::cenums)