)]}'
{
  "commit": "1b5140cdbd8dec5941c92544d871293a21cbbe38",
  "tree": "63c708b0e319514706a49170808a349909c3669b",
  "parents": [
    "d7582c4a45afff1afe2a171c8020658a4450024c",
    "663ec874a4d25b09d831f3c71fa8ebeae82a5342"
  ],
  "author": {
    "name": "gatecat",
    "email": "gatecat@ds0.me",
    "time": "Sat Jun 26 09:43:59 2021 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Sat Jun 26 09:43:59 2021 +0100"
  },
  "message": "Merge pull request #168 from nneonneo/master\n\nAdd a tool for automatic bitstream -\u003e Verilog conversion",
  "tree_diff": []
}