Merge pull request #172 from cr1901/facade
MachXO2 Support: Part 4
diff --git a/database b/database
index f7f8375..0ee729d 160000
--- a/database
+++ b/database
@@ -1 +1 @@
-Subproject commit f7f8375101dfa7f7d5ccb654ff8fcae73356ce48
+Subproject commit 0ee729d20eaf9f1e0f1d657bc6452e3ffe6a0d63
diff --git a/fuzzers/machxo2/051-pio_attrs/fuzzer.py b/fuzzers/machxo2/051-pio_attrs/fuzzer.py
index 9185f61..0d976d5 100644
--- a/fuzzers/machxo2/051-pio_attrs/fuzzer.py
+++ b/fuzzers/machxo2/051-pio_attrs/fuzzer.py
@@ -60,6 +60,30 @@
"side": "T",
"pins": [("28", "C"), ("27", "D")]
},
+
+ {
+ "cfg": FuzzConfig(job="PICRS0_IO", family="MachXO2", device="LCMXO2-1200HC",
+ ncl="empty.ncl", tiles=["PR3:PIC_RS0"]),
+ "side": "R",
+ "pins": [("71", "A"), ("70", "B")],
+ "package": "TQFP100"
+ },
+
+ {
+ "cfg": FuzzConfig(job="PICLS0_IO", family="MachXO2", device="LCMXO2-1200HC",
+ ncl="empty.ncl", tiles=["PL9:PIC_LS0"]),
+ "side": "L",
+ "pins": [("20", "A"), ("21", "B")],
+ "package": "TQFP100"
+ },
+
+ {
+ "cfg": FuzzConfig(job="PICL0VREF_IO", family="MachXO2", device="LCMXO2-1200HC",
+ ncl="empty.ncl", tiles=["PL4:PIC_L0_VREF3"]),
+ "side": "L",
+ "pins": [("11", "A"), ("12", "B"), ("13", "C"), ("14", "D")],
+ "package": "TQFP144"
+ },
]
# Function constructed from reading the MachXO2 sysIO Usage Guide.
diff --git a/fuzzers/machxo2/052-pio_fixup/fuzzer.py b/fuzzers/machxo2/052-pio_fixup/fuzzer.py
index 0bdf954..ee07d94 100644
--- a/fuzzers/machxo2/052-pio_fixup/fuzzer.py
+++ b/fuzzers/machxo2/052-pio_fixup/fuzzer.py
@@ -4,7 +4,10 @@
def main():
pytrellis.load_database("../../../database")
dbfixup.remove_enum_bits("MachXO2", "LCMXO2-1200HC", "PIC_L0", (29, 11))
+ dbfixup.remove_enum_bits("MachXO2", "LCMXO2-1200HC", "PIC_LS0", (29, 11))
+ dbfixup.remove_enum_bits("MachXO2", "LCMXO2-1200HC", "PIC_L0_VREF3", (29, 11))
dbfixup.remove_enum_bits("MachXO2", "LCMXO2-1200HC", "PIC_R0", (29, 59), (0, 48))
+ dbfixup.remove_enum_bits("MachXO2", "LCMXO2-1200HC", "PIC_RS0", (29, 59), (0, 48))
if __name__ == "__main__":
main()
diff --git a/libtrellis/src/Bels.cpp b/libtrellis/src/Bels.cpp
index 64a9025..5111c8a 100644
--- a/libtrellis/src/Bels.cpp
+++ b/libtrellis/src/Bels.cpp
@@ -753,9 +753,9 @@
bel.loc.y = y;
bel.z = z;
- graph.add_bel_input(bel, graph.ident("CLKI"), x, y, graph.ident(fmt("G_CLKI" << name << "_DCC")));
- graph.add_bel_input(bel, graph.ident("CE"), x, y, graph.ident(fmt("G_JCE" << name << "_DCC")));
- graph.add_bel_output(bel, graph.ident("CLKO"), x, y, graph.ident(fmt("G_CLKO" << name << "_DCC")));
+ graph.add_bel_input(bel, graph.ident("CLKI"), x, y, graph.ident(fmt("G_CLKI" << z << "_DCC")));
+ graph.add_bel_input(bel, graph.ident("CE"), x, y, graph.ident(fmt("G_JCE" << z << "_DCC")));
+ graph.add_bel_output(bel, graph.ident("CLKO"), x, y, graph.ident(fmt("G_CLKO" << z << "_DCC")));
graph.add_bel(bel);
}
diff --git a/util/fuzz/dbfixup.py b/util/fuzz/dbfixup.py
index 734522f..885849d 100644
--- a/util/fuzz/dbfixup.py
+++ b/util/fuzz/dbfixup.py
@@ -56,15 +56,14 @@
for enum in db.get_settings_enums():
fixed_enum = pytrellis.EnumSettingBits()
- for option in db.get_data_for_enum(enum).options:
- key = option.key()
+ for (option, data) in db.get_data_for_enum(enum).options.items():
fixed_bg = pytrellis.BitGroup()
- for bit in option.data().bits:
+ for bit in data.bits:
if in_bounding_box(bit):
fixed_bg.bits.add(bit)
- fixed_enum.options[key] = fixed_bg
+ fixed_enum.options[option] = fixed_bg
fixed_enum.name = db.get_data_for_enum(enum).name
fixed_enum.defval = db.get_data_for_enum(enum).defval
