commit 389c25162ee9c3c1d77b67b4643ed9d8df619614
author David Shah <dave@ds0.me> Wed Aug 26 20:01:18 2020 +0100
committer David Shah <dave@ds0.me> Wed Aug 26 20:01:18 2020 +0100
tree 6b5eb6e1dda1a839446117753727f65841be6e97
parent 8c0a6382e11b160ed88d17af8493c12a897617ed

fuzzers: Add missing JPADDI[AC]->JPADDI arc

Without this arc, there wasn't a complete path from dedicated clock
input pins to the global network. This meant that global clock inputs
weren't using the most predictable input path.

Signed-off-by: David Shah <dave@ds0.me>

database

diff --git a/database b/database
index c137076..09d1bbd 160000
--- a/database
+++ b/database
@@ -1 +1 @@
-Subproject commit c137076fdd8bfca3d2bf9cdacda9983dbbec599a
+Subproject commit 09d1bbd72f1a2350881139473a814614435429b4

fuzzers/ECP5/132-dlldel/fuzzer.py

diff --git a/fuzzers/ECP5/132-dlldel/fuzzer.py b/fuzzers/ECP5/132-dlldel/fuzzer.py
index 206cb91..9c552d2 100644
--- a/fuzzers/ECP5/132-dlldel/fuzzer.py
+++ b/fuzzers/ECP5/132-dlldel/fuzzer.py
@@ -6,15 +6,18 @@
 
 jobs = [(FuzzConfig(job="TDLLDEL", family="ECP5", device="LFE5U-45F", ncl="empty.ncl",
                     tiles=["MIB_R0C40:TMID_0", "MIB_R0C41:TMID_1"]),
-         [("DLLDEL_00", "R0C39"), ("DLLDEL_01", "R0C40"), ("DLLDEL_10", "R0C41"), ("DLLDEL_11", "R0C42")]
+         [("DLLDEL_00", "R0C39"), ("DLLDEL_01", "R0C40"), ("DLLDEL_10", "R0C41"), ("DLLDEL_11", "R0C42")],
+         ["R0C39_JPADDI", "R0C40_JPADDI", "R0C41_JPADDI", "R0C41_JPADDI"]
          ),
         (FuzzConfig(job="LDLLDEL", family="ECP5", device="LFE5U-45F", ncl="empty.ncl",
                     tiles=["CIB_R34C2:ECLK_L", "MIB_R34C3:LMID_0"]),
-         [("DLLDEL_61", "R36C0"), ("DLLDEL_60", "R35C0"), ("DLLDEL_71", "R34C0"), ("DLLDEL_70", "R33C0")]
+         [("DLLDEL_61", "R36C0"), ("DLLDEL_60", "R35C0"), ("DLLDEL_71", "R34C0"), ("DLLDEL_70", "R33C0")],
+         ["R36C0_JPADDI", "R35C0_JPADDI", "R34C0_JPADDI", "R33C0_JPADDI"]
          ),
         (FuzzConfig(job="RDLLDEL", family="ECP5", device="LFE5U-45F", ncl="empty.ncl",
                     tiles=["CIB_R34C88:ECLK_R", "MIB_R34C87:RMID_0"]),
-         [("DLLDEL_31", "R36C90"), ("DLLDEL_30", "R35C90"), ("DLLDEL_21", "R34C90"), ("DLLDEL_20", "R33C90")]
+         [("DLLDEL_31", "R36C90"), ("DLLDEL_30", "R35C90"), ("DLLDEL_21", "R34C90"), ("DLLDEL_20", "R33C90")],
+         ["R36C90_JPADDI", "R35C90_JPADDI", "R34C90_JPADDI", "R33C90_JPADDI"]
          ),
         ]
 
@@ -31,7 +34,7 @@
     pytrellis.load_database("../../../database")
 
     def per_job(job):
-        cfg, locs = job
+        cfg, locs, paddi = job
         cfg.setup()
 
         empty_bitfile = cfg.build_design(cfg.ncl, {})
@@ -81,7 +84,7 @@
                 "{}_JDIRECTION_DLLDEL".format(rc),
                 "{}_Z_DLLDEL".format(rc),
                 "{}_JINCK".format(rc),
-            ]
+            ] + paddi
 
             cfg.ncl = "dlldel_routing.ncl"
             interconnect.fuzz_interconnect_with_netnames(cfg, nets, bidir=True)