diff --git a/minitests/reg/async.v b/minitests/reg/async.v
new file mode 100644
index 0000000..23f921a
--- /dev/null
+++ b/minitests/reg/async.v
@@ -0,0 +1,7 @@
+module top(input clk, d, set, output reg q);
+    always @(posedge clk or posedge set)
+           if (set)
+                q <= 1'b1;
+           else
+                q <= d;
+endmodule
diff --git a/minitests/reg/ce.v b/minitests/reg/ce.v
new file mode 100644
index 0000000..bb4c05b
--- /dev/null
+++ b/minitests/reg/ce.v
@@ -0,0 +1,5 @@
+module top(input clk, input d, cen, output reg q);
+    always @(posedge clk)
+        if (cen)
+            q <= d;
+endmodule
diff --git a/minitests/reg/ce_over_lsr.v b/minitests/reg/ce_over_lsr.v
new file mode 100644
index 0000000..142ca13
--- /dev/null
+++ b/minitests/reg/ce_over_lsr.v
@@ -0,0 +1,8 @@
+module top(input clk, d, set, cen, output reg q);
+    always @(posedge clk)
+           if (cen)
+               if (set)
+                    q <= 1'b1;
+               else
+                    q <= d;
+endmodule
diff --git a/minitests/reg/clk_inv.v b/minitests/reg/clk_inv.v
new file mode 100644
index 0000000..83b51b7
--- /dev/null
+++ b/minitests/reg/clk_inv.v
@@ -0,0 +1,4 @@
+module top(input clk, input d, output reg q);
+    always @(negedge clk)
+        q <= d;
+endmodule
diff --git a/minitests/reg/plain.v b/minitests/reg/plain.v
new file mode 100644
index 0000000..1d7b658
--- /dev/null
+++ b/minitests/reg/plain.v
@@ -0,0 +1,4 @@
+module top(input clk, input d, output reg q);
+    always @(posedge clk)
+        q <= d;
+endmodule
diff --git a/minitests/reg/set.v b/minitests/reg/set.v
new file mode 100644
index 0000000..210803b
--- /dev/null
+++ b/minitests/reg/set.v
@@ -0,0 +1,7 @@
+module top(input clk, d, set, output reg q);
+    always @(posedge clk)
+           if (set)
+                q <= 1'b1;
+           else
+                q <= d;
+endmodule