minitests: Various IOLOGIC minitests
Signed-off-by: David Shah <davey1576@gmail.com>
diff --git a/fuzzers/061-basic_ddr/empty.ncl b/fuzzers/061-basic_ddr/empty.ncl
new file mode 100644
index 0000000..b9caf7a
--- /dev/null
+++ b/fuzzers/061-basic_ddr/empty.ncl
@@ -0,0 +1,12 @@
+::FROM-WRITER;
+design top
+{
+ device
+ {
+ architecture sa5p00;
+ device LFE5U-25F;
+ package CABGA381;
+ performance "8";
+ }
+
+}
diff --git a/fuzzers/061-basic_ddr/fuzzer.py b/fuzzers/061-basic_ddr/fuzzer.py
new file mode 100644
index 0000000..c987bd0
--- /dev/null
+++ b/fuzzers/061-basic_ddr/fuzzer.py
@@ -0,0 +1,117 @@
+from fuzzconfig import FuzzConfig
+import nonrouting
+import pytrellis
+import fuzzloops
+
+jobs = [
+ {
+ "cfg": FuzzConfig(job="IOLOGICLA", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
+ tiles=["MIB_R14C0:PICL0", "MIB_R15C0:PICL1", "MIB_R16C0:PICL2"]),
+ "side": "L",
+ "site": "IOL_L14A",
+ "iol": "A"
+ },
+ {
+ "cfg": FuzzConfig(job="IOLOGICLB", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
+ tiles=["MIB_R14C0:PICL0", "MIB_R15C0:PICL1", "MIB_R16C0:PICL2"]),
+ "side": "L",
+ "site": "IOL_L14B",
+ "iol": "B"
+ },
+ {
+ "cfg": FuzzConfig(job="IOLOGICLC", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
+ tiles=["MIB_R14C0:PICL0", "MIB_R15C0:PICL1", "MIB_R16C0:PICL2"]),
+ "side": "L",
+ "site": "IOL_L14C",
+ "iol": "C"
+ },
+ {
+ "cfg": FuzzConfig(job="IOLOGICLD", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
+ tiles=["MIB_R14C0:PICL0", "MIB_R15C0:PICL1", "MIB_R16C0:PICL2"]),
+ "side": "L",
+ "site": "IOL_L14D",
+ "iol": "D"
+ },
+ {
+ "cfg": FuzzConfig(job="IOLOGICRA", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
+ tiles=["MIB_R14C72:PICR0", "MIB_R15C72:PICR1", "MIB_R16C72:PICR2"]),
+ "side": "R",
+ "site": "IOL_R14A",
+ "iol": "A"
+ },
+ {
+ "cfg": FuzzConfig(job="IOLOGICRB", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
+ tiles=["MIB_R14C72:PICR0", "MIB_R15C72:PICR1", "MIB_R16C72:PICR2"]),
+ "side": "R",
+ "site": "IOL_R14B",
+ "iol": "B"
+ },
+ {
+ "cfg": FuzzConfig(job="IOLOGICRC", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
+ tiles=["MIB_R14C72:PICR0", "MIB_R15C72:PICR1", "MIB_R16C72:PICR2"]),
+ "side": "R",
+ "site": "IOL_R14C",
+ "iol": "C"
+ },
+ {
+ "cfg": FuzzConfig(job="IOLOGICRD", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
+ tiles=["MIB_R14C72:PICR0", "MIB_R15C72:PICR1", "MIB_R16C72:PICR2"]),
+ "side": "R",
+ "site": "IOL_R14D",
+ "iol": "D"
+ },
+ {
+ "cfg": FuzzConfig(job="IOLOGICTA", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
+ tiles=["MIB_R0C20:PIOT0", "MIB_R0C21:PIOT1", "MIB_R1C20:PICT0", "MIB_R1C21:PICT1"]),
+ "side": "T",
+ "site": "IOL_T20A",
+ "iol": "A"
+ },
+ {
+ "cfg": FuzzConfig(job="IOLOGICTB", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
+ tiles=["MIB_R0C20:PIOT0", "MIB_R0C21:PIOT1", "MIB_R1C20:PICT0", "MIB_R1C21:PICT1"]),
+ "side": "T",
+ "site": "IOL_T20B",
+ "iol": "B"
+ },
+]
+
+
+def main():
+ pytrellis.load_database("../../database")
+ pytrellis.load_database("../../database")
+
+ def per_job(job):
+ def get_substs(mode="IREG_OREG", program=[]):
+ if mode == "NONE":
+ comment = "//"
+ program = ""
+ else:
+ comment = ""
+ program = "program " + "\n\t\t\t".join(['"' + _ + ' "' for _ in program])
+ if side in ("T, B"):
+ s = "S"
+ else:
+ s = ""
+ return dict(loc=loc, mode=mode, program=program, comment=comment, s=s)
+
+ cfg = job["cfg"]
+ loc = job["site"]
+ iol = job["iol"]
+ side = job["side"]
+
+ cfg.setup()
+ empty_bitfile = cfg.build_design(cfg.ncl, {})
+ cfg.ncl = "iologic.ncl"
+ modes = ["NONE", "IREG_OREG", "IDDRX1_ODDRX1"]
+ if side in ("L", "R"):
+ modes += ["IDDRXN", "ODDRXN", "MIDDRX_MODDRX"]
+ tie_program = ["LSRIMUX:0", "LSROMUX:0"]
+ nonrouting.fuzz_enum_setting(cfg, "IOLOGIC{}.MODE".format(iol), modes,
+ lambda x: get_substs(mode=x, program=["MODE:" + x] + tie_program), empty_bitfile, False)
+
+ fuzzloops.parallel_foreach(jobs, per_job)
+
+
+if __name__ == "__main__":
+ main()
diff --git a/fuzzers/061-basic_ddr/iologic.ncl b/fuzzers/061-basic_ddr/iologic.ncl
new file mode 100644
index 0000000..582283c
--- /dev/null
+++ b/fuzzers/061-basic_ddr/iologic.ncl
@@ -0,0 +1,21 @@
+::FROM-WRITER;
+design top
+{
+ device
+ {
+ architecture sa5p00;
+ device LFE5U-25F;
+ package CABGA381;
+ performance "8";
+ }
+
+ ${comment} comp Q_MGIOL
+ ${comment} {
+ ${comment} logical
+ ${comment} {
+ ${comment} cellmodel-name ${s}IOLOGIC;
+ ${comment} ${program};
+ ${comment} }
+ ${comment} site ${loc};
+ ${comment} }
+}
diff --git a/minitests/iologic/iddr_LSR.v b/minitests/iologic/iddr_LSR.v
new file mode 100644
index 0000000..e20b3ed
--- /dev/null
+++ b/minitests/iologic/iddr_LSR.v
@@ -0,0 +1,6 @@
+module iddr(input [3:0] D, SCLK, RST, output [3:0] Q0, Q1);
+IDDRX1F iddr_i0(.D(D[0]), .SCLK(SCLK), .RST(RST), .Q0(Q0[0]), .Q1(Q1[0]));
+IDDRX1F iddr_i1(.D(D[1]), .SCLK(SCLK), .RST(!RST), .Q0(Q0[1]), .Q1(Q1[1]));
+IDDRX1F iddr_i2(.D(D[2]), .SCLK(SCLK), .RST(RST||Q0[0]), .Q0(Q0[2]), .Q1(Q1[2]));
+endmodule
+
diff --git a/minitests/iologic/iddr_inv.v b/minitests/iologic/iddr_inv.v
new file mode 100644
index 0000000..0e6d9be
--- /dev/null
+++ b/minitests/iologic/iddr_inv.v
@@ -0,0 +1,4 @@
+module iddr(input D, SCLK, RST, output Q0, Q1);
+IDDRX1F iddr_i(.D(D), .SCLK(!SCLK), .RST(RST), .Q0(Q0), .Q1(Q1));
+endmodule
+
diff --git a/minitests/iologic/oshx2a.v b/minitests/iologic/oshx2a.v
new file mode 100644
index 0000000..987b764
--- /dev/null
+++ b/minitests/iologic/oshx2a.v
@@ -0,0 +1,9 @@
+module oshx(input [1:0] D, input ECLK, RST, output Q);
+wire SCLK;
+
+CLKDIVF #(.DIV("2.0")) cdiv_i (.CLKI(ECLK), .RST(RST), .ALIGNWD(1'b0), .CDIVX(SCLK));
+
+OSHX2A OSHX2A_i(.D0(D[0]), .D1(D[1]),
+ .ECLK(ECLK), .SCLK(SCLK), .RST(RST),
+ .Q(Q));
+endmodule
