Add incomplete MachXO2 minitests and experiments.
diff --git a/experiments/machxo2/ccu2_mux/ccu2_diff.txt b/experiments/machxo2/ccu2_mux/ccu2_diff.txt
new file mode 100644
index 0000000..d11d3d7
--- /dev/null
+++ b/experiments/machxo2/ccu2_mux/ccu2_diff.txt
@@ -0,0 +1,322 @@
+CENTER10:CENTER_DUMMY
+CENTER11:CENTER_B_CIB
+CENTER1:CENTER_T_CIB
+CENTER2:CENTER_DUMMY
+CENTER3:CENTER_DUMMY
+CENTER4:CENTER4
+CENTER5:CENTER5
+CENTER6:CENTER_EBR_CIB
+CENTER7:CENTER6
+CENTER8:CENTER7
+CENTER9:CENTER8
+CENTER_B:CENTER_B
+CENTER_EBR14:CENTER_EBR
+CENTER_T:CENTER_T
+CIB_R11C10:CIB_PIC_B_DUMMY
+CIB_R11C11:CIB_PIC_B0
+CIB_R11C12:CIB_PIC_B_DUMMY
+CIB_R11C13:CIB_PIC_B_DUMMY
+CIB_R11C14:CIB_PIC_B_DUMMY
+CIB_R11C15:CIB_PIC_B0
+CIB_R11C16:CIB_PIC_B_DUMMY
+CIB_R11C17:CIB_PIC_B_DUMMY
+CIB_R11C18:CIB_PIC_B0
+CIB_R11C19:CIB_PIC_B_DUMMY
+CIB_R11C20:CIB_PIC_B0
+CIB_R11C21:CIB_PIC_B_DUMMY
+CIB_R11C2:CIB_PIC_B_DUMMY
+CIB_R11C3:CIB_PIC_B_DUMMY
+CIB_R11C4:CIB_PIC_B0
+CIB_R11C5:CIB_PIC_B_DUMMY
+CIB_R11C6:CIB_PIC_B0
+CIB_R11C7:CIB_PIC_B_DUMMY
+CIB_R11C8:CIB_PIC_B_DUMMY
+CIB_R11C9:CIB_PIC_B0
+CIB_R1C10:CIB_PIC_T0
+CIB_R1C11:CIB_PIC_T0
+CIB_R1C12:CIB_PIC_T0
+CIB_R1C13:CIB_PIC_T_DUMMY
+CIB_R1C14:CIB_PIC_T_DUMMY
+CIB_R1C15:CIB_PIC_T0
+CIB_R1C16:CIB_PIC_T0
+CIB_R1C17:CIB_PIC_T0
+CIB_R1C18:CIB_PIC_T_DUMMY
+CIB_R1C19:CIB_PIC_T_DUMMY
+CIB_R1C20:CIB_PIC_T_DUMMY
+CIB_R1C21:CIB_PIC_T_DUMMY
+CIB_R1C2:CIB_PIC_T_DUMMY
+CIB_R1C3:CIB_PIC_T_DUMMY
+CIB_R1C4:CIB_CFG0
+CIB_R1C5:CIB_CFG1
+CIB_R1C6:CIB_CFG2
+CIB_R1C7:CIB_CFG3
+CIB_R1C8:CIB_PIC_T_DUMMY
+CIB_R1C9:CIB_PIC_T0
+CIB_R6C10:CIB_EBR0
+CIB_R6C11:CIB_EBR1
+CIB_R6C12:CIB_EBR2
+CIB_R6C13:CIB_EBR_DUMMY
+CIB_R6C14:CIB_EBR0
+CIB_R6C15:CIB_EBR1
+CIB_R6C16:CIB_EBR2
+CIB_R6C17:CIB_EBR0
+CIB_R6C18:CIB_EBR1
+CIB_R6C19:CIB_EBR2
+CIB_R6C1:CIB_EBR0_END0
+CIB_R6C20:CIB_EBR0
+CIB_R6C21:CIB_EBR1
+CIB_R6C22:CIB_EBR2_END0
+CIB_R6C2:CIB_EBR1
+CIB_R6C3:CIB_EBR2
+CIB_R6C4:CIB_EBR0
+CIB_R6C5:CIB_EBR1
+CIB_R6C6:CIB_EBR2
+CIB_R6C7:CIB_EBR0
+CIB_R6C8:CIB_EBR1
+CIB_R6C9:CIB_EBR2
+EBR_R6C10:EBR0
+EBR_R6C11:EBR1
+EBR_R6C12:EBR2
+EBR_R6C13:EBR_DUMMY
+EBR_R6C14:EBR0
+EBR_R6C15:EBR1
+EBR_R6C16:EBR2
+EBR_R6C17:EBR0
+EBR_R6C18:EBR1
+EBR_R6C19:EBR2
+EBR_R6C1:EBR0_END
+EBR_R6C20:EBR0
+EBR_R6C21:EBR1
+EBR_R6C22:EBR2_END
+EBR_R6C2:EBR1
+EBR_R6C3:EBR2
+EBR_R6C4:EBR0
+EBR_R6C5:EBR1
+EBR_R6C6:EBR2
+EBR_R6C7:EBR0
+EBR_R6C8:EBR1
+EBR_R6C9:EBR2
+PB10:PIC_B_DUMMY_VREF
+PB11:PIC_B0
+PB12:PIC_B_DUMMY
+PB13:PIC_B_DUMMY_VIQ
+PB14:PIC_B_DUMMY
+PB15:PIC_B0
+PB16:PIC_B_DUMMY
+PB17:PIC_B_DUMMY
+PB18:PIC_B0
+PB19:PIC_B_DUMMY
+PB1:B_DUMMY_ENDL
+PB20:PIC_B0
+PB21:PIC_B_DUMMY
+PB22:B_DUMMY_ENDR
+PB2:DQSDLL_L
+PB3:PIC_B_DUMMY
+PB4:PIC_B0
+PB5:PIC_B_DUMMY
+PB6:PIC_B0
+PB7:PIC_B_DUMMY
+PB8:PIC_B_DUMMY
+PB9:PIC_B0
+PL10:PIC_L0
+PL11:LLC0
+PL1:ULC0
+PL2:PIC_L0
+PL3:PIC_L0
+PL4:PIC_L0_VREF3
+PL5:PIC_L0
+PL7:PIC_L0_DUMMY
+PL8:PIC_L0
+PL9:PIC_LS0
+PR10:PIC_R0
+PR11:LRC0
+PR1:URC0
+PR2:PIC_R0
+PR3:PIC_RS0
+PR4:PIC_R0
+PR5:PIC_R0
+PR7:PIC_R0_DUMMY
+PR8:PIC_R0
+PR9:PIC_R0
+PT10:PIC_T0
+PT11:PIC_T0
+PT12:PIC_T0
+PT13:PIC_T_DUMMY_VIQ
+PT14:PIC_T_DUMMY
+PT15:PIC_T0
+PT16:PIC_T0
+PT17:PIC_T0
+PT18:PIC_T_DUMMY
+PT19:PIC_T_DUMMY
+PT1:GPLL_L0
+PT20:PIC_T_DUMMY
+PT21:DQSDLL_R
+PT22:T_DUMMY_ENDR
+PT2:PIC_T_DUMMY
+PT3:PIC_T_DUMMY
+PT4:CFG0
+PT5:CFG1
+PT6:CFG2
+PT7:CFG3
+PT8:PIC_T_DUMMY_OSC
+PT9:PIC_T0
+R10C10:PLC
+R10C11:PLC !F24B13 !F24B14 !F24B15 !F24B16 !F24B17 !F24B18 F24B19 F24B20 F24B29 F24B30 !F24B31 !F24B32 !F24B33 !F24B34 !F24B35 !F24B36 F25B13 F25B14 F25B15 F25B16 F25B17 F25B18 F25B19 F25B20 F25B29 F25B30 F25B31 F25B32 F25B33 F25B34 F25B35 F25B36 F26B13 F26B14 F26B15 F26B16 F26B17 F26B18 F26B19 F26B20 F26B29 F26B30 F26B31 F26B32 F26B33 F26B34 F26B35 F26B36 F26B37 F26B38 F26B39 F26B40 F26B41 F26B42 F26B43 F26B44 !F27B13 !F27B14 !F27B15 !F27B16 !F27B17 !F27B18 F27B19 F27B20 F27B29 F27B30 !F27B31 !F27B32 !F27B33 !F27B34 !F27B35 !F27B36 !F27B37 !F27B38 !F27B39 !F27B40 !F27B41 !F27B42 F27B43 F27B44
+R10C12:PLC
+R10C13:PLC
+R10C14:PLC
+R10C15:PLC
+R10C16:PLC
+R10C17:PLC
+R10C18:PLC
+R10C19:PLC
+R10C20:PLC
+R10C21:PLC
+R10C2:PLC
+R10C3:PLC
+R10C4:PLC
+R10C5:PLC
+R10C6:PLC
+R10C7:PLC
+R10C8:PLC
+R10C9:PLC
+R2C10:PLC
+R2C11:PLC
+R2C12:PLC
+R2C13:PLC
+R2C14:PLC
+R2C15:PLC
+R2C16:PLC
+R2C17:PLC
+R2C18:PLC
+R2C19:PLC
+R2C20:PLC
+R2C21:PLC
+R2C2:PLC
+R2C3:PLC
+R2C4:PLC
+R2C5:PLC
+R2C6:PLC
+R2C7:PLC
+R2C8:PLC
+R2C9:PLC
+R3C10:PLC
+R3C11:PLC
+R3C12:PLC
+R3C13:PLC
+R3C14:PLC
+R3C15:PLC
+R3C16:PLC
+R3C17:PLC
+R3C18:PLC
+R3C19:PLC
+R3C20:PLC
+R3C21:PLC
+R3C2:PLC
+R3C3:PLC
+R3C4:PLC
+R3C5:PLC
+R3C6:PLC
+R3C7:PLC
+R3C8:PLC
+R3C9:PLC
+R4C10:PLC
+R4C11:PLC
+R4C12:PLC
+R4C13:PLC
+R4C14:PLC
+R4C15:PLC
+R4C16:PLC
+R4C17:PLC
+R4C18:PLC
+R4C19:PLC
+R4C20:PLC
+R4C21:PLC
+R4C2:PLC
+R4C3:PLC
+R4C4:PLC
+R4C5:PLC
+R4C6:PLC
+R4C7:PLC
+R4C8:PLC
+R4C9:PLC
+R5C10:PLC
+R5C11:PLC
+R5C12:PLC
+R5C13:PLC
+R5C14:PLC
+R5C15:PLC
+R5C16:PLC
+R5C17:PLC
+R5C18:PLC
+R5C19:PLC
+R5C20:PLC
+R5C21:PLC
+R5C2:PLC
+R5C3:PLC
+R5C4:PLC
+R5C5:PLC
+R5C6:PLC
+R5C7:PLC
+R5C8:PLC
+R5C9:PLC
+R7C10:PLC
+R7C11:PLC
+R7C12:PLC
+R7C13:PLC
+R7C14:PLC
+R7C15:PLC
+R7C16:PLC
+R7C17:PLC
+R7C18:PLC
+R7C19:PLC
+R7C20:PLC
+R7C21:PLC
+R7C2:PLC
+R7C3:PLC
+R7C4:PLC
+R7C5:PLC
+R7C6:PLC
+R7C7:PLC
+R7C8:PLC
+R7C9:PLC
+R8C10:PLC
+R8C11:PLC
+R8C12:PLC
+R8C13:PLC
+R8C14:PLC
+R8C15:PLC
+R8C16:PLC
+R8C17:PLC
+R8C18:PLC
+R8C19:PLC
+R8C20:PLC
+R8C21:PLC
+R8C2:PLC
+R8C3:PLC
+R8C4:PLC
+R8C5:PLC
+R8C6:PLC
+R8C7:PLC
+R8C8:PLC
+R8C9:PLC
+R9C10:PLC
+R9C11:PLC
+R9C12:PLC
+R9C13:PLC
+R9C14:PLC
+R9C15:PLC
+R9C16:PLC
+R9C17:PLC
+R9C18:PLC
+R9C19:PLC
+R9C20:PLC
+R9C21:PLC
+R9C2:PLC
+R9C3:PLC
+R9C4:PLC
+R9C5:PLC
+R9C6:PLC
+R9C7:PLC
+R9C8:PLC
+R9C9:PLC
diff --git a/experiments/machxo2/ccu2_mux/ccu2_mux.py b/experiments/machxo2/ccu2_mux/ccu2_mux.py
new file mode 100644
index 0000000..316a43f
--- /dev/null
+++ b/experiments/machxo2/ccu2_mux/ccu2_mux.py
@@ -0,0 +1,48 @@
+import diamond
+from string import Template
+import pytrellis
+import shutil
+import os
+
+# With this experiment, I concluded that CCU2 doesn't really control any bits.
+# This experiment doesn't run as-is- add.bit/sub.bit are missing. I may re-add
+# them later.
+
+device = "LCMXO2-1200HC"
+
+def run_get_tiles(muxcfg):
+ with open("ccu2_template.ncl", "r") as inf:
+ with open("work/ccu2.ncl", "w") as ouf:
+ ouf.write(Template(inf.read()).substitute(muxcfg=muxcfg))
+ diamond.run(device, "work/ccu2.ncl")
+ bs = pytrellis.Bitstream.read_bit("work/ccu2.bit")
+ chip = bs.deserialise_chip()
+ return chip.tiles
+
+
+def main():
+ pytrellis.load_database("../../../database")
+ shutil.rmtree("work", ignore_errors=True)
+ os.mkdir("work")
+ baseline = run_get_tiles("::B0=0,C0=0,D0=0,A1=0,B1=0,C1=0,D1=0 ")
+
+ # baseline = pytrellis.Bitstream.read_bit("../../../minitests/math/add.bit").deserialise_chip().tiles
+ # modified = pytrellis.Bitstream.read_bit("../../../minitests/math/sub.bit").deserialise_chip().tiles
+
+ with open("ccu2_diff.txt", "w") as f:
+ for m in ["::A0=0,B0=0,C0=0,D0=0,B1=0,C1=0,D1=0 "]:
+ modified = run_get_tiles(m)
+
+ tile_keys = []
+ for t in modified:
+ tile_keys.append(t.key())
+
+ for k in tile_keys:
+ diff = modified[k].cram - baseline[k].cram
+ diff_str = ["{}F{}B{}".format("!" if b.delta < 0 else "", b.frame, b.bit) for b in diff]
+ print("{0: <18}{1}".format(k, " ".join(diff_str)), file=f)
+ f.flush()
+
+
+if __name__ == "__main__":
+ main()
diff --git a/experiments/machxo2/ccu2_mux/ccu2_template.ncl b/experiments/machxo2/ccu2_mux/ccu2_template.ncl
new file mode 100644
index 0000000..d49ac03
--- /dev/null
+++ b/experiments/machxo2/ccu2_mux/ccu2_template.ncl
@@ -0,0 +1,25 @@
+::FROM-WRITER;
+design top
+{
+ device
+ {
+ architecture xo2c00;
+ device LCMXO2-1200HC;
+ package QFN32;
+ performance "6";
+ }
+
+ comp SLICE_0
+ {
+ logical
+ {
+ cellmodel-name SLICE;
+ program "MODE:CCU2 "
+ "CCU2::S0=0xfaaa,S1=0xfaaa${muxcfg}"
+ "FCO:FCO ";
+ primitive CCU2 "CCU";
+ }
+ site R10C11A;
+ }
+
+}
diff --git a/minitests/machxo2/efb/EFB.v b/minitests/machxo2/efb/EFB.v
new file mode 100644
index 0000000..03ef199
--- /dev/null
+++ b/minitests/machxo2/efb/EFB.v
@@ -0,0 +1,140 @@
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2 */
+/* Module Version: 1.2 */
+/* C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 50 -i2c1 -i2c1_freq 100 -i2c1_sa 0001000001 -i2c1_addr 10 -i2c2 -i2c2_freq 100 -i2c2_sa 0001000010 -i2c2_addr 10 -wb -dev 1200 */
+/* Tue Nov 13 20:08:07 2018 */
+
+
+`timescale 1 ns / 1 ps
+module EFB_top (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
+ wb_dat_i, wb_dat_o, wb_ack_o, i2c1_scl, i2c1_sda, i2c1_irqo,
+ i2c2_scl, i2c2_sda, i2c2_irqo)/* synthesis NGD_DRC_MASK=1 */;
+ input wire wb_clk_i;
+ input wire wb_rst_i;
+ input wire wb_cyc_i;
+ input wire wb_stb_i;
+ input wire wb_we_i;
+ input wire [7:0] wb_adr_i;
+ input wire [7:0] wb_dat_i;
+ output wire [7:0] wb_dat_o;
+ output wire wb_ack_o;
+ output wire i2c1_irqo;
+ output wire i2c2_irqo;
+ inout wire i2c1_scl;
+ inout wire i2c1_sda;
+ inout wire i2c2_scl;
+ inout wire i2c2_sda;
+
+ wire scuba_vhi;
+ wire scuba_vlo;
+ wire i2c2_sdaoen;
+ wire i2c2_sdao;
+ wire i2c2_scloen;
+ wire i2c2_sclo;
+ wire i2c2_sdai;
+ wire i2c2_scli;
+ wire i2c1_sdaoen;
+ wire i2c1_sdao;
+ wire i2c1_scloen;
+ wire i2c1_sclo;
+ wire i2c1_sdai;
+ wire i2c1_scli;
+
+ VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+ VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+ BB BB2_sda (.I(i2c2_sdao), .T(i2c2_sdaoen), .O(i2c2_sdai), .B(i2c2_sda));
+
+ BB BB2_scl (.I(i2c2_sclo), .T(i2c2_scloen), .O(i2c2_scli), .B(i2c2_scl));
+
+ BB BB1_sda (.I(i2c1_sdao), .T(i2c1_sdaoen), .O(i2c1_sdai), .B(i2c1_sda));
+
+ BB BB1_scl (.I(i2c1_sclo), .T(i2c1_scloen), .O(i2c1_scli), .B(i2c1_scl));
+
+ defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
+ defparam EFBInst_0.UFM_INIT_FILE_NAME = "NONE" ;
+ defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "ENABLED" ;
+ defparam EFBInst_0.UFM_INIT_START_PAGE = 0 ;
+ defparam EFBInst_0.UFM_INIT_PAGES = 0 ;
+ defparam EFBInst_0.DEV_DENSITY = "1200L" ;
+ defparam EFBInst_0.EFB_UFM = "DISABLED" ;
+ defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ;
+ defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ;
+ defparam EFBInst_0.TC_ICR_INT = "OFF" ;
+ defparam EFBInst_0.TC_OCR_INT = "OFF" ;
+ defparam EFBInst_0.TC_OV_INT = "OFF" ;
+ defparam EFBInst_0.TC_TOP_SEL = "OFF" ;
+ defparam EFBInst_0.TC_RESETN = "ENABLED" ;
+ defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ;
+ defparam EFBInst_0.TC_OCR_SET = 32767 ;
+ defparam EFBInst_0.TC_TOP_SET = 65535 ;
+ defparam EFBInst_0.GSR = "ENABLED" ;
+ defparam EFBInst_0.TC_CCLK_SEL = 1 ;
+ defparam EFBInst_0.TC_MODE = "CTCM" ;
+ defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ;
+ defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ;
+ defparam EFBInst_0.EFB_TC = "DISABLED" ;
+ defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ;
+ defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ;
+ defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ;
+ defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ;
+ defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ;
+ defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ;
+ defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ;
+ defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ;
+ defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ;
+ defparam EFBInst_0.SPI_CLK_DIVIDER = 1 ;
+ defparam EFBInst_0.SPI_MODE = "MASTER" ;
+ defparam EFBInst_0.EFB_SPI = "DISABLED" ;
+ defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ;
+ defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ;
+ defparam EFBInst_0.I2C2_CLK_DIVIDER = 125 ;
+ defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ;
+ defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b0001000010" ;
+ defparam EFBInst_0.I2C2_ADDRESSING = "10BIT" ;
+ defparam EFBInst_0.EFB_I2C2 = "ENABLED" ;
+ defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ;
+ defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ;
+ defparam EFBInst_0.I2C1_CLK_DIVIDER = 125 ;
+ defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ;
+ defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b0001000001" ;
+ defparam EFBInst_0.I2C1_ADDRESSING = "10BIT" ;
+ defparam EFBInst_0.EFB_I2C1 = "ENABLED" ;
+ defparam EFBInst_0.EFB_WB_CLK_FREQ = "50.0" ;
+ EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
+ .WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]),
+ .WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]),
+ .WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]),
+ .WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]),
+ .WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]),
+ .WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo),
+ .PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo),
+ .PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo),
+ .PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo),
+ .PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo),
+ .PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo),
+ .PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(i2c1_scli),
+ .I2C1SDAI(i2c1_sdai), .I2C2SCLI(i2c2_scli), .I2C2SDAI(i2c2_sdai),
+ .SPISCKI(scuba_vlo), .SPIMISOI(scuba_vlo), .SPIMOSII(scuba_vlo),
+ .SPISCSN(scuba_vlo), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo),
+ .UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]),
+ .WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]),
+ .WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]),
+ .WBACKO(wb_ack_o), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(),
+ .PLLWEO(), .PLLADRO4(), .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(),
+ .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
+ .PLLDATO2(), .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(i2c1_sclo), .I2C1SCLOEN(i2c1_scloen),
+ .I2C1SDAO(i2c1_sdao), .I2C1SDAOEN(i2c1_sdaoen), .I2C2SCLO(i2c2_sclo),
+ .I2C2SCLOEN(i2c2_scloen), .I2C2SDAO(i2c2_sdao), .I2C2SDAOEN(i2c2_sdaoen),
+ .I2C1IRQO(i2c1_irqo), .I2C2IRQO(i2c2_irqo), .SPISCKO(), .SPISCKEN(),
+ .SPIMISOO(), .SPIMISOEN(), .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN7(),
+ .SPIMCSN6(), .SPIMCSN5(), .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(),
+ .SPIMCSN1(), .SPIMCSN0(), .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(),
+ .WBCUFMIRQ(), .CFGWAKE(), .CFGSTDBY());
+
+
+
+ // exemplar begin
+ // exemplar end
+
+endmodule
diff --git a/minitests/machxo2/efb2/EFB.v b/minitests/machxo2/efb2/EFB.v
new file mode 100644
index 0000000..a7b7d55
--- /dev/null
+++ b/minitests/machxo2/efb2/EFB.v
@@ -0,0 +1,139 @@
+/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2 */
+/* Module Version: 1.2 */
+/* C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 50 -spi -spi_mode Both -spi_lsb -spi_freq 1 -spi_cs 3 -pll1 -wb -dev 1200 */
+/* Tue Nov 13 20:01:18 2018 */
+
+
+`timescale 1 ns / 1 ps
+module EFB_top (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
+ wb_dat_i, wb_dat_o, wb_ack_o, spi_clk, spi_miso, spi_mosi, spi_scsn,
+ spi_csn, pll0_bus_i, pll0_bus_o)/* synthesis NGD_DRC_MASK=1 */;
+ input wire wb_clk_i;
+ input wire wb_rst_i;
+ input wire wb_cyc_i;
+ input wire wb_stb_i;
+ input wire wb_we_i;
+ input wire [7:0] wb_adr_i;
+ input wire [7:0] wb_dat_i;
+ input wire spi_scsn;
+ input wire [8:0] pll0_bus_i;
+ output wire [7:0] wb_dat_o;
+ output wire wb_ack_o;
+ output wire [2:0] spi_csn;
+ output wire [16:0] pll0_bus_o;
+ inout wire spi_clk;
+ inout wire spi_miso;
+ inout wire spi_mosi;
+
+ wire scuba_vhi;
+ wire spi_mosi_oe;
+ wire spi_mosi_o;
+ wire spi_miso_oe;
+ wire spi_miso_o;
+ wire spi_clk_oe;
+ wire spi_clk_o;
+ wire spi_mosi_i;
+ wire spi_miso_i;
+ wire spi_clk_i;
+ wire scuba_vlo;
+
+ VHI scuba_vhi_inst (.Z(scuba_vhi));
+
+ BB BBspi_mosi (.I(spi_mosi_o), .T(spi_mosi_oe), .O(spi_mosi_i), .B(spi_mosi));
+
+ BB BBspi_miso (.I(spi_miso_o), .T(spi_miso_oe), .O(spi_miso_i), .B(spi_miso));
+
+ BB BBspi_clk (.I(spi_clk_o), .T(spi_clk_oe), .O(spi_clk_i), .B(spi_clk));
+
+ VLO scuba_vlo_inst (.Z(scuba_vlo));
+
+ defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
+ defparam EFBInst_0.UFM_INIT_FILE_NAME = "NONE" ;
+ defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "ENABLED" ;
+ defparam EFBInst_0.UFM_INIT_START_PAGE = 0 ;
+ defparam EFBInst_0.UFM_INIT_PAGES = 0 ;
+ defparam EFBInst_0.DEV_DENSITY = "1200L" ;
+ defparam EFBInst_0.EFB_UFM = "DISABLED" ;
+ defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ;
+ defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ;
+ defparam EFBInst_0.TC_ICR_INT = "OFF" ;
+ defparam EFBInst_0.TC_OCR_INT = "OFF" ;
+ defparam EFBInst_0.TC_OV_INT = "OFF" ;
+ defparam EFBInst_0.TC_TOP_SEL = "OFF" ;
+ defparam EFBInst_0.TC_RESETN = "ENABLED" ;
+ defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ;
+ defparam EFBInst_0.TC_OCR_SET = 32767 ;
+ defparam EFBInst_0.TC_TOP_SET = 65535 ;
+ defparam EFBInst_0.GSR = "ENABLED" ;
+ defparam EFBInst_0.TC_CCLK_SEL = 1 ;
+ defparam EFBInst_0.TC_MODE = "CTCM" ;
+ defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ;
+ defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ;
+ defparam EFBInst_0.EFB_TC = "DISABLED" ;
+ defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ;
+ defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ;
+ defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ;
+ defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ;
+ defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ;
+ defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ;
+ defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ;
+ defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ;
+ defparam EFBInst_0.SPI_LSB_FIRST = "ENABLED" ;
+ defparam EFBInst_0.SPI_CLK_DIVIDER = 50 ;
+ defparam EFBInst_0.SPI_MODE = "BOTH" ;
+ defparam EFBInst_0.EFB_SPI = "ENABLED" ;
+ defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ;
+ defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ;
+ defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ;
+ defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ;
+ defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ;
+ defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ;
+ defparam EFBInst_0.EFB_I2C2 = "DISABLED" ;
+ defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ;
+ defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ;
+ defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ;
+ defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ;
+ defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
+ defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
+ defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
+ defparam EFBInst_0.EFB_WB_CLK_FREQ = "50.0" ;
+ EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
+ .WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]),
+ .WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]),
+ .WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]),
+ .WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]),
+ .WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]),
+ .WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(pll0_bus_i[8]),
+ .PLL0DATI6(pll0_bus_i[7]), .PLL0DATI5(pll0_bus_i[6]), .PLL0DATI4(pll0_bus_i[5]),
+ .PLL0DATI3(pll0_bus_i[4]), .PLL0DATI2(pll0_bus_i[3]), .PLL0DATI1(pll0_bus_i[2]),
+ .PLL0DATI0(pll0_bus_i[1]), .PLL0ACKI(pll0_bus_i[0]), .PLL1DATI7(scuba_vlo),
+ .PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo),
+ .PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo),
+ .PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo),
+ .I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo),
+ .SPISCKI(spi_clk_i), .SPIMISOI(spi_miso_i), .SPIMOSII(spi_mosi_i),
+ .SPISCSN(spi_scsn), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo),
+ .UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]),
+ .WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]),
+ .WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]),
+ .WBACKO(wb_ack_o), .PLLCLKO(pll0_bus_o[16]), .PLLRSTO(pll0_bus_o[15]),
+ .PLL0STBO(pll0_bus_o[14]), .PLL1STBO(), .PLLWEO(pll0_bus_o[13]),
+ .PLLADRO4(pll0_bus_o[12]), .PLLADRO3(pll0_bus_o[11]), .PLLADRO2(pll0_bus_o[10]),
+ .PLLADRO1(pll0_bus_o[9]), .PLLADRO0(pll0_bus_o[8]), .PLLDATO7(pll0_bus_o[7]),
+ .PLLDATO6(pll0_bus_o[6]), .PLLDATO5(pll0_bus_o[5]), .PLLDATO4(pll0_bus_o[4]),
+ .PLLDATO3(pll0_bus_o[3]), .PLLDATO2(pll0_bus_o[2]), .PLLDATO1(pll0_bus_o[1]),
+ .PLLDATO0(pll0_bus_o[0]), .I2C1SCLO(), .I2C1SCLOEN(), .I2C1SDAO(),
+ .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(), .I2C2SDAOEN(),
+ .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(spi_clk_o), .SPISCKEN(spi_clk_oe),
+ .SPIMISOO(spi_miso_o), .SPIMISOEN(spi_miso_oe), .SPIMOSIO(spi_mosi_o),
+ .SPIMOSIEN(spi_mosi_oe), .SPIMCSN7(), .SPIMCSN6(), .SPIMCSN5(),
+ .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(spi_csn[2]), .SPIMCSN1(spi_csn[1]),
+ .SPIMCSN0(spi_csn[0]), .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(),
+ .WBCUFMIRQ(), .CFGWAKE(), .CFGSTDBY());
+
+
+
+ // exemplar begin
+ // exemplar end
+
+endmodule
diff --git a/minitests/machxo2/osch/osch.lpf b/minitests/machxo2/osch/osch.lpf
new file mode 100644
index 0000000..cfc4ddd
--- /dev/null
+++ b/minitests/machxo2/osch/osch.lpf
@@ -0,0 +1,3 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "clk" SITE "13" ;
diff --git a/minitests/machxo2/osch/osch.v b/minitests/machxo2/osch/osch.v
new file mode 100644
index 0000000..6374c14
--- /dev/null
+++ b/minitests/machxo2/osch/osch.v
@@ -0,0 +1,17 @@
+module osch (
+ input clk,
+ output stdby
+);
+
+ wire out;
+
+ OSCH #(
+ .NOM_FREQ("2.08")
+ ) osch_clk (
+ .STDBY(stdby),
+ .OSC(out)
+ );
+
+ assign clk = stdby;
+
+endmodule
diff --git a/minitests/machxo2/pio/bb_machxo2.v b/minitests/machxo2/pio/bb_machxo2.v
new file mode 100644
index 0000000..473981a
--- /dev/null
+++ b/minitests/machxo2/pio/bb_machxo2.v
@@ -0,0 +1,15 @@
+module top(input pad);
+
+wire dummyo, dummyi;
+
+(* LOC="PB11C" *)
+(* IO_TYPE="LVTTL33" *)
+BB i_b(.B(pad), .O(dummyo), .I(1'b1), .T(dummyi));
+
+// Dummy load
+GSR gsr_i(.GSR(dummyo));
+
+// Dummy source
+OSCH osc_i(.OSC(dummyi));
+
+endmodule
diff --git a/minitests/machxo2/vref/vref.lpf b/minitests/machxo2/vref/vref.lpf
new file mode 100644
index 0000000..8b62fef
--- /dev/null
+++ b/minitests/machxo2/vref/vref.lpf
@@ -0,0 +1,7 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "in" SITE "12" ;
+LOCATE COMP "out" SITE "13" ;
+IOBUF PORT "in" HYSTERESIS=NA IO_TYPE=LVCMOS25R33 VREF="MyVref" ;
+LOCATE VREF "MyVref" SITE "11" ;
+IOBUF PORT "out" IO_TYPE=LVCMOS33 ;
diff --git a/minitests/machxo2/vref/vref.v b/minitests/machxo2/vref/vref.v
new file mode 100644
index 0000000..325a5a8
--- /dev/null
+++ b/minitests/machxo2/vref/vref.v
@@ -0,0 +1,8 @@
+module vref (
+ input in,
+ output out
+);
+
+ assign out = in;
+
+endmodule
\ No newline at end of file
