)]}'
{
  "commit": "7b20e4b784e7cdd2779c5315b144391a0cef7243",
  "tree": "af8274ab86fe63a77799002d67b4fb6aaf1f8335",
  "parents": [
    "4ce7e26c48a96c45b519fd5461e6a689cc5f55b4"
  ],
  "author": {
    "name": "William D. Jones",
    "email": "thor0505@comcast.net",
    "time": "Mon Feb 01 23:55:53 2021 -0500"
  },
  "committer": {
    "name": "William D. Jones",
    "email": "thor0505@comcast.net",
    "time": "Mon Feb 01 23:55:53 2021 -0500"
  },
  "message": "machxo2: Make sure all left and right I/O connections are included in the routing graph.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "84eb625ddf1ea5983fad897fb6965288f6d26bf0",
      "old_mode": 33188,
      "old_path": "libtrellis/src/RoutingGraph.cpp",
      "new_id": "85e21169abc9c3fc6f8f56cbfb07e9fe7d9115da",
      "new_mode": 33188,
      "new_path": "libtrellis/src/RoutingGraph.cpp"
    }
  ]
}