commit 80e7cbfa808f09aec12ff1966996c1194220fff5
author William D. Jones <thor0505@comcast.net> Tue Jun 29 23:15:07 2021 -0400
committer William D. Jones <thor0505@comcast.net> Tue Jun 29 23:15:07 2021 -0400
tree e607648b9a9ad887cacfce0c796ece74fcfc8abf
parent c48df86e7c48ba4585ff207a2ee8177aa9d01b75

Add enum bit fuzzing for missing left-right tiles on 1200HC.

fuzzers/machxo2/051-pio_attrs/fuzzer.py

diff --git a/fuzzers/machxo2/051-pio_attrs/fuzzer.py b/fuzzers/machxo2/051-pio_attrs/fuzzer.py
index 9185f61..0d976d5 100644
--- a/fuzzers/machxo2/051-pio_attrs/fuzzer.py
+++ b/fuzzers/machxo2/051-pio_attrs/fuzzer.py
@@ -60,6 +60,30 @@
             "side": "T",
             "pins": [("28", "C"), ("27", "D")]
         },
+
+        {
+            "cfg": FuzzConfig(job="PICRS0_IO", family="MachXO2", device="LCMXO2-1200HC",
+                        ncl="empty.ncl", tiles=["PR3:PIC_RS0"]),
+            "side": "R",
+            "pins": [("71", "A"), ("70", "B")],
+            "package": "TQFP100"
+        },
+
+        {
+            "cfg": FuzzConfig(job="PICLS0_IO", family="MachXO2", device="LCMXO2-1200HC",
+                        ncl="empty.ncl", tiles=["PL9:PIC_LS0"]),
+            "side": "L",
+            "pins": [("20", "A"), ("21", "B")],
+            "package": "TQFP100"
+        },
+
+        {
+            "cfg": FuzzConfig(job="PICL0VREF_IO", family="MachXO2", device="LCMXO2-1200HC",
+                        ncl="empty.ncl", tiles=["PL4:PIC_L0_VREF3"]),
+            "side": "L",
+            "pins": [("11", "A"), ("12", "B"), ("13", "C"), ("14", "D")],
+            "package": "TQFP144"
+        },
 ]
 
 # Function constructed from reading the MachXO2 sysIO Usage Guide.

fuzzers/machxo2/052-pio_fixup/fuzzer.py

diff --git a/fuzzers/machxo2/052-pio_fixup/fuzzer.py b/fuzzers/machxo2/052-pio_fixup/fuzzer.py
index 0bdf954..ee07d94 100644
--- a/fuzzers/machxo2/052-pio_fixup/fuzzer.py
+++ b/fuzzers/machxo2/052-pio_fixup/fuzzer.py
@@ -4,7 +4,10 @@
 def main():
     pytrellis.load_database("../../../database")
     dbfixup.remove_enum_bits("MachXO2", "LCMXO2-1200HC", "PIC_L0", (29, 11))
+    dbfixup.remove_enum_bits("MachXO2", "LCMXO2-1200HC", "PIC_LS0", (29, 11))
+    dbfixup.remove_enum_bits("MachXO2", "LCMXO2-1200HC", "PIC_L0_VREF3", (29, 11))
     dbfixup.remove_enum_bits("MachXO2", "LCMXO2-1200HC", "PIC_R0", (29, 59), (0, 48))
+    dbfixup.remove_enum_bits("MachXO2", "LCMXO2-1200HC", "PIC_RS0", (29, 59), (0, 48))
 
 if __name__ == "__main__":
     main()

util/fuzz/dbfixup.py

diff --git a/util/fuzz/dbfixup.py b/util/fuzz/dbfixup.py
index 734522f..885849d 100644
--- a/util/fuzz/dbfixup.py
+++ b/util/fuzz/dbfixup.py
@@ -56,15 +56,14 @@
     for enum in db.get_settings_enums():
         fixed_enum = pytrellis.EnumSettingBits()
 
-        for option in db.get_data_for_enum(enum).options:
-            key = option.key()
+        for (option, data) in db.get_data_for_enum(enum).options.items():
             fixed_bg = pytrellis.BitGroup()
 
-            for bit in option.data().bits:
+            for bit in data.bits:
                 if in_bounding_box(bit):
                     fixed_bg.bits.add(bit)
 
-            fixed_enum.options[key] = fixed_bg
+            fixed_enum.options[option] = fixed_bg
 
         fixed_enum.name = db.get_data_for_enum(enum).name
         fixed_enum.defval = db.get_data_for_enum(enum).defval