diff --git a/minitests/reg/async_sr.v b/minitests/reg/async_sr.v
new file mode 100644
index 0000000..b56235f
--- /dev/null
+++ b/minitests/reg/async_sr.v
@@ -0,0 +1,9 @@
+module top(input clk, d, set, reset, cen, output reg q);
+    always @(posedge clk or posedge set or posedge reset)
+           if (set)
+              q <= 1'b1;
+           else if(reset)
+              q <= 1'b0;
+           else if(cen)
+                q <= d;
+endmodule
diff --git a/minitests/reg/lsr_over_ce.v b/minitests/reg/lsr_over_ce.v
new file mode 100644
index 0000000..5161010
--- /dev/null
+++ b/minitests/reg/lsr_over_ce.v
@@ -0,0 +1,8 @@
+module top(input clk, d, set, cen, output reg q);
+    always @(posedge clk)
+         if (set)
+            q <= 1'b1;
+         else
+             if (cen)
+                  q <= d;
+endmodule