Avoid copying nonexistent DCC mux bits in row 11.
diff --git a/fuzzers/machxo2/035-copy-cib_ebr0/fuzzer.py b/fuzzers/machxo2/035-copy-cib_ebr0/fuzzer.py
index a5a6841..fb71f52 100644
--- a/fuzzers/machxo2/035-copy-cib_ebr0/fuzzer.py
+++ b/fuzzers/machxo2/035-copy-cib_ebr0/fuzzer.py
@@ -20,6 +20,11 @@
return not (src.startswith("G_CLKO") or sink.startswith("G_CLKI"))
+def exclude_lrud_muxes(conn):
+ (src, sink) = conn
+
+ return not (src.startswith("G_CLKI") and sink.startswith("G_CLKO"))
+
def main():
pytrellis.load_database("../../../database")
@@ -27,7 +32,7 @@
dbcopy.dbcopy("MachXO2", "LCMXO2-1200HC", "CIB_EBR0", dest)
for dest in shared_tiles_no_lrudconns:
- dbcopy.dbcopy("MachXO2", "LCMXO2-1200HC", "CIB_EBR0", dest, copy_conns=False)
+ dbcopy.copy_muxes_with_predicate("MachXO2", "LCMXO2-1200HC", "CIB_EBR0", dest, exclude_lrud_muxes)
dbcopy.copy_conns_with_predicate("MachXO2", "LCMXO2-1200HC", "CIB_EBR0", dest, exclude_lrud_conns)
if __name__ == "__main__":
