fuzzers: Add DCU routing fuzzer
Signed-off-by: David Shah <davey1576@gmail.com>
diff --git a/fuzzers/110-dcu_routing/dcuroute.ncl b/fuzzers/110-dcu_routing/dcuroute.ncl
new file mode 100644
index 0000000..1825919
--- /dev/null
+++ b/fuzzers/110-dcu_routing/dcuroute.ncl
@@ -0,0 +1,30 @@
+::FROM-WRITER;
+design top
+{
+ device
+ {
+ architecture sa5p00g;
+ device LFE5UM5G-45F;
+ package CABGA381;
+ performance "8";
+ }
+
+ comp DCU
+ {
+ logical {
+ cellmodel-name DCU;
+ program "MODE:DCUA ";
+ }
+ site DCU0;
+ }
+
+ signal q_c
+ {
+ signal-pins
+ // drivers
+ (DCU, CH0_FF_RX_D_0),
+ // loads
+ (DCU, CH0_FF_TX_D_0);
+ ${route}
+ }
+}
diff --git a/fuzzers/110-dcu_routing/fuzzer.py b/fuzzers/110-dcu_routing/fuzzer.py
new file mode 100644
index 0000000..290a7c9
--- /dev/null
+++ b/fuzzers/110-dcu_routing/fuzzer.py
@@ -0,0 +1,32 @@
+from fuzzconfig import FuzzConfig
+import interconnect
+import nets
+import pytrellis
+import re
+
+jobs = [
+ ((71, 42), FuzzConfig(job="DCUROUTE0", family="ECP5", device="LFE5UM5G-45F", ncl="dcuroute.ncl",
+ tiles=["MIB_R71C42:DCU0", "MIB_R71C43:DCU1", "MIB_R71C44:DCU2", "MIB_R71C45:DCU3",
+ "MIB_R71C46:DCU4", "MIB_R71C47:DCU5", "MIB_R71C48:DCU6", "MIB_R71C49:DCU7",
+ "MIB_R71C50:DCU8"]))
+
+]
+
+
+def main():
+ pytrellis.load_database("../../database")
+ for job in jobs:
+ loc, cfg = job
+ cfg.setup()
+
+ def nn_filter(net, netnames):
+ return "DCU" in net or "PCS" in net
+
+ interconnect.fuzz_interconnect(config=cfg, location=loc,
+ netname_predicate=nn_filter,
+ netname_filter_union=False,
+ func_cib=True)
+
+
+if __name__ == "__main__":
+ main()
diff --git a/util/common/nets.py b/util/common/nets.py
index 401959d..a0213a8 100644
--- a/util/common/nets.py
+++ b/util/common/nets.py
@@ -23,6 +23,10 @@
# SED clock output
sed_clk_re = re.compile(r'R\d+C\d+_J?SEDCLKOUT')
+# SERDES reference clocks
+pcs_clk_re = re.compile(r'R\d+C\d+_J?PCS[AB][TR]XCLK\d')
+
+
# DDRDEL delay signals
ddr_delay_re = re.compile(r'R\d+C\d+_[UL][LR]DDRDEL')
@@ -61,6 +65,7 @@
dcc_clki_re.match(wire) or
dcs_sig_re.match(wire) or
dcs_clk_re.match(wire) or
+ pcs_clk_re.match(wire) or
center_clk_re.match(wire))
