commit dff1cbcb1bd30de7e96f8a059f2e19be1bb2e44d
author gatecat <gatecat@ds0.me> Tue Jul 06 14:06:38 2021 +0100
committer GitHub <noreply@github.com> Tue Jul 06 14:06:38 2021 +0100
tree 0accf864415340597d47697a334dfcf985206b71
parent a70c3339a317f8578167069c9fb396ffd4dec5d6
parent 5c62441c7816358b2edd149027e4e783e88a9699

Merge pull request #173 from YosysHQ/gatecat/ecp5-add-dcs

libtrellis: Add DCS bels

libtrellis/include/Bels.hpp

diff --git a/libtrellis/include/Bels.hpp b/libtrellis/include/Bels.hpp
index ad3faa8..79ce97f 100644
--- a/libtrellis/include/Bels.hpp
+++ b/libtrellis/include/Bels.hpp
@@ -10,6 +10,7 @@
 void add_lc(RoutingGraph &graph, int x, int y, int z);
 void add_pio(RoutingGraph &graph, int x, int y, int z);
 void add_dcc(RoutingGraph &graph, int x, int y, string side, string z);
+void add_dcs(RoutingGraph &graph, int x, int y, int z);
 void add_bram(RoutingGraph &graph, int x, int y, int z);
 void add_mult18(RoutingGraph &graph, int x, int y, int z);
 void add_alu54b(RoutingGraph &graph, int x, int y, int z);

libtrellis/src/Bels.cpp

diff --git a/libtrellis/src/Bels.cpp b/libtrellis/src/Bels.cpp
index 5111c8a..815828c 100644
--- a/libtrellis/src/Bels.cpp
+++ b/libtrellis/src/Bels.cpp
@@ -128,6 +128,24 @@
 
 }
 
+void add_dcs(RoutingGraph &graph, int x, int y, int z) {
+    string name = string("DCS") + std::to_string(z);
+    RoutingBel bel;
+    bel.name = graph.ident(name);
+    bel.type = graph.ident("DCSC");
+    bel.loc.x = x;
+    bel.loc.y = y;
+    bel.z = z + 4;
+    graph.add_bel_input(bel, graph.ident("CLK0"), 0, 0, graph.ident(fmt("G_CLK0_" << "DCS" << z)));
+    graph.add_bel_input(bel, graph.ident("CLK1"), 0, 0, graph.ident(fmt("G_CLK1_" << "DCS" << z)));
+    graph.add_bel_output(bel, graph.ident("DCSOUT"), 0, 0, graph.ident(fmt("G_DCSOUT_" << "DCS" << z)));
+    graph.add_bel_input(bel, graph.ident("MODESEL"), 0, 0, graph.ident(fmt("G_JMODESEL_" << "DCS" << z)));
+    graph.add_bel_input(bel, graph.ident("SEL0"), 0, 0, graph.ident(fmt("G_JSEL0_" << "DCS" << z)));
+    graph.add_bel_input(bel, graph.ident("SEL1"), 0, 0, graph.ident(fmt("G_JSEL1_" << "DCS" << z)));
+    graph.add_bel(bel);
+
+}
+
 void add_bram(RoutingGraph &graph, int x, int y, int z) {
     string name = string("EBR") + std::to_string(z);
     RoutingBel bel;

libtrellis/src/Chip.cpp

diff --git a/libtrellis/src/Chip.cpp b/libtrellis/src/Chip.cpp
index ce51a52..e804969 100644
--- a/libtrellis/src/Chip.cpp
+++ b/libtrellis/src/Chip.cpp
@@ -167,6 +167,10 @@
         if (tile->info.type == "BMID_0V" || tile->info.type == "BMID_0H")
             for (int z = 0; z < 16; z++)
                 Ecp5Bels::add_dcc(*rg, x, y, "B", std::to_string(z));
+        if (tile->info.type == "EBR_CMUX_UL" || tile->info.type == "DSP_CMUX_UL")
+            Ecp5Bels::add_dcs(*rg, x, y, 0);
+        if (tile->info.type == "EBR_CMUX_LL" || tile->info.type == "EBR_CMUX_LL_25K")
+            Ecp5Bels::add_dcs(*rg, x, y, 1);
         // RAM Bels
         if (tile->info.type == "MIB_EBR0" || tile->info.type == "EBR_CMUX_UR" || tile->info.type == "EBR_CMUX_LR"
             || tile->info.type == "EBR_CMUX_LR_25K")