commit 786e4cb9ac79b5b1c59133d1e2acfff1f990e89e
author David Shah <dave@ds0.me> Wed Apr 29 10:42:25 2020 +0100
committer David Shah <dave@ds0.me> Wed Apr 29 10:42:25 2020 +0100
tree 9fc301d625d4074c381dfad0a7a8f1ba71722ddb
parent d4760738c653338114d62204ace87a57c8f774e0

fuzzers: Add more programmable DSP inversions

Signed-off-by: David Shah <dave@ds0.me>

fuzzers/ECP5/071-dsp_constmux/fuzzer.py

diff --git a/fuzzers/ECP5/071-dsp_constmux/fuzzer.py b/fuzzers/ECP5/071-dsp_constmux/fuzzer.py
index 25a1c36..54cf9e6 100644
--- a/fuzzers/ECP5/071-dsp_constmux/fuzzer.py
+++ b/fuzzers/ECP5/071-dsp_constmux/fuzzer.py
@@ -24,6 +24,10 @@
                                             tiles=dsp_tiles)),
     ("MULT18_R13C9", "MULT18_5", FuzzConfig(job="MULT18_5", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
                                             tiles=dsp_tiles)),
+    ("ALU54_R13C7", "ALU54_3", FuzzConfig(job="ALU54_3", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
+                                            tiles=dsp_tiles)),
+    ("ALU54_R13C11", "ALU54_7", FuzzConfig(job="ALU54_7", family="ECP5", device="LFE5U-25F", ncl="empty.ncl",
+                                            tiles=dsp_tiles)),
 ]
 
 
@@ -51,7 +55,15 @@
                 nonrouting.fuzz_enum_setting(cfg, "{}.{}MUX".format(mult, sig), [sig, "INV"],
                                              lambda x: get_substs(sig, x), empty_bitfile,
                                              False)
-
+        extra_ports = []
+        if cellmodel == "ALU54":
+            extra_ports = ["OP{}".format(i) for i in range(11)]
+        if cellmodel == "MULT18":
+            extra_ports = ["SIGNEDA", "SIGNEDB", "SOURCEA", "SOURCEB"]
+        for port in extra_ports:
+            nonrouting.fuzz_enum_setting(cfg, "{}.{}MUX".format(mult, port), [port, "INV"],
+                                         lambda x: get_substs(port, x), empty_bitfile,
+                                         False)
     fuzzloops.parallel_foreach(jobs, per_job)