diff --git a/minitests/roi_harness/Makefile_mini b/minitests/roi_harness/Makefile_mini
index 583f68e..72fc1b8 100644
--- a/minitests/roi_harness/Makefile_mini
+++ b/minitests/roi_harness/Makefile_mini
@@ -14,7 +14,7 @@
 
 .PHONY: all clean
 
-top.bit: $(VIVADO) $(SOURCES) runme.py
+top.bit: $(SOURCES) runme.py
 	source zynqusp-swbut.sh; \
 	python runme.py
 	cp build/*.bit ./
@@ -26,8 +26,5 @@
         top.bit >top.fasm \
         || (rm -f top.fasm && exit 1)
 
-top.bits: top.bit
-	$(URAY_BITREAD) -part_file $(URAY_DIR)/database/zynqusp/$(PART)/part.yaml -o top.bits -z -y top.bit
-
-segprint.log: top.bits
-	$(URAY_SEGPRINT) -z -D -b top.bits > segprint.log
+top_patched.bit: top.fasm
+	fasm2bit.sh top.fasm top.bit $@
diff --git a/minitests/roi_harness/fasm2bit.sh b/minitests/roi_harness/fasm2bit.sh
index 3b5e5ff..373745c 100755
--- a/minitests/roi_harness/fasm2bit.sh
+++ b/minitests/roi_harness/fasm2bit.sh
@@ -27,13 +27,14 @@
 echo "Harness .bit: $bit_in"
 echo "Out .bit: $bit_out"
 
-${URAY_FASM2FRAMES} --sparse $fasm_in roi_partial.frm
+${URAY_FASM2FRAMES} $fasm_in roi_partial.frm
 
-${URAY_TOOLS_DIR}/xc7patch \
+${URAY_TOOLS_DIR}/xcpatch \
 	--part_name ${URAY_PART} \
 	--part_file ${URAY_PART_YAML} \
 	--bitstream_file $bit_in \
 	--frm_file roi_partial.frm \
+	--architecture UltraScalePlus \
 	--output_file $bit_out
 
 #openocd -f $URAY_DIR/utils/openocd/board-digilent-basys3.cfg -c "init; pld load 0 $bit_out; exit"
diff --git a/minitests/roi_harness/runme.py b/minitests/roi_harness/runme.py
index ca57f57..d93d5dc 100644
--- a/minitests/roi_harness/runme.py
+++ b/minitests/roi_harness/runme.py
@@ -24,9 +24,10 @@
         f.write('set_property IOSTANDARD LVCMOS33 [get_ports {}]\n'.format(key))
 
 with open(pre_imp_file, 'w') as f:
-    f.write('create_pblock roi\n')
-    f.write('add_cells_to_pblock [get_pblocks roi] [get_cells roi]\n')
-    f.write('resize_pblock [get_pblocks roi] -add "{}"\n'.format(os.environ['URAY_ROI']))
+    f.write('link_design -top top -part $::env(URAY_PART)\n')
+    #f.write('create_pblock roi\n')
+    #f.write('add_cells_to_pblock [get_pblocks roi] [get_cells roi]\n')
+    #f.write('resize_pblock [get_pblocks roi] -add "{}"\n'.format(os.environ['URAY_ROI']))
     f.write('set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]\n')
 
 with open(post_imp_file, 'w') as f:
diff --git a/utils/bitstream.py b/utils/bitstream.py
index 2dbb8c4..1a125ba 100644
--- a/utils/bitstream.py
+++ b/utils/bitstream.py
@@ -5,6 +5,7 @@
 # Break frames into WORD_SIZE bit words.
 WORD_SIZE_BITS = 16
 FRAME_ALIGNMENT = 0x100
+FRAME_WORD_COUNT = 93
 '''
 Sample:
 bit_0002000f_079_06
diff --git a/utils/environment.sh b/utils/environment.sh
index a04fa0a..a4c1d23 100644
--- a/utils/environment.sh
+++ b/utils/environment.sh
@@ -22,7 +22,7 @@
 
 # tools
 export URAY_GENHEADER="${URAY_UTILS_DIR}/genheader.sh"
-export URAY_BITREAD="${URAY_TOOLS_DIR}/bitread --part_file ${URAY_PART_YAML}"
+export URAY_BITREAD="${URAY_TOOLS_DIR}/bitread --part_file ${URAY_PART_YAML} --architecture ${URAY_ARCH}"
 export URAY_MERGEDB="bash ${URAY_UTILS_DIR}/mergedb.sh"
 export URAY_DBFIXUP="python3 ${URAY_UTILS_DIR}/dbfixup.py"
 export URAY_MASKMERGE="bash ${URAY_UTILS_DIR}/maskmerge.sh"
diff --git a/utils/fasm2frames.py b/utils/fasm2frames.py
index 25cd6bc..f3c9b61 100755
--- a/utils/fasm2frames.py
+++ b/utils/fasm2frames.py
@@ -131,11 +131,6 @@
         with open(os.path.join(db_root, part, "part.json"), "r") as fp:
             part_data = json.load(fp)
 
-        for bank, loc in part_data["iobanks"].items():
-            tile = "HCLK_IOI3_" + loc
-            bank_to_tile[bank].add(tile)
-            tile_to_bank[tile] = bank
-
         for pin in package_pins:
             bank_to_tile[pin["bank"]].add(pin["tile"])
             tile_to_bank[pin["tile"]] = pin["bank"]
diff --git a/utils/fasm_assembler.py b/utils/fasm_assembler.py
index 1775a4e..30dfb93 100644
--- a/utils/fasm_assembler.py
+++ b/utils/fasm_assembler.py
@@ -107,8 +107,8 @@
             '''Set or clear a single bit in a segment at the given word column and word bit position'''
 
             frame_addr = bit.word_column
-            word_addr = bit.word_bit // bitstream.WORD_SIZE_BITS
-            bit_index = bit.word_bit % bitstream.WORD_SIZE_BITS
+            word_addr = bit.word_bit // 32
+            bit_index = bit.word_bit % 32
             if bit.isset:
                 self.frame_set(frame_addr, word_addr, bit_index, line)
             else: