| commit | 796d74f6d9eac6320fba95420f0985297f92074f | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Tue Jan 07 11:01:30 2020 -0700 |
| committer | Tim 'mithro' Ansell <me@mith.ro> | Tue Jan 07 11:01:30 2020 -0700 |
| tree | 6b7a0abc595b780ed367ac7f42bf82a10c86085b | |
| parent | a2f7a77ccef16c1042c9517370a9eaffedfc5c1a [diff] |
Improving the README a little.
Project U-Ray is an attempt at documenting the bitstream format for the Xilinx Ultrascale and Ultrascale+ parts including all parts from the following lines;
It takes a lot of the learning from Project X-Ray and Project Trellis.
| Board | Maker | Price | Part |
|---|---|---|---|
| Ultra96-V2 Zynq UltraScale+ ZU3EG Development Board (ULTRA96-V2-G) | ??? | Xilinx Zynq UltraScale+ MPSoC ZU3EG | $USD249 |
| Genesys ZU: Zynq Ultrascale+ MPSoC Development Board | Digilent | Xilinx Zynq UltraScale+ MPSoC ZU3EG | $USD1,149 |
We have a goal of initially targeting parts supported by WebPack so that anyone can contribute.
WebPack supports the following parts;
Zynq UltraScale+ MPSoC -- UltraScale+ MPSoC