| commit | 8e8987995518eec151459e784b782f26019b696c | [log] [tgz] |
|---|---|---|
| author | Tomasz Michalak <tmichalak@antmicro.com> | Thu Jan 30 16:15:14 2020 +0100 |
| committer | Tomasz Michalak <tmichalak@antmicro.com> | Fri Jan 31 13:00:04 2020 +0100 |
| tree | fd6fb7dacbd0f79fe4fe665a498c74d55e97d261 | |
| parent | ba863b2d26b25f935dd58e7eb58272466f3be523 [diff] |
minitests: Add IODELAY minitests Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Project U-Ray is an attempt at documenting the bitstream format for the Xilinx Ultrascale and Ultrascale+ parts including all parts from the following lines;
It takes a lot of the learning from Project X-Ray and Project Trellis.
| Board | Maker | Price | Part |
|---|---|---|---|
| Ultra96-V2 Zynq UltraScale+ ZU3EG Development Board (ULTRA96-V2-G) | ??? | Xilinx Zynq UltraScale+ MPSoC ZU3EG | $USD249 |
| Genesys ZU: Zynq Ultrascale+ MPSoC Development Board | Digilent | Xilinx Zynq UltraScale+ MPSoC ZU3EG | $USD1,149 |
We have a goal of initially targeting parts supported by WebPack so that anyone can contribute.
WebPack supports the following parts;
Zynq UltraScale+ MPSoC -- UltraScale+ MPSoC