diff --git a/minitests/pll/top.v b/minitests/pll/top.v
index 69365e9..3bd237a 100644
--- a/minitests/pll/top.v
+++ b/minitests/pll/top.v
@@ -33,13 +33,13 @@
 	)
 	inst_0 (
 		.clk(clk),
-		.din(din[  0 +: 7]),
-		.dout(dout[ 0 +: 2])
+		.din(din[  0 +: 2]),
+		.dout(dout[ 0 +: 7])
 	);
 endmodule
 
 // ---------------------------------------------------------------------
-module my_PLL (input clk, input [6:0] din, output [1:0] dout);
+module my_PLL (input clk, input [1:0] din, output [6:0] dout);
 
    parameter LOC = "";
 
@@ -69,7 +69,7 @@
       .CLKOUT0B(dout[2]),       // 1-bit output: Inverted CLKOUT0
       .CLKOUT1(dout[3]),         // 1-bit output: General Clock output
       .CLKOUT1B(dout[4]),       // 1-bit output: Inverted CLKOUT1
-      .CLKOUTPHY(dout[5]),     // 1-bit output: Bitslice clock
+      .CLKOUTPHY(),     // 1-bit output: Bitslice clock
       .LOCKED(dout[6]),           // 1-bit output: LOCK
       .CLKFBIN(),         // 1-bit input: Feedback clock
       .CLKIN(clk),             // 1-bit input: Input clock