import edalize
import os
import glob

work_root = 'build'

post_imp_file = os.path.realpath(os.path.join(work_root, 'post.tcl'))

os.makedirs(work_root, exist_ok=True)

synth_tool = 'yosys'
yosys_synth_options = '-iopad -family xcup'

srcs = glob.glob("*.v")

with open(post_imp_file, 'w') as f:
    f.write('write_checkpoint -force design.dcp')

files = [
    {'name': os.path.realpath('../src.vivado/lowrisc_systems_top_earlgrey_zcu104_0.1/data/pins_zcu104.xdc'), 'file_type': 'xdc'}
]

parameters = {
}

for src in srcs:
    files.append({'name': os.path.realpath(src), 'file_type': 'verilogSource'})

tool = 'vivado'

incdirs = {}

edam = {
  'files' : files,
  'name'  : 'design',
  'toplevel': 'top_earlgrey_zcu104',
  'parameters': parameters,
  'tool_options' : {'vivado' : {
    'part' : os.environ['XRAY_PART'],
    'post_imp' : post_imp_file,
    'synth' : synth_tool,
    'yosys_synth_options' : yosys_synth_options
    }}
}

backend = edalize.get_edatool(tool)(edam=edam, work_root=work_root)

backend.configure("")
backend.build()