)]}'
{
  "commit": "d960817d8072e9e134fa13e03180d3911e1099c5",
  "tree": "3e56a34d4aa47f433be0025db6f4300486c90fc6",
  "parents": [
    "450aca4e581179128e439f08f58d95c0c84b416e"
  ],
  "author": {
    "name": "Tomasz Michalak",
    "email": "tmichalak@antmicro.com",
    "time": "Mon Mar 09 10:01:25 2020 +0100"
  },
  "committer": {
    "name": "Tomasz Michalak",
    "email": "tmichalak@antmicro.com",
    "time": "Mon Mar 09 10:35:36 2020 +0100"
  },
  "message": "minitests: Copy modules to work around Yosys bugs\n\nYosys is unable to infer OBUFTs when they are instantiated in submodule,\nneither does it handle inference of RAMB36 TDP if 2 port memories\nare instantiated in the same verilog module.\nBoth issues have been reported:\nhttps://github.com/YosysHQ/yosys/issues/1737\nhttps://github.com/YosysHQ/yosys/issues/1748\n\nSigned-off-by: Tomasz Michalak \u003ctmichalak@antmicro.com\u003e\n",
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