tree 3e56a34d4aa47f433be0025db6f4300486c90fc6
parent 450aca4e581179128e439f08f58d95c0c84b416e
author Tomasz Michalak <tmichalak@antmicro.com> 1583744485 +0100
committer Tomasz Michalak <tmichalak@antmicro.com> 1583746536 +0100

minitests: Copy modules to work around Yosys bugs

Yosys is unable to infer OBUFTs when they are instantiated in submodule,
neither does it handle inference of RAMB36 TDP if 2 port memories
are instantiated in the same verilog module.
Both issues have been reported:
https://github.com/YosysHQ/yosys/issues/1737
https://github.com/YosysHQ/yosys/issues/1748

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>