| commit | ac4fcf8d3954e6dc8c9551ab7791a3ce2994117c | [log] [tgz] |
|---|---|---|
| author | Piotr Binkowski <pbinkowski@antmicro.com> | Mon Feb 24 16:58:08 2020 +0100 |
| committer | Piotr Binkowski <pbinkowski@antmicro.com> | Wed Feb 26 09:33:14 2020 +0100 |
| tree | e77de469ae7c7e7ea359ae3de3291cbd68b98f0c | |
| parent | e306f62fa599fda1abb192ad5a34384169c1e110 [diff] |
minitests: use edalize to run minitests Signed-off-by: Piotr Binkowski <pbinkowski@antmicro.com>
Project U-Ray is an attempt at documenting the bitstream format for the Xilinx Ultrascale and Ultrascale+ parts including all parts from the following lines;
It takes a lot of the learning from Project X-Ray and Project Trellis.
| Board | Maker | Price | Part |
|---|---|---|---|
| Ultra96-V2 Zynq UltraScale+ ZU3EG Development Board (ULTRA96-V2-G) | ??? | Xilinx Zynq UltraScale+ MPSoC ZU3EG | $USD249 |
| Genesys ZU: Zynq Ultrascale+ MPSoC Development Board | Digilent | Xilinx Zynq UltraScale+ MPSoC ZU3EG | $USD1,149 |
We have a goal of initially targeting parts supported by WebPack so that anyone can contribute.
WebPack supports the following parts;
Zynq UltraScale+ MPSoC -- UltraScale+ MPSoC