diff --git a/minitests/util/runme.py b/minitests/util/runme.py
new file mode 100644
index 0000000..1b56b8f
--- /dev/null
+++ b/minitests/util/runme.py
@@ -0,0 +1,58 @@
+import edalize
+import os
+
+work_root = 'build'
+
+pins = {
+    'clk': os.environ['XRAY_PIN_00'],
+    'stb': os.environ['XRAY_PIN_01'],
+    'di':  os.environ['XRAY_PIN_02'],
+    'do':  os.environ['XRAY_PIN_03'],
+}
+
+xdc_file = os.path.realpath(os.path.join(work_root, 'top.xdc'))
+pre_imp_file = os.path.realpath(os.path.join(work_root, 'pre.tcl'))
+post_imp_file = os.path.realpath(os.path.join(work_root, 'post.tcl'))
+
+os.makedirs(work_root, exist_ok=True)
+
+synth_tool = 'yosys' if 'USE_YOSYS' in os.environ else 'vivado'
+
+with open(xdc_file, 'w') as f:
+    f.write('set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets *]\n')
+    for key, val in pins.items():
+        f.write('set_property PACKAGE_PIN {} [get_ports {}]\n'.format(val, key))
+        f.write('set_property IOSTANDARD LVCMOS33 [get_ports {}]\n'.format(key))
+
+with open(pre_imp_file, 'w') as f:
+    f.write('create_pblock roi\n')
+    f.write('add_cells_to_pblock [get_pblocks roi] [get_cells roi]\n')
+    f.write('resize_pblock [get_pblocks roi] -add "{}"\n'.format(os.environ['XRAY_ROI']))
+    f.write('set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]\n')
+
+with open(post_imp_file, 'w') as f:
+    f.write('write_checkpoint -force design.dcp')
+
+files = [
+    {'name': os.path.realpath('top.v'), 'file_type': 'verilogSource'},
+    {'name': xdc_file, 'file_type': 'xdc'},
+]
+
+tool = 'vivado'
+
+edam = {
+  'files' : files,
+  'name'  : 'design',
+  'toplevel': 'top',
+  'tool_options' : {'vivado' : {
+    'part' : os.environ['XRAY_PART'],
+    'pre_imp' : pre_imp_file,
+    'post_imp' : post_imp_file,
+    'synth' : synth_tool
+    }}
+}
+
+backend = edalize.get_edatool(tool)(edam=edam, work_root=work_root)
+
+backend.configure("")
+backend.build()
diff --git a/minitests/util/runme.sh b/minitests/util/runme.sh
index 118e51a..45938b5 100755
--- a/minitests/util/runme.sh
+++ b/minitests/util/runme.sh
@@ -1,9 +1,9 @@
 #!/bin/bash
 
 set -ex
-${XRAY_VIVADO} -mode batch -source $XRAY_DIR/minitests/util/runme.tcl
-${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
-test -z "$(fgrep CRITICAL vivado.log)"
+python3 $XRAY_DIR/minitests/util/runme.py
+${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y build/design.bit
+test -z "$(fgrep CRITICAL build/vivado.log)"
 # TODO uncomment once tilegrid generation works
 #${XRAY_SEGPRINT} -z -D design.bits  >design.txt
 
diff --git a/minitests/util/runme.tcl b/minitests/util/runme.tcl
deleted file mode 100644
index 02d605c..0000000
--- a/minitests/util/runme.tcl
+++ /dev/null
@@ -1,24 +0,0 @@
-create_project -force -part $::env(XRAY_PART) design design
-read_verilog top.v
-synth_design -top top -flatten_hierarchy none
-
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
-set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
-
-create_pblock roi
-add_cells_to_pblock [get_pblocks roi] [get_cells roi]
-resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
-
-#set_property CFGBVS VCCO [current_design]
-#set_property CONFIG_VOLTAGE 3.3 [current_design]
-set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
-
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
-
-place_design
-route_design
-
-write_checkpoint -force design.dcp
-write_bitstream -force design.bit