| commit | f3f502b386480e8e308ac95d6240bb9a68e01885 | [log] [tgz] |
|---|---|---|
| author | Tomasz Michalak <tmichalak@antmicro.com> | Thu Mar 26 07:09:02 2020 +0100 |
| committer | Tomasz Michalak <tmichalak@antmicro.com> | Thu Mar 26 07:09:02 2020 +0100 |
| tree | fbb2c2b5e2f2dd6036176cf5111c450c46f44a71 | |
| parent | c0aeeda3dd8543d10255158d856a44b4ec260caf [diff] |
roi_harness: Add .frm files to make clean target Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Project U-Ray is an attempt at documenting the bitstream format for the Xilinx Ultrascale and Ultrascale+ parts including all parts from the following lines;
It takes a lot of the learning from Project X-Ray and Project Trellis.
| Board | Maker | Price | Part |
|---|---|---|---|
| Ultra96-V2 Zynq UltraScale+ ZU3EG Development Board (ULTRA96-V2-G) | ??? | Xilinx Zynq UltraScale+ MPSoC ZU3EG | $USD249 |
| Genesys ZU: Zynq Ultrascale+ MPSoC Development Board | Digilent | Xilinx Zynq UltraScale+ MPSoC ZU3EG | $USD1,149 |
We have a goal of initially targeting parts supported by WebPack so that anyone can contribute.
WebPack supports the following parts;
Zynq UltraScale+ MPSoC -- UltraScale+ MPSoC