| commit | ed7f538f827b0759d1fecac8ad1551be7a7281e8 | [log] [tgz] |
|---|---|---|
| author | Tomasz Michalak <tmichalak@antmicro.com> | Tue Feb 11 09:38:32 2020 +0100 |
| committer | Tomasz Michalak <tmichalak@antmicro.com> | Tue Feb 11 13:47:38 2020 +0100 |
| tree | c1e82d350fb710745f521a098dbbb165c4b45c80 | |
| parent | 30536ea4f7afbfff8b5d64444cacde363e2e70c1 [diff] |
002-tilegrid: clb: Add base address calculation for clb tiles Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Project U-Ray is an attempt at documenting the bitstream format for the Xilinx Ultrascale and Ultrascale+ parts including all parts from the following lines;
It takes a lot of the learning from Project X-Ray and Project Trellis.
| Board | Maker | Price | Part |
|---|---|---|---|
| Ultra96-V2 Zynq UltraScale+ ZU3EG Development Board (ULTRA96-V2-G) | ??? | Xilinx Zynq UltraScale+ MPSoC ZU3EG | $USD249 |
| Genesys ZU: Zynq Ultrascale+ MPSoC Development Board | Digilent | Xilinx Zynq UltraScale+ MPSoC ZU3EG | $USD1,149 |
We have a goal of initially targeting parts supported by WebPack so that anyone can contribute.
WebPack supports the following parts;
Zynq UltraScale+ MPSoC -- UltraScale+ MPSoC