Updating all based on "Merge pull request #1468 from litghost/fixup_requirements"
See [Info File](Info.md) for details.
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
diff --git a/Info.md b/Info.md
index 315f6c0..7e522ab 100644
--- a/Info.md
+++ b/Info.md
@@ -37,20 +37,20 @@
# Details
-Last updated on Wed 21 Oct 2020 07:04:17 PM UTC (2020-10-21T19:04:17+00:00).
+Last updated on Mon 26 Oct 2020 04:10:08 PM UTC (2020-10-26T16:10:08+00:00).
-Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [34043d1b](https://github.com/SymbiFlow/prjxray/commit/34043d1b3d2a420cb581a89ddd3b30203fa918ac).
+Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [1b17af7d](https://github.com/SymbiFlow/prjxray/commit/1b17af7d5c5fff30a627c89e63c0863822f29387).
Latest commit was;
```
-commit 34043d1b3d2a420cb581a89ddd3b30203fa918ac
-Merge: ac8d30e3 69d40a05
-Author: litghost <537074+litghost@users.noreply.github.com>
-Date: Tue Oct 20 15:44:37 2020 -0700
+commit 1b17af7d5c5fff30a627c89e63c0863822f29387
+Merge: aff076b4 6497a56b
+Author: Tim Ansell <me@mith.ro>
+Date: Sat Oct 24 11:55:14 2020 -0700
- Merge pull request #1447 from litghost/add_mmcm_pips
+ Merge pull request #1468 from litghost/fixup_requirements
- Add initial MMCM feature and PIP support.
+ Fixup doc requirements to work around https://github.com/pypa/pip/issues/9031
```
@@ -59,7 +59,7 @@
### Settings
-Created using following [settings/artix7.sh (sha256: a067074fade87ce054484872304ec70ee6992e5487c492f76a86143f6da45e03)](https://github.com/SymbiFlow/prjxray/blob/34043d1b3d2a420cb581a89ddd3b30203fa918ac/settings/artix7.sh)
+Created using following [settings/artix7.sh (sha256: a067074fade87ce054484872304ec70ee6992e5487c492f76a86143f6da45e03)](https://github.com/SymbiFlow/prjxray/blob/1b17af7d5c5fff30a627c89e63c0863822f29387/settings/artix7.sh)
```shell
#!/bin/bash
# Copyright (C) 2017-2020 The Project X-Ray Authors.
@@ -232,12 +232,12 @@
* [`f2e01a0371694c49d9f6d975767416b5e429058874a0d2ab54567584b6a9e7b7 ./artix7/ppips_rioi3_tbyteterm.db`](./artix7/ppips_rioi3_tbyteterm.db)
* [`8a2136e564ac92c06b226ef8715a122050fcabbb063f69eeaf46cfee5c89670f ./artix7/segbits_bram_l.block_ram.db`](./artix7/segbits_bram_l.block_ram.db)
* [`0cb9b3fb3c7627b1c16330f28fc212188441e087c30b0aefd506883676cde42f ./artix7/segbits_bram_l.block_ram.origin_info.db`](./artix7/segbits_bram_l.block_ram.origin_info.db)
- * [`53d975bf59b763b9f764106db362ee7f6a753e9e72a5e2be334041658a5ea4ba ./artix7/segbits_bram_l.db`](./artix7/segbits_bram_l.db)
- * [`f17801a157ece0bc755668de44455d82b16f48cabc56606d0d9567aaf2a7018a ./artix7/segbits_bram_l.origin_info.db`](./artix7/segbits_bram_l.origin_info.db)
+ * [`a70cb7eaf85f9aeb355cd7306fc7cc887122c81a3f5e81a014b4c8d7c1ddbae9 ./artix7/segbits_bram_l.db`](./artix7/segbits_bram_l.db)
+ * [`168e66e3354e1e6713d6c2af1e1ede8dd18a4c0e9ef9c11e5fb51ba873c03fbf ./artix7/segbits_bram_l.origin_info.db`](./artix7/segbits_bram_l.origin_info.db)
* [`a635577b55878c69df492c16b67a1dfbd1d4b786a695abe3e95a62d9540ecea5 ./artix7/segbits_bram_r.block_ram.db`](./artix7/segbits_bram_r.block_ram.db)
* [`217912bce67c76dbcff4960facaed240204d230884ce91da298c16a7c88f5ead ./artix7/segbits_bram_r.block_ram.origin_info.db`](./artix7/segbits_bram_r.block_ram.origin_info.db)
- * [`b826680f3768091cb345ca6e62e3210ffb53a88ebdfdf4ca70f466f80cdacb1f ./artix7/segbits_bram_r.db`](./artix7/segbits_bram_r.db)
- * [`956236cd62bc6d4004506bae881d7fd81f92c448d94710175f7fec8a3ec66c42 ./artix7/segbits_bram_r.origin_info.db`](./artix7/segbits_bram_r.origin_info.db)
+ * [`51c8eb3f1eb8332446841515ed6c9aed24d4f3c7e96e6508f11b121a12839b2c ./artix7/segbits_bram_r.db`](./artix7/segbits_bram_r.db)
+ * [`3d1e156d3af404707a8b44f9f1b1ad86d5b34a4e8bbbeb46c2a9eb2d7d704910 ./artix7/segbits_bram_r.origin_info.db`](./artix7/segbits_bram_r.origin_info.db)
* [`7f65ab9eba491f02e059615f3491e1d6037e9644d9b9ee034c114e67d9ae3b4a ./artix7/segbits_cfg_center_mid.db`](./artix7/segbits_cfg_center_mid.db)
* [`744710ce4e9c38ce1b8befae8f9d015ef38f14c6de291d932ac56eb5543bf499 ./artix7/segbits_cfg_center_mid.origin_info.db`](./artix7/segbits_cfg_center_mid.origin_info.db)
* [`9bf6bdffdc814569a7da53c696e46207aab23ea66c9dd92c47e50a6211dd739b ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db)
@@ -281,9 +281,9 @@
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
* [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./artix7/segbits_hclk_r.origin_info.db`](./artix7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
- * [`e5b05be3f1e8b2eda6b2614097fd676eb13065d83a01a26b56b26e7beaa1b5fa ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
+ * [`b9f9f3bbe0dc75e516db24e6e67d2e45d48afb275aba859eb52f4a7281b4f62e ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
- * [`5375a2f04a1b921b48b8c1566b425c2c7dd73ad361ba1869ea5534bb5a23d5b0 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
+ * [`75c443c5ada9f58872b27777655fa1258eddd22da8699dc997735759697559ac ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
* [`392e91def4df6eebb3ce5ed15570c01f6090be793a79054e1880549082eb6f23 ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db)
* [`6ffdf37ae2c6625eed093d59458f3319928bab0ac268abfdeed04c92c4673cfb ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db)
* [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff ./artix7/segbits_lioi3.db`](./artix7/segbits_lioi3.db)
@@ -569,7 +569,7 @@
### Settings
-Created using following [settings/kintex7.sh (sha256: 8c4c506cbdc6a25696436bbe6359e3617c82a11931ad6e406a1c433b263527c4)](https://github.com/SymbiFlow/prjxray/blob/34043d1b3d2a420cb581a89ddd3b30203fa918ac/settings/kintex7.sh)
+Created using following [settings/kintex7.sh (sha256: 8c4c506cbdc6a25696436bbe6359e3617c82a11931ad6e406a1c433b263527c4)](https://github.com/SymbiFlow/prjxray/blob/1b17af7d5c5fff30a627c89e63c0863822f29387/settings/kintex7.sh)
```shell
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
@@ -708,12 +708,12 @@
* [`b6255a5ec971695a0aadd4901f2021d839c20b9cff781b2fccc8f5e779295319 ./kintex7/ppips_lioi3_tbyteterm.db`](./kintex7/ppips_lioi3_tbyteterm.db)
* [`8a2136e564ac92c06b226ef8715a122050fcabbb063f69eeaf46cfee5c89670f ./kintex7/segbits_bram_l.block_ram.db`](./kintex7/segbits_bram_l.block_ram.db)
* [`0cb9b3fb3c7627b1c16330f28fc212188441e087c30b0aefd506883676cde42f ./kintex7/segbits_bram_l.block_ram.origin_info.db`](./kintex7/segbits_bram_l.block_ram.origin_info.db)
- * [`53d975bf59b763b9f764106db362ee7f6a753e9e72a5e2be334041658a5ea4ba ./kintex7/segbits_bram_l.db`](./kintex7/segbits_bram_l.db)
- * [`f17801a157ece0bc755668de44455d82b16f48cabc56606d0d9567aaf2a7018a ./kintex7/segbits_bram_l.origin_info.db`](./kintex7/segbits_bram_l.origin_info.db)
+ * [`a70cb7eaf85f9aeb355cd7306fc7cc887122c81a3f5e81a014b4c8d7c1ddbae9 ./kintex7/segbits_bram_l.db`](./kintex7/segbits_bram_l.db)
+ * [`168e66e3354e1e6713d6c2af1e1ede8dd18a4c0e9ef9c11e5fb51ba873c03fbf ./kintex7/segbits_bram_l.origin_info.db`](./kintex7/segbits_bram_l.origin_info.db)
* [`a635577b55878c69df492c16b67a1dfbd1d4b786a695abe3e95a62d9540ecea5 ./kintex7/segbits_bram_r.block_ram.db`](./kintex7/segbits_bram_r.block_ram.db)
* [`217912bce67c76dbcff4960facaed240204d230884ce91da298c16a7c88f5ead ./kintex7/segbits_bram_r.block_ram.origin_info.db`](./kintex7/segbits_bram_r.block_ram.origin_info.db)
- * [`b826680f3768091cb345ca6e62e3210ffb53a88ebdfdf4ca70f466f80cdacb1f ./kintex7/segbits_bram_r.db`](./kintex7/segbits_bram_r.db)
- * [`956236cd62bc6d4004506bae881d7fd81f92c448d94710175f7fec8a3ec66c42 ./kintex7/segbits_bram_r.origin_info.db`](./kintex7/segbits_bram_r.origin_info.db)
+ * [`51c8eb3f1eb8332446841515ed6c9aed24d4f3c7e96e6508f11b121a12839b2c ./kintex7/segbits_bram_r.db`](./kintex7/segbits_bram_r.db)
+ * [`3d1e156d3af404707a8b44f9f1b1ad86d5b34a4e8bbbeb46c2a9eb2d7d704910 ./kintex7/segbits_bram_r.origin_info.db`](./kintex7/segbits_bram_r.origin_info.db)
* [`7f65ab9eba491f02e059615f3491e1d6037e9644d9b9ee034c114e67d9ae3b4a ./kintex7/segbits_cfg_center_mid.db`](./kintex7/segbits_cfg_center_mid.db)
* [`744710ce4e9c38ce1b8befae8f9d015ef38f14c6de291d932ac56eb5543bf499 ./kintex7/segbits_cfg_center_mid.origin_info.db`](./kintex7/segbits_cfg_center_mid.origin_info.db)
* [`9bf6bdffdc814569a7da53c696e46207aab23ea66c9dd92c47e50a6211dd739b ./kintex7/segbits_clbll_l.db`](./kintex7/segbits_clbll_l.db)
@@ -757,9 +757,9 @@
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db)
* [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./kintex7/segbits_hclk_r.origin_info.db`](./kintex7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
- * [`444e7917ce354b011c3ecdb98b8785f1edf99770d9cad27fc89e9d1f9cd22eb5 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
+ * [`5680302c374ee237ce6043d7f5679056343eaa7ad22b8557980daa5e5eaa7467 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
- * [`61eb508ad94dd35a33d9b91a4c667349b01107cd3e533928eefd8a312bf31ac0 ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
+ * [`bb366fb25a36bfb46359ca8b12460534e2f83f3995c16de30f0ae8ac6b781937 ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
* [`392e91def4df6eebb3ce5ed15570c01f6090be793a79054e1880549082eb6f23 ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db)
* [`6ffdf37ae2c6625eed093d59458f3319928bab0ac268abfdeed04c92c4673cfb ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db)
* [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff ./kintex7/segbits_lioi3.db`](./kintex7/segbits_lioi3.db)
@@ -952,7 +952,7 @@
### Settings
-Created using following [settings/zynq7.sh (sha256: 790d0886285b195daff0950f82ddb42635257c7c6400dcc5c7fb5b13f66ee6ba)](https://github.com/SymbiFlow/prjxray/blob/34043d1b3d2a420cb581a89ddd3b30203fa918ac/settings/zynq7.sh)
+Created using following [settings/zynq7.sh (sha256: 790d0886285b195daff0950f82ddb42635257c7c6400dcc5c7fb5b13f66ee6ba)](https://github.com/SymbiFlow/prjxray/blob/1b17af7d5c5fff30a627c89e63c0863822f29387/settings/zynq7.sh)
```shell
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
@@ -1105,12 +1105,12 @@
* [`be3770d6261c832fe571f9662463f1ccb825bd1f8fa919a23488a71c17680336 ./zynq7/ps7_ports.json`](./zynq7/ps7_ports.json)
* [`8a2136e564ac92c06b226ef8715a122050fcabbb063f69eeaf46cfee5c89670f ./zynq7/segbits_bram_l.block_ram.db`](./zynq7/segbits_bram_l.block_ram.db)
* [`0cb9b3fb3c7627b1c16330f28fc212188441e087c30b0aefd506883676cde42f ./zynq7/segbits_bram_l.block_ram.origin_info.db`](./zynq7/segbits_bram_l.block_ram.origin_info.db)
- * [`53d975bf59b763b9f764106db362ee7f6a753e9e72a5e2be334041658a5ea4ba ./zynq7/segbits_bram_l.db`](./zynq7/segbits_bram_l.db)
- * [`f17801a157ece0bc755668de44455d82b16f48cabc56606d0d9567aaf2a7018a ./zynq7/segbits_bram_l.origin_info.db`](./zynq7/segbits_bram_l.origin_info.db)
+ * [`a70cb7eaf85f9aeb355cd7306fc7cc887122c81a3f5e81a014b4c8d7c1ddbae9 ./zynq7/segbits_bram_l.db`](./zynq7/segbits_bram_l.db)
+ * [`168e66e3354e1e6713d6c2af1e1ede8dd18a4c0e9ef9c11e5fb51ba873c03fbf ./zynq7/segbits_bram_l.origin_info.db`](./zynq7/segbits_bram_l.origin_info.db)
* [`a635577b55878c69df492c16b67a1dfbd1d4b786a695abe3e95a62d9540ecea5 ./zynq7/segbits_bram_r.block_ram.db`](./zynq7/segbits_bram_r.block_ram.db)
* [`217912bce67c76dbcff4960facaed240204d230884ce91da298c16a7c88f5ead ./zynq7/segbits_bram_r.block_ram.origin_info.db`](./zynq7/segbits_bram_r.block_ram.origin_info.db)
- * [`b826680f3768091cb345ca6e62e3210ffb53a88ebdfdf4ca70f466f80cdacb1f ./zynq7/segbits_bram_r.db`](./zynq7/segbits_bram_r.db)
- * [`956236cd62bc6d4004506bae881d7fd81f92c448d94710175f7fec8a3ec66c42 ./zynq7/segbits_bram_r.origin_info.db`](./zynq7/segbits_bram_r.origin_info.db)
+ * [`51c8eb3f1eb8332446841515ed6c9aed24d4f3c7e96e6508f11b121a12839b2c ./zynq7/segbits_bram_r.db`](./zynq7/segbits_bram_r.db)
+ * [`3d1e156d3af404707a8b44f9f1b1ad86d5b34a4e8bbbeb46c2a9eb2d7d704910 ./zynq7/segbits_bram_r.origin_info.db`](./zynq7/segbits_bram_r.origin_info.db)
* [`1cb97b31823973edf1fd439e677573ad37318c697e06588d3c63ab50229b7ed4 ./zynq7/segbits_cfg_center_mid.db`](./zynq7/segbits_cfg_center_mid.db)
* [`9bb41bd62de7a85d79a38a32101927f9cf273f0c892fdf37500ab529777acdd5 ./zynq7/segbits_cfg_center_mid.origin_info.db`](./zynq7/segbits_cfg_center_mid.origin_info.db)
* [`9bf6bdffdc814569a7da53c696e46207aab23ea66c9dd92c47e50a6211dd739b ./zynq7/segbits_clbll_l.db`](./zynq7/segbits_clbll_l.db)
@@ -1154,9 +1154,9 @@
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db)
* [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./zynq7/segbits_hclk_r.origin_info.db`](./zynq7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db)
- * [`5fc5ab48a9b407991e79f2afb04f323071f75cce8892c1b34fc677d840016738 ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
+ * [`c42e6413cf7aeb5c7295691577b42f7a8ff8d3da9bcedea2dd9ea36c63bd700f ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db)
- * [`ccd1e9aae8a04ea951bbe123f34cb3277144b365ab00046e3a5a013aaeebafbd ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
+ * [`1628b4cfe299f69b8a8216ef8fdb3b045c41c2a93e7853d00b9d3fee75e82bf0 ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
* [`392e91def4df6eebb3ce5ed15570c01f6090be793a79054e1880549082eb6f23 ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db)
* [`6ffdf37ae2c6625eed093d59458f3319928bab0ac268abfdeed04c92c4673cfb ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db)
* [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff ./zynq7/segbits_lioi3.db`](./zynq7/segbits_lioi3.db)
@@ -1349,7 +1349,7 @@
* [`5afccb72fdc7e9a452988e5db5dd7517ab38792ba21af020f9f1885f686ae5a3 ./zynq7/timings/HCLK_CMT.sdf`](./zynq7/timings/HCLK_CMT.sdf)
* [`5afccb72fdc7e9a452988e5db5dd7517ab38792ba21af020f9f1885f686ae5a3 ./zynq7/timings/HCLK_CMT_L.sdf`](./zynq7/timings/HCLK_CMT_L.sdf)
* [`b5d5ca72d453879fca2bf2470fb0a670ebfb38d6e85cdbfdb3967e2e4f59ee73 ./zynq7/timings/HCLK_IOI3.sdf`](./zynq7/timings/HCLK_IOI3.sdf)
- * [`a64ba6e07bedc352898bc06d44b3677111739e9c0ecdf989fa57f1a200547b14 ./zynq7/timings/LIOB33.sdf`](./zynq7/timings/LIOB33.sdf)
+ * [`9313a012de7cbb7120baf15fe30bf8d44b238cad6226ece1a9776746e2857863 ./zynq7/timings/LIOB33.sdf`](./zynq7/timings/LIOB33.sdf)
* [`0fdaf6a593346b5cac8899eebf4f62d1732d6d6fb0a17c9f4b6a4e54e03c3523 ./zynq7/timings/LIOB33_SING.sdf`](./zynq7/timings/LIOB33_SING.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./zynq7/timings/LIOI3.sdf`](./zynq7/timings/LIOI3.sdf)
* [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1 ./zynq7/timings/LIOI3_SING.sdf`](./zynq7/timings/LIOI3_SING.sdf)
diff --git a/artix7/segbits_bram_l.db b/artix7/segbits_bram_l.db
index f45296d..81608f4 100644
--- a/artix7/segbits_bram_l.db
+++ b/artix7/segbits_bram_l.db
@@ -450,3 +450,4 @@
BRAM_L.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER !27_188
BRAM_L.RAMB36.RAM_EXTENSION_B_LOWER 27_187
BRAM_L.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER !27_187
+BRAM_L.RAMB36.BRAM36_IN_USE 27_179 27_180 27_181 27_184
diff --git a/artix7/segbits_bram_l.origin_info.db b/artix7/segbits_bram_l.origin_info.db
index b18eb88..ff75f92 100644
--- a/artix7/segbits_bram_l.origin_info.db
+++ b/artix7/segbits_bram_l.origin_info.db
@@ -450,3 +450,4 @@
BRAM_L.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER origin:027-bram36-config !27_188
BRAM_L.RAMB36.RAM_EXTENSION_B_LOWER origin:027-bram36-config 27_187
BRAM_L.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER origin:027-bram36-config !27_187
+BRAM_L.RAMB36.BRAM36_IN_USE origin:027-bram36-config 27_179 27_180 27_181 27_184
diff --git a/artix7/segbits_bram_r.db b/artix7/segbits_bram_r.db
index 1cf2a2c..212bbb2 100644
--- a/artix7/segbits_bram_r.db
+++ b/artix7/segbits_bram_r.db
@@ -450,3 +450,4 @@
BRAM_R.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER !27_188
BRAM_R.RAMB36.RAM_EXTENSION_B_LOWER 27_187
BRAM_R.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER !27_187
+BRAM_R.RAMB36.BRAM36_IN_USE 27_179 27_180 27_181 27_184
diff --git a/artix7/segbits_bram_r.origin_info.db b/artix7/segbits_bram_r.origin_info.db
index 8971f08..cd0aebc 100644
--- a/artix7/segbits_bram_r.origin_info.db
+++ b/artix7/segbits_bram_r.origin_info.db
@@ -450,3 +450,4 @@
BRAM_R.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER origin:027-bram36-config !27_188
BRAM_R.RAMB36.RAM_EXTENSION_B_LOWER origin:027-bram36-config 27_187
BRAM_R.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER origin:027-bram36-config !27_187
+BRAM_R.RAMB36.BRAM36_IN_USE origin:027-bram36-config 27_179 27_180 27_181 27_184
diff --git a/artix7/segbits_int_l.origin_info.db b/artix7/segbits_int_l.origin_info.db
index 4c1eb1f..fd290e1 100644
--- a/artix7/segbits_int_l.origin_info.db
+++ b/artix7/segbits_int_l.origin_info.db
@@ -170,7 +170,7 @@
INT_L.BYP_ALT7.BYP_BOUNCE6 origin:050-pip-seed !22_63 !23_63 !25_63 21_63 24_63
INT_L.BYP_ALT7.EL1END_S3_0 origin:050-pip-seed !23_63 17_63 22_63 24_63 25_63
INT_L.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
-INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:056-pip-rem !22_63 21_63 23_63 24_63 25_63
+INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
INT_L.BYP_ALT7.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_63 20_63 23_63 24_63 25_63
INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
@@ -301,7 +301,7 @@
INT_L.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
-INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
+INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
INT_L.FAN_ALT0.SR1END_N3_3 origin:050-pip-seed !23_00 19_01 22_00 24_00 25_00
INT_L.FAN_ALT0.SS2END_N0_3 origin:050-pip-seed !22_00 !23_00 !24_00 17_00 25_00
INT_L.FAN_ALT0.SW2END_N0_3 origin:050-pip-seed !22_00 !23_00 !25_00 17_00 24_00
@@ -1937,7 +1937,7 @@
INT_L.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
INT_L.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
INT_L.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_L.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
+INT_L.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
INT_L.EL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_20 14_21
INT_L.EL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_21 14_21
INT_L.EL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_21 13_21
@@ -2253,7 +2253,7 @@
INT_L.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39
INT_L.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36
INT_L.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37
-INT_L.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36
+INT_L.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36
INT_L.NE6BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_53 04_54
INT_L.NE6BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_53 07_53
INT_L.NE6BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_52 07_53
@@ -2491,7 +2491,7 @@
INT_L.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
INT_L.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
INT_L.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
-INT_L.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
+INT_L.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
INT_L.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
INT_L.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
INT_L.NR1BEG0.LOGIC_OUTS_L0 origin:050-pip-seed 11_07 14_07
@@ -2887,7 +2887,7 @@
INT_L.SE6BEG3.NE2END3 origin:050-pip-seed 03_58 04_56
INT_L.SE6BEG3.NE6END3 origin:050-pip-seed 04_56 04_59
INT_L.SE6BEG3.NN2END3 origin:050-pip-seed 02_59 04_56
-INT_L.SE6BEG3.NN6END3 origin:056-pip-rem 04_56 07_59
+INT_L.SE6BEG3.NN6END3 origin:050-pip-seed 04_56 07_59
INT_L.SE6BEG3.SE2END3 origin:050-pip-seed 02_58 03_58
INT_L.SE6BEG3.SE6END3 origin:050-pip-seed 02_58 07_59
INT_L.SE6BEG3.SS2END3 origin:050-pip-seed 02_59 05_58
@@ -3302,7 +3302,7 @@
INT_L.SW6BEG1.LOGIC_OUTS_L23 origin:050-pip-seed 04_30 06_28
INT_L.SW6BEG1.LV_L9 origin:056-pip-rem 04_30 05_28
INT_L.SW6BEG1.EE2END1 origin:050-pip-seed 03_28 04_29
-INT_L.SW6BEG1.EE4END1 origin:056-pip-rem 04_29 05_28
+INT_L.SW6BEG1.EE4END1 origin:050-pip-seed 04_29 05_28
INT_L.SW6BEG1.LH6 origin:056-pip-rem 05_28 07_29
INT_L.SW6BEG1.NW2END2 origin:050-pip-seed 02_29 05_31
INT_L.SW6BEG1.NW6END2 origin:050-pip-seed 05_31 06_28
diff --git a/artix7/segbits_int_r.origin_info.db b/artix7/segbits_int_r.origin_info.db
index eed46d5..e0eae39 100644
--- a/artix7/segbits_int_r.origin_info.db
+++ b/artix7/segbits_int_r.origin_info.db
@@ -705,7 +705,7 @@
INT_R.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
INT_R.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
INT_R.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
-INT_R.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
+INT_R.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
INT_R.EE4BEG3.LOGIC_OUTS3 origin:050-pip-seed 02_57 07_57
INT_R.EE4BEG3.LOGIC_OUTS7 origin:050-pip-seed 02_57 04_58
INT_R.EE4BEG3.LOGIC_OUTS11 origin:050-pip-seed 03_56 04_58
@@ -725,7 +725,7 @@
INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
+INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
INT_R.EL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_20 14_21
INT_R.EL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_21 14_21
INT_R.EL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_21 13_21
@@ -2273,7 +2273,7 @@
INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
+INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17
INT_R.NL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_17 14_17
INT_R.NL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_17 13_17
@@ -2471,7 +2471,7 @@
INT_R.NN6BEG2.NW2END2 origin:050-pip-seed 03_38 04_36
INT_R.NN6BEG2.NW6END2 origin:050-pip-seed 04_36 07_39
INT_R.NN6BEG2.SE2END2 origin:050-pip-seed 03_38 05_38
-INT_R.NN6BEG2.SE6END2 origin:056-pip-rem 05_38 07_39
+INT_R.NN6BEG2.SE6END2 origin:050-pip-seed 05_38 07_39
INT_R.NN6BEG2.WW2END1 origin:050-pip-seed 02_39 04_36
INT_R.NN6BEG2.WW4END2 origin:050-pip-seed 04_36 04_39
INT_R.NN6BEG3.LOGIC_OUTS3 origin:050-pip-seed 03_54 06_54
@@ -2491,7 +2491,7 @@
INT_R.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
INT_R.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
INT_R.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
-INT_R.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
+INT_R.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
INT_R.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
INT_R.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
INT_R.NR1BEG0.LOGIC_OUTS0 origin:050-pip-seed 11_07 14_07
@@ -3301,7 +3301,7 @@
INT_R.SW6BEG1.LOGIC_OUTS19 origin:050-pip-seed 06_28 07_29
INT_R.SW6BEG1.LOGIC_OUTS23 origin:050-pip-seed 04_30 06_28
INT_R.SW6BEG1.EE2END1 origin:050-pip-seed 03_28 04_29
-INT_R.SW6BEG1.EE4END1 origin:050-pip-seed 04_29 05_28
+INT_R.SW6BEG1.EE4END1 origin:056-pip-rem 04_29 05_28
INT_R.SW6BEG1.LH6 origin:056-pip-rem 05_28 07_29
INT_R.SW6BEG1.LV9 origin:056-pip-rem 04_30 05_28
INT_R.SW6BEG1.NW2END2 origin:050-pip-seed 02_29 05_31
@@ -3321,7 +3321,7 @@
INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
diff --git a/kintex7/segbits_bram_l.db b/kintex7/segbits_bram_l.db
index f45296d..81608f4 100644
--- a/kintex7/segbits_bram_l.db
+++ b/kintex7/segbits_bram_l.db
@@ -450,3 +450,4 @@
BRAM_L.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER !27_188
BRAM_L.RAMB36.RAM_EXTENSION_B_LOWER 27_187
BRAM_L.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER !27_187
+BRAM_L.RAMB36.BRAM36_IN_USE 27_179 27_180 27_181 27_184
diff --git a/kintex7/segbits_bram_l.origin_info.db b/kintex7/segbits_bram_l.origin_info.db
index b18eb88..ff75f92 100644
--- a/kintex7/segbits_bram_l.origin_info.db
+++ b/kintex7/segbits_bram_l.origin_info.db
@@ -450,3 +450,4 @@
BRAM_L.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER origin:027-bram36-config !27_188
BRAM_L.RAMB36.RAM_EXTENSION_B_LOWER origin:027-bram36-config 27_187
BRAM_L.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER origin:027-bram36-config !27_187
+BRAM_L.RAMB36.BRAM36_IN_USE origin:027-bram36-config 27_179 27_180 27_181 27_184
diff --git a/kintex7/segbits_bram_r.db b/kintex7/segbits_bram_r.db
index 1cf2a2c..212bbb2 100644
--- a/kintex7/segbits_bram_r.db
+++ b/kintex7/segbits_bram_r.db
@@ -450,3 +450,4 @@
BRAM_R.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER !27_188
BRAM_R.RAMB36.RAM_EXTENSION_B_LOWER 27_187
BRAM_R.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER !27_187
+BRAM_R.RAMB36.BRAM36_IN_USE 27_179 27_180 27_181 27_184
diff --git a/kintex7/segbits_bram_r.origin_info.db b/kintex7/segbits_bram_r.origin_info.db
index 8971f08..cd0aebc 100644
--- a/kintex7/segbits_bram_r.origin_info.db
+++ b/kintex7/segbits_bram_r.origin_info.db
@@ -450,3 +450,4 @@
BRAM_R.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER origin:027-bram36-config !27_188
BRAM_R.RAMB36.RAM_EXTENSION_B_LOWER origin:027-bram36-config 27_187
BRAM_R.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER origin:027-bram36-config !27_187
+BRAM_R.RAMB36.BRAM36_IN_USE origin:027-bram36-config 27_179 27_180 27_181 27_184
diff --git a/kintex7/segbits_int_l.origin_info.db b/kintex7/segbits_int_l.origin_info.db
index c0a62ce..937be95 100644
--- a/kintex7/segbits_int_l.origin_info.db
+++ b/kintex7/segbits_int_l.origin_info.db
@@ -1937,7 +1937,7 @@
INT_L.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
INT_L.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
INT_L.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_L.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
+INT_L.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
INT_L.EL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_20 14_21
INT_L.EL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_21 14_21
INT_L.EL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_21 13_21
@@ -2271,7 +2271,7 @@
INT_L.NE6BEG3.NW2END3 origin:050-pip-seed 02_53 04_53
INT_L.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
-INT_L.NE6BEG3.SE6END3 origin:056-pip-rem 05_55 06_52
+INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17
@@ -3302,7 +3302,7 @@
INT_L.SW6BEG1.LOGIC_OUTS_L23 origin:050-pip-seed 04_30 06_28
INT_L.SW6BEG1.LV_L9 origin:056-pip-rem 04_30 05_28
INT_L.SW6BEG1.EE2END1 origin:050-pip-seed 03_28 04_29
-INT_L.SW6BEG1.EE4END1 origin:050-pip-seed 04_29 05_28
+INT_L.SW6BEG1.EE4END1 origin:056-pip-rem 04_29 05_28
INT_L.SW6BEG1.LH6 origin:056-pip-rem 05_28 07_29
INT_L.SW6BEG1.NW2END2 origin:050-pip-seed 02_29 05_31
INT_L.SW6BEG1.NW6END2 origin:050-pip-seed 05_31 06_28
@@ -3323,7 +3323,7 @@
INT_L.SW6BEG2.LVB_L0 origin:056-pip-rem 04_46 05_44
INT_L.SW6BEG2.LVB_L12 origin:056-pip-rem 05_44 07_45
INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
+INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
INT_L.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
INT_L.SW6BEG2.NW6END3 origin:050-pip-seed 05_47 06_44
INT_L.SW6BEG2.SE2END2 origin:050-pip-seed 02_45 04_45
@@ -3345,7 +3345,7 @@
INT_L.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60
INT_L.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63
INT_L.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
-INT_L.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
+INT_L.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
INT_L.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
INT_L.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61
INT_L.SW6BEG3.SE6END3 origin:050-pip-seed 04_61 06_60
@@ -3603,7 +3603,7 @@
INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
-INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
+INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
diff --git a/kintex7/segbits_int_r.origin_info.db b/kintex7/segbits_int_r.origin_info.db
index 3807463..4a04dae 100644
--- a/kintex7/segbits_int_r.origin_info.db
+++ b/kintex7/segbits_int_r.origin_info.db
@@ -237,7 +237,7 @@
INT_R.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
INT_R.FAN_ALT0.LOGIC_OUTS0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
INT_R.FAN_ALT0.LOGIC_OUTS12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
-INT_R.FAN_ALT0.LOGIC_OUTS22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
+INT_R.FAN_ALT0.LOGIC_OUTS22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
INT_R.FAN_ALT0.SR1END_N3_3 origin:050-pip-seed !23_00 19_01 22_00 24_00 25_00
INT_R.FAN_ALT0.SS2END_N0_3 origin:050-pip-seed !22_00 !23_00 !24_00 17_00 25_00
INT_R.FAN_ALT0.SW2END_N0_3 origin:050-pip-seed !22_00 !23_00 !25_00 17_00 24_00
@@ -328,7 +328,7 @@
INT_R.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56
INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
-INT_R.FAN_ALT4.FAN_BOUNCE2 origin:056-pip-rem !23_08 20_08 22_08 24_08 25_08
+INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
@@ -685,7 +685,7 @@
INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
-INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
+INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
INT_R.EE4BEG2.LOGIC_OUTS2 origin:050-pip-seed 02_41 04_42
INT_R.EE4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_41 07_41
INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
@@ -2491,7 +2491,7 @@
INT_R.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
INT_R.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
INT_R.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
-INT_R.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
+INT_R.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
INT_R.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
INT_R.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
INT_R.NR1BEG0.LOGIC_OUTS0 origin:050-pip-seed 11_07 14_07
@@ -3321,7 +3321,7 @@
INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
diff --git a/zynq7/segbits_bram_l.db b/zynq7/segbits_bram_l.db
index f45296d..81608f4 100644
--- a/zynq7/segbits_bram_l.db
+++ b/zynq7/segbits_bram_l.db
@@ -450,3 +450,4 @@
BRAM_L.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER !27_188
BRAM_L.RAMB36.RAM_EXTENSION_B_LOWER 27_187
BRAM_L.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER !27_187
+BRAM_L.RAMB36.BRAM36_IN_USE 27_179 27_180 27_181 27_184
diff --git a/zynq7/segbits_bram_l.origin_info.db b/zynq7/segbits_bram_l.origin_info.db
index b18eb88..ff75f92 100644
--- a/zynq7/segbits_bram_l.origin_info.db
+++ b/zynq7/segbits_bram_l.origin_info.db
@@ -450,3 +450,4 @@
BRAM_L.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER origin:027-bram36-config !27_188
BRAM_L.RAMB36.RAM_EXTENSION_B_LOWER origin:027-bram36-config 27_187
BRAM_L.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER origin:027-bram36-config !27_187
+BRAM_L.RAMB36.BRAM36_IN_USE origin:027-bram36-config 27_179 27_180 27_181 27_184
diff --git a/zynq7/segbits_bram_r.db b/zynq7/segbits_bram_r.db
index 1cf2a2c..212bbb2 100644
--- a/zynq7/segbits_bram_r.db
+++ b/zynq7/segbits_bram_r.db
@@ -450,3 +450,4 @@
BRAM_R.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER !27_188
BRAM_R.RAMB36.RAM_EXTENSION_B_LOWER 27_187
BRAM_R.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER !27_187
+BRAM_R.RAMB36.BRAM36_IN_USE 27_179 27_180 27_181 27_184
diff --git a/zynq7/segbits_bram_r.origin_info.db b/zynq7/segbits_bram_r.origin_info.db
index 8971f08..cd0aebc 100644
--- a/zynq7/segbits_bram_r.origin_info.db
+++ b/zynq7/segbits_bram_r.origin_info.db
@@ -450,3 +450,4 @@
BRAM_R.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER origin:027-bram36-config !27_188
BRAM_R.RAMB36.RAM_EXTENSION_B_LOWER origin:027-bram36-config 27_187
BRAM_R.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER origin:027-bram36-config !27_187
+BRAM_R.RAMB36.BRAM36_IN_USE origin:027-bram36-config 27_179 27_180 27_181 27_184
diff --git a/zynq7/segbits_int_l.origin_info.db b/zynq7/segbits_int_l.origin_info.db
index 51fc51a..d305299 100644
--- a/zynq7/segbits_int_l.origin_info.db
+++ b/zynq7/segbits_int_l.origin_info.db
@@ -1917,7 +1917,7 @@
INT_L.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
INT_L.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
INT_L.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
-INT_L.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
+INT_L.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
INT_L.EE4BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_57 07_57
INT_L.EE4BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_57 04_58
INT_L.EE4BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_56 04_58
@@ -2273,7 +2273,7 @@
INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
+INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17
INT_L.NL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_17 14_17
INT_L.NL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_17 13_17
@@ -2491,7 +2491,7 @@
INT_L.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
INT_L.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
INT_L.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
-INT_L.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
+INT_L.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
INT_L.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
INT_L.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
INT_L.NR1BEG0.LOGIC_OUTS_L0 origin:050-pip-seed 11_07 14_07
@@ -3603,7 +3603,7 @@
INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
-INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
+INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
diff --git a/zynq7/segbits_int_r.origin_info.db b/zynq7/segbits_int_r.origin_info.db
index 816ece8..b3b6058 100644
--- a/zynq7/segbits_int_r.origin_info.db
+++ b/zynq7/segbits_int_r.origin_info.db
@@ -685,7 +685,7 @@
INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
-INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
+INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
INT_R.EE4BEG2.LOGIC_OUTS2 origin:050-pip-seed 02_41 04_42
INT_R.EE4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_41 07_41
INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
@@ -725,7 +725,7 @@
INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
+INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
INT_R.EL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_20 14_21
INT_R.EL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_21 14_21
INT_R.EL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_21 13_21
@@ -2273,7 +2273,7 @@
INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
+INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17
INT_R.NL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_17 14_17
INT_R.NL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_17 13_17
@@ -3301,7 +3301,7 @@
INT_R.SW6BEG1.LOGIC_OUTS19 origin:050-pip-seed 06_28 07_29
INT_R.SW6BEG1.LOGIC_OUTS23 origin:050-pip-seed 04_30 06_28
INT_R.SW6BEG1.EE2END1 origin:050-pip-seed 03_28 04_29
-INT_R.SW6BEG1.EE4END1 origin:050-pip-seed 04_29 05_28
+INT_R.SW6BEG1.EE4END1 origin:056-pip-rem 04_29 05_28
INT_R.SW6BEG1.LH6 origin:056-pip-rem 05_28 07_29
INT_R.SW6BEG1.LV9 origin:056-pip-rem 04_30 05_28
INT_R.SW6BEG1.NW2END2 origin:050-pip-seed 02_29 05_31
@@ -3321,7 +3321,7 @@
INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
@@ -3603,7 +3603,7 @@
INT_R.WW4BEG2.LVB0 origin:056-pip-rem 04_34 05_32
INT_R.WW4BEG2.LVB12 origin:056-pip-rem 05_32 07_33
INT_R.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
-INT_R.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
+INT_R.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
INT_R.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
INT_R.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
INT_R.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
diff --git a/zynq7/timings/LIOB33.sdf b/zynq7/timings/LIOB33.sdf
index bfd9395..43ad6e0 100644
--- a/zynq7/timings/LIOB33.sdf
+++ b/zynq7/timings/LIOB33.sdf
@@ -4,11 +4,11 @@
(TIMESCALE 1ns)
(CELL
- (CELLTYPE "IOB33_INBUF_ENIOB33_IOB_INBUF_EN")
+ (CELLTYPE "IOB33M_INBUF_ENIOB33_IOBM_INBUF_EN")
(INSTANCE IOB33M)
(DELAY
(ABSOLUTE
- (IOPATH IBUFDISABLE OUT (0.339::0.390)(1.027::1.182))
+ (IOPATH IBUFDISABLE OUT (0.339::0.390)(1.016::1.169))
)
)
)
