Updating all based on "Merge pull request #1447 from litghost/add_mmcm_pips" See [Info File](Info.md) for details. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>

commit: 76ef27c727f1b8e4d8c0ee681f71c4f4d4eab3c9 [log] [tgz]
author: Tim 'mithro' Ansell <me@mith.ro> Wed Oct 21 12:04:33 2020 -0700
committer: Tim 'mithro' Ansell <me@mith.ro> Wed Oct 21 12:05:08 2020 -0700
tree: ca62fbb8ec6f315ce123bab91772d0380b8d8edd
parent: 303a61d8bc552f7a533b91b17448c59e908aa391 [diff]
diff --git a/Info.md b/Info.md
index bd03889..315f6c0 100644
--- a/Info.md
+++ b/Info.md

@@ -37,20 +37,20 @@
 
 # Details
 
-Last updated on Tue 04 Aug 2020 05:44:42 PM UTC (2020-08-04T17:44:42+00:00).
+Last updated on Wed 21 Oct 2020 07:04:17 PM UTC (2020-10-21T19:04:17+00:00).
 
-Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [0339695c](https://github.com/SymbiFlow/prjxray/commit/0339695c0d30a5e10119705102f51e9443c5f28c).
+Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [34043d1b](https://github.com/SymbiFlow/prjxray/commit/34043d1b3d2a420cb581a89ddd3b30203fa918ac).
 
 Latest commit was;
 ```
-commit 0339695c0d30a5e10119705102f51e9443c5f28c
-Merge: 4e63f301 8780e2e6
+commit 34043d1b3d2a420cb581a89ddd3b30203fa918ac
+Merge: ac8d30e3 69d40a05
 Author: litghost <537074+litghost@users.noreply.github.com>
-Date:   Thu Jul 30 10:12:56 2020 -0700
+Date:   Tue Oct 20 15:44:37 2020 -0700
 
-    Merge pull request #1407 from antmicro/iserdes-features-grouping
+    Merge pull request #1447 from litghost/add_mmcm_pips
     
-    Fix tag grouping for ISERDES
+    Add initial MMCM feature and PIP support.
 ```
 
 
@@ -59,7 +59,7 @@
 
 ### Settings
 
-Created using following [settings/artix7.sh (sha256: a067074fade87ce054484872304ec70ee6992e5487c492f76a86143f6da45e03)](https://github.com/SymbiFlow/prjxray/blob/0339695c0d30a5e10119705102f51e9443c5f28c/settings/artix7.sh)
+Created using following [settings/artix7.sh (sha256: a067074fade87ce054484872304ec70ee6992e5487c492f76a86143f6da45e03)](https://github.com/SymbiFlow/prjxray/blob/34043d1b3d2a420cb581a89ddd3b30203fa918ac/settings/artix7.sh)
 ```shell
 #!/bin/bash
 # Copyright (C) 2017-2020  The Project X-Ray Authors.
@@ -168,13 +168,13 @@
  * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd  ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./artix7/mask_hclk_r.origin_info.db`](./artix7/mask_hclk_r.origin_info.db)
  * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./artix7/mask_liob33.db`](./artix7/mask_liob33.db)
- * [`383c4685449b553c61878b78712a87b5827e4e438f5f3a572cc0a20fc21d5f14  ./artix7/mask_lioi3.db`](./artix7/mask_lioi3.db)
- * [`383c4685449b553c61878b78712a87b5827e4e438f5f3a572cc0a20fc21d5f14  ./artix7/mask_lioi3_tbytesrc.db`](./artix7/mask_lioi3_tbytesrc.db)
- * [`383c4685449b553c61878b78712a87b5827e4e438f5f3a572cc0a20fc21d5f14  ./artix7/mask_lioi3_tbyteterm.db`](./artix7/mask_lioi3_tbyteterm.db)
+ * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./artix7/mask_lioi3.db`](./artix7/mask_lioi3.db)
+ * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./artix7/mask_lioi3_tbytesrc.db`](./artix7/mask_lioi3_tbytesrc.db)
+ * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./artix7/mask_lioi3_tbyteterm.db`](./artix7/mask_lioi3_tbyteterm.db)
  * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./artix7/mask_riob33.db`](./artix7/mask_riob33.db)
- * [`383c4685449b553c61878b78712a87b5827e4e438f5f3a572cc0a20fc21d5f14  ./artix7/mask_rioi3.db`](./artix7/mask_rioi3.db)
- * [`383c4685449b553c61878b78712a87b5827e4e438f5f3a572cc0a20fc21d5f14  ./artix7/mask_rioi3_tbytesrc.db`](./artix7/mask_rioi3_tbytesrc.db)
- * [`383c4685449b553c61878b78712a87b5827e4e438f5f3a572cc0a20fc21d5f14  ./artix7/mask_rioi3_tbyteterm.db`](./artix7/mask_rioi3_tbyteterm.db)
+ * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./artix7/mask_rioi3.db`](./artix7/mask_rioi3.db)
+ * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./artix7/mask_rioi3_tbytesrc.db`](./artix7/mask_rioi3_tbytesrc.db)
+ * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./artix7/mask_rioi3_tbyteterm.db`](./artix7/mask_rioi3_tbyteterm.db)
  * [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf  ./artix7/ppips_bram_int_interface_l.db`](./artix7/ppips_bram_int_interface_l.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./artix7/ppips_bram_int_interface_l.origin_info.db`](./artix7/ppips_bram_int_interface_l.origin_info.db)
  * [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae  ./artix7/ppips_bram_int_interface_r.db`](./artix7/ppips_bram_int_interface_r.db)
@@ -249,19 +249,23 @@
  * [`3ddfeca1b01bdc04b4f1b3d0dc73cf39f4230708fbbcb5b6170d5b50dc49ad64  ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db)
  * [`24bc3e7052d683b896e273210cf626e7544b34b7829508b8c4ad178926307e5e  ./artix7/segbits_clblm_r.origin_info.db`](./artix7/segbits_clblm_r.origin_info.db)
  * [`8d43bd09b2f7127ff9ed4803b92303d72c827d10b8b8d943c295343257b3e818  ./artix7/segbits_clk_bufg_bot_r.db`](./artix7/segbits_clk_bufg_bot_r.db)
- * [`a0ed10aa1039af4dce795a1c48cb1c908d845727be480b34b68084b7220fd94e  ./artix7/segbits_clk_bufg_bot_r.origin_info.db`](./artix7/segbits_clk_bufg_bot_r.origin_info.db)
+ * [`9abfcf14a91347582e92eec78e43fb3ff51f522d452bf1658f7655348a5df5d2  ./artix7/segbits_clk_bufg_bot_r.origin_info.db`](./artix7/segbits_clk_bufg_bot_r.origin_info.db)
  * [`d094c55a62408bd79c2606a8fc10839b23d979e4e924ced0d4276d285db7810f  ./artix7/segbits_clk_bufg_rebuf.db`](./artix7/segbits_clk_bufg_rebuf.db)
  * [`129662c05faf1ed9e12c7dd850c2b8753453c64d18750bbfc18324e1f0dcf4ef  ./artix7/segbits_clk_bufg_rebuf.origin_info.db`](./artix7/segbits_clk_bufg_rebuf.origin_info.db)
  * [`6da9671e724a74e370b805ddd47e04eefd89daa0af4331e841720f7586d7eb2a  ./artix7/segbits_clk_bufg_top_r.db`](./artix7/segbits_clk_bufg_top_r.db)
- * [`1efb8d63a68a6a920f912e158bbb2f511498f184f53c0f88e0d9a6bcdbcf8da3  ./artix7/segbits_clk_bufg_top_r.origin_info.db`](./artix7/segbits_clk_bufg_top_r.origin_info.db)
+ * [`2f0d0b9c95989ea190fff37c6111f53884394afc506aa059d9d4fc831e952a43  ./artix7/segbits_clk_bufg_top_r.origin_info.db`](./artix7/segbits_clk_bufg_top_r.origin_info.db)
  * [`5b22e19775dfa493f75bb3edbfccc06709a50b829e89857dc20aee1cbc8f6794  ./artix7/segbits_clk_hrow_bot_r.db`](./artix7/segbits_clk_hrow_bot_r.db)
  * [`cf71a4438ae35cb2493b614e895e3d5cf577613a8d9c10cf1c566872a2ea9b4f  ./artix7/segbits_clk_hrow_bot_r.origin_info.db`](./artix7/segbits_clk_hrow_bot_r.origin_info.db)
  * [`8ab24467b7f56fa8ff0dd334c0588cb196a4d875895abb48afcd33e1e2ba1deb  ./artix7/segbits_clk_hrow_top_r.db`](./artix7/segbits_clk_hrow_top_r.db)
  * [`cf14bb07343da1aede131d701579bcda71a147da4d8cbefa85e8017f2c54225d  ./artix7/segbits_clk_hrow_top_r.origin_info.db`](./artix7/segbits_clk_hrow_top_r.origin_info.db)
- * [`c041f80049a9ff5c173edabd4216b34a98c2236601d39312f0010be0029f0cc6  ./artix7/segbits_cmt_top_l_upper_t.db`](./artix7/segbits_cmt_top_l_upper_t.db)
- * [`934ae1ce7ac907b52facc9c6608564919e9f7811b9b67f7b24df68ca1f86af31  ./artix7/segbits_cmt_top_l_upper_t.origin_info.db`](./artix7/segbits_cmt_top_l_upper_t.origin_info.db)
- * [`ab6513e8e64cac60f33bf52c6d52d4c198b8c61bb8ac63d9a57c6d2f4bbe27d9  ./artix7/segbits_cmt_top_r_upper_t.db`](./artix7/segbits_cmt_top_r_upper_t.db)
- * [`da400f3f15b25a25f26a2b400559677e3e2799dcf809484d283f6731c7109dfc  ./artix7/segbits_cmt_top_r_upper_t.origin_info.db`](./artix7/segbits_cmt_top_r_upper_t.origin_info.db)
+ * [`22657f61814835da3421fc6512b2bf6f09d47f6b7321b17c6ae9c734bea5ba7f  ./artix7/segbits_cmt_top_l_lower_b.db`](./artix7/segbits_cmt_top_l_lower_b.db)
+ * [`0c8b7e872d53ddcd376ce73f04235012be77f94116191480d3ca75fb2444254e  ./artix7/segbits_cmt_top_l_lower_b.origin_info.db`](./artix7/segbits_cmt_top_l_lower_b.origin_info.db)
+ * [`8c385232c1123d062d161054aca2c0089c9f3d89dac37f2fe35cbf18a2bc10a3  ./artix7/segbits_cmt_top_l_upper_t.db`](./artix7/segbits_cmt_top_l_upper_t.db)
+ * [`79e0d3fbf25cee9b675e356ad190b75e7063ded499a0a6155cc6bded3a36046a  ./artix7/segbits_cmt_top_l_upper_t.origin_info.db`](./artix7/segbits_cmt_top_l_upper_t.origin_info.db)
+ * [`17f9b9a6481cc794c029d97ec4972d7559391299ba867db517e89bc694276292  ./artix7/segbits_cmt_top_r_lower_b.db`](./artix7/segbits_cmt_top_r_lower_b.db)
+ * [`07a079152b48a88263859d1b8171c442e6aba82b4394a726e05835171c66f3a4  ./artix7/segbits_cmt_top_r_lower_b.origin_info.db`](./artix7/segbits_cmt_top_r_lower_b.origin_info.db)
+ * [`05dd5d01374a8b40883444d33ea467e5e4363fc329e89402ee9618bde4d6752b  ./artix7/segbits_cmt_top_r_upper_t.db`](./artix7/segbits_cmt_top_r_upper_t.db)
+ * [`1117a583fc1c9265aa6dcea7d32f363dd2c5ebe0e657f3a242c5fb0ceb8555fc  ./artix7/segbits_cmt_top_r_upper_t.origin_info.db`](./artix7/segbits_cmt_top_r_upper_t.origin_info.db)
  * [`0d9f730a1328a61f471c2f6abd98463a39c7e5e70ff557adc6228e1830560c64  ./artix7/segbits_dsp_l.db`](./artix7/segbits_dsp_l.db)
  * [`10a6e47f7b26f0d21cf0a011d4a5f2a4266538bb8d028a07fd981323dc1f0da0  ./artix7/segbits_dsp_l.origin_info.db`](./artix7/segbits_dsp_l.origin_info.db)
  * [`f81459ae1c84e0e73815c4577a7d0b19b497dd7f16029763c3fc4f3b8410dcc2  ./artix7/segbits_dsp_r.db`](./artix7/segbits_dsp_r.db)
@@ -277,25 +281,25 @@
  * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9  ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
  * [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0  ./artix7/segbits_hclk_r.origin_info.db`](./artix7/segbits_hclk_r.origin_info.db)
  * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520  ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
- * [`3703403b01cf027f5f66837720aef0fe62f4b08b630e343832fdd9449cd06521  ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
+ * [`e5b05be3f1e8b2eda6b2614097fd676eb13065d83a01a26b56b26e7beaa1b5fa  ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
  * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556  ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
- * [`6c71a1e60814434e03db08cf5dbdcd7874b71cc0474b9b0df1bfdbecd8a9ea23  ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
+ * [`5375a2f04a1b921b48b8c1566b425c2c7dd73ad361ba1869ea5534bb5a23d5b0  ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
  * [`392e91def4df6eebb3ce5ed15570c01f6090be793a79054e1880549082eb6f23  ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db)
- * [`0fca9c6530589b14c77b738e68c63ed4246713e44e1e699e153b69907e77e09e  ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db)
- * [`78f15c4b7b7ccb486dc5ba8ea02c1703ecd9d5101e22ab173291aeef70d001e3  ./artix7/segbits_lioi3.db`](./artix7/segbits_lioi3.db)
- * [`cdc66476c9896172f5d07d2cda0d63bc945300065e0e8246c95e2a097d960d15  ./artix7/segbits_lioi3.origin_info.db`](./artix7/segbits_lioi3.origin_info.db)
- * [`d6d3d28d3ba48cf7d2dbfa99aef4709eec7b2c2114086ad3ce8286192b4b081d  ./artix7/segbits_lioi3_tbytesrc.db`](./artix7/segbits_lioi3_tbytesrc.db)
- * [`5661c5162cb8d010d74db127d09564333e2986f31719eddad2b17c38c01adce8  ./artix7/segbits_lioi3_tbytesrc.origin_info.db`](./artix7/segbits_lioi3_tbytesrc.origin_info.db)
- * [`13794b0252ab318df174f57875400fb84161125cbc08bbbefbd2d4567d88471c  ./artix7/segbits_lioi3_tbyteterm.db`](./artix7/segbits_lioi3_tbyteterm.db)
- * [`15d28dfc9ab6d93b6269fca88c1fea1d9754f684478bba203340fc806b1d4210  ./artix7/segbits_lioi3_tbyteterm.origin_info.db`](./artix7/segbits_lioi3_tbyteterm.origin_info.db)
+ * [`6ffdf37ae2c6625eed093d59458f3319928bab0ac268abfdeed04c92c4673cfb  ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db)
+ * [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff  ./artix7/segbits_lioi3.db`](./artix7/segbits_lioi3.db)
+ * [`4b1dd698dba50fdf44426b05641189c2faaff29a99d387543d1874983fd68a50  ./artix7/segbits_lioi3.origin_info.db`](./artix7/segbits_lioi3.origin_info.db)
+ * [`0fb3e4c3427cb3fe2426445f9e6ebd1a33a3a5900904f28c7aea339a5f71530e  ./artix7/segbits_lioi3_tbytesrc.db`](./artix7/segbits_lioi3_tbytesrc.db)
+ * [`cbc24997471fa0a4cc59db46589a3daea9f59b4d599ca802a1f62b730090c89c  ./artix7/segbits_lioi3_tbytesrc.origin_info.db`](./artix7/segbits_lioi3_tbytesrc.origin_info.db)
+ * [`e81ad6e17e179647d06b9dc193588c8297af448e8eb7bd6c4b807a832631e07b  ./artix7/segbits_lioi3_tbyteterm.db`](./artix7/segbits_lioi3_tbyteterm.db)
+ * [`bf79280a339e566244220050232020c5d3b8dceed7bd80bcf23da7b4a53cb250  ./artix7/segbits_lioi3_tbyteterm.origin_info.db`](./artix7/segbits_lioi3_tbyteterm.origin_info.db)
  * [`ded5f7b0cdadb7558470dbca9102d7293e4237ecb563b5f69821e01b41e4aad1  ./artix7/segbits_riob33.db`](./artix7/segbits_riob33.db)
- * [`3a62e9a5ca328fd2a6838656759116ab186cb1c50bf4d4e7e3037424bc77903c  ./artix7/segbits_riob33.origin_info.db`](./artix7/segbits_riob33.origin_info.db)
- * [`e0d0d8ca2906e44d446b49afa210920ba715c7e4792a80d9df3aa8a4eebeec82  ./artix7/segbits_rioi3.db`](./artix7/segbits_rioi3.db)
- * [`dcc46ed5d4d72987aea39961fca2c3823ddb3550189492db72d90cadbc12c2fe  ./artix7/segbits_rioi3.origin_info.db`](./artix7/segbits_rioi3.origin_info.db)
- * [`c3c30acc0ebed2068979226fab3ba18c9da9fd306faa40b4778ae0c86d13c42f  ./artix7/segbits_rioi3_tbytesrc.db`](./artix7/segbits_rioi3_tbytesrc.db)
- * [`4ae87ae13dd959bdca6dbac4630f6746fee1d7de31315f4975ca450d7e1226f7  ./artix7/segbits_rioi3_tbytesrc.origin_info.db`](./artix7/segbits_rioi3_tbytesrc.origin_info.db)
- * [`4b23fed56175025c99536a2d27f84f111aad2be905bd6adf63f6c20f0c18835b  ./artix7/segbits_rioi3_tbyteterm.db`](./artix7/segbits_rioi3_tbyteterm.db)
- * [`5d8ea92e462d75025b9f69eb41b039a0ce76637bd274b7ee188f1e2afd349174  ./artix7/segbits_rioi3_tbyteterm.origin_info.db`](./artix7/segbits_rioi3_tbyteterm.origin_info.db)
+ * [`49456622ba534f8a616fe6e8bb0e3006c3ca292f2439f190ef07f82743f09613  ./artix7/segbits_riob33.origin_info.db`](./artix7/segbits_riob33.origin_info.db)
+ * [`712cc4b66ff35ea6033cb76e41d8dde1225857836f4b799834925ab5c3e8575a  ./artix7/segbits_rioi3.db`](./artix7/segbits_rioi3.db)
+ * [`4d0e9719c7016a0dece266060eabf4db7218b6cc982449cb93b87e7b2d0c755b  ./artix7/segbits_rioi3.origin_info.db`](./artix7/segbits_rioi3.origin_info.db)
+ * [`6823106be1cdccae2cf0c1332c7a36ee11a1a86c31376100f16921b6b579ea19  ./artix7/segbits_rioi3_tbytesrc.db`](./artix7/segbits_rioi3_tbytesrc.db)
+ * [`b9865b3e3095be11c76a2666ce8752af7ba8fe9f5e0ae92db786324803ec6e3a  ./artix7/segbits_rioi3_tbytesrc.origin_info.db`](./artix7/segbits_rioi3_tbytesrc.origin_info.db)
+ * [`dcec55e405772728cf8c4dd2d981e76d25e9e3aed5142b5a78164a2959ad4d1a  ./artix7/segbits_rioi3_tbyteterm.db`](./artix7/segbits_rioi3_tbyteterm.db)
+ * [`3f6660e877e33e129233bfc3de090ced8c9895e03b4540068258f3c09a0ce1f4  ./artix7/segbits_rioi3_tbyteterm.origin_info.db`](./artix7/segbits_rioi3_tbyteterm.origin_info.db)
  * [`2bc07bf06b86af1985fe1c76da7bd6d858768dd6d9e99344a3c52d490b797cdb  ./artix7/settings.sh`](./artix7/settings.sh)
  * [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70  ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
  * [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be  ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
@@ -523,49 +527,49 @@
  * [`277906907e43846ac8a52115983cd0ece673b2310d8d10c9b2253d6537bf1a02  ./artix7/xc7a100tcsg324-1/part.json`](./artix7/xc7a100tcsg324-1/part.json)
  * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92  ./artix7/xc7a100tcsg324-1/part.yaml`](./artix7/xc7a100tcsg324-1/part.yaml)
  * [`9cf701615e6f9ed6e89d86738f10ebb9d5bf1a233f1e3251315b2f9159f73391  ./artix7/xc7a100tcsg324-1/tileconn.json`](./artix7/xc7a100tcsg324-1/tileconn.json)
- * [`39cc9858c25af7026cab740cc5eeca7cea3a658cbb56ac2828d68e652dcbcb2e  ./artix7/xc7a100tcsg324-1/tilegrid.json`](./artix7/xc7a100tcsg324-1/tilegrid.json)
+ * [`2557ebae8a5913253e86b213034bcedcd79188f8b32a81b7d0efdd7f2c09e45b  ./artix7/xc7a100tcsg324-1/tilegrid.json`](./artix7/xc7a100tcsg324-1/tilegrid.json)
  * [`bf25d62e58330960eb582f0b3b99196bd59df046db0d7de5330634b64cd397ad  ./artix7/xc7a100tfgg676-1/package_pins.csv`](./artix7/xc7a100tfgg676-1/package_pins.csv)
  * [`78909bda2084de19e6095258ab1b1ad549c2db376abdd8699235a7bdc3aa19fb  ./artix7/xc7a100tfgg676-1/part.json`](./artix7/xc7a100tfgg676-1/part.json)
  * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92  ./artix7/xc7a100tfgg676-1/part.yaml`](./artix7/xc7a100tfgg676-1/part.yaml)
  * [`9cf701615e6f9ed6e89d86738f10ebb9d5bf1a233f1e3251315b2f9159f73391  ./artix7/xc7a100tfgg676-1/tileconn.json`](./artix7/xc7a100tfgg676-1/tileconn.json)
- * [`39cc9858c25af7026cab740cc5eeca7cea3a658cbb56ac2828d68e652dcbcb2e  ./artix7/xc7a100tfgg676-1/tilegrid.json`](./artix7/xc7a100tfgg676-1/tilegrid.json)
+ * [`2557ebae8a5913253e86b213034bcedcd79188f8b32a81b7d0efdd7f2c09e45b  ./artix7/xc7a100tfgg676-1/tilegrid.json`](./artix7/xc7a100tfgg676-1/tilegrid.json)
  * [`72dd638f5c8f6c36e74765915c01b2fa28e3c28b2c0afd91871ab7b0490a14f3  ./artix7/xc7a200tffg1156-1/package_pins.csv`](./artix7/xc7a200tffg1156-1/package_pins.csv)
  * [`fe44ca57c10c7b804357ded2cdea392c008b7b4d5a82ad917fa3148a756e4e42  ./artix7/xc7a200tffg1156-1/part.json`](./artix7/xc7a200tffg1156-1/part.json)
  * [`a3d493aef436b9978b2ed1c98c4e1364ab9eb096f824e19acd7cce3f7d920e97  ./artix7/xc7a200tffg1156-1/part.yaml`](./artix7/xc7a200tffg1156-1/part.yaml)
  * [`bed4bf8553b0faa4a63964100e6b4a8b5f9ac77dbcac474a2d2cbe7240aa4617  ./artix7/xc7a200tffg1156-1/tileconn.json`](./artix7/xc7a200tffg1156-1/tileconn.json)
- * [`204bfabb44bd39ed5341fd7289360b703077bdd41ff649a7594353b1a42d6e18  ./artix7/xc7a200tffg1156-1/tilegrid.json`](./artix7/xc7a200tffg1156-1/tilegrid.json)
+ * [`70c08a33466cd71c2df51405195b67ae2e50e144dd1c7edfa8a464b79bdbe6e9  ./artix7/xc7a200tffg1156-1/tilegrid.json`](./artix7/xc7a200tffg1156-1/tilegrid.json)
  * [`05ee7ad4ee7b7afd4872ab847708778fedbb76f1ebf9d3659fc4c02bd709064a  ./artix7/xc7a200tsbg484-1/package_pins.csv`](./artix7/xc7a200tsbg484-1/package_pins.csv)
  * [`3261e1163801969f3bfa443040729d1b19a7f5f71c96263e582ffdc0e67b3aa4  ./artix7/xc7a200tsbg484-1/part.json`](./artix7/xc7a200tsbg484-1/part.json)
  * [`a3d493aef436b9978b2ed1c98c4e1364ab9eb096f824e19acd7cce3f7d920e97  ./artix7/xc7a200tsbg484-1/part.yaml`](./artix7/xc7a200tsbg484-1/part.yaml)
  * [`bed4bf8553b0faa4a63964100e6b4a8b5f9ac77dbcac474a2d2cbe7240aa4617  ./artix7/xc7a200tsbg484-1/tileconn.json`](./artix7/xc7a200tsbg484-1/tileconn.json)
- * [`204bfabb44bd39ed5341fd7289360b703077bdd41ff649a7594353b1a42d6e18  ./artix7/xc7a200tsbg484-1/tilegrid.json`](./artix7/xc7a200tsbg484-1/tilegrid.json)
+ * [`70c08a33466cd71c2df51405195b67ae2e50e144dd1c7edfa8a464b79bdbe6e9  ./artix7/xc7a200tsbg484-1/tilegrid.json`](./artix7/xc7a200tsbg484-1/tilegrid.json)
  * [`89d8d472bad8232a422a5d52f6dec96215269aad78a16281ed7d2f9cc71e3a71  ./artix7/xc7a35tcpg236-1/package_pins.csv`](./artix7/xc7a35tcpg236-1/package_pins.csv)
  * [`be8a8ab158cf85d4135c64a54577412cc1a99833c11ce331a303d90425b673f2  ./artix7/xc7a35tcpg236-1/part.json`](./artix7/xc7a35tcpg236-1/part.json)
  * [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d  ./artix7/xc7a35tcpg236-1/part.yaml`](./artix7/xc7a35tcpg236-1/part.yaml)
  * [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b  ./artix7/xc7a35tcpg236-1/tileconn.json`](./artix7/xc7a35tcpg236-1/tileconn.json)
- * [`9def36c3beb0d370335743a8225684f6148010574487c93ffb531aecd9e935b1  ./artix7/xc7a35tcpg236-1/tilegrid.json`](./artix7/xc7a35tcpg236-1/tilegrid.json)
+ * [`c2349cde3037918cfe29ea3dc4605c40d7276b83558fb072627d0ad164759598  ./artix7/xc7a35tcpg236-1/tilegrid.json`](./artix7/xc7a35tcpg236-1/tilegrid.json)
  * [`d656d80d3969b020050190034ddb573a320eeba76733b9fb850479902bb7b5c1  ./artix7/xc7a35tcsg324-1/package_pins.csv`](./artix7/xc7a35tcsg324-1/package_pins.csv)
  * [`dc3987e61a543697837430bf83d554726d0cf65e33dbcd69c395edee36c8273d  ./artix7/xc7a35tcsg324-1/part.json`](./artix7/xc7a35tcsg324-1/part.json)
  * [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d  ./artix7/xc7a35tcsg324-1/part.yaml`](./artix7/xc7a35tcsg324-1/part.yaml)
  * [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b  ./artix7/xc7a35tcsg324-1/tileconn.json`](./artix7/xc7a35tcsg324-1/tileconn.json)
- * [`9def36c3beb0d370335743a8225684f6148010574487c93ffb531aecd9e935b1  ./artix7/xc7a35tcsg324-1/tilegrid.json`](./artix7/xc7a35tcsg324-1/tilegrid.json)
+ * [`c2349cde3037918cfe29ea3dc4605c40d7276b83558fb072627d0ad164759598  ./artix7/xc7a35tcsg324-1/tilegrid.json`](./artix7/xc7a35tcsg324-1/tilegrid.json)
  * [`48c715243411156182302fe04f461e6605d4f2008a4fb8fc40c7fa73948c2f2d  ./artix7/xc7a35tftg256-1/package_pins.csv`](./artix7/xc7a35tftg256-1/package_pins.csv)
  * [`56434a2445f9a972c7e8e10ec09955d4a273a81d00d67ee614af70acda4a8ea0  ./artix7/xc7a35tftg256-1/part.json`](./artix7/xc7a35tftg256-1/part.json)
  * [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d  ./artix7/xc7a35tftg256-1/part.yaml`](./artix7/xc7a35tftg256-1/part.yaml)
  * [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b  ./artix7/xc7a35tftg256-1/tileconn.json`](./artix7/xc7a35tftg256-1/tileconn.json)
- * [`9def36c3beb0d370335743a8225684f6148010574487c93ffb531aecd9e935b1  ./artix7/xc7a35tftg256-1/tilegrid.json`](./artix7/xc7a35tftg256-1/tilegrid.json)
+ * [`c2349cde3037918cfe29ea3dc4605c40d7276b83558fb072627d0ad164759598  ./artix7/xc7a35tftg256-1/tilegrid.json`](./artix7/xc7a35tftg256-1/tilegrid.json)
  * [`1b01a06e9bae479981698cdb89fff971c825c75266b3b529cd69cd54815ce805  ./artix7/xc7a50tfgg484-1/package_pins.csv`](./artix7/xc7a50tfgg484-1/package_pins.csv)
  * [`6f58dc1e7f454bb28592ecfc9b343541283593d596dba555d0088d0bff9ca1ae  ./artix7/xc7a50tfgg484-1/part.json`](./artix7/xc7a50tfgg484-1/part.json)
  * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3  ./artix7/xc7a50tfgg484-1/part.yaml`](./artix7/xc7a50tfgg484-1/part.yaml)
  * [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b  ./artix7/xc7a50tfgg484-1/tileconn.json`](./artix7/xc7a50tfgg484-1/tileconn.json)
- * [`9def36c3beb0d370335743a8225684f6148010574487c93ffb531aecd9e935b1  ./artix7/xc7a50tfgg484-1/tilegrid.json`](./artix7/xc7a50tfgg484-1/tilegrid.json)
+ * [`c2349cde3037918cfe29ea3dc4605c40d7276b83558fb072627d0ad164759598  ./artix7/xc7a50tfgg484-1/tilegrid.json`](./artix7/xc7a50tfgg484-1/tilegrid.json)
 
 
 ## Database for [kintex7](kintex7/)
 
 ### Settings
 
-Created using following [settings/kintex7.sh (sha256: 8c4c506cbdc6a25696436bbe6359e3617c82a11931ad6e406a1c433b263527c4)](https://github.com/SymbiFlow/prjxray/blob/0339695c0d30a5e10119705102f51e9443c5f28c/settings/kintex7.sh)
+Created using following [settings/kintex7.sh (sha256: 8c4c506cbdc6a25696436bbe6359e3617c82a11931ad6e406a1c433b263527c4)](https://github.com/SymbiFlow/prjxray/blob/34043d1b3d2a420cb581a89ddd3b30203fa918ac/settings/kintex7.sh)
 ```shell
 # Copyright (C) 2017-2020  The Project X-Ray Authors.
 #
@@ -644,13 +648,13 @@
  * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd  ./kintex7/mask_hclk_r.db`](./kintex7/mask_hclk_r.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./kintex7/mask_hclk_r.origin_info.db`](./kintex7/mask_hclk_r.origin_info.db)
  * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./kintex7/mask_liob33.db`](./kintex7/mask_liob33.db)
- * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./kintex7/mask_lioi3.db`](./kintex7/mask_lioi3.db)
- * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./kintex7/mask_lioi3_tbytesrc.db`](./kintex7/mask_lioi3_tbytesrc.db)
- * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./kintex7/mask_lioi3_tbyteterm.db`](./kintex7/mask_lioi3_tbyteterm.db)
+ * [`919dd02f5275750fd8bc8ace4707ecd94f1fad7deb8c67879894c0b7d6a8ae2f  ./kintex7/mask_lioi3.db`](./kintex7/mask_lioi3.db)
+ * [`919dd02f5275750fd8bc8ace4707ecd94f1fad7deb8c67879894c0b7d6a8ae2f  ./kintex7/mask_lioi3_tbytesrc.db`](./kintex7/mask_lioi3_tbytesrc.db)
+ * [`919dd02f5275750fd8bc8ace4707ecd94f1fad7deb8c67879894c0b7d6a8ae2f  ./kintex7/mask_lioi3_tbyteterm.db`](./kintex7/mask_lioi3_tbyteterm.db)
  * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./kintex7/mask_riob33.db`](./kintex7/mask_riob33.db)
- * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./kintex7/mask_rioi3.db`](./kintex7/mask_rioi3.db)
- * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./kintex7/mask_rioi3_tbytesrc.db`](./kintex7/mask_rioi3_tbytesrc.db)
- * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./kintex7/mask_rioi3_tbyteterm.db`](./kintex7/mask_rioi3_tbyteterm.db)
+ * [`919dd02f5275750fd8bc8ace4707ecd94f1fad7deb8c67879894c0b7d6a8ae2f  ./kintex7/mask_rioi3.db`](./kintex7/mask_rioi3.db)
+ * [`919dd02f5275750fd8bc8ace4707ecd94f1fad7deb8c67879894c0b7d6a8ae2f  ./kintex7/mask_rioi3_tbytesrc.db`](./kintex7/mask_rioi3_tbytesrc.db)
+ * [`919dd02f5275750fd8bc8ace4707ecd94f1fad7deb8c67879894c0b7d6a8ae2f  ./kintex7/mask_rioi3_tbyteterm.db`](./kintex7/mask_rioi3_tbyteterm.db)
  * [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf  ./kintex7/ppips_bram_int_interface_l.db`](./kintex7/ppips_bram_int_interface_l.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./kintex7/ppips_bram_int_interface_l.origin_info.db`](./kintex7/ppips_bram_int_interface_l.origin_info.db)
  * [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae  ./kintex7/ppips_bram_int_interface_r.db`](./kintex7/ppips_bram_int_interface_r.db)
@@ -721,19 +725,23 @@
  * [`3ddfeca1b01bdc04b4f1b3d0dc73cf39f4230708fbbcb5b6170d5b50dc49ad64  ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db)
  * [`24bc3e7052d683b896e273210cf626e7544b34b7829508b8c4ad178926307e5e  ./kintex7/segbits_clblm_r.origin_info.db`](./kintex7/segbits_clblm_r.origin_info.db)
  * [`8d43bd09b2f7127ff9ed4803b92303d72c827d10b8b8d943c295343257b3e818  ./kintex7/segbits_clk_bufg_bot_r.db`](./kintex7/segbits_clk_bufg_bot_r.db)
- * [`a0ed10aa1039af4dce795a1c48cb1c908d845727be480b34b68084b7220fd94e  ./kintex7/segbits_clk_bufg_bot_r.origin_info.db`](./kintex7/segbits_clk_bufg_bot_r.origin_info.db)
+ * [`9abfcf14a91347582e92eec78e43fb3ff51f522d452bf1658f7655348a5df5d2  ./kintex7/segbits_clk_bufg_bot_r.origin_info.db`](./kintex7/segbits_clk_bufg_bot_r.origin_info.db)
  * [`d094c55a62408bd79c2606a8fc10839b23d979e4e924ced0d4276d285db7810f  ./kintex7/segbits_clk_bufg_rebuf.db`](./kintex7/segbits_clk_bufg_rebuf.db)
  * [`129662c05faf1ed9e12c7dd850c2b8753453c64d18750bbfc18324e1f0dcf4ef  ./kintex7/segbits_clk_bufg_rebuf.origin_info.db`](./kintex7/segbits_clk_bufg_rebuf.origin_info.db)
  * [`6da9671e724a74e370b805ddd47e04eefd89daa0af4331e841720f7586d7eb2a  ./kintex7/segbits_clk_bufg_top_r.db`](./kintex7/segbits_clk_bufg_top_r.db)
- * [`1efb8d63a68a6a920f912e158bbb2f511498f184f53c0f88e0d9a6bcdbcf8da3  ./kintex7/segbits_clk_bufg_top_r.origin_info.db`](./kintex7/segbits_clk_bufg_top_r.origin_info.db)
+ * [`2f0d0b9c95989ea190fff37c6111f53884394afc506aa059d9d4fc831e952a43  ./kintex7/segbits_clk_bufg_top_r.origin_info.db`](./kintex7/segbits_clk_bufg_top_r.origin_info.db)
  * [`5b22e19775dfa493f75bb3edbfccc06709a50b829e89857dc20aee1cbc8f6794  ./kintex7/segbits_clk_hrow_bot_r.db`](./kintex7/segbits_clk_hrow_bot_r.db)
  * [`cf71a4438ae35cb2493b614e895e3d5cf577613a8d9c10cf1c566872a2ea9b4f  ./kintex7/segbits_clk_hrow_bot_r.origin_info.db`](./kintex7/segbits_clk_hrow_bot_r.origin_info.db)
  * [`89ca5e5d4e9bc222815bd81e6d94cbff6950b99e3d2e80ac677334dcde40e4c2  ./kintex7/segbits_clk_hrow_top_r.db`](./kintex7/segbits_clk_hrow_top_r.db)
  * [`b9a1e70499c2597a6ae2381d3ab47780f2a69430073c87f2b639901d1f563e65  ./kintex7/segbits_clk_hrow_top_r.origin_info.db`](./kintex7/segbits_clk_hrow_top_r.origin_info.db)
- * [`472ee93385729d9b8615794d907ddd7ca757955c36eba4ead583a89c960c8688  ./kintex7/segbits_cmt_top_l_upper_t.db`](./kintex7/segbits_cmt_top_l_upper_t.db)
- * [`0299f92a761a2c651751fc40e8e7aec9c27876b904c9e5f823be1eb00596557e  ./kintex7/segbits_cmt_top_l_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_l_upper_t.origin_info.db)
- * [`712a8f426c47b5d02483404d8e7bfd816a26a99787c82b01966b9f04fbd28b87  ./kintex7/segbits_cmt_top_r_upper_t.db`](./kintex7/segbits_cmt_top_r_upper_t.db)
- * [`592e2a9143a8502f9f41c727439bddd59a04c0572adf538d2af4a37570bcb192  ./kintex7/segbits_cmt_top_r_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_r_upper_t.origin_info.db)
+ * [`22657f61814835da3421fc6512b2bf6f09d47f6b7321b17c6ae9c734bea5ba7f  ./kintex7/segbits_cmt_top_l_lower_b.db`](./kintex7/segbits_cmt_top_l_lower_b.db)
+ * [`0c8b7e872d53ddcd376ce73f04235012be77f94116191480d3ca75fb2444254e  ./kintex7/segbits_cmt_top_l_lower_b.origin_info.db`](./kintex7/segbits_cmt_top_l_lower_b.origin_info.db)
+ * [`3e33276e75c69bf622e1019c4bf4b8cf3f7bb8bebcdd500f16e160b49e5a6811  ./kintex7/segbits_cmt_top_l_upper_t.db`](./kintex7/segbits_cmt_top_l_upper_t.db)
+ * [`a8ba9d40de847f2175429ab3328c585242372124e499a520af2a2d8fb97d1550  ./kintex7/segbits_cmt_top_l_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_l_upper_t.origin_info.db)
+ * [`17f9b9a6481cc794c029d97ec4972d7559391299ba867db517e89bc694276292  ./kintex7/segbits_cmt_top_r_lower_b.db`](./kintex7/segbits_cmt_top_r_lower_b.db)
+ * [`07a079152b48a88263859d1b8171c442e6aba82b4394a726e05835171c66f3a4  ./kintex7/segbits_cmt_top_r_lower_b.origin_info.db`](./kintex7/segbits_cmt_top_r_lower_b.origin_info.db)
+ * [`ff3f5ed631016fb97d2e949d02b6a4eda93b5291a14b43cda962a93eeed88894  ./kintex7/segbits_cmt_top_r_upper_t.db`](./kintex7/segbits_cmt_top_r_upper_t.db)
+ * [`a6ea0f1abacda03e873459b43b5fda477a027904533d9bff94c0763bc2e30cef  ./kintex7/segbits_cmt_top_r_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_r_upper_t.origin_info.db)
  * [`0d9f730a1328a61f471c2f6abd98463a39c7e5e70ff557adc6228e1830560c64  ./kintex7/segbits_dsp_l.db`](./kintex7/segbits_dsp_l.db)
  * [`10a6e47f7b26f0d21cf0a011d4a5f2a4266538bb8d028a07fd981323dc1f0da0  ./kintex7/segbits_dsp_l.origin_info.db`](./kintex7/segbits_dsp_l.origin_info.db)
  * [`f81459ae1c84e0e73815c4577a7d0b19b497dd7f16029763c3fc4f3b8410dcc2  ./kintex7/segbits_dsp_r.db`](./kintex7/segbits_dsp_r.db)
@@ -749,25 +757,25 @@
  * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9  ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db)
  * [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0  ./kintex7/segbits_hclk_r.origin_info.db`](./kintex7/segbits_hclk_r.origin_info.db)
  * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520  ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
- * [`096b8bf4f2b685fa364309e2f54ce34d8e961409dc08205ad1b4f395357bd057  ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
+ * [`444e7917ce354b011c3ecdb98b8785f1edf99770d9cad27fc89e9d1f9cd22eb5  ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
  * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556  ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
- * [`d299c5ae6e9e46b8e62630cc12432a1d7b1b2213d21ccaaebc759083fa37a364  ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
+ * [`61eb508ad94dd35a33d9b91a4c667349b01107cd3e533928eefd8a312bf31ac0  ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
  * [`392e91def4df6eebb3ce5ed15570c01f6090be793a79054e1880549082eb6f23  ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db)
- * [`0fca9c6530589b14c77b738e68c63ed4246713e44e1e699e153b69907e77e09e  ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db)
- * [`78f15c4b7b7ccb486dc5ba8ea02c1703ecd9d5101e22ab173291aeef70d001e3  ./kintex7/segbits_lioi3.db`](./kintex7/segbits_lioi3.db)
- * [`cdc66476c9896172f5d07d2cda0d63bc945300065e0e8246c95e2a097d960d15  ./kintex7/segbits_lioi3.origin_info.db`](./kintex7/segbits_lioi3.origin_info.db)
- * [`d6d3d28d3ba48cf7d2dbfa99aef4709eec7b2c2114086ad3ce8286192b4b081d  ./kintex7/segbits_lioi3_tbytesrc.db`](./kintex7/segbits_lioi3_tbytesrc.db)
- * [`5661c5162cb8d010d74db127d09564333e2986f31719eddad2b17c38c01adce8  ./kintex7/segbits_lioi3_tbytesrc.origin_info.db`](./kintex7/segbits_lioi3_tbytesrc.origin_info.db)
- * [`13794b0252ab318df174f57875400fb84161125cbc08bbbefbd2d4567d88471c  ./kintex7/segbits_lioi3_tbyteterm.db`](./kintex7/segbits_lioi3_tbyteterm.db)
- * [`15d28dfc9ab6d93b6269fca88c1fea1d9754f684478bba203340fc806b1d4210  ./kintex7/segbits_lioi3_tbyteterm.origin_info.db`](./kintex7/segbits_lioi3_tbyteterm.origin_info.db)
+ * [`6ffdf37ae2c6625eed093d59458f3319928bab0ac268abfdeed04c92c4673cfb  ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db)
+ * [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff  ./kintex7/segbits_lioi3.db`](./kintex7/segbits_lioi3.db)
+ * [`4b1dd698dba50fdf44426b05641189c2faaff29a99d387543d1874983fd68a50  ./kintex7/segbits_lioi3.origin_info.db`](./kintex7/segbits_lioi3.origin_info.db)
+ * [`0fb3e4c3427cb3fe2426445f9e6ebd1a33a3a5900904f28c7aea339a5f71530e  ./kintex7/segbits_lioi3_tbytesrc.db`](./kintex7/segbits_lioi3_tbytesrc.db)
+ * [`cbc24997471fa0a4cc59db46589a3daea9f59b4d599ca802a1f62b730090c89c  ./kintex7/segbits_lioi3_tbytesrc.origin_info.db`](./kintex7/segbits_lioi3_tbytesrc.origin_info.db)
+ * [`e81ad6e17e179647d06b9dc193588c8297af448e8eb7bd6c4b807a832631e07b  ./kintex7/segbits_lioi3_tbyteterm.db`](./kintex7/segbits_lioi3_tbyteterm.db)
+ * [`bf79280a339e566244220050232020c5d3b8dceed7bd80bcf23da7b4a53cb250  ./kintex7/segbits_lioi3_tbyteterm.origin_info.db`](./kintex7/segbits_lioi3_tbyteterm.origin_info.db)
  * [`ded5f7b0cdadb7558470dbca9102d7293e4237ecb563b5f69821e01b41e4aad1  ./kintex7/segbits_riob33.db`](./kintex7/segbits_riob33.db)
- * [`3a62e9a5ca328fd2a6838656759116ab186cb1c50bf4d4e7e3037424bc77903c  ./kintex7/segbits_riob33.origin_info.db`](./kintex7/segbits_riob33.origin_info.db)
- * [`e0d0d8ca2906e44d446b49afa210920ba715c7e4792a80d9df3aa8a4eebeec82  ./kintex7/segbits_rioi3.db`](./kintex7/segbits_rioi3.db)
- * [`dcc46ed5d4d72987aea39961fca2c3823ddb3550189492db72d90cadbc12c2fe  ./kintex7/segbits_rioi3.origin_info.db`](./kintex7/segbits_rioi3.origin_info.db)
- * [`c3c30acc0ebed2068979226fab3ba18c9da9fd306faa40b4778ae0c86d13c42f  ./kintex7/segbits_rioi3_tbytesrc.db`](./kintex7/segbits_rioi3_tbytesrc.db)
- * [`4ae87ae13dd959bdca6dbac4630f6746fee1d7de31315f4975ca450d7e1226f7  ./kintex7/segbits_rioi3_tbytesrc.origin_info.db`](./kintex7/segbits_rioi3_tbytesrc.origin_info.db)
- * [`4b23fed56175025c99536a2d27f84f111aad2be905bd6adf63f6c20f0c18835b  ./kintex7/segbits_rioi3_tbyteterm.db`](./kintex7/segbits_rioi3_tbyteterm.db)
- * [`5d8ea92e462d75025b9f69eb41b039a0ce76637bd274b7ee188f1e2afd349174  ./kintex7/segbits_rioi3_tbyteterm.origin_info.db`](./kintex7/segbits_rioi3_tbyteterm.origin_info.db)
+ * [`49456622ba534f8a616fe6e8bb0e3006c3ca292f2439f190ef07f82743f09613  ./kintex7/segbits_riob33.origin_info.db`](./kintex7/segbits_riob33.origin_info.db)
+ * [`712cc4b66ff35ea6033cb76e41d8dde1225857836f4b799834925ab5c3e8575a  ./kintex7/segbits_rioi3.db`](./kintex7/segbits_rioi3.db)
+ * [`4d0e9719c7016a0dece266060eabf4db7218b6cc982449cb93b87e7b2d0c755b  ./kintex7/segbits_rioi3.origin_info.db`](./kintex7/segbits_rioi3.origin_info.db)
+ * [`6823106be1cdccae2cf0c1332c7a36ee11a1a86c31376100f16921b6b579ea19  ./kintex7/segbits_rioi3_tbytesrc.db`](./kintex7/segbits_rioi3_tbytesrc.db)
+ * [`b9865b3e3095be11c76a2666ce8752af7ba8fe9f5e0ae92db786324803ec6e3a  ./kintex7/segbits_rioi3_tbytesrc.origin_info.db`](./kintex7/segbits_rioi3_tbytesrc.origin_info.db)
+ * [`dcec55e405772728cf8c4dd2d981e76d25e9e3aed5142b5a78164a2959ad4d1a  ./kintex7/segbits_rioi3_tbyteterm.db`](./kintex7/segbits_rioi3_tbyteterm.db)
+ * [`3f6660e877e33e129233bfc3de090ced8c9895e03b4540068258f3c09a0ce1f4  ./kintex7/segbits_rioi3_tbyteterm.origin_info.db`](./kintex7/segbits_rioi3_tbyteterm.origin_info.db)
  * [`c4fe49753a5ba6b4abc688337d5df26f2101ccfca3dd4270ca77e39e5221bfe9  ./kintex7/settings.sh`](./kintex7/settings.sh)
  * [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70  ./kintex7/site_type_BSCAN.json`](./kintex7/site_type_BSCAN.json)
  * [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be  ./kintex7/site_type_BUFGCTRL.json`](./kintex7/site_type_BUFGCTRL.json)
@@ -937,14 +945,14 @@
  * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966  ./kintex7/xc7k70tfbg676-2/part.json`](./kintex7/xc7k70tfbg676-2/part.json)
  * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38  ./kintex7/xc7k70tfbg676-2/part.yaml`](./kintex7/xc7k70tfbg676-2/part.yaml)
  * [`77985c4643b2984db517096deb4fc80ae992794089aea91c21b456d81fcbadd2  ./kintex7/xc7k70tfbg676-2/tileconn.json`](./kintex7/xc7k70tfbg676-2/tileconn.json)
- * [`5e8ec1f7c1eac004ad284119127fd21c52c57cd22f7dd91b15767e0dbf5239ce  ./kintex7/xc7k70tfbg676-2/tilegrid.json`](./kintex7/xc7k70tfbg676-2/tilegrid.json)
+ * [`ad68c3cb4cac3846e55da96ab182a829a52372269a6a9b50c539e47252b66279  ./kintex7/xc7k70tfbg676-2/tilegrid.json`](./kintex7/xc7k70tfbg676-2/tilegrid.json)
 
 
 ## Database for [zynq7](zynq7/)
 
 ### Settings
 
-Created using following [settings/zynq7.sh (sha256: 790d0886285b195daff0950f82ddb42635257c7c6400dcc5c7fb5b13f66ee6ba)](https://github.com/SymbiFlow/prjxray/blob/0339695c0d30a5e10119705102f51e9443c5f28c/settings/zynq7.sh)
+Created using following [settings/zynq7.sh (sha256: 790d0886285b195daff0950f82ddb42635257c7c6400dcc5c7fb5b13f66ee6ba)](https://github.com/SymbiFlow/prjxray/blob/34043d1b3d2a420cb581a89ddd3b30203fa918ac/settings/zynq7.sh)
 ```shell
 # Copyright (C) 2017-2020  The Project X-Ray Authors.
 #
@@ -1000,13 +1008,13 @@
  * [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d  ./zynq7/mask_bram_r.block_ram.db`](./zynq7/mask_bram_r.block_ram.db)
  * [`bd011fe1a63f4f35366b266b6f3e1557fc021754e684e97cc2704f29f307e50c  ./zynq7/mask_bram_r.db`](./zynq7/mask_bram_r.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./zynq7/mask_bram_r.origin_info.db`](./zynq7/mask_bram_r.origin_info.db)
- * [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7  ./zynq7/mask_clbll_l.db`](./zynq7/mask_clbll_l.db)
+ * [`dae6bd639ae3cf0ddb9bbdf78e7d5f79bb9971573fa84d0a8c071bac79555120  ./zynq7/mask_clbll_l.db`](./zynq7/mask_clbll_l.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./zynq7/mask_clbll_l.origin_info.db`](./zynq7/mask_clbll_l.origin_info.db)
- * [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7  ./zynq7/mask_clbll_r.db`](./zynq7/mask_clbll_r.db)
+ * [`dae6bd639ae3cf0ddb9bbdf78e7d5f79bb9971573fa84d0a8c071bac79555120  ./zynq7/mask_clbll_r.db`](./zynq7/mask_clbll_r.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./zynq7/mask_clbll_r.origin_info.db`](./zynq7/mask_clbll_r.origin_info.db)
- * [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b  ./zynq7/mask_clblm_l.db`](./zynq7/mask_clblm_l.db)
+ * [`a26c1eb79e1fbacc8dd1401cbd27dfdc27988d59c969fddb59f1489a38e348de  ./zynq7/mask_clblm_l.db`](./zynq7/mask_clblm_l.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./zynq7/mask_clblm_l.origin_info.db`](./zynq7/mask_clblm_l.origin_info.db)
- * [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b  ./zynq7/mask_clblm_r.db`](./zynq7/mask_clblm_r.db)
+ * [`a26c1eb79e1fbacc8dd1401cbd27dfdc27988d59c969fddb59f1489a38e348de  ./zynq7/mask_clblm_r.db`](./zynq7/mask_clblm_r.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./zynq7/mask_clblm_r.origin_info.db`](./zynq7/mask_clblm_r.origin_info.db)
  * [`9c35071320dd49be8a4820964b462a13945ca1fe88fd50daf59dd299b81233b3  ./zynq7/mask_clk_bufg_bot_r.db`](./zynq7/mask_clk_bufg_bot_r.db)
  * [`fab582dba708b87f84b7d493cfc738317201a90cdf73a438a753f7512eee7dea  ./zynq7/mask_clk_bufg_rebuf.db`](./zynq7/mask_clk_bufg_rebuf.db)
@@ -1026,13 +1034,13 @@
  * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd  ./zynq7/mask_hclk_r.db`](./zynq7/mask_hclk_r.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./zynq7/mask_hclk_r.origin_info.db`](./zynq7/mask_hclk_r.origin_info.db)
  * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./zynq7/mask_liob33.db`](./zynq7/mask_liob33.db)
- * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./zynq7/mask_lioi3.db`](./zynq7/mask_lioi3.db)
- * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./zynq7/mask_lioi3_tbytesrc.db`](./zynq7/mask_lioi3_tbytesrc.db)
- * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./zynq7/mask_lioi3_tbyteterm.db`](./zynq7/mask_lioi3_tbyteterm.db)
+ * [`04905dcedfe5b075d28c7ca2af92f4c3b9677675fc27d64813c43b8569f493ae  ./zynq7/mask_lioi3.db`](./zynq7/mask_lioi3.db)
+ * [`04905dcedfe5b075d28c7ca2af92f4c3b9677675fc27d64813c43b8569f493ae  ./zynq7/mask_lioi3_tbytesrc.db`](./zynq7/mask_lioi3_tbytesrc.db)
+ * [`04905dcedfe5b075d28c7ca2af92f4c3b9677675fc27d64813c43b8569f493ae  ./zynq7/mask_lioi3_tbyteterm.db`](./zynq7/mask_lioi3_tbyteterm.db)
  * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./zynq7/mask_riob33.db`](./zynq7/mask_riob33.db)
- * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./zynq7/mask_rioi3.db`](./zynq7/mask_rioi3.db)
- * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./zynq7/mask_rioi3_tbytesrc.db`](./zynq7/mask_rioi3_tbytesrc.db)
- * [`e189322ecc5395aaff1b7100fc3ef5f259b7f1425a05a4464835eacc509a2576  ./zynq7/mask_rioi3_tbyteterm.db`](./zynq7/mask_rioi3_tbyteterm.db)
+ * [`04905dcedfe5b075d28c7ca2af92f4c3b9677675fc27d64813c43b8569f493ae  ./zynq7/mask_rioi3.db`](./zynq7/mask_rioi3.db)
+ * [`04905dcedfe5b075d28c7ca2af92f4c3b9677675fc27d64813c43b8569f493ae  ./zynq7/mask_rioi3_tbytesrc.db`](./zynq7/mask_rioi3_tbytesrc.db)
+ * [`04905dcedfe5b075d28c7ca2af92f4c3b9677675fc27d64813c43b8569f493ae  ./zynq7/mask_rioi3_tbyteterm.db`](./zynq7/mask_rioi3_tbyteterm.db)
  * [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf  ./zynq7/ppips_bram_int_interface_l.db`](./zynq7/ppips_bram_int_interface_l.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./zynq7/ppips_bram_int_interface_l.origin_info.db`](./zynq7/ppips_bram_int_interface_l.origin_info.db)
  * [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae  ./zynq7/ppips_bram_int_interface_r.db`](./zynq7/ppips_bram_int_interface_r.db)
@@ -1114,19 +1122,23 @@
  * [`3ddfeca1b01bdc04b4f1b3d0dc73cf39f4230708fbbcb5b6170d5b50dc49ad64  ./zynq7/segbits_clblm_r.db`](./zynq7/segbits_clblm_r.db)
  * [`24bc3e7052d683b896e273210cf626e7544b34b7829508b8c4ad178926307e5e  ./zynq7/segbits_clblm_r.origin_info.db`](./zynq7/segbits_clblm_r.origin_info.db)
  * [`8d43bd09b2f7127ff9ed4803b92303d72c827d10b8b8d943c295343257b3e818  ./zynq7/segbits_clk_bufg_bot_r.db`](./zynq7/segbits_clk_bufg_bot_r.db)
- * [`a0ed10aa1039af4dce795a1c48cb1c908d845727be480b34b68084b7220fd94e  ./zynq7/segbits_clk_bufg_bot_r.origin_info.db`](./zynq7/segbits_clk_bufg_bot_r.origin_info.db)
+ * [`9abfcf14a91347582e92eec78e43fb3ff51f522d452bf1658f7655348a5df5d2  ./zynq7/segbits_clk_bufg_bot_r.origin_info.db`](./zynq7/segbits_clk_bufg_bot_r.origin_info.db)
  * [`d094c55a62408bd79c2606a8fc10839b23d979e4e924ced0d4276d285db7810f  ./zynq7/segbits_clk_bufg_rebuf.db`](./zynq7/segbits_clk_bufg_rebuf.db)
  * [`129662c05faf1ed9e12c7dd850c2b8753453c64d18750bbfc18324e1f0dcf4ef  ./zynq7/segbits_clk_bufg_rebuf.origin_info.db`](./zynq7/segbits_clk_bufg_rebuf.origin_info.db)
  * [`6da9671e724a74e370b805ddd47e04eefd89daa0af4331e841720f7586d7eb2a  ./zynq7/segbits_clk_bufg_top_r.db`](./zynq7/segbits_clk_bufg_top_r.db)
- * [`1efb8d63a68a6a920f912e158bbb2f511498f184f53c0f88e0d9a6bcdbcf8da3  ./zynq7/segbits_clk_bufg_top_r.origin_info.db`](./zynq7/segbits_clk_bufg_top_r.origin_info.db)
+ * [`2f0d0b9c95989ea190fff37c6111f53884394afc506aa059d9d4fc831e952a43  ./zynq7/segbits_clk_bufg_top_r.origin_info.db`](./zynq7/segbits_clk_bufg_top_r.origin_info.db)
  * [`dc4fc20f5ffdddefde25b7490dfc03d4b19785de3b8d2dc3ab7a02107eb5ab26  ./zynq7/segbits_clk_hrow_bot_r.db`](./zynq7/segbits_clk_hrow_bot_r.db)
  * [`c913b6c8399b21d515063a9eba05749e06fcdb24fc40d7a4e1e009e91d7b9c02  ./zynq7/segbits_clk_hrow_bot_r.origin_info.db`](./zynq7/segbits_clk_hrow_bot_r.origin_info.db)
  * [`4c9c9effdaa6039eaa0df3c44056be0ceeaa1a34eab9134821f9f3e85f46738c  ./zynq7/segbits_clk_hrow_top_r.db`](./zynq7/segbits_clk_hrow_top_r.db)
  * [`dce4badb8750dc9ddf3db28e818df81abf4f2258c189891c35a427616c0cfc71  ./zynq7/segbits_clk_hrow_top_r.origin_info.db`](./zynq7/segbits_clk_hrow_top_r.origin_info.db)
- * [`472ee93385729d9b8615794d907ddd7ca757955c36eba4ead583a89c960c8688  ./zynq7/segbits_cmt_top_l_upper_t.db`](./zynq7/segbits_cmt_top_l_upper_t.db)
- * [`0299f92a761a2c651751fc40e8e7aec9c27876b904c9e5f823be1eb00596557e  ./zynq7/segbits_cmt_top_l_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_l_upper_t.origin_info.db)
- * [`712a8f426c47b5d02483404d8e7bfd816a26a99787c82b01966b9f04fbd28b87  ./zynq7/segbits_cmt_top_r_upper_t.db`](./zynq7/segbits_cmt_top_r_upper_t.db)
- * [`592e2a9143a8502f9f41c727439bddd59a04c0572adf538d2af4a37570bcb192  ./zynq7/segbits_cmt_top_r_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_r_upper_t.origin_info.db)
+ * [`e88ef40aabfa37d6d5f1b3ee154144d42501a3f7da29879b34160228870eb59c  ./zynq7/segbits_cmt_top_l_lower_b.db`](./zynq7/segbits_cmt_top_l_lower_b.db)
+ * [`56c1a463b24602f9e0c66e66491a74f753b4382346db0e99a60722a22bc24e13  ./zynq7/segbits_cmt_top_l_lower_b.origin_info.db`](./zynq7/segbits_cmt_top_l_lower_b.origin_info.db)
+ * [`3e33276e75c69bf622e1019c4bf4b8cf3f7bb8bebcdd500f16e160b49e5a6811  ./zynq7/segbits_cmt_top_l_upper_t.db`](./zynq7/segbits_cmt_top_l_upper_t.db)
+ * [`a8ba9d40de847f2175429ab3328c585242372124e499a520af2a2d8fb97d1550  ./zynq7/segbits_cmt_top_l_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_l_upper_t.origin_info.db)
+ * [`a056685a5edd98818b8f4a4512d6789797cc2ae54e106aefb897e108b2487800  ./zynq7/segbits_cmt_top_r_lower_b.db`](./zynq7/segbits_cmt_top_r_lower_b.db)
+ * [`53800d9220925d056d38d47b9477f084b5380ea914ae5db6404bad63cba5b398  ./zynq7/segbits_cmt_top_r_lower_b.origin_info.db`](./zynq7/segbits_cmt_top_r_lower_b.origin_info.db)
+ * [`ff3f5ed631016fb97d2e949d02b6a4eda93b5291a14b43cda962a93eeed88894  ./zynq7/segbits_cmt_top_r_upper_t.db`](./zynq7/segbits_cmt_top_r_upper_t.db)
+ * [`a6ea0f1abacda03e873459b43b5fda477a027904533d9bff94c0763bc2e30cef  ./zynq7/segbits_cmt_top_r_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_r_upper_t.origin_info.db)
  * [`0d9f730a1328a61f471c2f6abd98463a39c7e5e70ff557adc6228e1830560c64  ./zynq7/segbits_dsp_l.db`](./zynq7/segbits_dsp_l.db)
  * [`10a6e47f7b26f0d21cf0a011d4a5f2a4266538bb8d028a07fd981323dc1f0da0  ./zynq7/segbits_dsp_l.origin_info.db`](./zynq7/segbits_dsp_l.origin_info.db)
  * [`f81459ae1c84e0e73815c4577a7d0b19b497dd7f16029763c3fc4f3b8410dcc2  ./zynq7/segbits_dsp_r.db`](./zynq7/segbits_dsp_r.db)
@@ -1142,25 +1154,25 @@
  * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9  ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db)
  * [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0  ./zynq7/segbits_hclk_r.origin_info.db`](./zynq7/segbits_hclk_r.origin_info.db)
  * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520  ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db)
- * [`53f0117e2838f3d7b71a9132f35aec36950a59186cfcd4cb9c39d86149ee28a0  ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
+ * [`5fc5ab48a9b407991e79f2afb04f323071f75cce8892c1b34fc677d840016738  ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
  * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556  ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db)
- * [`4d71d5ca74c00f43b4278845de8a46158f5f7a6990704c096ff469989b30beb1  ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
+ * [`ccd1e9aae8a04ea951bbe123f34cb3277144b365ab00046e3a5a013aaeebafbd  ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
  * [`392e91def4df6eebb3ce5ed15570c01f6090be793a79054e1880549082eb6f23  ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db)
- * [`0fca9c6530589b14c77b738e68c63ed4246713e44e1e699e153b69907e77e09e  ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db)
- * [`78f15c4b7b7ccb486dc5ba8ea02c1703ecd9d5101e22ab173291aeef70d001e3  ./zynq7/segbits_lioi3.db`](./zynq7/segbits_lioi3.db)
- * [`cdc66476c9896172f5d07d2cda0d63bc945300065e0e8246c95e2a097d960d15  ./zynq7/segbits_lioi3.origin_info.db`](./zynq7/segbits_lioi3.origin_info.db)
- * [`d6d3d28d3ba48cf7d2dbfa99aef4709eec7b2c2114086ad3ce8286192b4b081d  ./zynq7/segbits_lioi3_tbytesrc.db`](./zynq7/segbits_lioi3_tbytesrc.db)
- * [`5661c5162cb8d010d74db127d09564333e2986f31719eddad2b17c38c01adce8  ./zynq7/segbits_lioi3_tbytesrc.origin_info.db`](./zynq7/segbits_lioi3_tbytesrc.origin_info.db)
- * [`13794b0252ab318df174f57875400fb84161125cbc08bbbefbd2d4567d88471c  ./zynq7/segbits_lioi3_tbyteterm.db`](./zynq7/segbits_lioi3_tbyteterm.db)
- * [`15d28dfc9ab6d93b6269fca88c1fea1d9754f684478bba203340fc806b1d4210  ./zynq7/segbits_lioi3_tbyteterm.origin_info.db`](./zynq7/segbits_lioi3_tbyteterm.origin_info.db)
+ * [`6ffdf37ae2c6625eed093d59458f3319928bab0ac268abfdeed04c92c4673cfb  ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db)
+ * [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff  ./zynq7/segbits_lioi3.db`](./zynq7/segbits_lioi3.db)
+ * [`4b1dd698dba50fdf44426b05641189c2faaff29a99d387543d1874983fd68a50  ./zynq7/segbits_lioi3.origin_info.db`](./zynq7/segbits_lioi3.origin_info.db)
+ * [`0fb3e4c3427cb3fe2426445f9e6ebd1a33a3a5900904f28c7aea339a5f71530e  ./zynq7/segbits_lioi3_tbytesrc.db`](./zynq7/segbits_lioi3_tbytesrc.db)
+ * [`cbc24997471fa0a4cc59db46589a3daea9f59b4d599ca802a1f62b730090c89c  ./zynq7/segbits_lioi3_tbytesrc.origin_info.db`](./zynq7/segbits_lioi3_tbytesrc.origin_info.db)
+ * [`e81ad6e17e179647d06b9dc193588c8297af448e8eb7bd6c4b807a832631e07b  ./zynq7/segbits_lioi3_tbyteterm.db`](./zynq7/segbits_lioi3_tbyteterm.db)
+ * [`bf79280a339e566244220050232020c5d3b8dceed7bd80bcf23da7b4a53cb250  ./zynq7/segbits_lioi3_tbyteterm.origin_info.db`](./zynq7/segbits_lioi3_tbyteterm.origin_info.db)
  * [`ded5f7b0cdadb7558470dbca9102d7293e4237ecb563b5f69821e01b41e4aad1  ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db)
- * [`3a62e9a5ca328fd2a6838656759116ab186cb1c50bf4d4e7e3037424bc77903c  ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db)
- * [`e0d0d8ca2906e44d446b49afa210920ba715c7e4792a80d9df3aa8a4eebeec82  ./zynq7/segbits_rioi3.db`](./zynq7/segbits_rioi3.db)
- * [`dcc46ed5d4d72987aea39961fca2c3823ddb3550189492db72d90cadbc12c2fe  ./zynq7/segbits_rioi3.origin_info.db`](./zynq7/segbits_rioi3.origin_info.db)
- * [`c3c30acc0ebed2068979226fab3ba18c9da9fd306faa40b4778ae0c86d13c42f  ./zynq7/segbits_rioi3_tbytesrc.db`](./zynq7/segbits_rioi3_tbytesrc.db)
- * [`4ae87ae13dd959bdca6dbac4630f6746fee1d7de31315f4975ca450d7e1226f7  ./zynq7/segbits_rioi3_tbytesrc.origin_info.db`](./zynq7/segbits_rioi3_tbytesrc.origin_info.db)
- * [`4b23fed56175025c99536a2d27f84f111aad2be905bd6adf63f6c20f0c18835b  ./zynq7/segbits_rioi3_tbyteterm.db`](./zynq7/segbits_rioi3_tbyteterm.db)
- * [`5d8ea92e462d75025b9f69eb41b039a0ce76637bd274b7ee188f1e2afd349174  ./zynq7/segbits_rioi3_tbyteterm.origin_info.db`](./zynq7/segbits_rioi3_tbyteterm.origin_info.db)
+ * [`49456622ba534f8a616fe6e8bb0e3006c3ca292f2439f190ef07f82743f09613  ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db)
+ * [`712cc4b66ff35ea6033cb76e41d8dde1225857836f4b799834925ab5c3e8575a  ./zynq7/segbits_rioi3.db`](./zynq7/segbits_rioi3.db)
+ * [`4d0e9719c7016a0dece266060eabf4db7218b6cc982449cb93b87e7b2d0c755b  ./zynq7/segbits_rioi3.origin_info.db`](./zynq7/segbits_rioi3.origin_info.db)
+ * [`6823106be1cdccae2cf0c1332c7a36ee11a1a86c31376100f16921b6b579ea19  ./zynq7/segbits_rioi3_tbytesrc.db`](./zynq7/segbits_rioi3_tbytesrc.db)
+ * [`b9865b3e3095be11c76a2666ce8752af7ba8fe9f5e0ae92db786324803ec6e3a  ./zynq7/segbits_rioi3_tbytesrc.origin_info.db`](./zynq7/segbits_rioi3_tbytesrc.origin_info.db)
+ * [`dcec55e405772728cf8c4dd2d981e76d25e9e3aed5142b5a78164a2959ad4d1a  ./zynq7/segbits_rioi3_tbyteterm.db`](./zynq7/segbits_rioi3_tbyteterm.db)
+ * [`3f6660e877e33e129233bfc3de090ced8c9895e03b4540068258f3c09a0ce1f4  ./zynq7/segbits_rioi3_tbyteterm.origin_info.db`](./zynq7/segbits_rioi3_tbyteterm.origin_info.db)
  * [`ee26e7dbf78c2a37118c49ce7edb5fa44afd51850a24824ba8b68e34366f0787  ./zynq7/settings.sh`](./zynq7/settings.sh)
  * [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70  ./zynq7/site_type_BSCAN.json`](./zynq7/site_type_BSCAN.json)
  * [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be  ./zynq7/site_type_BUFGCTRL.json`](./zynq7/site_type_BUFGCTRL.json)
@@ -1337,7 +1349,7 @@
  * [`5afccb72fdc7e9a452988e5db5dd7517ab38792ba21af020f9f1885f686ae5a3  ./zynq7/timings/HCLK_CMT.sdf`](./zynq7/timings/HCLK_CMT.sdf)
  * [`5afccb72fdc7e9a452988e5db5dd7517ab38792ba21af020f9f1885f686ae5a3  ./zynq7/timings/HCLK_CMT_L.sdf`](./zynq7/timings/HCLK_CMT_L.sdf)
  * [`b5d5ca72d453879fca2bf2470fb0a670ebfb38d6e85cdbfdb3967e2e4f59ee73  ./zynq7/timings/HCLK_IOI3.sdf`](./zynq7/timings/HCLK_IOI3.sdf)
- * [`9313a012de7cbb7120baf15fe30bf8d44b238cad6226ece1a9776746e2857863  ./zynq7/timings/LIOB33.sdf`](./zynq7/timings/LIOB33.sdf)
+ * [`a64ba6e07bedc352898bc06d44b3677111739e9c0ecdf989fa57f1a200547b14  ./zynq7/timings/LIOB33.sdf`](./zynq7/timings/LIOB33.sdf)
  * [`0fdaf6a593346b5cac8899eebf4f62d1732d6d6fb0a17c9f4b6a4e54e03c3523  ./zynq7/timings/LIOB33_SING.sdf`](./zynq7/timings/LIOB33_SING.sdf)
  * [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1  ./zynq7/timings/LIOI3.sdf`](./zynq7/timings/LIOI3.sdf)
  * [`3bb5a39c36bcd83a540200072baa4c36057960fa1e35f5fcba875f2a755c34a1  ./zynq7/timings/LIOI3_SING.sdf`](./zynq7/timings/LIOI3_SING.sdf)
@@ -1360,15 +1372,15 @@
  * [`43a136f26603c51bd97e9489d223bbc80f278fcc234225ed9fde404402f22683  ./zynq7/xc7z010clg400-1/part.yaml`](./zynq7/xc7z010clg400-1/part.yaml)
  * [`899966167308aa91e3651f66bba8611ee465acaf8e58bd3ba87d5b1777c0f625  ./zynq7/xc7z010clg400-1/required_features.fasm`](./zynq7/xc7z010clg400-1/required_features.fasm)
  * [`e6d0ebf9b27f60f4afdab85a357bff4d7cf2cd77c3a6c0f2d887022cda874066  ./zynq7/xc7z010clg400-1/tileconn.json`](./zynq7/xc7z010clg400-1/tileconn.json)
- * [`83207014af5c82fa0201164ce5f8f3838a2463fdd0a36a7a4b655aecedd0f8b4  ./zynq7/xc7z010clg400-1/tilegrid.json`](./zynq7/xc7z010clg400-1/tilegrid.json)
+ * [`db16874f2827fc05248ad4a7ef5769deaa8e70158a60c8dd40194c48713479ee  ./zynq7/xc7z010clg400-1/tilegrid.json`](./zynq7/xc7z010clg400-1/tilegrid.json)
  * [`52eac7be98da1e8bda491fa07699ae84c0e7eca1e09cde8b308be1df2ab5590f  ./zynq7/xc7z020clg400-1/package_pins.csv`](./zynq7/xc7z020clg400-1/package_pins.csv)
  * [`40734e0dad409b7728403109f9eeb47adfbfcdcb8780414a8e81c04c44b96c49  ./zynq7/xc7z020clg400-1/part.json`](./zynq7/xc7z020clg400-1/part.json)
  * [`a5e33398424d02770e3fdccc4d7fe41f0ba8b8440b79a62ad09b60cae6048174  ./zynq7/xc7z020clg400-1/part.yaml`](./zynq7/xc7z020clg400-1/part.yaml)
  * [`aedbb30dc143aaec2ca2bc76597ca4ebe546aa7913f0e4de710cecf3e0f31f23  ./zynq7/xc7z020clg400-1/required_features.fasm`](./zynq7/xc7z020clg400-1/required_features.fasm)
  * [`8c3c23f987f1c0a2e55ab2a7467a9724f30762d1268e6cc5fce00eb65bf00ad3  ./zynq7/xc7z020clg400-1/tileconn.json`](./zynq7/xc7z020clg400-1/tileconn.json)
- * [`e9f5a30f17f3c1aec9ae3cc421f4f4bbe0f74c94b4386d73450f195efd736379  ./zynq7/xc7z020clg400-1/tilegrid.json`](./zynq7/xc7z020clg400-1/tilegrid.json)
+ * [`c980c8eb552d50ef8c210a6709043c6c0355b95b695a36f99cfa9716d853c61d  ./zynq7/xc7z020clg400-1/tilegrid.json`](./zynq7/xc7z020clg400-1/tilegrid.json)
  * [`55a9a5d444f71774d8b072adb3de03338d68f78ba18f9c817ab1bf239613b1dc  ./zynq7/xc7z020clg484-1/package_pins.csv`](./zynq7/xc7z020clg484-1/package_pins.csv)
  * [`47d494b96865d61458ec9c5e0d720886bcd755d9eebcae46ca9045fd679d2f2d  ./zynq7/xc7z020clg484-1/part.json`](./zynq7/xc7z020clg484-1/part.json)
  * [`a5e33398424d02770e3fdccc4d7fe41f0ba8b8440b79a62ad09b60cae6048174  ./zynq7/xc7z020clg484-1/part.yaml`](./zynq7/xc7z020clg484-1/part.yaml)
  * [`8c3c23f987f1c0a2e55ab2a7467a9724f30762d1268e6cc5fce00eb65bf00ad3  ./zynq7/xc7z020clg484-1/tileconn.json`](./zynq7/xc7z020clg484-1/tileconn.json)
- * [`e9f5a30f17f3c1aec9ae3cc421f4f4bbe0f74c94b4386d73450f195efd736379  ./zynq7/xc7z020clg484-1/tilegrid.json`](./zynq7/xc7z020clg484-1/tilegrid.json)
+ * [`c980c8eb552d50ef8c210a6709043c6c0355b95b695a36f99cfa9716d853c61d  ./zynq7/xc7z020clg484-1/tilegrid.json`](./zynq7/xc7z020clg484-1/tilegrid.json)

diff --git a/artix7/mask_lioi3.db b/artix7/mask_lioi3.db
index 5f32097..4a5f68d 100644
--- a/artix7/mask_lioi3.db
+++ b/artix7/mask_lioi3.db

@@ -1,5 +1,5 @@
-bit 25_00
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
 bit 25_23

diff --git a/artix7/mask_lioi3_tbytesrc.db b/artix7/mask_lioi3_tbytesrc.db
index 5f32097..4a5f68d 100644
--- a/artix7/mask_lioi3_tbytesrc.db
+++ b/artix7/mask_lioi3_tbytesrc.db

@@ -1,5 +1,5 @@
-bit 25_00
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
 bit 25_23

diff --git a/artix7/mask_lioi3_tbyteterm.db b/artix7/mask_lioi3_tbyteterm.db
index 5f32097..4a5f68d 100644
--- a/artix7/mask_lioi3_tbyteterm.db
+++ b/artix7/mask_lioi3_tbyteterm.db

@@ -1,5 +1,5 @@
-bit 25_00
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
 bit 25_23

diff --git a/artix7/mask_rioi3.db b/artix7/mask_rioi3.db
index 5f32097..4a5f68d 100644
--- a/artix7/mask_rioi3.db
+++ b/artix7/mask_rioi3.db

@@ -1,5 +1,5 @@
-bit 25_00
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
 bit 25_23

diff --git a/artix7/mask_rioi3_tbytesrc.db b/artix7/mask_rioi3_tbytesrc.db
index 5f32097..4a5f68d 100644
--- a/artix7/mask_rioi3_tbytesrc.db
+++ b/artix7/mask_rioi3_tbytesrc.db

@@ -1,5 +1,5 @@
-bit 25_00
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
 bit 25_23

diff --git a/artix7/mask_rioi3_tbyteterm.db b/artix7/mask_rioi3_tbyteterm.db
index 5f32097..4a5f68d 100644
--- a/artix7/mask_rioi3_tbyteterm.db
+++ b/artix7/mask_rioi3_tbyteterm.db

@@ -1,5 +1,5 @@
-bit 25_00
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
 bit 25_23

diff --git a/artix7/segbits_clk_bufg_bot_r.origin_info.db b/artix7/segbits_clk_bufg_bot_r.origin_info.db
index f18cf2e..f679954 100644
--- a/artix7/segbits_clk_bufg_bot_r.origin_info.db
+++ b/artix7/segbits_clk_bufg_bot_r.origin_info.db

@@ -178,159 +178,159 @@
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_08 26_07 27_06
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_08 !27_06 26_07
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_07 !26_08 27_06
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_07 !26_08 !27_06
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_07 !26_08 !27_06
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_BOT_R_CK_MUXED1 origin:046-clk-bufg-muxed-pips !26_05 !27_05 26_04
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_04 26_05 27_05
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_04 !26_05 27_05
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_04 !27_05 26_05
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_04 !26_05 !27_05
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_04 !26_05 !27_05
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_BOT_R_CK_MUXED2 origin:046-clk-bufg-muxed-pips !26_23 !27_22 26_24
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_24 !27_22 26_23
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_24 26_23 27_22
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_23 !26_24 27_22
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_23 !26_24 !27_22
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_23 !26_24 !27_22
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_BOT_R_CK_MUXED3 origin:046-clk-bufg-muxed-pips !26_21 !27_21 26_20
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_20 !26_21 27_21
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_20 26_21 27_21
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_20 !27_21 26_21
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_20 !26_21 !27_21
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_20 !26_21 !27_21
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_BOT_R_CK_MUXED4 origin:046-clk-bufg-muxed-pips !26_39 !27_38 26_40
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_40 !27_38 26_39
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_40 26_39 27_38
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_39 !26_40 27_38
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_39 !26_40 !27_38
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_39 !26_40 !27_38
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_BOT_R_CK_MUXED5 origin:046-clk-bufg-muxed-pips !26_37 !27_37 26_36
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_36 !26_37 27_37
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_36 26_37 27_37
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_36 !27_37 26_37
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_36 !26_37 !27_37
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_36 !26_37 !27_37
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_BOT_R_CK_MUXED6 origin:046-clk-bufg-muxed-pips !26_55 !27_54 26_56
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_56 !27_54 26_55
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_56 26_55 27_54
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_55 !26_56 27_54
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_55 !26_56 !27_54
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_55 !26_56 !27_54
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_BOT_R_CK_MUXED7 origin:046-clk-bufg-muxed-pips !26_53 !27_53 26_52
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_52 !26_53 27_53
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_52 26_53 27_53
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_52 !27_53 26_53
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_52 !26_53 !27_53
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_52 !26_53 !27_53
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_BOT_R_CK_MUXED8 origin:046-clk-bufg-muxed-pips !26_71 !27_70 26_72
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_72 !27_70 26_71
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_72 26_71 27_70
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_71 !26_72 27_70
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_71 !26_72 !27_70
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_71 !26_72 !27_70
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_BOT_R_CK_MUXED9 origin:046-clk-bufg-muxed-pips !26_69 !27_69 26_68
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_68 !26_69 27_69
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_68 26_69 27_69
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_68 !27_69 26_69
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_68 !26_69 !27_69
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_68 !26_69 !27_69
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_BOT_R_CK_MUXED10 origin:046-clk-bufg-muxed-pips !26_87 !27_86 26_88
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_88 !27_86 26_87
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_88 26_87 27_86
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_87 !26_88 27_86
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_87 !26_88 !27_86
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_87 !26_88 !27_86
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_BOT_R_CK_MUXED11 origin:046-clk-bufg-muxed-pips !26_85 !27_85 26_84
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_84 !26_85 27_85
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_84 26_85 27_85
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_84 !27_85 26_85
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_84 !26_85 !27_85
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_84 !26_85 !27_85
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_BOT_R_CK_MUXED12 origin:046-clk-bufg-muxed-pips !26_103 !27_102 26_104
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_104 !27_102 26_103
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_104 26_103 27_102
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_103 !26_104 27_102
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_103 !26_104 !27_102
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_103 !26_104 !27_102
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_BOT_R_CK_MUXED13 origin:046-clk-bufg-muxed-pips !26_101 !27_101 26_100
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_100 !26_101 27_101
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_100 26_101 27_101
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_100 !27_101 26_101
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_100 !26_101 !27_101
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_100 !26_101 !27_101
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_BOT_R_CK_MUXED14 origin:046-clk-bufg-muxed-pips !26_119 !27_118 26_120
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_120 !27_118 26_119
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_120 26_119 27_118
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_119 !26_120 27_118
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_119 !26_120 !27_118
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_119 !26_120 !27_118
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_BOT_R_CK_MUXED15 origin:046-clk-bufg-muxed-pips !26_117 !27_117 26_116
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_116 !26_117 27_117
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_116 26_117 27_117
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_116 !27_117 26_117
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_116 !26_117 !27_117
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_116 !26_117 !27_117
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_BOT_R_CK_MUXED16 origin:046-clk-bufg-muxed-pips !26_135 !27_134 26_136
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_136 !27_134 26_135
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_136 26_135 27_134
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_135 !26_136 27_134
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_135 !26_136 !27_134
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_135 !26_136 !27_134
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_BOT_R_CK_MUXED17 origin:046-clk-bufg-muxed-pips !26_133 !27_133 26_132
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_132 !26_133 27_133
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_132 26_133 27_133
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_132 !27_133 26_133
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_132 !26_133 !27_133
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_132 !26_133 !27_133
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_BOT_R_CK_MUXED18 origin:046-clk-bufg-muxed-pips !26_151 !27_150 26_152
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_152 !27_150 26_151
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_152 26_151 27_150
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_151 !26_152 27_150
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_151 !26_152 !27_150
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_151 !26_152 !27_150
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_BOT_R_CK_MUXED19 origin:046-clk-bufg-muxed-pips !26_149 !27_149 26_148
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_148 !26_149 27_149
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_148 26_149 27_149
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_148 !27_149 26_149
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_148 !26_149 !27_149
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_148 !26_149 !27_149
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_BOT_R_CK_MUXED20 origin:046-clk-bufg-muxed-pips !26_167 !27_166 26_168
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_168 !27_166 26_167
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_168 26_167 27_166
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_167 !26_168 27_166
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_167 !26_168 !27_166
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_167 !26_168 !27_166
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_BOT_R_CK_MUXED21 origin:046-clk-bufg-muxed-pips !26_165 !27_165 26_164
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_164 !26_165 27_165
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_164 26_165 27_165
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_164 !27_165 26_165
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_164 !26_165 !27_165
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_164 !26_165 !27_165
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_BOT_R_CK_MUXED22 origin:046-clk-bufg-muxed-pips !26_183 !27_182 26_184
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_184 !27_182 26_183
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_184 26_183 27_182
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_183 !26_184 27_182
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_183 !26_184 !27_182
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_183 !26_184 !27_182
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_BOT_R_CK_MUXED23 origin:046-clk-bufg-muxed-pips !26_181 !27_181 26_180
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_180 !26_181 27_181
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_180 26_181 27_181
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_180 !27_181 26_181
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_180 !26_181 !27_181
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_180 !26_181 !27_181
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_BOT_R_CK_MUXED24 origin:046-clk-bufg-muxed-pips !26_199 !27_198 26_200
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_200 !27_198 26_199
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_200 26_199 27_198
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_199 !26_200 27_198
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_199 !26_200 !27_198
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_199 !26_200 !27_198
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_BOT_R_CK_MUXED25 origin:046-clk-bufg-muxed-pips !26_197 !27_197 26_196
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_196 !26_197 27_197
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_196 26_197 27_197
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_196 !27_197 26_197
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_196 !26_197 !27_197
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_196 !26_197 !27_197
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_BOT_R_CK_MUXED26 origin:046-clk-bufg-muxed-pips !26_215 !27_214 26_216
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_216 !27_214 26_215
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_216 26_215 27_214
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_215 !26_216 27_214
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_215 !26_216 !27_214
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_215 !26_216 !27_214
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_BOT_R_CK_MUXED27 origin:046-clk-bufg-muxed-pips !26_213 !27_213 26_212
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_212 !26_213 27_213
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_212 26_213 27_213
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_212 !27_213 26_213
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_212 !26_213 !27_213
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_212 !26_213 !27_213
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_BOT_R_CK_MUXED28 origin:046-clk-bufg-muxed-pips !26_231 !27_230 26_232
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_232 !27_230 26_231
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_232 26_231 27_230
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_231 !26_232 27_230
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_231 !26_232 !27_230
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_231 !26_232 !27_230
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_BOT_R_CK_MUXED29 origin:046-clk-bufg-muxed-pips !26_229 !27_229 26_228
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_228 !26_229 27_229
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_228 26_229 27_229
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_228 !27_229 26_229
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_228 !26_229 !27_229
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_228 !26_229 !27_229
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_BOT_R_CK_MUXED30 origin:046-clk-bufg-muxed-pips !26_247 !27_246 26_248
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_248 26_247 27_246
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_248 !27_246 26_247
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_247 !26_248 27_246
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_247 !26_248 !27_246
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_247 !26_248 !27_246
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_BOT_R_CK_MUXED31 origin:046-clk-bufg-muxed-pips !26_245 !27_245 26_244
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_244 26_245 27_245
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_244 !26_245 27_245
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_244 !27_245 26_245
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_244 !26_245 !27_245
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_244 !26_245 !27_245

diff --git a/artix7/segbits_clk_bufg_top_r.origin_info.db b/artix7/segbits_clk_bufg_top_r.origin_info.db
index b23f2e4..ddcc016 100644
--- a/artix7/segbits_clk_bufg_top_r.origin_info.db
+++ b/artix7/segbits_clk_bufg_top_r.origin_info.db

@@ -178,159 +178,159 @@
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_08 !27_06 26_07
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0 origin:046-clk-bufg-muxed-pips !26_07 !27_06 26_08
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_07 !26_08 27_06
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_07 !26_08 !27_06
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_07 !26_08 !27_06
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_04 26_05 27_05
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_04 !26_05 27_05
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_TOP_R_CK_MUXED1 origin:046-clk-bufg-muxed-pips !26_05 !27_05 26_04
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_04 !27_05 26_05
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_04 !26_05 !27_05
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_04 !26_05 !27_05
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_24 !27_22 26_23
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_24 26_23 27_22
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_TOP_R_CK_MUXED2 origin:046-clk-bufg-muxed-pips !26_23 !27_22 26_24
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_23 !26_24 27_22
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_23 !26_24 !27_22
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_23 !26_24 !27_22
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_20 !26_21 27_21
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_20 26_21 27_21
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_TOP_R_CK_MUXED3 origin:046-clk-bufg-muxed-pips !26_21 !27_21 26_20
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_20 !27_21 26_21
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_20 !26_21 !27_21
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_20 !26_21 !27_21
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_40 !27_38 26_39
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_40 26_39 27_38
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_TOP_R_CK_MUXED4 origin:046-clk-bufg-muxed-pips !26_39 !27_38 26_40
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_39 !26_40 27_38
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_39 !26_40 !27_38
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_39 !26_40 !27_38
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_36 !26_37 27_37
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_36 26_37 27_37
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_TOP_R_CK_MUXED5 origin:046-clk-bufg-muxed-pips !26_37 !27_37 26_36
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_36 !27_37 26_37
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_36 !26_37 !27_37
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_36 !26_37 !27_37
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_56 !27_54 26_55
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_56 26_55 27_54
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_TOP_R_CK_MUXED6 origin:046-clk-bufg-muxed-pips !26_55 !27_54 26_56
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_55 !26_56 27_54
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_55 !26_56 !27_54
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_55 !26_56 !27_54
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_52 !26_53 27_53
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_52 26_53 27_53
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_TOP_R_CK_MUXED7 origin:046-clk-bufg-muxed-pips !26_53 !27_53 26_52
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_52 !27_53 26_53
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_52 !26_53 !27_53
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_52 !26_53 !27_53
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_72 !27_70 26_71
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_72 26_71 27_70
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_TOP_R_CK_MUXED8 origin:046-clk-bufg-muxed-pips !26_71 !27_70 26_72
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_71 !26_72 27_70
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_71 !26_72 !27_70
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_71 !26_72 !27_70
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_68 !26_69 27_69
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_68 26_69 27_69
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_TOP_R_CK_MUXED9 origin:046-clk-bufg-muxed-pips !26_69 !27_69 26_68
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_68 !27_69 26_69
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_68 !26_69 !27_69
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_68 !26_69 !27_69
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_88 !27_86 26_87
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_88 26_87 27_86
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_TOP_R_CK_MUXED10 origin:046-clk-bufg-muxed-pips !26_87 !27_86 26_88
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_87 !26_88 27_86
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_87 !26_88 !27_86
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_87 !26_88 !27_86
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_84 !26_85 27_85
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_84 26_85 27_85
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_TOP_R_CK_MUXED11 origin:046-clk-bufg-muxed-pips !26_85 !27_85 26_84
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_84 !27_85 26_85
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_84 !26_85 !27_85
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_84 !26_85 !27_85
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_104 !27_102 26_103
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_104 26_103 27_102
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_TOP_R_CK_MUXED12 origin:046-clk-bufg-muxed-pips !26_103 !27_102 26_104
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_103 !26_104 27_102
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_103 !26_104 !27_102
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_103 !26_104 !27_102
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_100 !26_101 27_101
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_100 26_101 27_101
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_TOP_R_CK_MUXED13 origin:046-clk-bufg-muxed-pips !26_101 !27_101 26_100
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_100 !27_101 26_101
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_100 !26_101 !27_101
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_100 !26_101 !27_101
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_120 !27_118 26_119
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_120 26_119 27_118
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_TOP_R_CK_MUXED14 origin:046-clk-bufg-muxed-pips !26_119 !27_118 26_120
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_119 !26_120 27_118
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_119 !26_120 !27_118
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_119 !26_120 !27_118
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_116 !26_117 27_117
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_116 26_117 27_117
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_TOP_R_CK_MUXED15 origin:046-clk-bufg-muxed-pips !26_117 !27_117 26_116
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_116 !27_117 26_117
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_116 !26_117 !27_117
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_116 !26_117 !27_117
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_136 !27_134 26_135
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_136 26_135 27_134
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_TOP_R_CK_MUXED16 origin:046-clk-bufg-muxed-pips !26_135 !27_134 26_136
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_135 !26_136 27_134
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_135 !26_136 !27_134
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_135 !26_136 !27_134
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_132 !26_133 27_133
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_132 26_133 27_133
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_TOP_R_CK_MUXED17 origin:046-clk-bufg-muxed-pips !26_133 !27_133 26_132
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_132 !27_133 26_133
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_132 !26_133 !27_133
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_132 !26_133 !27_133
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_152 !27_150 26_151
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_152 26_151 27_150
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_TOP_R_CK_MUXED18 origin:046-clk-bufg-muxed-pips !26_151 !27_150 26_152
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_151 !26_152 27_150
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_151 !26_152 !27_150
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_151 !26_152 !27_150
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_148 !26_149 27_149
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_148 26_149 27_149
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_TOP_R_CK_MUXED19 origin:046-clk-bufg-muxed-pips !26_149 !27_149 26_148
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_148 !27_149 26_149
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_148 !26_149 !27_149
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_148 !26_149 !27_149
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_168 !27_166 26_167
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_168 26_167 27_166
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_TOP_R_CK_MUXED20 origin:046-clk-bufg-muxed-pips !26_167 !27_166 26_168
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_167 !26_168 27_166
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_167 !26_168 !27_166
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_167 !26_168 !27_166
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_164 !26_165 27_165
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_164 26_165 27_165
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_TOP_R_CK_MUXED21 origin:046-clk-bufg-muxed-pips !26_165 !27_165 26_164
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_164 !27_165 26_165
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_164 !26_165 !27_165
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_164 !26_165 !27_165
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_184 !27_182 26_183
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_184 26_183 27_182
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_TOP_R_CK_MUXED22 origin:046-clk-bufg-muxed-pips !26_183 !27_182 26_184
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_183 !26_184 27_182
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_183 !26_184 !27_182
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_183 !26_184 !27_182
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_180 !26_181 27_181
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_180 26_181 27_181
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_TOP_R_CK_MUXED23 origin:046-clk-bufg-muxed-pips !26_181 !27_181 26_180
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_180 !27_181 26_181
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_180 !26_181 !27_181
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_180 !26_181 !27_181
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_200 !27_198 26_199
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_200 26_199 27_198
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_TOP_R_CK_MUXED24 origin:046-clk-bufg-muxed-pips !26_199 !27_198 26_200
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_199 !26_200 27_198
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_199 !26_200 !27_198
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_199 !26_200 !27_198
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_196 !26_197 27_197
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_196 26_197 27_197
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_TOP_R_CK_MUXED25 origin:046-clk-bufg-muxed-pips !26_197 !27_197 26_196
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_196 !27_197 26_197
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_196 !26_197 !27_197
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_196 !26_197 !27_197
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_216 !27_214 26_215
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_216 26_215 27_214
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_TOP_R_CK_MUXED26 origin:046-clk-bufg-muxed-pips !26_215 !27_214 26_216
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_215 !26_216 27_214
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_215 !26_216 !27_214
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_215 !26_216 !27_214
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_212 !26_213 27_213
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_212 26_213 27_213
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_TOP_R_CK_MUXED27 origin:046-clk-bufg-muxed-pips !26_213 !27_213 26_212
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_212 !27_213 26_213
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_212 !26_213 !27_213
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_212 !26_213 !27_213
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_232 !27_230 26_231
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_232 26_231 27_230
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_TOP_R_CK_MUXED28 origin:046-clk-bufg-muxed-pips !26_231 !27_230 26_232
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_231 !26_232 27_230
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_231 !26_232 !27_230
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_231 !26_232 !27_230
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_228 !26_229 27_229
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_228 26_229 27_229
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_TOP_R_CK_MUXED29 origin:046-clk-bufg-muxed-pips !26_229 !27_229 26_228
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_228 !27_229 26_229
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_228 !26_229 !27_229
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_228 !26_229 !27_229
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_248 26_247 27_246
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_248 !27_246 26_247
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_TOP_R_CK_MUXED30 origin:046-clk-bufg-muxed-pips !26_247 !27_246 26_248
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_247 !26_248 27_246
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_247 !26_248 !27_246
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_247 !26_248 !27_246
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_244 26_245 27_245
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_244 !26_245 27_245
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_TOP_R_CK_MUXED31 origin:046-clk-bufg-muxed-pips !26_245 !27_245 26_244
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_244 !27_245 26_245
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_244 !26_245 !27_245
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_244 !26_245 !27_245

diff --git a/artix7/segbits_cmt_top_l_lower_b.db b/artix7/segbits_cmt_top_l_lower_b.db
new file mode 100644
index 0000000..e95270c
--- /dev/null
+++ b/artix7/segbits_cmt_top_l_lower_b.db

@@ -0,0 +1,396 @@
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB0 !28_1012 28_1013 29_979 29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB1 !28_1012 !28_1013 29_979 29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB2 !28_1012 28_1013 29_979 !29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB3 !28_1012 !28_1013 29_979 !29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_IN3_HCLK 28_1012 !28_1013 29_979 !29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_IN3_INT 28_1012 28_1013 29_979 !29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_LR_LOWER_B_CLKFBOUT2IN 28_980 28_981 29_980
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB0 28_1014 !29_1013 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB1 28_1014 !29_1013 !29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB2 !28_1014 !29_1013 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB3 !28_1014 !29_1013 !29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_IN1_HCLK !28_1014 29_1013 !29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_IN1_INT !28_1014 29_1013 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB0 !28_1015 28_1016 29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB1 !28_1015 !28_1016 29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB2 !28_1015 28_1016 !29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB3 !28_1015 !28_1016 !29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_IN2_HCLK 28_1015 !28_1016 !29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_IN2_INT 28_1015 28_1016 !29_1015
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS0_ACTIVE 28_1066 28_1074 29_1056
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS1_ACTIVE 28_1057 28_1067 28_1075
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840
+CMT_TOP_L_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_110 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 28_1015 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_110 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1013 29_1018
+CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL 29_109
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] 29_823
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] 28_823
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] 29_822
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] 28_822
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] 29_821
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] 28_821
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] 29_820
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] 28_820
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] 29_819
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] 28_819
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] 29_815
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] 28_815
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] 29_814
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] 28_814
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] 29_813
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] 28_813
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] 29_812
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] 28_812
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] 29_811
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] 28_811
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] 29_831
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] 28_831
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] 29_830
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] 28_830
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] 29_829
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] 28_829
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] 29_828
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] 28_828
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] 29_827
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] 28_827
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] 29_818
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] 28_818
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] 29_817
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] 28_817
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] 29_816
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] 29_810
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] 28_810
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] 29_809
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] 28_809
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] 29_808
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696
+CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT 29_94
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] 29_389
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] 28_388
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] 29_387
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] 28_386
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] 29_385
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] 28_384
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] 29_395
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] 28_394
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] 29_393
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] 28_392
+CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN 28_111
+CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST 29_111
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808

diff --git a/artix7/segbits_cmt_top_l_lower_b.origin_info.db b/artix7/segbits_cmt_top_l_lower_b.origin_info.db
new file mode 100644
index 0000000..d74dc78
--- /dev/null
+++ b/artix7/segbits_cmt_top_l_lower_b.origin_info.db

@@ -0,0 +1,396 @@
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !28_1012 28_1013 29_1012 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !28_1012 !28_1013 29_1012 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1012 !29_1012 28_1013 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1012 !28_1013 !29_1012 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_IN3_HCLK origin:034b-cmt-mmcm-pips !28_1013 !29_1012 28_1012 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_IN3_INT origin:034b-cmt-mmcm-pips !29_1012 28_1012 28_1013 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_LR_LOWER_B_CLKFBOUT2IN origin:034b-cmt-mmcm-pips 28_980 28_981 29_980
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !29_1013 28_1014 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !29_1013 !29_1014 28_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1014 !29_1013 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1014 !29_1013 !29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_IN1_HCLK origin:034b-cmt-mmcm-pips !28_1014 !29_1014 29_1013
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_IN1_INT origin:034b-cmt-mmcm-pips !28_1014 29_1013 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !28_1015 28_1016 29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !28_1015 !28_1016 29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1015 !29_1015 28_1016
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1015 !28_1016 !29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_IN2_HCLK origin:034b-cmt-mmcm-pips !28_1016 !29_1015 28_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_IN2_INT origin:034b-cmt-mmcm-pips !29_1015 28_1015 28_1016
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS0_ACTIVE origin:034b-cmt-mmcm-pips 28_1066 28_1074 29_1056
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS1_ACTIVE origin:034b-cmt-mmcm-pips 28_1057 28_1067 28_1075
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068 28_1076 29_1057
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
+CMT_TOP_L_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_1015 28_110 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1013 29_1018 29_110 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
+CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
+CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392
+CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
+CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808

diff --git a/artix7/segbits_cmt_top_l_upper_t.db b/artix7/segbits_cmt_top_l_upper_t.db
index 059a29e..07f73cc 100644
--- a/artix7/segbits_cmt_top_l_upper_t.db
+++ b/artix7/segbits_cmt_top_l_upper_t.db

@@ -1,364 +1,368 @@
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN !28_11 28_43 !28_44 !29_10 !29_11 29_42 29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN !28_11 !28_43 28_44 !29_10 29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT !28_11 !28_43 28_44 29_10 29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_09 !28_10 !29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 28_09 !28_10 !29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 !28_09 !28_10 29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 28_09 !28_10 29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 !28_09 28_10 !29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_09 28_10 !29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_08 !29_07 !29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_08 29_07 !29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 28_08 !29_07 !29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 28_08 29_07 !29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 !28_08 !29_07 29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT !28_08 29_07 29_08
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175
-CMT_TOP_L_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_06
-CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44
-CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_41 29_04
-CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_06
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183
-CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_05 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
-CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_722
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_200
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_200
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_201
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_201
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_202
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_202
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_203
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_203
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_204
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_204
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_208
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_208
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_209
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_209
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_210
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_210
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_211
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_211
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_212
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_212
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_192
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_192
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_193
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_193
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_194
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_194
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_195
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_195
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_196
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_196
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_205
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_205
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_206
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_206
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_207
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_213
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_213
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_214
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_214
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_215
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327
-CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_737
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_634
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_635
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_636
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_637
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_638
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_639
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_628
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_629
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_630
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_631
-CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_720
-CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_720
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN !28_43 28_75 !28_76 !29_42 !29_43 29_74 29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN !28_43 !28_75 28_76 !29_42 29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_43 !28_75 28_76 !29_42 !29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_43 !28_75 28_76 29_42 !29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 28_43 !28_75 28_76 !29_42 !29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 28_43 !28_75 28_76 29_42 !29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT !28_43 !28_75 28_76 29_42 29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_41 !28_42 !29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 28_41 !28_42 !29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 !28_41 !28_42 29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 28_41 !28_42 29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 !28_41 28_42 !29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_41 28_42 !29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_40 !29_39 !29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_40 29_39 !29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 28_40 !29_39 !29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 28_40 29_39 !29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 !28_40 !29_39 29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT !28_40 29_39 29_40
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
+CMT_TOP_L_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_38
+CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
+CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
+CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_38
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215
+CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
+CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_754
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_232
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_232
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_233
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_233
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_234
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_234
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_235
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_235
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_236
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_236
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_240
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_240
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_241
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_241
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_242
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_242
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_243
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_243
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_244
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_244
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_224
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_224
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_225
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_225
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_226
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_226
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_227
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_227
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_228
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_228
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_237
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_237
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_238
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_238
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_239
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_245
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_245
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_246
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_246
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_247
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359
+CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_769
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_666
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_667
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_668
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_669
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_670
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_671
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_660
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_661
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_662
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_663
+CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_752
+CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_752
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247

diff --git a/artix7/segbits_cmt_top_l_upper_t.origin_info.db b/artix7/segbits_cmt_top_l_upper_t.origin_info.db
index dd66297..fbdd8d9 100644
--- a/artix7/segbits_cmt_top_l_upper_t.origin_info.db
+++ b/artix7/segbits_cmt_top_l_upper_t.origin_info.db

@@ -1,364 +1,368 @@
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN origin:034-cmt-pll-pips !28_11 !28_44 !29_10 !29_11 28_43 29_42 29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_42 !29_43 28_44 29_11
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_11 !29_42 !29_43 28_44
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_11 !28_43 !29_11 !29_42 !29_43 28_44 29_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_43 !29_10 !29_11 !29_42 !29_43 28_11 28_44
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_43 !29_11 !29_42 !29_43 28_11 28_44 29_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_11 !28_43 !29_42 !29_43 28_44 29_10 29_11
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_09 !28_10 !29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_10 !29_09 28_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_09 !28_10 29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_10 28_09 29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_09 !29_09 28_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !29_09 28_09 28_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_08 !29_07 !29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_08 !29_08 29_07
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !29_07 !29_08 28_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !29_08 28_08 29_07
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_08 !29_07 29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_08 29_07 29_08
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
-CMT_TOP_L_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_06
-CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44
-CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_41 29_04
-CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_06
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183
-CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
-CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327
-CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631
-CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720
-CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN origin:034-cmt-pll-pips !28_43 !28_76 !29_42 !29_43 28_75 29_74 29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_43 !28_75 !29_42 !29_74 !29_75 28_76 29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_43 !28_75 !29_42 !29_43 !29_74 !29_75 28_76
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_43 !28_75 !29_43 !29_74 !29_75 28_76 29_42
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_75 !29_42 !29_43 !29_74 !29_75 28_43 28_76
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_75 !29_43 !29_74 !29_75 28_43 28_76 29_42
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_43 !28_75 !29_74 !29_75 28_76 29_42 29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_41 !28_42 !29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_42 !29_41 28_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_41 !28_42 29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_42 28_41 29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_41 !29_41 28_42
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !29_41 28_41 28_42
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_40 !29_39 !29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_40 !29_40 29_39
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !29_39 !29_40 28_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !29_40 28_40 29_39
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_40 !29_39 29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_40 29_39 29_40
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09 29_17
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
+CMT_TOP_L_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_38
+CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
+CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
+CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_38
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
+CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
+CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
+CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663
+CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752
+CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247

diff --git a/artix7/segbits_cmt_top_r_lower_b.db b/artix7/segbits_cmt_top_r_lower_b.db
new file mode 100644
index 0000000..b810699
--- /dev/null
+++ b/artix7/segbits_cmt_top_r_lower_b.db

@@ -0,0 +1,396 @@
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_LR_LOWER_B_CLKFBOUT2IN 28_980 28_981 29_980
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB0 !28_1012 28_1013 29_979 29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB1 !28_1012 !28_1013 29_979 29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB2 !28_1012 28_1013 29_979 !29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB3 !28_1012 !28_1013 29_979 !29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_IN3_HCLK 28_1012 !28_1013 29_979 !29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_IN3_INT 28_1012 28_1013 29_979 !29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB0 28_1014 !29_1013 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB1 28_1014 !29_1013 !29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB2 !28_1014 !29_1013 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB3 !28_1014 !29_1013 !29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_IN1_HCLK !28_1014 29_1013 !29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_IN1_INT !28_1014 29_1013 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB0 !28_1015 28_1016 29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB1 !28_1015 !28_1016 29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB2 !28_1015 28_1016 !29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB3 !28_1015 !28_1016 !29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_IN2_HCLK 28_1015 !28_1016 !29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_IN2_INT 28_1015 28_1016 !29_1015
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS0_ACTIVE 28_1066 28_1074 29_1056
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS1_ACTIVE 28_1057 28_1067 28_1075
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840
+CMT_TOP_R_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_110 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 28_1015 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_110 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1013 29_1018
+CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL 29_109
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] 29_823
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] 28_823
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] 29_822
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] 28_822
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] 29_821
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] 28_821
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] 29_820
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] 28_820
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] 29_819
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] 28_819
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] 29_815
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] 28_815
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] 29_814
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] 28_814
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] 29_813
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] 28_813
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] 29_812
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] 28_812
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] 29_811
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] 28_811
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] 29_831
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] 28_831
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] 29_830
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] 28_830
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] 29_829
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] 28_829
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] 29_828
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] 28_828
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] 29_827
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] 28_827
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] 29_818
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] 28_818
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] 29_817
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] 28_817
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] 29_816
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] 29_810
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] 28_810
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] 29_809
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] 28_809
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] 29_808
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696
+CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT 29_94
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] 29_389
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] 28_388
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] 29_387
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] 28_386
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] 29_385
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] 28_384
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] 29_395
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] 28_394
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] 29_393
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] 28_392
+CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN 28_111
+CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST 29_111
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808

diff --git a/artix7/segbits_cmt_top_r_lower_b.origin_info.db b/artix7/segbits_cmt_top_r_lower_b.origin_info.db
new file mode 100644
index 0000000..31c4804
--- /dev/null
+++ b/artix7/segbits_cmt_top_r_lower_b.origin_info.db

@@ -0,0 +1,396 @@
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_LR_LOWER_B_CLKFBOUT2IN origin:034b-cmt-mmcm-pips 28_980 28_981 29_980
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !28_1012 28_1013 29_1012 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !28_1012 !28_1013 29_1012 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1012 !29_1012 28_1013 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1012 !28_1013 !29_1012 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_IN3_HCLK origin:034b-cmt-mmcm-pips !28_1013 !29_1012 28_1012 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_IN3_INT origin:034b-cmt-mmcm-pips !29_1012 28_1012 28_1013 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !29_1013 28_1014 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !29_1013 !29_1014 28_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1014 !29_1013 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1014 !29_1013 !29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_IN1_HCLK origin:034b-cmt-mmcm-pips !28_1014 !29_1014 29_1013
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_IN1_INT origin:034b-cmt-mmcm-pips !28_1014 29_1013 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !28_1015 28_1016 29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !28_1015 !28_1016 29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1015 !29_1015 28_1016
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1015 !28_1016 !29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_IN2_HCLK origin:034b-cmt-mmcm-pips !28_1016 !29_1015 28_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_IN2_INT origin:034b-cmt-mmcm-pips !29_1015 28_1015 28_1016
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS0_ACTIVE origin:034b-cmt-mmcm-pips 28_1066 28_1074 29_1056
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS1_ACTIVE origin:034b-cmt-mmcm-pips 28_1057 28_1067 28_1075
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068 28_1076 29_1057
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
+CMT_TOP_R_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_1015 28_110 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1013 29_1018 29_110 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
+CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
+CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392
+CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
+CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808

diff --git a/artix7/segbits_cmt_top_r_upper_t.db b/artix7/segbits_cmt_top_r_upper_t.db
index e819e75..0f8bc38 100644
--- a/artix7/segbits_cmt_top_r_upper_t.db
+++ b/artix7/segbits_cmt_top_r_upper_t.db

@@ -1,364 +1,368 @@
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN !28_11 28_43 !28_44 !29_10 !29_11 29_42 29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN !28_11 !28_43 28_44 !29_10 29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 !28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT !28_11 !28_43 28_44 29_10 29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_09 !28_10 !29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 28_09 !28_10 !29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 !28_09 !28_10 29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 28_09 !28_10 29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 !28_09 28_10 !29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT 28_09 28_10 !29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_08 !29_07 !29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 !28_08 29_07 !29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 28_08 !29_07 !29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 28_08 29_07 !29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 !28_08 !29_07 29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT !28_08 29_07 29_08
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175
-CMT_TOP_R_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_06
-CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44
-CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_41 29_04
-CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_06
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183
-CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_05 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
-CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_722
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_200
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_200
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_201
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_201
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_202
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_202
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_203
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_203
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_204
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_204
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_208
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_208
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_209
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_209
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_210
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_210
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_211
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_211
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_212
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_212
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_192
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_192
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_193
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_193
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_194
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_194
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_195
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_195
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_196
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_196
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_205
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_205
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_206
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_206
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_207
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_213
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_213
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_214
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_214
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_215
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327
-CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_737
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_634
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_635
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_636
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_637
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_638
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_639
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_628
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_629
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_630
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_631
-CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_720
-CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_720
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN !28_01 !28_02 !28_43 28_75 !28_76 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_42 !29_43 29_74 29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN !28_01 !28_02 !28_43 !28_75 28_76 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_42 29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_01 !28_02 !28_43 !28_75 28_76 29_00 !29_01 29_09 !29_10 !29_11 !29_12 29_17 !29_18 !29_19 !29_20 !29_42 !29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 28_01 !28_02 !28_43 !28_75 28_76 !29_00 !29_01 !29_09 29_10 !29_11 !29_12 !29_17 29_18 !29_19 !29_20 29_42 !29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 !28_01 !28_02 28_43 !28_75 28_76 !29_00 29_01 !29_09 !29_10 29_11 !29_12 !29_17 !29_18 29_19 !29_20 !29_42 !29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 !28_01 28_02 28_43 !28_75 28_76 !29_00 !29_01 !29_09 !29_10 !29_11 29_12 !29_17 !29_18 !29_19 29_20 29_42 !29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT !28_01 !28_02 !28_43 !28_75 28_76 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 29_42 29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_01 !28_02 !28_41 !28_42 29_00 !29_01 29_09 !29_10 !29_11 !29_12 29_17 !29_18 !29_19 !29_20 !29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 28_01 !28_02 28_41 !28_42 !29_00 !29_01 !29_09 29_10 !29_11 !29_12 !29_17 29_18 !29_19 !29_20 !29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 !28_01 !28_02 !28_41 !28_42 !29_00 29_01 !29_09 !29_10 29_11 !29_12 !29_17 !29_18 29_19 !29_20 29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 !28_01 28_02 28_41 !28_42 !29_00 !29_01 !29_09 !29_10 !29_11 29_12 !29_17 !29_18 !29_19 29_20 29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 !28_01 !28_02 !28_41 28_42 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT !28_01 !28_02 28_41 28_42 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_01 !28_02 !28_40 29_00 !29_01 29_09 !29_10 !29_11 !29_12 29_17 !29_18 !29_19 !29_20 !29_39 !29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 28_01 !28_02 !28_40 !29_00 !29_01 !29_09 29_10 !29_11 !29_12 !29_17 29_18 !29_19 !29_20 29_39 !29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 !28_01 !28_02 28_40 !29_00 29_01 !29_09 !29_10 29_11 !29_12 !29_17 !29_18 29_19 !29_20 !29_39 !29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 !28_01 28_02 28_40 !29_00 !29_01 !29_09 !29_10 !29_11 29_12 !29_17 !29_18 !29_19 29_20 29_39 !29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 !28_01 !28_02 !28_40 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_39 29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT !28_01 !28_02 !28_40 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 29_39 29_40
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
+CMT_TOP_R_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_38
+CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
+CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
+CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_38
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215
+CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
+CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_754
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_232
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_232
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_233
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_233
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_234
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_234
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_235
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_235
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_236
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_236
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_240
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_240
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_241
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_241
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_242
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_242
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_243
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_243
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_244
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_244
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_224
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_224
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_225
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_225
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_226
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_226
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_227
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_227
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_228
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_228
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_237
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_237
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_238
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_238
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_239
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_245
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_245
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_246
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_246
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_247
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359
+CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_769
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_666
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_667
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_668
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_669
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_670
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_671
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_660
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_661
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_662
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_663
+CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_752
+CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_752
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247

diff --git a/artix7/segbits_cmt_top_r_upper_t.origin_info.db b/artix7/segbits_cmt_top_r_upper_t.origin_info.db
index c1782e8..9afcdc3 100644
--- a/artix7/segbits_cmt_top_r_upper_t.origin_info.db
+++ b/artix7/segbits_cmt_top_r_upper_t.origin_info.db

@@ -1,364 +1,368 @@
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN origin:034-cmt-pll-pips !28_11 !28_44 !29_10 !29_11 28_43 29_42 29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_42 !29_43 28_44 29_11
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_11 !29_42 !29_43 28_44
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_11 !28_43 !29_11 !29_42 !29_43 28_44 29_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_43 !29_10 !29_11 !29_42 !29_43 28_11 28_44
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_43 !29_11 !29_42 !29_43 28_11 28_44 29_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_11 !28_43 !29_42 !29_43 28_44 29_10 29_11
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_09 !28_10 !29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_10 !29_09 28_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_09 !28_10 29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_10 28_09 29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_09 !29_09 28_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !29_09 28_09 28_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_08 !29_07 !29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_08 !29_08 29_07
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !29_07 !29_08 28_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !29_08 28_08 29_07
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_08 !29_07 29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_08 29_07 29_08
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
-CMT_TOP_R_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_06
-CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44
-CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_41 29_04
-CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_06
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183
-CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
-CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327
-CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631
-CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720
-CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN origin:034-cmt-pll-pips !28_01 !28_02 !28_43 !28_76 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_42 !29_43 28_75 29_74 29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_01 !28_02 !28_43 !28_75 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_42 !29_74 !29_75 28_76 29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_01 !28_02 !28_43 !28_75 !29_01 !29_10 !29_11 !29_12 !29_18 !29_19 !29_20 !29_42 !29_43 !29_74 !29_75 28_76 29_00 29_09 29_17
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_02 !28_43 !28_75 !29_00 !29_01 !29_09 !29_11 !29_12 !29_17 !29_19 !29_20 !29_43 !29_74 !29_75 28_01 28_76 29_10 29_18 29_42
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_01 !28_02 !28_75 !29_00 !29_09 !29_10 !29_12 !29_17 !29_18 !29_20 !29_42 !29_43 !29_74 !29_75 28_43 28_76 29_01 29_11 29_19
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_01 !28_75 !29_00 !29_01 !29_09 !29_10 !29_11 !29_17 !29_18 !29_19 !29_43 !29_74 !29_75 28_02 28_43 28_76 29_12 29_20 29_42
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_01 !28_02 !28_43 !28_75 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_74 !29_75 28_76 29_42 29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_01 !28_02 !28_41 !28_42 !29_01 !29_10 !29_11 !29_12 !29_18 !29_19 !29_20 !29_41 29_00 29_09 29_17
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_02 !28_42 !29_00 !29_01 !29_09 !29_11 !29_12 !29_17 !29_19 !29_20 !29_41 28_01 28_41 29_10 29_18
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_01 !28_02 !28_41 !28_42 !29_00 !29_09 !29_10 !29_12 !29_17 !29_18 !29_20 29_01 29_11 29_19 29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_01 !28_42 !29_00 !29_01 !29_09 !29_10 !29_11 !29_17 !29_18 !29_19 28_02 28_41 29_12 29_20 29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_01 !28_02 !28_41 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_41 28_42
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !28_01 !28_02 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_41 28_41 28_42
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_01 !28_02 !28_40 !29_01 !29_10 !29_11 !29_12 !29_18 !29_19 !29_20 !29_39 !29_40 29_00 29_09 29_17
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_02 !28_40 !29_00 !29_01 !29_09 !29_11 !29_12 !29_17 !29_19 !29_20 !29_40 28_01 29_10 29_18 29_39
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_01 !28_02 !29_00 !29_09 !29_10 !29_12 !29_17 !29_18 !29_20 !29_39 !29_40 28_40 29_01 29_11 29_19
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_01 !29_00 !29_01 !29_09 !29_10 !29_11 !29_17 !29_18 !29_19 !29_40 28_02 28_40 29_12 29_20 29_39
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_01 !28_02 !28_40 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_39 29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_01 !28_02 !28_40 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 29_39 29_40
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09 29_17
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
+CMT_TOP_R_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_38
+CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
+CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
+CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_38
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
+CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
+CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
+CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663
+CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752
+CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247

diff --git a/artix7/segbits_int_l.origin_info.db b/artix7/segbits_int_l.origin_info.db
index 413247b..4c1eb1f 100644
--- a/artix7/segbits_int_l.origin_info.db
+++ b/artix7/segbits_int_l.origin_info.db

@@ -170,7 +170,7 @@
 INT_L.BYP_ALT7.BYP_BOUNCE6 origin:050-pip-seed !22_63 !23_63 !25_63 21_63 24_63
 INT_L.BYP_ALT7.EL1END_S3_0 origin:050-pip-seed !23_63 17_63 22_63 24_63 25_63
 INT_L.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
-INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
+INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:056-pip-rem !22_63 21_63 23_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_63 20_63 23_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
 INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
@@ -301,7 +301,7 @@
 INT_L.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
 INT_L.FAN_ALT0.LOGIC_OUTS_L0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
 INT_L.FAN_ALT0.LOGIC_OUTS_L12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
-INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
+INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
 INT_L.FAN_ALT0.SR1END_N3_3 origin:050-pip-seed !23_00 19_01 22_00 24_00 25_00
 INT_L.FAN_ALT0.SS2END_N0_3 origin:050-pip-seed !22_00 !23_00 !24_00 17_00 25_00
 INT_L.FAN_ALT0.SW2END_N0_3 origin:050-pip-seed !22_00 !23_00 !25_00 17_00 24_00
@@ -1917,7 +1917,7 @@
 INT_L.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
 INT_L.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
 INT_L.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
-INT_L.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
+INT_L.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
 INT_L.EE4BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_57 07_57
 INT_L.EE4BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_57 04_58
 INT_L.EE4BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_56 04_58
@@ -1937,7 +1937,7 @@
 INT_L.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
 INT_L.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
 INT_L.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_L.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
+INT_L.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
 INT_L.EL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_20 14_21
 INT_L.EL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_21 14_21
 INT_L.EL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_21 13_21
@@ -2233,7 +2233,7 @@
 INT_L.NE6BEG1.SE2END1 origin:050-pip-seed 02_21 05_23
 INT_L.NE6BEG1.SE6END1 origin:050-pip-seed 05_23 06_20
 INT_L.NE6BEG1.WW2END0 origin:050-pip-seed 03_20 04_21
-INT_L.NE6BEG1.WW4END1 origin:056-pip-rem 04_21 05_20
+INT_L.NE6BEG1.WW4END1 origin:050-pip-seed 04_21 05_20
 INT_L.NE6BEG2.LOGIC_OUTS_L2 origin:050-pip-seed 02_37 07_37
 INT_L.NE6BEG2.LOGIC_OUTS_L6 origin:050-pip-seed 02_37 04_38
 INT_L.NE6BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_36 04_38
@@ -2253,7 +2253,7 @@
 INT_L.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39
 INT_L.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36
 INT_L.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37
-INT_L.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36
+INT_L.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36
 INT_L.NE6BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_53 04_54
 INT_L.NE6BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_53 07_53
 INT_L.NE6BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_52 07_53
@@ -2662,7 +2662,7 @@
 INT_L.NW6BEG0.LOGIC_OUTS_L22 origin:050-pip-seed 06_02 07_03
 INT_L.NW6BEG0.LV_L0 origin:056-pip-rem 04_03 06_02
 INT_L.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00
-INT_L.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03
+INT_L.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03
 INT_L.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00
 INT_L.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03
 INT_L.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03
@@ -2887,7 +2887,7 @@
 INT_L.SE6BEG3.NE2END3 origin:050-pip-seed 03_58 04_56
 INT_L.SE6BEG3.NE6END3 origin:050-pip-seed 04_56 04_59
 INT_L.SE6BEG3.NN2END3 origin:050-pip-seed 02_59 04_56
-INT_L.SE6BEG3.NN6END3 origin:050-pip-seed 04_56 07_59
+INT_L.SE6BEG3.NN6END3 origin:056-pip-rem 04_56 07_59
 INT_L.SE6BEG3.SE2END3 origin:050-pip-seed 02_58 03_58
 INT_L.SE6BEG3.SE6END3 origin:050-pip-seed 02_58 07_59
 INT_L.SE6BEG3.SS2END3 origin:050-pip-seed 02_59 05_58
@@ -3302,7 +3302,7 @@
 INT_L.SW6BEG1.LOGIC_OUTS_L23 origin:050-pip-seed 04_30 06_28
 INT_L.SW6BEG1.LV_L9 origin:056-pip-rem 04_30 05_28
 INT_L.SW6BEG1.EE2END1 origin:050-pip-seed 03_28 04_29
-INT_L.SW6BEG1.EE4END1 origin:050-pip-seed 04_29 05_28
+INT_L.SW6BEG1.EE4END1 origin:056-pip-rem 04_29 05_28
 INT_L.SW6BEG1.LH6 origin:056-pip-rem 05_28 07_29
 INT_L.SW6BEG1.NW2END2 origin:050-pip-seed 02_29 05_31
 INT_L.SW6BEG1.NW6END2 origin:050-pip-seed 05_31 06_28
@@ -3323,7 +3323,7 @@
 INT_L.SW6BEG2.LVB_L0 origin:056-pip-rem 04_46 05_44
 INT_L.SW6BEG2.LVB_L12 origin:056-pip-rem 05_44 07_45
 INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
+INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
 INT_L.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
 INT_L.SW6BEG2.NW6END3 origin:050-pip-seed 05_47 06_44
 INT_L.SW6BEG2.SE2END2 origin:050-pip-seed 02_45 04_45

diff --git a/artix7/segbits_int_r.origin_info.db b/artix7/segbits_int_r.origin_info.db
index f91b2cd..eed46d5 100644
--- a/artix7/segbits_int_r.origin_info.db
+++ b/artix7/segbits_int_r.origin_info.db

@@ -332,7 +332,7 @@
 INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
-INT_R.FAN_ALT4.LOGIC_OUTS18 origin:056-pip-rem !22_08 !23_08 !25_08 21_08 24_08
+INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
 INT_R.FAN_ALT4.SR1BEG_S0 origin:050-pip-seed !23_08 19_09 22_08 24_08 25_08
 INT_R.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
 INT_R.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
@@ -685,7 +685,7 @@
 INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
 INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
 INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
-INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
+INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
 INT_R.EE4BEG2.LOGIC_OUTS2 origin:050-pip-seed 02_41 04_42
 INT_R.EE4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_41 07_41
 INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
@@ -725,7 +725,7 @@
 INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
 INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
 INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
+INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
 INT_R.EL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_20 14_21
 INT_R.EL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_21 14_21
 INT_R.EL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_21 13_21
@@ -2471,7 +2471,7 @@
 INT_R.NN6BEG2.NW2END2 origin:050-pip-seed 03_38 04_36
 INT_R.NN6BEG2.NW6END2 origin:050-pip-seed 04_36 07_39
 INT_R.NN6BEG2.SE2END2 origin:050-pip-seed 03_38 05_38
-INT_R.NN6BEG2.SE6END2 origin:050-pip-seed 05_38 07_39
+INT_R.NN6BEG2.SE6END2 origin:056-pip-rem 05_38 07_39
 INT_R.NN6BEG2.WW2END1 origin:050-pip-seed 02_39 04_36
 INT_R.NN6BEG2.WW4END2 origin:050-pip-seed 04_36 04_39
 INT_R.NN6BEG3.LOGIC_OUTS3 origin:050-pip-seed 03_54 06_54
@@ -3321,7 +3321,7 @@
 INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
 INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
 INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
 INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
 INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
 INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47

diff --git a/artix7/segbits_liob33.origin_info.db b/artix7/segbits_liob33.origin_info.db
index c0a134f..0490cb8 100644
--- a/artix7/segbits_liob33.origin_info.db
+++ b/artix7/segbits_liob33.origin_info.db

@@ -37,10 +37,10 @@
 LIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87
 LIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST origin:030-iob !38_106 38_110 39_105 39_107 39_109 39_111
 LIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45
-LIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_4 !38_6 !39_5 !39_7
-LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_4 38_6 39_5 39_7
-LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_6 38_4 39_5 39_7
-LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_6 !39_5 38_4 39_7
+LIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_04 !38_06 !39_05 !39_07
+LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07
+LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07
+LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07
 LIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
 LIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63
 LIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35

diff --git a/artix7/segbits_lioi3.db b/artix7/segbits_lioi3.db
index f781c22..465ab9b 100644
--- a/artix7/segbits_lioi3.db
+++ b/artix7/segbits_lioi3.db

@@ -40,6 +40,7 @@
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+LIOI3.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 LIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 LIOI3.ILOGIC_Y0.IDELMUXE3.P0 29_101
 LIOI3.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 LIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+LIOI3.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 LIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 LIOI3.OLOGIC_Y0.IS_D7_INVERTED 31_118
 LIOI3.OLOGIC_Y0.IS_D8_INVERTED 30_125
 LIOI3.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+LIOI3.OLOGIC_Y0.ODDR.SRUSED 32_112
+LIOI3.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 LIOI3.OLOGIC_Y0.OMUX.D1 33_111
 LIOI3.OLOGIC_Y0.OQUSED 31_86
 LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.IN_USE 33_73
 LIOI3.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 LIOI3.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 LIOI3.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 LIOI3.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+LIOI3.OLOGIC_Y0.TDDR.SRUSED 33_89
 LIOI3.OLOGIC_Y0.ZINIT_OQ 33_97
 LIOI3.OLOGIC_Y0.ZINIT_TQ 30_75
-LIOI3.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+LIOI3.OLOGIC_Y0.ZINV_CLK 31_90
 LIOI3.OLOGIC_Y0.ZINV_T1 30_67
 LIOI3.OLOGIC_Y0.ZINV_T2 30_71
 LIOI3.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 LIOI3.OLOGIC_Y1.IS_D7_INVERTED 30_09
 LIOI3.OLOGIC_Y1.IS_D8_INVERTED 31_02
 LIOI3.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+LIOI3.OLOGIC_Y1.ODDR.SRUSED 33_15
+LIOI3.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 LIOI3.OLOGIC_Y1.OMUX.D1 32_16
 LIOI3.OLOGIC_Y1.OQUSED 30_41
 LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.IN_USE 32_54
 LIOI3.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 LIOI3.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 LIOI3.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 LIOI3.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+LIOI3.OLOGIC_Y1.TDDR.SRUSED 32_38
 LIOI3.OLOGIC_Y1.ZINIT_OQ 32_30
 LIOI3.OLOGIC_Y1.ZINIT_TQ 31_52
-LIOI3.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+LIOI3.OLOGIC_Y1.ZINV_CLK 30_37
 LIOI3.OLOGIC_Y1.ZINV_T1 31_60
 LIOI3.OLOGIC_Y1.ZINV_T2 31_56
 LIOI3.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/artix7/segbits_lioi3.origin_info.db b/artix7/segbits_lioi3.origin_info.db
index a80d11c..e7e201c 100644
--- a/artix7/segbits_lioi3.origin_info.db
+++ b/artix7/segbits_lioi3.origin_info.db

@@ -40,6 +40,7 @@
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+LIOI3.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 LIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 LIOI3.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 LIOI3.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 LIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+LIOI3.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 LIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 LIOI3.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 LIOI3.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 LIOI3.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-LIOI3.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 LIOI3.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 LIOI3.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 LIOI3.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 LIOI3.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 LIOI3.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 LIOI3.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-LIOI3.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 LIOI3.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 LIOI3.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 LIOI3.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 LIOI3.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 LIOI3.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 LIOI3.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+LIOI3.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+LIOI3.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 LIOI3.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 LIOI3.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-LIOI3.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 LIOI3.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 LIOI3.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 LIOI3.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 LIOI3.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+LIOI3.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 LIOI3.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 LIOI3.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-LIOI3.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+LIOI3.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 LIOI3.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 LIOI3.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 LIOI3.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 LIOI3.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 LIOI3.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 LIOI3.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+LIOI3.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+LIOI3.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 LIOI3.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 LIOI3.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-LIOI3.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 LIOI3.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 LIOI3.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 LIOI3.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 LIOI3.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+LIOI3.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 LIOI3.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 LIOI3.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-LIOI3.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+LIOI3.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 LIOI3.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 LIOI3.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 LIOI3.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/artix7/segbits_lioi3_tbytesrc.db b/artix7/segbits_lioi3_tbytesrc.db
index 304a60b..f58db14 100644
--- a/artix7/segbits_lioi3_tbytesrc.db
+++ b/artix7/segbits_lioi3_tbytesrc.db

@@ -40,6 +40,7 @@
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+LIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 LIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 29_101
 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 LIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+LIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 LIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 LIOI3_TBYTESRC.OLOGIC_Y0.IS_D7_INVERTED 31_118
 LIOI3_TBYTESRC.OLOGIC_Y0.IS_D8_INVERTED 30_125
 LIOI3_TBYTESRC.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+LIOI3_TBYTESRC.OLOGIC_Y0.ODDR.SRUSED 32_112
+LIOI3_TBYTESRC.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 LIOI3_TBYTESRC.OLOGIC_Y0.OMUX.D1 33_111
 LIOI3_TBYTESRC.OLOGIC_Y0.OQUSED 31_86
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE 33_73
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+LIOI3_TBYTESRC.OLOGIC_Y0.TDDR.SRUSED 33_89
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_OQ 33_97
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_TQ 30_75
-LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK 31_90
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T1 30_67
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T2 30_71
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 LIOI3_TBYTESRC.OLOGIC_Y1.IS_D7_INVERTED 30_09
 LIOI3_TBYTESRC.OLOGIC_Y1.IS_D8_INVERTED 31_02
 LIOI3_TBYTESRC.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+LIOI3_TBYTESRC.OLOGIC_Y1.ODDR.SRUSED 33_15
+LIOI3_TBYTESRC.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 LIOI3_TBYTESRC.OLOGIC_Y1.OMUX.D1 32_16
 LIOI3_TBYTESRC.OLOGIC_Y1.OQUSED 30_41
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE 32_54
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+LIOI3_TBYTESRC.OLOGIC_Y1.TDDR.SRUSED 32_38
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_OQ 32_30
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_TQ 31_52
-LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK 30_37
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T1 31_60
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T2 31_56
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/artix7/segbits_lioi3_tbytesrc.origin_info.db b/artix7/segbits_lioi3_tbytesrc.origin_info.db
index 8d0ae06..2ac3c07 100644
--- a/artix7/segbits_lioi3_tbytesrc.origin_info.db
+++ b/artix7/segbits_lioi3_tbytesrc.origin_info.db

@@ -40,6 +40,7 @@
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+LIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 LIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 LIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+LIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 LIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 LIOI3_TBYTESRC.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 LIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 LIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 LIOI3_TBYTESRC.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 LIOI3_TBYTESRC.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 LIOI3_TBYTESRC.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+LIOI3_TBYTESRC.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+LIOI3_TBYTESRC.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 LIOI3_TBYTESRC.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 LIOI3_TBYTESRC.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+LIOI3_TBYTESRC.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 LIOI3_TBYTESRC.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 LIOI3_TBYTESRC.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 LIOI3_TBYTESRC.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+LIOI3_TBYTESRC.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+LIOI3_TBYTESRC.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 LIOI3_TBYTESRC.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 LIOI3_TBYTESRC.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+LIOI3_TBYTESRC.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/artix7/segbits_lioi3_tbyteterm.db b/artix7/segbits_lioi3_tbyteterm.db
index d60dde9..0c20c4d 100644
--- a/artix7/segbits_lioi3_tbyteterm.db
+++ b/artix7/segbits_lioi3_tbyteterm.db

@@ -40,6 +40,7 @@
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+LIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 LIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 29_101
 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 LIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+LIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 LIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 LIOI3_TBYTETERM.OLOGIC_Y0.IS_D7_INVERTED 31_118
 LIOI3_TBYTETERM.OLOGIC_Y0.IS_D8_INVERTED 30_125
 LIOI3_TBYTETERM.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+LIOI3_TBYTETERM.OLOGIC_Y0.ODDR.SRUSED 32_112
+LIOI3_TBYTETERM.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 LIOI3_TBYTETERM.OLOGIC_Y0.OMUX.D1 33_111
 LIOI3_TBYTETERM.OLOGIC_Y0.OQUSED 31_86
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE 33_73
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+LIOI3_TBYTETERM.OLOGIC_Y0.TDDR.SRUSED 33_89
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_OQ 33_97
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_TQ 30_75
-LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK 31_90
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T1 30_67
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T2 30_71
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 LIOI3_TBYTETERM.OLOGIC_Y1.IS_D7_INVERTED 30_09
 LIOI3_TBYTETERM.OLOGIC_Y1.IS_D8_INVERTED 31_02
 LIOI3_TBYTETERM.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+LIOI3_TBYTETERM.OLOGIC_Y1.ODDR.SRUSED 33_15
+LIOI3_TBYTETERM.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 LIOI3_TBYTETERM.OLOGIC_Y1.OMUX.D1 32_16
 LIOI3_TBYTETERM.OLOGIC_Y1.OQUSED 30_41
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE 32_54
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+LIOI3_TBYTETERM.OLOGIC_Y1.TDDR.SRUSED 32_38
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_OQ 32_30
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_TQ 31_52
-LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK 30_37
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T1 31_60
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T2 31_56
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/artix7/segbits_lioi3_tbyteterm.origin_info.db b/artix7/segbits_lioi3_tbyteterm.origin_info.db
index e72ab0e..8559928 100644
--- a/artix7/segbits_lioi3_tbyteterm.origin_info.db
+++ b/artix7/segbits_lioi3_tbyteterm.origin_info.db

@@ -40,6 +40,7 @@
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+LIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 LIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 LIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+LIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 LIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 LIOI3_TBYTETERM.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 LIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 LIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 LIOI3_TBYTETERM.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 LIOI3_TBYTETERM.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 LIOI3_TBYTETERM.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+LIOI3_TBYTETERM.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+LIOI3_TBYTETERM.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 LIOI3_TBYTETERM.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 LIOI3_TBYTETERM.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+LIOI3_TBYTETERM.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 LIOI3_TBYTETERM.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 LIOI3_TBYTETERM.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 LIOI3_TBYTETERM.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+LIOI3_TBYTETERM.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+LIOI3_TBYTETERM.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 LIOI3_TBYTETERM.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 LIOI3_TBYTETERM.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+LIOI3_TBYTETERM.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/artix7/segbits_riob33.origin_info.db b/artix7/segbits_riob33.origin_info.db
index a6d64c5..8db23c8 100644
--- a/artix7/segbits_riob33.origin_info.db
+++ b/artix7/segbits_riob33.origin_info.db

@@ -37,10 +37,10 @@
 RIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87
 RIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST origin:030-iob !38_106 38_110 39_105 39_107 39_109 39_111
 RIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45
-RIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_4 !38_6 !39_5 !39_7
-RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_4 38_6 39_5 39_7
-RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_6 38_4 39_5 39_7
-RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_6 !39_5 38_4 39_7
+RIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_04 !38_06 !39_05 !39_07
+RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07
+RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07
+RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07
 RIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
 RIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63
 RIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35

diff --git a/artix7/segbits_rioi3.db b/artix7/segbits_rioi3.db
index 852f46e..8d44a45 100644
--- a/artix7/segbits_rioi3.db
+++ b/artix7/segbits_rioi3.db

@@ -40,6 +40,7 @@
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+RIOI3.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 RIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 RIOI3.ILOGIC_Y0.IDELMUXE3.P0 29_101
 RIOI3.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 RIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+RIOI3.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 RIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 RIOI3.OLOGIC_Y0.IS_D7_INVERTED 31_118
 RIOI3.OLOGIC_Y0.IS_D8_INVERTED 30_125
 RIOI3.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+RIOI3.OLOGIC_Y0.ODDR.SRUSED 32_112
+RIOI3.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 RIOI3.OLOGIC_Y0.OMUX.D1 33_111
 RIOI3.OLOGIC_Y0.OQUSED 31_86
 RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.IN_USE 33_73
 RIOI3.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 RIOI3.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 RIOI3.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 RIOI3.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+RIOI3.OLOGIC_Y0.TDDR.SRUSED 33_89
 RIOI3.OLOGIC_Y0.ZINIT_OQ 33_97
 RIOI3.OLOGIC_Y0.ZINIT_TQ 30_75
-RIOI3.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+RIOI3.OLOGIC_Y0.ZINV_CLK 31_90
 RIOI3.OLOGIC_Y0.ZINV_T1 30_67
 RIOI3.OLOGIC_Y0.ZINV_T2 30_71
 RIOI3.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 RIOI3.OLOGIC_Y1.IS_D7_INVERTED 30_09
 RIOI3.OLOGIC_Y1.IS_D8_INVERTED 31_02
 RIOI3.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+RIOI3.OLOGIC_Y1.ODDR.SRUSED 33_15
+RIOI3.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 RIOI3.OLOGIC_Y1.OMUX.D1 32_16
 RIOI3.OLOGIC_Y1.OQUSED 30_41
 RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.IN_USE 32_54
 RIOI3.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 RIOI3.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 RIOI3.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 RIOI3.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+RIOI3.OLOGIC_Y1.TDDR.SRUSED 32_38
 RIOI3.OLOGIC_Y1.ZINIT_OQ 32_30
 RIOI3.OLOGIC_Y1.ZINIT_TQ 31_52
-RIOI3.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+RIOI3.OLOGIC_Y1.ZINV_CLK 30_37
 RIOI3.OLOGIC_Y1.ZINV_T1 31_60
 RIOI3.OLOGIC_Y1.ZINV_T2 31_56
 RIOI3.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/artix7/segbits_rioi3.origin_info.db b/artix7/segbits_rioi3.origin_info.db
index 5c6e73b..a796d38 100644
--- a/artix7/segbits_rioi3.origin_info.db
+++ b/artix7/segbits_rioi3.origin_info.db

@@ -40,6 +40,7 @@
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+RIOI3.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 RIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 RIOI3.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 RIOI3.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 RIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+RIOI3.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 RIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 RIOI3.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 RIOI3.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 RIOI3.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-RIOI3.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 RIOI3.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 RIOI3.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 RIOI3.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 RIOI3.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 RIOI3.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 RIOI3.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-RIOI3.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 RIOI3.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 RIOI3.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 RIOI3.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 RIOI3.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 RIOI3.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 RIOI3.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+RIOI3.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+RIOI3.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 RIOI3.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 RIOI3.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-RIOI3.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 RIOI3.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 RIOI3.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 RIOI3.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 RIOI3.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+RIOI3.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 RIOI3.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 RIOI3.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-RIOI3.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+RIOI3.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 RIOI3.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 RIOI3.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 RIOI3.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 RIOI3.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 RIOI3.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 RIOI3.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+RIOI3.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+RIOI3.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 RIOI3.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 RIOI3.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-RIOI3.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 RIOI3.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 RIOI3.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 RIOI3.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 RIOI3.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+RIOI3.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 RIOI3.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 RIOI3.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-RIOI3.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+RIOI3.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 RIOI3.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 RIOI3.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 RIOI3.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/artix7/segbits_rioi3_tbytesrc.db b/artix7/segbits_rioi3_tbytesrc.db
index c2b6214..87be7f7 100644
--- a/artix7/segbits_rioi3_tbytesrc.db
+++ b/artix7/segbits_rioi3_tbytesrc.db

@@ -40,6 +40,7 @@
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+RIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 RIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 29_101
 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 RIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+RIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 RIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 RIOI3_TBYTESRC.OLOGIC_Y0.IS_D7_INVERTED 31_118
 RIOI3_TBYTESRC.OLOGIC_Y0.IS_D8_INVERTED 30_125
 RIOI3_TBYTESRC.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+RIOI3_TBYTESRC.OLOGIC_Y0.ODDR.SRUSED 32_112
+RIOI3_TBYTESRC.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 RIOI3_TBYTESRC.OLOGIC_Y0.OMUX.D1 33_111
 RIOI3_TBYTESRC.OLOGIC_Y0.OQUSED 31_86
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE 33_73
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+RIOI3_TBYTESRC.OLOGIC_Y0.TDDR.SRUSED 33_89
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_OQ 33_97
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_TQ 30_75
-RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK 31_90
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T1 30_67
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T2 30_71
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 RIOI3_TBYTESRC.OLOGIC_Y1.IS_D7_INVERTED 30_09
 RIOI3_TBYTESRC.OLOGIC_Y1.IS_D8_INVERTED 31_02
 RIOI3_TBYTESRC.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+RIOI3_TBYTESRC.OLOGIC_Y1.ODDR.SRUSED 33_15
+RIOI3_TBYTESRC.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 RIOI3_TBYTESRC.OLOGIC_Y1.OMUX.D1 32_16
 RIOI3_TBYTESRC.OLOGIC_Y1.OQUSED 30_41
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE 32_54
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+RIOI3_TBYTESRC.OLOGIC_Y1.TDDR.SRUSED 32_38
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_OQ 32_30
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_TQ 31_52
-RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK 30_37
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T1 31_60
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T2 31_56
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/artix7/segbits_rioi3_tbytesrc.origin_info.db b/artix7/segbits_rioi3_tbytesrc.origin_info.db
index 440fa78..23c8e8e 100644
--- a/artix7/segbits_rioi3_tbytesrc.origin_info.db
+++ b/artix7/segbits_rioi3_tbytesrc.origin_info.db

@@ -40,6 +40,7 @@
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+RIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 RIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 RIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+RIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 RIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 RIOI3_TBYTESRC.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 RIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 RIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 RIOI3_TBYTESRC.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 RIOI3_TBYTESRC.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 RIOI3_TBYTESRC.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+RIOI3_TBYTESRC.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+RIOI3_TBYTESRC.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 RIOI3_TBYTESRC.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 RIOI3_TBYTESRC.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+RIOI3_TBYTESRC.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 RIOI3_TBYTESRC.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 RIOI3_TBYTESRC.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 RIOI3_TBYTESRC.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+RIOI3_TBYTESRC.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+RIOI3_TBYTESRC.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 RIOI3_TBYTESRC.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 RIOI3_TBYTESRC.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+RIOI3_TBYTESRC.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/artix7/segbits_rioi3_tbyteterm.db b/artix7/segbits_rioi3_tbyteterm.db
index bafc348..95901a8 100644
--- a/artix7/segbits_rioi3_tbyteterm.db
+++ b/artix7/segbits_rioi3_tbyteterm.db

@@ -40,6 +40,7 @@
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+RIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 RIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 29_101
 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 RIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+RIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 RIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 RIOI3_TBYTETERM.OLOGIC_Y0.IS_D7_INVERTED 31_118
 RIOI3_TBYTETERM.OLOGIC_Y0.IS_D8_INVERTED 30_125
 RIOI3_TBYTETERM.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+RIOI3_TBYTETERM.OLOGIC_Y0.ODDR.SRUSED 32_112
+RIOI3_TBYTETERM.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 RIOI3_TBYTETERM.OLOGIC_Y0.OMUX.D1 33_111
 RIOI3_TBYTETERM.OLOGIC_Y0.OQUSED 31_86
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE 33_73
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+RIOI3_TBYTETERM.OLOGIC_Y0.TDDR.SRUSED 33_89
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_OQ 33_97
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_TQ 30_75
-RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK 31_90
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T1 30_67
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T2 30_71
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 RIOI3_TBYTETERM.OLOGIC_Y1.IS_D7_INVERTED 30_09
 RIOI3_TBYTETERM.OLOGIC_Y1.IS_D8_INVERTED 31_02
 RIOI3_TBYTETERM.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+RIOI3_TBYTETERM.OLOGIC_Y1.ODDR.SRUSED 33_15
+RIOI3_TBYTETERM.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 RIOI3_TBYTETERM.OLOGIC_Y1.OMUX.D1 32_16
 RIOI3_TBYTETERM.OLOGIC_Y1.OQUSED 30_41
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE 32_54
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+RIOI3_TBYTETERM.OLOGIC_Y1.TDDR.SRUSED 32_38
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_OQ 32_30
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_TQ 31_52
-RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK 30_37
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T1 31_60
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T2 31_56
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/artix7/segbits_rioi3_tbyteterm.origin_info.db b/artix7/segbits_rioi3_tbyteterm.origin_info.db
index 106e4ad..d2489b9 100644
--- a/artix7/segbits_rioi3_tbyteterm.origin_info.db
+++ b/artix7/segbits_rioi3_tbyteterm.origin_info.db

@@ -40,6 +40,7 @@
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+RIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 RIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 RIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+RIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 RIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 RIOI3_TBYTETERM.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 RIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 RIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 RIOI3_TBYTETERM.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 RIOI3_TBYTETERM.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 RIOI3_TBYTETERM.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+RIOI3_TBYTETERM.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+RIOI3_TBYTETERM.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 RIOI3_TBYTETERM.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 RIOI3_TBYTETERM.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+RIOI3_TBYTETERM.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 RIOI3_TBYTETERM.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 RIOI3_TBYTETERM.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 RIOI3_TBYTETERM.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+RIOI3_TBYTETERM.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+RIOI3_TBYTETERM.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 RIOI3_TBYTETERM.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 RIOI3_TBYTETERM.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+RIOI3_TBYTETERM.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/artix7/xc7a100tcsg324-1/tilegrid.json b/artix7/xc7a100tcsg324-1/tilegrid.json
index 434a65b..c5fb322 100644
--- a/artix7/xc7a100tcsg324-1/tilegrid.json
+++ b/artix7/xc7a100tcsg324-1/tilegrid.json

@@ -173498,7 +173498,7 @@
                 "baseaddr": "0x00401C00",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y1",
@@ -173517,7 +173517,7 @@
                 "baseaddr": "0x00001C00",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y2",
@@ -173599,8 +173599,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00401C00",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y1",
@@ -173618,8 +173618,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00001C00",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y2",
@@ -173638,7 +173638,7 @@
                 "baseaddr": "0x00420080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y0",
@@ -173657,7 +173657,7 @@
                 "baseaddr": "0x00400080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y1",
@@ -173676,7 +173676,7 @@
                 "baseaddr": "0x00000080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y2",
@@ -173695,7 +173695,7 @@
                 "baseaddr": "0x00020080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y3",
@@ -173841,8 +173841,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00420080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y0",
@@ -173860,8 +173860,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00400080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y1",
@@ -173879,8 +173879,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00000080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y2",
@@ -173898,8 +173898,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00020080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y3",

diff --git a/artix7/xc7a100tfgg676-1/tilegrid.json b/artix7/xc7a100tfgg676-1/tilegrid.json
index 434a65b..c5fb322 100644
--- a/artix7/xc7a100tfgg676-1/tilegrid.json
+++ b/artix7/xc7a100tfgg676-1/tilegrid.json

@@ -173498,7 +173498,7 @@
                 "baseaddr": "0x00401C00",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y1",
@@ -173517,7 +173517,7 @@
                 "baseaddr": "0x00001C00",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y2",
@@ -173599,8 +173599,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00401C00",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y1",
@@ -173618,8 +173618,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00001C00",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y2",
@@ -173638,7 +173638,7 @@
                 "baseaddr": "0x00420080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y0",
@@ -173657,7 +173657,7 @@
                 "baseaddr": "0x00400080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y1",
@@ -173676,7 +173676,7 @@
                 "baseaddr": "0x00000080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y2",
@@ -173695,7 +173695,7 @@
                 "baseaddr": "0x00020080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y3",
@@ -173841,8 +173841,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00420080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y0",
@@ -173860,8 +173860,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00400080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y1",
@@ -173879,8 +173879,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00000080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y2",
@@ -173898,8 +173898,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00020080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y3",

diff --git a/artix7/xc7a200tffg1156-1/tilegrid.json b/artix7/xc7a200tffg1156-1/tilegrid.json
index e1920f9..0c8170d 100644
--- a/artix7/xc7a200tffg1156-1/tilegrid.json
+++ b/artix7/xc7a200tffg1156-1/tilegrid.json

@@ -373257,7 +373257,7 @@
                 "baseaddr": "0x00443400",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y0",
@@ -373276,7 +373276,7 @@
                 "baseaddr": "0x00423400",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y1",
@@ -373295,7 +373295,7 @@
                 "baseaddr": "0x00403400",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y2",
@@ -373314,7 +373314,7 @@
                 "baseaddr": "0x00003400",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y3",
@@ -373333,7 +373333,7 @@
                 "baseaddr": "0x00023400",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y4",
@@ -373511,8 +373511,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00443400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y0",
@@ -373530,8 +373530,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00423400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y1",
@@ -373549,8 +373549,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00403400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y2",
@@ -373568,8 +373568,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00003400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y3",
@@ -373587,8 +373587,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00023400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y4",
@@ -373607,7 +373607,7 @@
                 "baseaddr": "0x00440080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y0",
@@ -373626,7 +373626,7 @@
                 "baseaddr": "0x00420080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y1",
@@ -373645,7 +373645,7 @@
                 "baseaddr": "0x00400080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y2",
@@ -373664,7 +373664,7 @@
                 "baseaddr": "0x00000080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y3",
@@ -373683,7 +373683,7 @@
                 "baseaddr": "0x00020080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y4",
@@ -373861,8 +373861,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00440080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y0",
@@ -373880,8 +373880,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00420080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y1",
@@ -373899,8 +373899,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00400080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y2",
@@ -373918,8 +373918,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00000080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y3",
@@ -373937,8 +373937,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00020080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y4",

diff --git a/artix7/xc7a200tsbg484-1/tilegrid.json b/artix7/xc7a200tsbg484-1/tilegrid.json
index e1920f9..0c8170d 100644
--- a/artix7/xc7a200tsbg484-1/tilegrid.json
+++ b/artix7/xc7a200tsbg484-1/tilegrid.json

@@ -373257,7 +373257,7 @@
                 "baseaddr": "0x00443400",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y0",
@@ -373276,7 +373276,7 @@
                 "baseaddr": "0x00423400",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y1",
@@ -373295,7 +373295,7 @@
                 "baseaddr": "0x00403400",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y2",
@@ -373314,7 +373314,7 @@
                 "baseaddr": "0x00003400",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y3",
@@ -373333,7 +373333,7 @@
                 "baseaddr": "0x00023400",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y4",
@@ -373511,8 +373511,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00443400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y0",
@@ -373530,8 +373530,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00423400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y1",
@@ -373549,8 +373549,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00403400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y2",
@@ -373568,8 +373568,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00003400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y3",
@@ -373587,8 +373587,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00023400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y4",
@@ -373607,7 +373607,7 @@
                 "baseaddr": "0x00440080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y0",
@@ -373626,7 +373626,7 @@
                 "baseaddr": "0x00420080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y1",
@@ -373645,7 +373645,7 @@
                 "baseaddr": "0x00400080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y2",
@@ -373664,7 +373664,7 @@
                 "baseaddr": "0x00000080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y3",
@@ -373683,7 +373683,7 @@
                 "baseaddr": "0x00020080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y4",
@@ -373861,8 +373861,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00440080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y0",
@@ -373880,8 +373880,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00420080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y1",
@@ -373899,8 +373899,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00400080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y2",
@@ -373918,8 +373918,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00000080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y3",
@@ -373937,8 +373937,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00020080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y4",

diff --git a/artix7/xc7a35tcpg236-1/tilegrid.json b/artix7/xc7a35tcpg236-1/tilegrid.json
index e244b10..4a4ff13 100644
--- a/artix7/xc7a35tcpg236-1/tilegrid.json
+++ b/artix7/xc7a35tcpg236-1/tilegrid.json

@@ -90144,7 +90144,7 @@
                 "baseaddr": "0x00401500",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y0",
@@ -90163,7 +90163,7 @@
                 "baseaddr": "0x00001500",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y1",
@@ -90245,8 +90245,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00401500",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y0",
@@ -90264,8 +90264,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00001500",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y1",
@@ -90284,7 +90284,7 @@
                 "baseaddr": "0x00400080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y0",
@@ -90303,7 +90303,7 @@
                 "baseaddr": "0x00000080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y1",
@@ -90322,7 +90322,7 @@
                 "baseaddr": "0x00020080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y2",
@@ -90436,8 +90436,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00400080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y0",
@@ -90455,8 +90455,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00000080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y1",
@@ -90474,8 +90474,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00020080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y2",

diff --git a/artix7/xc7a35tcsg324-1/tilegrid.json b/artix7/xc7a35tcsg324-1/tilegrid.json
index e244b10..4a4ff13 100644
--- a/artix7/xc7a35tcsg324-1/tilegrid.json
+++ b/artix7/xc7a35tcsg324-1/tilegrid.json

@@ -90144,7 +90144,7 @@
                 "baseaddr": "0x00401500",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y0",
@@ -90163,7 +90163,7 @@
                 "baseaddr": "0x00001500",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y1",
@@ -90245,8 +90245,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00401500",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y0",
@@ -90264,8 +90264,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00001500",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y1",
@@ -90284,7 +90284,7 @@
                 "baseaddr": "0x00400080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y0",
@@ -90303,7 +90303,7 @@
                 "baseaddr": "0x00000080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y1",
@@ -90322,7 +90322,7 @@
                 "baseaddr": "0x00020080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y2",
@@ -90436,8 +90436,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00400080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y0",
@@ -90455,8 +90455,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00000080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y1",
@@ -90474,8 +90474,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00020080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y2",

diff --git a/artix7/xc7a35tftg256-1/tilegrid.json b/artix7/xc7a35tftg256-1/tilegrid.json
index e244b10..4a4ff13 100644
--- a/artix7/xc7a35tftg256-1/tilegrid.json
+++ b/artix7/xc7a35tftg256-1/tilegrid.json

@@ -90144,7 +90144,7 @@
                 "baseaddr": "0x00401500",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y0",
@@ -90163,7 +90163,7 @@
                 "baseaddr": "0x00001500",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y1",
@@ -90245,8 +90245,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00401500",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y0",
@@ -90264,8 +90264,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00001500",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y1",
@@ -90284,7 +90284,7 @@
                 "baseaddr": "0x00400080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y0",
@@ -90303,7 +90303,7 @@
                 "baseaddr": "0x00000080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y1",
@@ -90322,7 +90322,7 @@
                 "baseaddr": "0x00020080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y2",
@@ -90436,8 +90436,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00400080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y0",
@@ -90455,8 +90455,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00000080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y1",
@@ -90474,8 +90474,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00020080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y2",

diff --git a/artix7/xc7a50tfgg484-1/tilegrid.json b/artix7/xc7a50tfgg484-1/tilegrid.json
index e244b10..4a4ff13 100644
--- a/artix7/xc7a50tfgg484-1/tilegrid.json
+++ b/artix7/xc7a50tfgg484-1/tilegrid.json

@@ -90144,7 +90144,7 @@
                 "baseaddr": "0x00401500",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y0",
@@ -90163,7 +90163,7 @@
                 "baseaddr": "0x00001500",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y1",
@@ -90245,8 +90245,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00401500",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y0",
@@ -90264,8 +90264,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00001500",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y1",
@@ -90284,7 +90284,7 @@
                 "baseaddr": "0x00400080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y0",
@@ -90303,7 +90303,7 @@
                 "baseaddr": "0x00000080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y1",
@@ -90322,7 +90322,7 @@
                 "baseaddr": "0x00020080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y2",
@@ -90436,8 +90436,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00400080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y0",
@@ -90455,8 +90455,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00000080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y1",
@@ -90474,8 +90474,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00020080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y2",

diff --git a/kintex7/mask_lioi3.db b/kintex7/mask_lioi3.db
index 4c3181d..584510c 100644
--- a/kintex7/mask_lioi3.db
+++ b/kintex7/mask_lioi3.db

@@ -1,7 +1,7 @@
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
-bit 25_31
 bit 25_32
 bit 25_34
 bit 25_35

diff --git a/kintex7/mask_lioi3_tbytesrc.db b/kintex7/mask_lioi3_tbytesrc.db
index 4c3181d..584510c 100644
--- a/kintex7/mask_lioi3_tbytesrc.db
+++ b/kintex7/mask_lioi3_tbytesrc.db

@@ -1,7 +1,7 @@
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
-bit 25_31
 bit 25_32
 bit 25_34
 bit 25_35

diff --git a/kintex7/mask_lioi3_tbyteterm.db b/kintex7/mask_lioi3_tbyteterm.db
index 4c3181d..584510c 100644
--- a/kintex7/mask_lioi3_tbyteterm.db
+++ b/kintex7/mask_lioi3_tbyteterm.db

@@ -1,7 +1,7 @@
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
-bit 25_31
 bit 25_32
 bit 25_34
 bit 25_35

diff --git a/kintex7/mask_rioi3.db b/kintex7/mask_rioi3.db
index 4c3181d..584510c 100644
--- a/kintex7/mask_rioi3.db
+++ b/kintex7/mask_rioi3.db

@@ -1,7 +1,7 @@
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
-bit 25_31
 bit 25_32
 bit 25_34
 bit 25_35

diff --git a/kintex7/mask_rioi3_tbytesrc.db b/kintex7/mask_rioi3_tbytesrc.db
index 4c3181d..584510c 100644
--- a/kintex7/mask_rioi3_tbytesrc.db
+++ b/kintex7/mask_rioi3_tbytesrc.db

@@ -1,7 +1,7 @@
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
-bit 25_31
 bit 25_32
 bit 25_34
 bit 25_35

diff --git a/kintex7/mask_rioi3_tbyteterm.db b/kintex7/mask_rioi3_tbyteterm.db
index 4c3181d..584510c 100644
--- a/kintex7/mask_rioi3_tbyteterm.db
+++ b/kintex7/mask_rioi3_tbyteterm.db

@@ -1,7 +1,7 @@
 bit 25_07
+bit 25_16
 bit 25_20
 bit 25_21
-bit 25_31
 bit 25_32
 bit 25_34
 bit 25_35

diff --git a/kintex7/segbits_clk_bufg_bot_r.origin_info.db b/kintex7/segbits_clk_bufg_bot_r.origin_info.db
index f18cf2e..f679954 100644
--- a/kintex7/segbits_clk_bufg_bot_r.origin_info.db
+++ b/kintex7/segbits_clk_bufg_bot_r.origin_info.db

@@ -178,159 +178,159 @@
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_08 26_07 27_06
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_08 !27_06 26_07
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_07 !26_08 27_06
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_07 !26_08 !27_06
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_07 !26_08 !27_06
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_BOT_R_CK_MUXED1 origin:046-clk-bufg-muxed-pips !26_05 !27_05 26_04
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_04 26_05 27_05
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_04 !26_05 27_05
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_04 !27_05 26_05
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_04 !26_05 !27_05
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_04 !26_05 !27_05
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_BOT_R_CK_MUXED2 origin:046-clk-bufg-muxed-pips !26_23 !27_22 26_24
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_24 !27_22 26_23
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_24 26_23 27_22
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_23 !26_24 27_22
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_23 !26_24 !27_22
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_23 !26_24 !27_22
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_BOT_R_CK_MUXED3 origin:046-clk-bufg-muxed-pips !26_21 !27_21 26_20
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_20 !26_21 27_21
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_20 26_21 27_21
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_20 !27_21 26_21
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_20 !26_21 !27_21
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_20 !26_21 !27_21
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_BOT_R_CK_MUXED4 origin:046-clk-bufg-muxed-pips !26_39 !27_38 26_40
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_40 !27_38 26_39
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_40 26_39 27_38
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_39 !26_40 27_38
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_39 !26_40 !27_38
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_39 !26_40 !27_38
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_BOT_R_CK_MUXED5 origin:046-clk-bufg-muxed-pips !26_37 !27_37 26_36
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_36 !26_37 27_37
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_36 26_37 27_37
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_36 !27_37 26_37
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_36 !26_37 !27_37
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_36 !26_37 !27_37
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_BOT_R_CK_MUXED6 origin:046-clk-bufg-muxed-pips !26_55 !27_54 26_56
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_56 !27_54 26_55
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_56 26_55 27_54
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_55 !26_56 27_54
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_55 !26_56 !27_54
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_55 !26_56 !27_54
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_BOT_R_CK_MUXED7 origin:046-clk-bufg-muxed-pips !26_53 !27_53 26_52
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_52 !26_53 27_53
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_52 26_53 27_53
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_52 !27_53 26_53
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_52 !26_53 !27_53
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_52 !26_53 !27_53
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_BOT_R_CK_MUXED8 origin:046-clk-bufg-muxed-pips !26_71 !27_70 26_72
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_72 !27_70 26_71
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_72 26_71 27_70
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_71 !26_72 27_70
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_71 !26_72 !27_70
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_71 !26_72 !27_70
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_BOT_R_CK_MUXED9 origin:046-clk-bufg-muxed-pips !26_69 !27_69 26_68
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_68 !26_69 27_69
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_68 26_69 27_69
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_68 !27_69 26_69
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_68 !26_69 !27_69
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_68 !26_69 !27_69
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_BOT_R_CK_MUXED10 origin:046-clk-bufg-muxed-pips !26_87 !27_86 26_88
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_88 !27_86 26_87
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_88 26_87 27_86
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_87 !26_88 27_86
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_87 !26_88 !27_86
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_87 !26_88 !27_86
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_BOT_R_CK_MUXED11 origin:046-clk-bufg-muxed-pips !26_85 !27_85 26_84
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_84 !26_85 27_85
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_84 26_85 27_85
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_84 !27_85 26_85
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_84 !26_85 !27_85
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_84 !26_85 !27_85
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_BOT_R_CK_MUXED12 origin:046-clk-bufg-muxed-pips !26_103 !27_102 26_104
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_104 !27_102 26_103
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_104 26_103 27_102
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_103 !26_104 27_102
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_103 !26_104 !27_102
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_103 !26_104 !27_102
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_BOT_R_CK_MUXED13 origin:046-clk-bufg-muxed-pips !26_101 !27_101 26_100
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_100 !26_101 27_101
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_100 26_101 27_101
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_100 !27_101 26_101
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_100 !26_101 !27_101
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_100 !26_101 !27_101
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_BOT_R_CK_MUXED14 origin:046-clk-bufg-muxed-pips !26_119 !27_118 26_120
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_120 !27_118 26_119
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_120 26_119 27_118
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_119 !26_120 27_118
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_119 !26_120 !27_118
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_119 !26_120 !27_118
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_BOT_R_CK_MUXED15 origin:046-clk-bufg-muxed-pips !26_117 !27_117 26_116
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_116 !26_117 27_117
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_116 26_117 27_117
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_116 !27_117 26_117
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_116 !26_117 !27_117
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_116 !26_117 !27_117
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_BOT_R_CK_MUXED16 origin:046-clk-bufg-muxed-pips !26_135 !27_134 26_136
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_136 !27_134 26_135
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_136 26_135 27_134
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_135 !26_136 27_134
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_135 !26_136 !27_134
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_135 !26_136 !27_134
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_BOT_R_CK_MUXED17 origin:046-clk-bufg-muxed-pips !26_133 !27_133 26_132
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_132 !26_133 27_133
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_132 26_133 27_133
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_132 !27_133 26_133
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_132 !26_133 !27_133
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_132 !26_133 !27_133
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_BOT_R_CK_MUXED18 origin:046-clk-bufg-muxed-pips !26_151 !27_150 26_152
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_152 !27_150 26_151
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_152 26_151 27_150
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_151 !26_152 27_150
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_151 !26_152 !27_150
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_151 !26_152 !27_150
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_BOT_R_CK_MUXED19 origin:046-clk-bufg-muxed-pips !26_149 !27_149 26_148
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_148 !26_149 27_149
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_148 26_149 27_149
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_148 !27_149 26_149
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_148 !26_149 !27_149
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_148 !26_149 !27_149
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_BOT_R_CK_MUXED20 origin:046-clk-bufg-muxed-pips !26_167 !27_166 26_168
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_168 !27_166 26_167
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_168 26_167 27_166
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_167 !26_168 27_166
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_167 !26_168 !27_166
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_167 !26_168 !27_166
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_BOT_R_CK_MUXED21 origin:046-clk-bufg-muxed-pips !26_165 !27_165 26_164
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_164 !26_165 27_165
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_164 26_165 27_165
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_164 !27_165 26_165
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_164 !26_165 !27_165
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_164 !26_165 !27_165
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_BOT_R_CK_MUXED22 origin:046-clk-bufg-muxed-pips !26_183 !27_182 26_184
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_184 !27_182 26_183
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_184 26_183 27_182
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_183 !26_184 27_182
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_183 !26_184 !27_182
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_183 !26_184 !27_182
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_BOT_R_CK_MUXED23 origin:046-clk-bufg-muxed-pips !26_181 !27_181 26_180
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_180 !26_181 27_181
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_180 26_181 27_181
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_180 !27_181 26_181
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_180 !26_181 !27_181
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_180 !26_181 !27_181
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_BOT_R_CK_MUXED24 origin:046-clk-bufg-muxed-pips !26_199 !27_198 26_200
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_200 !27_198 26_199
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_200 26_199 27_198
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_199 !26_200 27_198
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_199 !26_200 !27_198
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_199 !26_200 !27_198
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_BOT_R_CK_MUXED25 origin:046-clk-bufg-muxed-pips !26_197 !27_197 26_196
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_196 !26_197 27_197
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_196 26_197 27_197
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_196 !27_197 26_197
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_196 !26_197 !27_197
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_196 !26_197 !27_197
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_BOT_R_CK_MUXED26 origin:046-clk-bufg-muxed-pips !26_215 !27_214 26_216
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_216 !27_214 26_215
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_216 26_215 27_214
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_215 !26_216 27_214
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_215 !26_216 !27_214
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_215 !26_216 !27_214
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_BOT_R_CK_MUXED27 origin:046-clk-bufg-muxed-pips !26_213 !27_213 26_212
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_212 !26_213 27_213
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_212 26_213 27_213
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_212 !27_213 26_213
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_212 !26_213 !27_213
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_212 !26_213 !27_213
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_BOT_R_CK_MUXED28 origin:046-clk-bufg-muxed-pips !26_231 !27_230 26_232
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_232 !27_230 26_231
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_232 26_231 27_230
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_231 !26_232 27_230
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_231 !26_232 !27_230
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_231 !26_232 !27_230
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_BOT_R_CK_MUXED29 origin:046-clk-bufg-muxed-pips !26_229 !27_229 26_228
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_228 !26_229 27_229
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_228 26_229 27_229
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_228 !27_229 26_229
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_228 !26_229 !27_229
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_228 !26_229 !27_229
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_BOT_R_CK_MUXED30 origin:046-clk-bufg-muxed-pips !26_247 !27_246 26_248
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_248 26_247 27_246
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_248 !27_246 26_247
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_247 !26_248 27_246
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_247 !26_248 !27_246
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_247 !26_248 !27_246
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_BOT_R_CK_MUXED31 origin:046-clk-bufg-muxed-pips !26_245 !27_245 26_244
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_244 26_245 27_245
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_244 !26_245 27_245
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_244 !27_245 26_245
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_244 !26_245 !27_245
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_244 !26_245 !27_245

diff --git a/kintex7/segbits_clk_bufg_top_r.origin_info.db b/kintex7/segbits_clk_bufg_top_r.origin_info.db
index b23f2e4..ddcc016 100644
--- a/kintex7/segbits_clk_bufg_top_r.origin_info.db
+++ b/kintex7/segbits_clk_bufg_top_r.origin_info.db

@@ -178,159 +178,159 @@
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_08 !27_06 26_07
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0 origin:046-clk-bufg-muxed-pips !26_07 !27_06 26_08
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_07 !26_08 27_06
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_07 !26_08 !27_06
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_07 !26_08 !27_06
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_04 26_05 27_05
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_04 !26_05 27_05
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_TOP_R_CK_MUXED1 origin:046-clk-bufg-muxed-pips !26_05 !27_05 26_04
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_04 !27_05 26_05
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_04 !26_05 !27_05
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_04 !26_05 !27_05
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_24 !27_22 26_23
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_24 26_23 27_22
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_TOP_R_CK_MUXED2 origin:046-clk-bufg-muxed-pips !26_23 !27_22 26_24
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_23 !26_24 27_22
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_23 !26_24 !27_22
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_23 !26_24 !27_22
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_20 !26_21 27_21
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_20 26_21 27_21
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_TOP_R_CK_MUXED3 origin:046-clk-bufg-muxed-pips !26_21 !27_21 26_20
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_20 !27_21 26_21
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_20 !26_21 !27_21
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_20 !26_21 !27_21
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_40 !27_38 26_39
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_40 26_39 27_38
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_TOP_R_CK_MUXED4 origin:046-clk-bufg-muxed-pips !26_39 !27_38 26_40
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_39 !26_40 27_38
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_39 !26_40 !27_38
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_39 !26_40 !27_38
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_36 !26_37 27_37
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_36 26_37 27_37
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_TOP_R_CK_MUXED5 origin:046-clk-bufg-muxed-pips !26_37 !27_37 26_36
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_36 !27_37 26_37
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_36 !26_37 !27_37
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_36 !26_37 !27_37
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_56 !27_54 26_55
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_56 26_55 27_54
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_TOP_R_CK_MUXED6 origin:046-clk-bufg-muxed-pips !26_55 !27_54 26_56
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_55 !26_56 27_54
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_55 !26_56 !27_54
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_55 !26_56 !27_54
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_52 !26_53 27_53
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_52 26_53 27_53
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_TOP_R_CK_MUXED7 origin:046-clk-bufg-muxed-pips !26_53 !27_53 26_52
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_52 !27_53 26_53
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_52 !26_53 !27_53
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_52 !26_53 !27_53
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_72 !27_70 26_71
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_72 26_71 27_70
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_TOP_R_CK_MUXED8 origin:046-clk-bufg-muxed-pips !26_71 !27_70 26_72
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_71 !26_72 27_70
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_71 !26_72 !27_70
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_71 !26_72 !27_70
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_68 !26_69 27_69
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_68 26_69 27_69
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_TOP_R_CK_MUXED9 origin:046-clk-bufg-muxed-pips !26_69 !27_69 26_68
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_68 !27_69 26_69
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_68 !26_69 !27_69
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_68 !26_69 !27_69
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_88 !27_86 26_87
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_88 26_87 27_86
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_TOP_R_CK_MUXED10 origin:046-clk-bufg-muxed-pips !26_87 !27_86 26_88
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_87 !26_88 27_86
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_87 !26_88 !27_86
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_87 !26_88 !27_86
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_84 !26_85 27_85
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_84 26_85 27_85
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_TOP_R_CK_MUXED11 origin:046-clk-bufg-muxed-pips !26_85 !27_85 26_84
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_84 !27_85 26_85
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_84 !26_85 !27_85
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_84 !26_85 !27_85
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_104 !27_102 26_103
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_104 26_103 27_102
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_TOP_R_CK_MUXED12 origin:046-clk-bufg-muxed-pips !26_103 !27_102 26_104
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_103 !26_104 27_102
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_103 !26_104 !27_102
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_103 !26_104 !27_102
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_100 !26_101 27_101
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_100 26_101 27_101
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_TOP_R_CK_MUXED13 origin:046-clk-bufg-muxed-pips !26_101 !27_101 26_100
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_100 !27_101 26_101
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_100 !26_101 !27_101
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_100 !26_101 !27_101
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_120 !27_118 26_119
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_120 26_119 27_118
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_TOP_R_CK_MUXED14 origin:046-clk-bufg-muxed-pips !26_119 !27_118 26_120
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_119 !26_120 27_118
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_119 !26_120 !27_118
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_119 !26_120 !27_118
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_116 !26_117 27_117
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_116 26_117 27_117
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_TOP_R_CK_MUXED15 origin:046-clk-bufg-muxed-pips !26_117 !27_117 26_116
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_116 !27_117 26_117
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_116 !26_117 !27_117
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_116 !26_117 !27_117
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_136 !27_134 26_135
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_136 26_135 27_134
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_TOP_R_CK_MUXED16 origin:046-clk-bufg-muxed-pips !26_135 !27_134 26_136
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_135 !26_136 27_134
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_135 !26_136 !27_134
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_135 !26_136 !27_134
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_132 !26_133 27_133
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_132 26_133 27_133
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_TOP_R_CK_MUXED17 origin:046-clk-bufg-muxed-pips !26_133 !27_133 26_132
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_132 !27_133 26_133
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_132 !26_133 !27_133
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_132 !26_133 !27_133
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_152 !27_150 26_151
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_152 26_151 27_150
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_TOP_R_CK_MUXED18 origin:046-clk-bufg-muxed-pips !26_151 !27_150 26_152
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_151 !26_152 27_150
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_151 !26_152 !27_150
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_151 !26_152 !27_150
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_148 !26_149 27_149
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_148 26_149 27_149
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_TOP_R_CK_MUXED19 origin:046-clk-bufg-muxed-pips !26_149 !27_149 26_148
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_148 !27_149 26_149
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_148 !26_149 !27_149
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_148 !26_149 !27_149
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_168 !27_166 26_167
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_168 26_167 27_166
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_TOP_R_CK_MUXED20 origin:046-clk-bufg-muxed-pips !26_167 !27_166 26_168
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_167 !26_168 27_166
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_167 !26_168 !27_166
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_167 !26_168 !27_166
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_164 !26_165 27_165
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_164 26_165 27_165
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_TOP_R_CK_MUXED21 origin:046-clk-bufg-muxed-pips !26_165 !27_165 26_164
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_164 !27_165 26_165
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_164 !26_165 !27_165
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_164 !26_165 !27_165
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_184 !27_182 26_183
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_184 26_183 27_182
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_TOP_R_CK_MUXED22 origin:046-clk-bufg-muxed-pips !26_183 !27_182 26_184
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_183 !26_184 27_182
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_183 !26_184 !27_182
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_183 !26_184 !27_182
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_180 !26_181 27_181
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_180 26_181 27_181
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_TOP_R_CK_MUXED23 origin:046-clk-bufg-muxed-pips !26_181 !27_181 26_180
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_180 !27_181 26_181
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_180 !26_181 !27_181
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_180 !26_181 !27_181
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_200 !27_198 26_199
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_200 26_199 27_198
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_TOP_R_CK_MUXED24 origin:046-clk-bufg-muxed-pips !26_199 !27_198 26_200
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_199 !26_200 27_198
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_199 !26_200 !27_198
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_199 !26_200 !27_198
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_196 !26_197 27_197
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_196 26_197 27_197
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_TOP_R_CK_MUXED25 origin:046-clk-bufg-muxed-pips !26_197 !27_197 26_196
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_196 !27_197 26_197
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_196 !26_197 !27_197
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_196 !26_197 !27_197
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_216 !27_214 26_215
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_216 26_215 27_214
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_TOP_R_CK_MUXED26 origin:046-clk-bufg-muxed-pips !26_215 !27_214 26_216
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_215 !26_216 27_214
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_215 !26_216 !27_214
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_215 !26_216 !27_214
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_212 !26_213 27_213
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_212 26_213 27_213
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_TOP_R_CK_MUXED27 origin:046-clk-bufg-muxed-pips !26_213 !27_213 26_212
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_212 !27_213 26_213
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_212 !26_213 !27_213
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_212 !26_213 !27_213
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_232 !27_230 26_231
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_232 26_231 27_230
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_TOP_R_CK_MUXED28 origin:046-clk-bufg-muxed-pips !26_231 !27_230 26_232
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_231 !26_232 27_230
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_231 !26_232 !27_230
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_231 !26_232 !27_230
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_228 !26_229 27_229
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_228 26_229 27_229
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_TOP_R_CK_MUXED29 origin:046-clk-bufg-muxed-pips !26_229 !27_229 26_228
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_228 !27_229 26_229
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_228 !26_229 !27_229
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_228 !26_229 !27_229
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_248 26_247 27_246
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_248 !27_246 26_247
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_TOP_R_CK_MUXED30 origin:046-clk-bufg-muxed-pips !26_247 !27_246 26_248
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_247 !26_248 27_246
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_247 !26_248 !27_246
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_247 !26_248 !27_246
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_244 26_245 27_245
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_244 !26_245 27_245
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_TOP_R_CK_MUXED31 origin:046-clk-bufg-muxed-pips !26_245 !27_245 26_244
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_244 !27_245 26_245
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_244 !26_245 !27_245
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_244 !26_245 !27_245

diff --git a/kintex7/segbits_cmt_top_l_lower_b.db b/kintex7/segbits_cmt_top_l_lower_b.db
new file mode 100644
index 0000000..e95270c
--- /dev/null
+++ b/kintex7/segbits_cmt_top_l_lower_b.db

@@ -0,0 +1,396 @@
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB0 !28_1012 28_1013 29_979 29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB1 !28_1012 !28_1013 29_979 29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB2 !28_1012 28_1013 29_979 !29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB3 !28_1012 !28_1013 29_979 !29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_IN3_HCLK 28_1012 !28_1013 29_979 !29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_IN3_INT 28_1012 28_1013 29_979 !29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_LR_LOWER_B_CLKFBOUT2IN 28_980 28_981 29_980
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB0 28_1014 !29_1013 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB1 28_1014 !29_1013 !29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB2 !28_1014 !29_1013 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB3 !28_1014 !29_1013 !29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_IN1_HCLK !28_1014 29_1013 !29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_IN1_INT !28_1014 29_1013 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB0 !28_1015 28_1016 29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB1 !28_1015 !28_1016 29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB2 !28_1015 28_1016 !29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB3 !28_1015 !28_1016 !29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_IN2_HCLK 28_1015 !28_1016 !29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_IN2_INT 28_1015 28_1016 !29_1015
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS0_ACTIVE 28_1066 28_1074 29_1056
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS1_ACTIVE 28_1057 28_1067 28_1075
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840
+CMT_TOP_L_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_110 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 28_1015 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_110 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1013 29_1018
+CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL 29_109
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] 29_823
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] 28_823
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] 29_822
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] 28_822
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] 29_821
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] 28_821
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] 29_820
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] 28_820
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] 29_819
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] 28_819
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] 29_815
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] 28_815
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] 29_814
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] 28_814
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] 29_813
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] 28_813
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] 29_812
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] 28_812
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] 29_811
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] 28_811
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] 29_831
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] 28_831
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] 29_830
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] 28_830
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] 29_829
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] 28_829
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] 29_828
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] 28_828
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] 29_827
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] 28_827
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] 29_818
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] 28_818
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] 29_817
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] 28_817
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] 29_816
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] 29_810
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] 28_810
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] 29_809
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] 28_809
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] 29_808
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696
+CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT 29_94
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] 29_389
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] 28_388
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] 29_387
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] 28_386
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] 29_385
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] 28_384
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] 29_395
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] 28_394
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] 29_393
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] 28_392
+CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN 28_111
+CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST 29_111
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808

diff --git a/kintex7/segbits_cmt_top_l_lower_b.origin_info.db b/kintex7/segbits_cmt_top_l_lower_b.origin_info.db
new file mode 100644
index 0000000..d74dc78
--- /dev/null
+++ b/kintex7/segbits_cmt_top_l_lower_b.origin_info.db

@@ -0,0 +1,396 @@
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !28_1012 28_1013 29_1012 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !28_1012 !28_1013 29_1012 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1012 !29_1012 28_1013 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1012 !28_1013 !29_1012 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_IN3_HCLK origin:034b-cmt-mmcm-pips !28_1013 !29_1012 28_1012 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_IN3_INT origin:034b-cmt-mmcm-pips !29_1012 28_1012 28_1013 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_LR_LOWER_B_CLKFBOUT2IN origin:034b-cmt-mmcm-pips 28_980 28_981 29_980
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !29_1013 28_1014 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !29_1013 !29_1014 28_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1014 !29_1013 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1014 !29_1013 !29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_IN1_HCLK origin:034b-cmt-mmcm-pips !28_1014 !29_1014 29_1013
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_IN1_INT origin:034b-cmt-mmcm-pips !28_1014 29_1013 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !28_1015 28_1016 29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !28_1015 !28_1016 29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1015 !29_1015 28_1016
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1015 !28_1016 !29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_IN2_HCLK origin:034b-cmt-mmcm-pips !28_1016 !29_1015 28_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_IN2_INT origin:034b-cmt-mmcm-pips !29_1015 28_1015 28_1016
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS0_ACTIVE origin:034b-cmt-mmcm-pips 28_1066 28_1074 29_1056
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS1_ACTIVE origin:034b-cmt-mmcm-pips 28_1057 28_1067 28_1075
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068 28_1076 29_1057
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
+CMT_TOP_L_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_1015 28_110 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1013 29_1018 29_110 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
+CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
+CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392
+CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
+CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808

diff --git a/kintex7/segbits_cmt_top_l_upper_t.db b/kintex7/segbits_cmt_top_l_upper_t.db
index 8d3b53d..4859101 100644
--- a/kintex7/segbits_cmt_top_l_upper_t.db
+++ b/kintex7/segbits_cmt_top_l_upper_t.db

@@ -1,362 +1,366 @@
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN !28_11 28_43 !28_44 !29_10 !29_11 29_42 29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN !28_11 !28_43 28_44 !29_10 29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT !28_11 !28_43 28_44 29_10 29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_09 !28_10 !29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 28_09 !28_10 !29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 !28_09 !28_10 29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 28_09 !28_10 29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 !28_09 28_10 !29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_09 28_10 !29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_08 !29_07 !29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_08 29_07 !29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 28_08 !29_07 !29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 28_08 29_07 !29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 !28_08 !29_07 29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT !28_08 29_07 29_08
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175
-CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44
-CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_41 29_04
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183
-CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_05 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
-CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_722
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_200
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_200
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_201
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_201
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_202
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_202
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_203
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_203
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_204
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_204
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_208
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_208
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_209
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_209
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_210
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_210
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_211
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_211
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_212
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_212
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_192
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_192
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_193
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_193
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_194
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_194
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_195
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_195
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_196
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_196
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_205
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_205
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_206
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_206
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_207
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_213
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_213
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_214
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_214
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_215
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327
-CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_737
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_634
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_635
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_636
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_637
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_638
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_639
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_628
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_629
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_630
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_631
-CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_720
-CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_720
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN !28_43 28_75 !28_76 !29_42 !29_43 29_74 29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN !28_43 !28_75 28_76 !29_42 29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_43 !28_75 28_76 !29_42 !29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_43 !28_75 28_76 29_42 !29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 28_43 !28_75 28_76 !29_42 !29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 28_43 !28_75 28_76 29_42 !29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT !28_43 !28_75 28_76 29_42 29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_41 !28_42 !29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 28_41 !28_42 !29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 !28_41 !28_42 29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 28_41 !28_42 29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 !28_41 28_42 !29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_41 28_42 !29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_40 !29_39 !29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_40 29_39 !29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 28_40 !29_39 !29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 28_40 29_39 !29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 !28_40 !29_39 29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT !28_40 29_39 29_40
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
+CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
+CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215
+CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
+CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_754
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_232
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_232
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_233
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_233
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_234
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_234
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_235
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_235
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_236
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_236
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_240
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_240
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_241
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_241
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_242
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_242
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_243
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_243
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_244
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_244
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_224
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_224
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_225
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_225
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_226
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_226
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_227
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_227
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_228
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_228
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_237
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_237
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_238
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_238
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_239
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_245
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_245
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_246
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_246
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_247
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359
+CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_769
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_666
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_667
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_668
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_669
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_670
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_671
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_660
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_661
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_662
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_663
+CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_752
+CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_752
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247

diff --git a/kintex7/segbits_cmt_top_l_upper_t.origin_info.db b/kintex7/segbits_cmt_top_l_upper_t.origin_info.db
index 31fb3df..bfa0faf 100644
--- a/kintex7/segbits_cmt_top_l_upper_t.origin_info.db
+++ b/kintex7/segbits_cmt_top_l_upper_t.origin_info.db

@@ -1,362 +1,366 @@
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN origin:034-cmt-pll-pips !28_11 !28_44 !29_10 !29_11 28_43 29_42 29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_42 !29_43 28_44 29_11
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_11 !29_42 !29_43 28_44
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_11 !28_43 !29_11 !29_42 !29_43 28_44 29_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_43 !29_10 !29_11 !29_42 !29_43 28_11 28_44
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_43 !29_11 !29_42 !29_43 28_11 28_44 29_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_11 !28_43 !29_42 !29_43 28_44 29_10 29_11
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_09 !28_10 !29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_10 !29_09 28_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_09 !28_10 29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_10 28_09 29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_09 !29_09 28_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !29_09 28_09 28_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_08 !29_07 !29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_08 !29_08 29_07
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !29_07 !29_08 28_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !29_08 28_08 29_07
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_08 !29_07 29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_08 29_07 29_08
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
-CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44
-CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_41 29_04
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183
-CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
-CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327
-CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631
-CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720
-CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN origin:034-cmt-pll-pips !28_43 !28_76 !29_42 !29_43 28_75 29_74 29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_43 !28_75 !29_42 !29_74 !29_75 28_76 29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_43 !28_75 !29_42 !29_43 !29_74 !29_75 28_76
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_43 !28_75 !29_43 !29_74 !29_75 28_76 29_42
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_75 !29_42 !29_43 !29_74 !29_75 28_43 28_76
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_75 !29_43 !29_74 !29_75 28_43 28_76 29_42
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_43 !28_75 !29_74 !29_75 28_76 29_42 29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_41 !28_42 !29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_42 !29_41 28_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_41 !28_42 29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_42 28_41 29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_41 !29_41 28_42
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !29_41 28_41 28_42
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_40 !29_39 !29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_40 !29_40 29_39
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !29_39 !29_40 28_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !29_40 28_40 29_39
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_40 !29_39 29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_40 29_39 29_40
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09 29_17
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
+CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
+CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
+CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
+CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
+CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663
+CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752
+CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247

diff --git a/kintex7/segbits_cmt_top_r_lower_b.db b/kintex7/segbits_cmt_top_r_lower_b.db
new file mode 100644
index 0000000..b810699
--- /dev/null
+++ b/kintex7/segbits_cmt_top_r_lower_b.db

@@ -0,0 +1,396 @@
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_LR_LOWER_B_CLKFBOUT2IN 28_980 28_981 29_980
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB0 !28_1012 28_1013 29_979 29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB1 !28_1012 !28_1013 29_979 29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB2 !28_1012 28_1013 29_979 !29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB3 !28_1012 !28_1013 29_979 !29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_IN3_HCLK 28_1012 !28_1013 29_979 !29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_IN3_INT 28_1012 28_1013 29_979 !29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB0 28_1014 !29_1013 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB1 28_1014 !29_1013 !29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB2 !28_1014 !29_1013 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB3 !28_1014 !29_1013 !29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_IN1_HCLK !28_1014 29_1013 !29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_IN1_INT !28_1014 29_1013 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB0 !28_1015 28_1016 29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB1 !28_1015 !28_1016 29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB2 !28_1015 28_1016 !29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB3 !28_1015 !28_1016 !29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_IN2_HCLK 28_1015 !28_1016 !29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_IN2_INT 28_1015 28_1016 !29_1015
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS0_ACTIVE 28_1066 28_1074 29_1056
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS1_ACTIVE 28_1057 28_1067 28_1075
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840
+CMT_TOP_R_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_110 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 28_1015 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_110 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1013 29_1018
+CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL 29_109
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] 29_823
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] 28_823
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] 29_822
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] 28_822
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] 29_821
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] 28_821
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] 29_820
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] 28_820
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] 29_819
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] 28_819
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] 29_815
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] 28_815
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] 29_814
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] 28_814
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] 29_813
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] 28_813
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] 29_812
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] 28_812
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] 29_811
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] 28_811
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] 29_831
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] 28_831
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] 29_830
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] 28_830
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] 29_829
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] 28_829
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] 29_828
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] 28_828
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] 29_827
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] 28_827
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] 29_818
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] 28_818
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] 29_817
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] 28_817
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] 29_816
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] 29_810
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] 28_810
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] 29_809
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] 28_809
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] 29_808
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696
+CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT 29_94
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] 29_389
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] 28_388
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] 29_387
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] 28_386
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] 29_385
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] 28_384
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] 29_395
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] 28_394
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] 29_393
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] 28_392
+CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN 28_111
+CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST 29_111
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808

diff --git a/kintex7/segbits_cmt_top_r_lower_b.origin_info.db b/kintex7/segbits_cmt_top_r_lower_b.origin_info.db
new file mode 100644
index 0000000..31c4804
--- /dev/null
+++ b/kintex7/segbits_cmt_top_r_lower_b.origin_info.db

@@ -0,0 +1,396 @@
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_LR_LOWER_B_CLKFBOUT2IN origin:034b-cmt-mmcm-pips 28_980 28_981 29_980
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !28_1012 28_1013 29_1012 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !28_1012 !28_1013 29_1012 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1012 !29_1012 28_1013 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1012 !28_1013 !29_1012 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_IN3_HCLK origin:034b-cmt-mmcm-pips !28_1013 !29_1012 28_1012 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_IN3_INT origin:034b-cmt-mmcm-pips !29_1012 28_1012 28_1013 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !29_1013 28_1014 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !29_1013 !29_1014 28_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1014 !29_1013 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1014 !29_1013 !29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_IN1_HCLK origin:034b-cmt-mmcm-pips !28_1014 !29_1014 29_1013
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_IN1_INT origin:034b-cmt-mmcm-pips !28_1014 29_1013 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !28_1015 28_1016 29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !28_1015 !28_1016 29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1015 !29_1015 28_1016
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1015 !28_1016 !29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_IN2_HCLK origin:034b-cmt-mmcm-pips !28_1016 !29_1015 28_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_IN2_INT origin:034b-cmt-mmcm-pips !29_1015 28_1015 28_1016
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS0_ACTIVE origin:034b-cmt-mmcm-pips 28_1066 28_1074 29_1056
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS1_ACTIVE origin:034b-cmt-mmcm-pips 28_1057 28_1067 28_1075
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068 28_1076 29_1057
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
+CMT_TOP_R_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_1015 28_110 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1013 29_1018 29_110 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
+CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
+CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392
+CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
+CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808

diff --git a/kintex7/segbits_cmt_top_r_upper_t.db b/kintex7/segbits_cmt_top_r_upper_t.db
index 315be13..0e40593 100644
--- a/kintex7/segbits_cmt_top_r_upper_t.db
+++ b/kintex7/segbits_cmt_top_r_upper_t.db

@@ -1,362 +1,366 @@
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN !28_11 28_43 !28_44 !29_10 !29_11 29_42 29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN !28_11 !28_43 28_44 !29_10 29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 !28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT !28_11 !28_43 28_44 29_10 29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_09 !28_10 !29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 28_09 !28_10 !29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 !28_09 !28_10 29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 28_09 !28_10 29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 !28_09 28_10 !29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT 28_09 28_10 !29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_08 !29_07 !29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 !28_08 29_07 !29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 28_08 !29_07 !29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 28_08 29_07 !29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 !28_08 !29_07 29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT !28_08 29_07 29_08
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175
-CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44
-CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_41 29_04
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183
-CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_05 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
-CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_722
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_200
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_200
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_201
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_201
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_202
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_202
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_203
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_203
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_204
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_204
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_208
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_208
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_209
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_209
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_210
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_210
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_211
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_211
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_212
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_212
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_192
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_192
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_193
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_193
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_194
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_194
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_195
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_195
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_196
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_196
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_205
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_205
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_206
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_206
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_207
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_213
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_213
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_214
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_214
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_215
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327
-CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_737
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_634
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_635
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_636
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_637
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_638
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_639
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_628
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_629
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_630
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_631
-CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_720
-CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_720
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN !28_01 !28_02 !28_43 28_75 !28_76 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_42 !29_43 29_74 29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN !28_01 !28_02 !28_43 !28_75 28_76 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_42 29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_01 !28_02 !28_43 !28_75 28_76 29_00 !29_01 29_09 !29_10 !29_11 !29_12 29_17 !29_18 !29_19 !29_20 !29_42 !29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 28_01 !28_02 !28_43 !28_75 28_76 !29_00 !29_01 !29_09 29_10 !29_11 !29_12 !29_17 29_18 !29_19 !29_20 29_42 !29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 !28_01 !28_02 28_43 !28_75 28_76 !29_00 29_01 !29_09 !29_10 29_11 !29_12 !29_17 !29_18 29_19 !29_20 !29_42 !29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 !28_01 28_02 28_43 !28_75 28_76 !29_00 !29_01 !29_09 !29_10 !29_11 29_12 !29_17 !29_18 !29_19 29_20 29_42 !29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT !28_01 !28_02 !28_43 !28_75 28_76 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 29_42 29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_01 !28_02 !28_41 !28_42 29_00 !29_01 29_09 !29_10 !29_11 !29_12 29_17 !29_18 !29_19 !29_20 !29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 28_01 !28_02 28_41 !28_42 !29_00 !29_01 !29_09 29_10 !29_11 !29_12 !29_17 29_18 !29_19 !29_20 !29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 !28_01 !28_02 !28_41 !28_42 !29_00 29_01 !29_09 !29_10 29_11 !29_12 !29_17 !29_18 29_19 !29_20 29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 !28_01 28_02 28_41 !28_42 !29_00 !29_01 !29_09 !29_10 !29_11 29_12 !29_17 !29_18 !29_19 29_20 29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 !28_01 !28_02 !28_41 28_42 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT !28_01 !28_02 28_41 28_42 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_01 !28_02 !28_40 29_00 !29_01 29_09 !29_10 !29_11 !29_12 29_17 !29_18 !29_19 !29_20 !29_39 !29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 28_01 !28_02 !28_40 !29_00 !29_01 !29_09 29_10 !29_11 !29_12 !29_17 29_18 !29_19 !29_20 29_39 !29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 !28_01 !28_02 28_40 !29_00 29_01 !29_09 !29_10 29_11 !29_12 !29_17 !29_18 29_19 !29_20 !29_39 !29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 !28_01 28_02 28_40 !29_00 !29_01 !29_09 !29_10 !29_11 29_12 !29_17 !29_18 !29_19 29_20 29_39 !29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 !28_01 !28_02 !28_40 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_39 29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT !28_01 !28_02 !28_40 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 29_39 29_40
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
+CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
+CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215
+CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
+CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_754
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_232
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_232
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_233
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_233
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_234
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_234
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_235
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_235
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_236
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_236
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_240
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_240
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_241
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_241
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_242
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_242
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_243
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_243
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_244
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_244
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_224
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_224
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_225
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_225
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_226
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_226
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_227
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_227
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_228
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_228
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_237
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_237
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_238
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_238
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_239
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_245
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_245
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_246
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_246
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_247
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359
+CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_769
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_666
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_667
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_668
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_669
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_670
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_671
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_660
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_661
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_662
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_663
+CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_752
+CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_752
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247

diff --git a/kintex7/segbits_cmt_top_r_upper_t.origin_info.db b/kintex7/segbits_cmt_top_r_upper_t.origin_info.db
index f571184..6ee0558 100644
--- a/kintex7/segbits_cmt_top_r_upper_t.origin_info.db
+++ b/kintex7/segbits_cmt_top_r_upper_t.origin_info.db

@@ -1,362 +1,366 @@
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN origin:034-cmt-pll-pips !28_11 !28_44 !29_10 !29_11 28_43 29_42 29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_42 !29_43 28_44 29_11
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_11 !29_42 !29_43 28_44
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_11 !28_43 !29_11 !29_42 !29_43 28_44 29_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_43 !29_10 !29_11 !29_42 !29_43 28_11 28_44
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_43 !29_11 !29_42 !29_43 28_11 28_44 29_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_11 !28_43 !29_42 !29_43 28_44 29_10 29_11
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_09 !28_10 !29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_10 !29_09 28_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_09 !28_10 29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_10 28_09 29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_09 !29_09 28_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !29_09 28_09 28_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_08 !29_07 !29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_08 !29_08 29_07
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !29_07 !29_08 28_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !29_08 28_08 29_07
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_08 !29_07 29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_08 29_07 29_08
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
-CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44
-CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_41 29_04
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183
-CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
-CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327
-CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631
-CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720
-CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN origin:034-cmt-pll-pips !28_01 !28_02 !28_43 !28_76 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_42 !29_43 28_75 29_74 29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_01 !28_02 !28_43 !28_75 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_42 !29_74 !29_75 28_76 29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_01 !28_02 !28_43 !28_75 !29_01 !29_10 !29_11 !29_12 !29_18 !29_19 !29_20 !29_42 !29_43 !29_74 !29_75 28_76 29_00 29_09 29_17
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_02 !28_43 !28_75 !29_00 !29_01 !29_09 !29_11 !29_12 !29_17 !29_19 !29_20 !29_43 !29_74 !29_75 28_01 28_76 29_10 29_18 29_42
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_01 !28_02 !28_75 !29_00 !29_09 !29_10 !29_12 !29_17 !29_18 !29_20 !29_42 !29_43 !29_74 !29_75 28_43 28_76 29_01 29_11 29_19
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_01 !28_75 !29_00 !29_01 !29_09 !29_10 !29_11 !29_17 !29_18 !29_19 !29_43 !29_74 !29_75 28_02 28_43 28_76 29_12 29_20 29_42
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_01 !28_02 !28_43 !28_75 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_74 !29_75 28_76 29_42 29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_01 !28_02 !28_41 !28_42 !29_01 !29_10 !29_11 !29_12 !29_18 !29_19 !29_20 !29_41 29_00 29_09 29_17
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_02 !28_42 !29_00 !29_01 !29_09 !29_11 !29_12 !29_17 !29_19 !29_20 !29_41 28_01 28_41 29_10 29_18
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_01 !28_02 !28_41 !28_42 !29_00 !29_09 !29_10 !29_12 !29_17 !29_18 !29_20 29_01 29_11 29_19 29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_01 !28_42 !29_00 !29_01 !29_09 !29_10 !29_11 !29_17 !29_18 !29_19 28_02 28_41 29_12 29_20 29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_01 !28_02 !28_41 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_41 28_42
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !28_01 !28_02 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_41 28_41 28_42
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_01 !28_02 !28_40 !29_01 !29_10 !29_11 !29_12 !29_18 !29_19 !29_20 !29_39 !29_40 29_00 29_09 29_17
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_02 !28_40 !29_00 !29_01 !29_09 !29_11 !29_12 !29_17 !29_19 !29_20 !29_40 28_01 29_10 29_18 29_39
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_01 !28_02 !29_00 !29_09 !29_10 !29_12 !29_17 !29_18 !29_20 !29_39 !29_40 28_40 29_01 29_11 29_19
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_01 !29_00 !29_01 !29_09 !29_10 !29_11 !29_17 !29_18 !29_19 !29_40 28_02 28_40 29_12 29_20 29_39
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_01 !28_02 !28_40 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_39 29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_01 !28_02 !28_40 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 29_39 29_40
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09 29_17
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
+CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
+CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
+CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
+CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
+CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663
+CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752
+CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247

diff --git a/kintex7/segbits_int_l.origin_info.db b/kintex7/segbits_int_l.origin_info.db
index 3a63a45..c0a62ce 100644
--- a/kintex7/segbits_int_l.origin_info.db
+++ b/kintex7/segbits_int_l.origin_info.db

@@ -301,7 +301,7 @@
 INT_L.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
 INT_L.FAN_ALT0.LOGIC_OUTS_L0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
 INT_L.FAN_ALT0.LOGIC_OUTS_L12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
-INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
+INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
 INT_L.FAN_ALT0.SR1END_N3_3 origin:050-pip-seed !23_00 19_01 22_00 24_00 25_00
 INT_L.FAN_ALT0.SS2END_N0_3 origin:050-pip-seed !22_00 !23_00 !24_00 17_00 25_00
 INT_L.FAN_ALT0.SW2END_N0_3 origin:050-pip-seed !22_00 !23_00 !25_00 17_00 24_00
@@ -1917,7 +1917,7 @@
 INT_L.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
 INT_L.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
 INT_L.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
-INT_L.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
+INT_L.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
 INT_L.EE4BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_57 07_57
 INT_L.EE4BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_57 04_58
 INT_L.EE4BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_56 04_58
@@ -2271,7 +2271,7 @@
 INT_L.NE6BEG3.NW2END3 origin:050-pip-seed 02_53 04_53
 INT_L.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52
 INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
-INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
+INT_L.NE6BEG3.SE6END3 origin:056-pip-rem 05_55 06_52
 INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
 INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
 INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17
@@ -3323,7 +3323,7 @@
 INT_L.SW6BEG2.LVB_L0 origin:056-pip-rem 04_46 05_44
 INT_L.SW6BEG2.LVB_L12 origin:056-pip-rem 05_44 07_45
 INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
+INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
 INT_L.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
 INT_L.SW6BEG2.NW6END3 origin:050-pip-seed 05_47 06_44
 INT_L.SW6BEG2.SE2END2 origin:050-pip-seed 02_45 04_45

diff --git a/kintex7/segbits_int_r.origin_info.db b/kintex7/segbits_int_r.origin_info.db
index 481c778..3807463 100644
--- a/kintex7/segbits_int_r.origin_info.db
+++ b/kintex7/segbits_int_r.origin_info.db

@@ -170,7 +170,7 @@
 INT_R.BYP_ALT7.BYP_BOUNCE6 origin:050-pip-seed !22_63 !23_63 !25_63 21_63 24_63
 INT_R.BYP_ALT7.EL1END_S3_0 origin:050-pip-seed !23_63 17_63 22_63 24_63 25_63
 INT_R.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
-INT_R.BYP_ALT7.FAN_BOUNCE_S3_6 origin:056-pip-rem !22_63 21_63 23_63 24_63 25_63
+INT_R.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
 INT_R.BYP_ALT7.LOGIC_OUTS3 origin:051-pip-imuxlout-bypalts !22_63 20_63 23_63 24_63 25_63
 INT_R.BYP_ALT7.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
 INT_R.BYP_ALT7.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
@@ -237,7 +237,7 @@
 INT_R.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
 INT_R.FAN_ALT0.LOGIC_OUTS0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
 INT_R.FAN_ALT0.LOGIC_OUTS12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
-INT_R.FAN_ALT0.LOGIC_OUTS22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
+INT_R.FAN_ALT0.LOGIC_OUTS22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
 INT_R.FAN_ALT0.SR1END_N3_3 origin:050-pip-seed !23_00 19_01 22_00 24_00 25_00
 INT_R.FAN_ALT0.SS2END_N0_3 origin:050-pip-seed !22_00 !23_00 !24_00 17_00 25_00
 INT_R.FAN_ALT0.SW2END_N0_3 origin:050-pip-seed !22_00 !23_00 !25_00 17_00 24_00
@@ -328,7 +328,7 @@
 INT_R.FAN_ALT3.WW2END3 origin:050-pip-seed !22_56 !23_56 !24_56 19_57 25_56
 INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
 INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
-INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
+INT_R.FAN_ALT4.FAN_BOUNCE2 origin:056-pip-rem !23_08 20_08 22_08 24_08 25_08
 INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
@@ -685,7 +685,7 @@
 INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
 INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
 INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
-INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
+INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
 INT_R.EE4BEG2.LOGIC_OUTS2 origin:050-pip-seed 02_41 04_42
 INT_R.EE4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_41 07_41
 INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
@@ -725,7 +725,7 @@
 INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
 INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
 INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
+INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
 INT_R.EL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_20 14_21
 INT_R.EL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_21 14_21
 INT_R.EL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_21 13_21
@@ -2273,7 +2273,7 @@
 INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
 INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
 INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
+INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
 INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17
 INT_R.NL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_17 14_17
 INT_R.NL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_17 13_17
@@ -3321,7 +3321,7 @@
 INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
 INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
 INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
 INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
 INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
 INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
@@ -3344,7 +3344,7 @@
 INT_R.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60
 INT_R.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63
 INT_R.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
-INT_R.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
+INT_R.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
 INT_R.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
 INT_R.SW6BEG3.LV18 origin:056-pip-rem 05_60 07_61
 INT_R.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61

diff --git a/kintex7/segbits_liob33.origin_info.db b/kintex7/segbits_liob33.origin_info.db
index c0a134f..0490cb8 100644
--- a/kintex7/segbits_liob33.origin_info.db
+++ b/kintex7/segbits_liob33.origin_info.db

@@ -37,10 +37,10 @@
 LIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87
 LIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST origin:030-iob !38_106 38_110 39_105 39_107 39_109 39_111
 LIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45
-LIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_4 !38_6 !39_5 !39_7
-LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_4 38_6 39_5 39_7
-LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_6 38_4 39_5 39_7
-LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_6 !39_5 38_4 39_7
+LIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_04 !38_06 !39_05 !39_07
+LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07
+LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07
+LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07
 LIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
 LIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63
 LIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35

diff --git a/kintex7/segbits_lioi3.db b/kintex7/segbits_lioi3.db
index f781c22..465ab9b 100644
--- a/kintex7/segbits_lioi3.db
+++ b/kintex7/segbits_lioi3.db

@@ -40,6 +40,7 @@
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+LIOI3.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 LIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 LIOI3.ILOGIC_Y0.IDELMUXE3.P0 29_101
 LIOI3.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 LIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+LIOI3.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 LIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 LIOI3.OLOGIC_Y0.IS_D7_INVERTED 31_118
 LIOI3.OLOGIC_Y0.IS_D8_INVERTED 30_125
 LIOI3.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+LIOI3.OLOGIC_Y0.ODDR.SRUSED 32_112
+LIOI3.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 LIOI3.OLOGIC_Y0.OMUX.D1 33_111
 LIOI3.OLOGIC_Y0.OQUSED 31_86
 LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.IN_USE 33_73
 LIOI3.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 LIOI3.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 LIOI3.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 LIOI3.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+LIOI3.OLOGIC_Y0.TDDR.SRUSED 33_89
 LIOI3.OLOGIC_Y0.ZINIT_OQ 33_97
 LIOI3.OLOGIC_Y0.ZINIT_TQ 30_75
-LIOI3.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+LIOI3.OLOGIC_Y0.ZINV_CLK 31_90
 LIOI3.OLOGIC_Y0.ZINV_T1 30_67
 LIOI3.OLOGIC_Y0.ZINV_T2 30_71
 LIOI3.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 LIOI3.OLOGIC_Y1.IS_D7_INVERTED 30_09
 LIOI3.OLOGIC_Y1.IS_D8_INVERTED 31_02
 LIOI3.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+LIOI3.OLOGIC_Y1.ODDR.SRUSED 33_15
+LIOI3.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 LIOI3.OLOGIC_Y1.OMUX.D1 32_16
 LIOI3.OLOGIC_Y1.OQUSED 30_41
 LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.IN_USE 32_54
 LIOI3.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 LIOI3.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 LIOI3.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 LIOI3.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+LIOI3.OLOGIC_Y1.TDDR.SRUSED 32_38
 LIOI3.OLOGIC_Y1.ZINIT_OQ 32_30
 LIOI3.OLOGIC_Y1.ZINIT_TQ 31_52
-LIOI3.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+LIOI3.OLOGIC_Y1.ZINV_CLK 30_37
 LIOI3.OLOGIC_Y1.ZINV_T1 31_60
 LIOI3.OLOGIC_Y1.ZINV_T2 31_56
 LIOI3.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/kintex7/segbits_lioi3.origin_info.db b/kintex7/segbits_lioi3.origin_info.db
index a80d11c..e7e201c 100644
--- a/kintex7/segbits_lioi3.origin_info.db
+++ b/kintex7/segbits_lioi3.origin_info.db

@@ -40,6 +40,7 @@
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+LIOI3.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 LIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 LIOI3.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 LIOI3.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 LIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+LIOI3.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 LIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 LIOI3.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 LIOI3.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 LIOI3.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-LIOI3.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 LIOI3.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 LIOI3.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 LIOI3.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 LIOI3.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 LIOI3.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 LIOI3.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-LIOI3.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 LIOI3.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 LIOI3.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 LIOI3.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 LIOI3.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 LIOI3.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 LIOI3.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+LIOI3.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+LIOI3.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 LIOI3.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 LIOI3.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-LIOI3.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 LIOI3.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 LIOI3.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 LIOI3.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 LIOI3.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+LIOI3.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 LIOI3.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 LIOI3.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-LIOI3.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+LIOI3.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 LIOI3.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 LIOI3.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 LIOI3.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 LIOI3.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 LIOI3.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 LIOI3.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+LIOI3.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+LIOI3.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 LIOI3.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 LIOI3.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-LIOI3.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 LIOI3.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 LIOI3.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 LIOI3.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 LIOI3.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+LIOI3.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 LIOI3.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 LIOI3.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-LIOI3.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+LIOI3.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 LIOI3.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 LIOI3.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 LIOI3.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/kintex7/segbits_lioi3_tbytesrc.db b/kintex7/segbits_lioi3_tbytesrc.db
index 304a60b..f58db14 100644
--- a/kintex7/segbits_lioi3_tbytesrc.db
+++ b/kintex7/segbits_lioi3_tbytesrc.db

@@ -40,6 +40,7 @@
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+LIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 LIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 29_101
 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 LIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+LIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 LIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 LIOI3_TBYTESRC.OLOGIC_Y0.IS_D7_INVERTED 31_118
 LIOI3_TBYTESRC.OLOGIC_Y0.IS_D8_INVERTED 30_125
 LIOI3_TBYTESRC.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+LIOI3_TBYTESRC.OLOGIC_Y0.ODDR.SRUSED 32_112
+LIOI3_TBYTESRC.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 LIOI3_TBYTESRC.OLOGIC_Y0.OMUX.D1 33_111
 LIOI3_TBYTESRC.OLOGIC_Y0.OQUSED 31_86
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE 33_73
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+LIOI3_TBYTESRC.OLOGIC_Y0.TDDR.SRUSED 33_89
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_OQ 33_97
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_TQ 30_75
-LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK 31_90
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T1 30_67
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T2 30_71
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 LIOI3_TBYTESRC.OLOGIC_Y1.IS_D7_INVERTED 30_09
 LIOI3_TBYTESRC.OLOGIC_Y1.IS_D8_INVERTED 31_02
 LIOI3_TBYTESRC.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+LIOI3_TBYTESRC.OLOGIC_Y1.ODDR.SRUSED 33_15
+LIOI3_TBYTESRC.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 LIOI3_TBYTESRC.OLOGIC_Y1.OMUX.D1 32_16
 LIOI3_TBYTESRC.OLOGIC_Y1.OQUSED 30_41
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE 32_54
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+LIOI3_TBYTESRC.OLOGIC_Y1.TDDR.SRUSED 32_38
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_OQ 32_30
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_TQ 31_52
-LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK 30_37
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T1 31_60
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T2 31_56
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/kintex7/segbits_lioi3_tbytesrc.origin_info.db b/kintex7/segbits_lioi3_tbytesrc.origin_info.db
index 8d0ae06..2ac3c07 100644
--- a/kintex7/segbits_lioi3_tbytesrc.origin_info.db
+++ b/kintex7/segbits_lioi3_tbytesrc.origin_info.db

@@ -40,6 +40,7 @@
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+LIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 LIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 LIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+LIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 LIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 LIOI3_TBYTESRC.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 LIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 LIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 LIOI3_TBYTESRC.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 LIOI3_TBYTESRC.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 LIOI3_TBYTESRC.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+LIOI3_TBYTESRC.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+LIOI3_TBYTESRC.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 LIOI3_TBYTESRC.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 LIOI3_TBYTESRC.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+LIOI3_TBYTESRC.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 LIOI3_TBYTESRC.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 LIOI3_TBYTESRC.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 LIOI3_TBYTESRC.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+LIOI3_TBYTESRC.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+LIOI3_TBYTESRC.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 LIOI3_TBYTESRC.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 LIOI3_TBYTESRC.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+LIOI3_TBYTESRC.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/kintex7/segbits_lioi3_tbyteterm.db b/kintex7/segbits_lioi3_tbyteterm.db
index d60dde9..0c20c4d 100644
--- a/kintex7/segbits_lioi3_tbyteterm.db
+++ b/kintex7/segbits_lioi3_tbyteterm.db

@@ -40,6 +40,7 @@
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+LIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 LIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 29_101
 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 LIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+LIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 LIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 LIOI3_TBYTETERM.OLOGIC_Y0.IS_D7_INVERTED 31_118
 LIOI3_TBYTETERM.OLOGIC_Y0.IS_D8_INVERTED 30_125
 LIOI3_TBYTETERM.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+LIOI3_TBYTETERM.OLOGIC_Y0.ODDR.SRUSED 32_112
+LIOI3_TBYTETERM.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 LIOI3_TBYTETERM.OLOGIC_Y0.OMUX.D1 33_111
 LIOI3_TBYTETERM.OLOGIC_Y0.OQUSED 31_86
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE 33_73
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+LIOI3_TBYTETERM.OLOGIC_Y0.TDDR.SRUSED 33_89
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_OQ 33_97
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_TQ 30_75
-LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK 31_90
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T1 30_67
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T2 30_71
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 LIOI3_TBYTETERM.OLOGIC_Y1.IS_D7_INVERTED 30_09
 LIOI3_TBYTETERM.OLOGIC_Y1.IS_D8_INVERTED 31_02
 LIOI3_TBYTETERM.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+LIOI3_TBYTETERM.OLOGIC_Y1.ODDR.SRUSED 33_15
+LIOI3_TBYTETERM.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 LIOI3_TBYTETERM.OLOGIC_Y1.OMUX.D1 32_16
 LIOI3_TBYTETERM.OLOGIC_Y1.OQUSED 30_41
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE 32_54
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+LIOI3_TBYTETERM.OLOGIC_Y1.TDDR.SRUSED 32_38
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_OQ 32_30
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_TQ 31_52
-LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK 30_37
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T1 31_60
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T2 31_56
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/kintex7/segbits_lioi3_tbyteterm.origin_info.db b/kintex7/segbits_lioi3_tbyteterm.origin_info.db
index e72ab0e..8559928 100644
--- a/kintex7/segbits_lioi3_tbyteterm.origin_info.db
+++ b/kintex7/segbits_lioi3_tbyteterm.origin_info.db

@@ -40,6 +40,7 @@
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+LIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 LIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 LIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+LIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 LIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 LIOI3_TBYTETERM.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 LIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 LIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 LIOI3_TBYTETERM.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 LIOI3_TBYTETERM.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 LIOI3_TBYTETERM.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+LIOI3_TBYTETERM.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+LIOI3_TBYTETERM.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 LIOI3_TBYTETERM.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 LIOI3_TBYTETERM.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+LIOI3_TBYTETERM.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 LIOI3_TBYTETERM.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 LIOI3_TBYTETERM.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 LIOI3_TBYTETERM.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+LIOI3_TBYTETERM.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+LIOI3_TBYTETERM.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 LIOI3_TBYTETERM.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 LIOI3_TBYTETERM.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+LIOI3_TBYTETERM.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/kintex7/segbits_riob33.origin_info.db b/kintex7/segbits_riob33.origin_info.db
index a6d64c5..8db23c8 100644
--- a/kintex7/segbits_riob33.origin_info.db
+++ b/kintex7/segbits_riob33.origin_info.db

@@ -37,10 +37,10 @@
 RIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87
 RIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST origin:030-iob !38_106 38_110 39_105 39_107 39_109 39_111
 RIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45
-RIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_4 !38_6 !39_5 !39_7
-RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_4 38_6 39_5 39_7
-RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_6 38_4 39_5 39_7
-RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_6 !39_5 38_4 39_7
+RIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_04 !38_06 !39_05 !39_07
+RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07
+RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07
+RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07
 RIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
 RIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63
 RIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35

diff --git a/kintex7/segbits_rioi3.db b/kintex7/segbits_rioi3.db
index 852f46e..8d44a45 100644
--- a/kintex7/segbits_rioi3.db
+++ b/kintex7/segbits_rioi3.db

@@ -40,6 +40,7 @@
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+RIOI3.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 RIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 RIOI3.ILOGIC_Y0.IDELMUXE3.P0 29_101
 RIOI3.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 RIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+RIOI3.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 RIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 RIOI3.OLOGIC_Y0.IS_D7_INVERTED 31_118
 RIOI3.OLOGIC_Y0.IS_D8_INVERTED 30_125
 RIOI3.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+RIOI3.OLOGIC_Y0.ODDR.SRUSED 32_112
+RIOI3.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 RIOI3.OLOGIC_Y0.OMUX.D1 33_111
 RIOI3.OLOGIC_Y0.OQUSED 31_86
 RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.IN_USE 33_73
 RIOI3.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 RIOI3.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 RIOI3.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 RIOI3.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+RIOI3.OLOGIC_Y0.TDDR.SRUSED 33_89
 RIOI3.OLOGIC_Y0.ZINIT_OQ 33_97
 RIOI3.OLOGIC_Y0.ZINIT_TQ 30_75
-RIOI3.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+RIOI3.OLOGIC_Y0.ZINV_CLK 31_90
 RIOI3.OLOGIC_Y0.ZINV_T1 30_67
 RIOI3.OLOGIC_Y0.ZINV_T2 30_71
 RIOI3.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 RIOI3.OLOGIC_Y1.IS_D7_INVERTED 30_09
 RIOI3.OLOGIC_Y1.IS_D8_INVERTED 31_02
 RIOI3.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+RIOI3.OLOGIC_Y1.ODDR.SRUSED 33_15
+RIOI3.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 RIOI3.OLOGIC_Y1.OMUX.D1 32_16
 RIOI3.OLOGIC_Y1.OQUSED 30_41
 RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.IN_USE 32_54
 RIOI3.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 RIOI3.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 RIOI3.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 RIOI3.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+RIOI3.OLOGIC_Y1.TDDR.SRUSED 32_38
 RIOI3.OLOGIC_Y1.ZINIT_OQ 32_30
 RIOI3.OLOGIC_Y1.ZINIT_TQ 31_52
-RIOI3.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+RIOI3.OLOGIC_Y1.ZINV_CLK 30_37
 RIOI3.OLOGIC_Y1.ZINV_T1 31_60
 RIOI3.OLOGIC_Y1.ZINV_T2 31_56
 RIOI3.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/kintex7/segbits_rioi3.origin_info.db b/kintex7/segbits_rioi3.origin_info.db
index 5c6e73b..a796d38 100644
--- a/kintex7/segbits_rioi3.origin_info.db
+++ b/kintex7/segbits_rioi3.origin_info.db

@@ -40,6 +40,7 @@
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+RIOI3.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 RIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 RIOI3.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 RIOI3.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 RIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+RIOI3.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 RIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 RIOI3.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 RIOI3.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 RIOI3.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-RIOI3.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 RIOI3.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 RIOI3.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 RIOI3.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 RIOI3.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 RIOI3.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 RIOI3.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-RIOI3.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 RIOI3.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 RIOI3.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 RIOI3.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 RIOI3.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 RIOI3.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 RIOI3.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+RIOI3.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+RIOI3.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 RIOI3.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 RIOI3.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-RIOI3.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 RIOI3.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 RIOI3.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 RIOI3.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 RIOI3.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+RIOI3.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 RIOI3.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 RIOI3.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-RIOI3.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+RIOI3.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 RIOI3.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 RIOI3.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 RIOI3.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 RIOI3.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 RIOI3.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 RIOI3.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+RIOI3.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+RIOI3.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 RIOI3.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 RIOI3.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-RIOI3.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 RIOI3.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 RIOI3.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 RIOI3.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 RIOI3.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+RIOI3.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 RIOI3.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 RIOI3.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-RIOI3.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+RIOI3.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 RIOI3.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 RIOI3.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 RIOI3.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/kintex7/segbits_rioi3_tbytesrc.db b/kintex7/segbits_rioi3_tbytesrc.db
index c2b6214..87be7f7 100644
--- a/kintex7/segbits_rioi3_tbytesrc.db
+++ b/kintex7/segbits_rioi3_tbytesrc.db

@@ -40,6 +40,7 @@
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+RIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 RIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 29_101
 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 RIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+RIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 RIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 RIOI3_TBYTESRC.OLOGIC_Y0.IS_D7_INVERTED 31_118
 RIOI3_TBYTESRC.OLOGIC_Y0.IS_D8_INVERTED 30_125
 RIOI3_TBYTESRC.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+RIOI3_TBYTESRC.OLOGIC_Y0.ODDR.SRUSED 32_112
+RIOI3_TBYTESRC.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 RIOI3_TBYTESRC.OLOGIC_Y0.OMUX.D1 33_111
 RIOI3_TBYTESRC.OLOGIC_Y0.OQUSED 31_86
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE 33_73
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+RIOI3_TBYTESRC.OLOGIC_Y0.TDDR.SRUSED 33_89
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_OQ 33_97
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_TQ 30_75
-RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK 31_90
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T1 30_67
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T2 30_71
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 RIOI3_TBYTESRC.OLOGIC_Y1.IS_D7_INVERTED 30_09
 RIOI3_TBYTESRC.OLOGIC_Y1.IS_D8_INVERTED 31_02
 RIOI3_TBYTESRC.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+RIOI3_TBYTESRC.OLOGIC_Y1.ODDR.SRUSED 33_15
+RIOI3_TBYTESRC.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 RIOI3_TBYTESRC.OLOGIC_Y1.OMUX.D1 32_16
 RIOI3_TBYTESRC.OLOGIC_Y1.OQUSED 30_41
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE 32_54
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+RIOI3_TBYTESRC.OLOGIC_Y1.TDDR.SRUSED 32_38
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_OQ 32_30
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_TQ 31_52
-RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK 30_37
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T1 31_60
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T2 31_56
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/kintex7/segbits_rioi3_tbytesrc.origin_info.db b/kintex7/segbits_rioi3_tbytesrc.origin_info.db
index 440fa78..23c8e8e 100644
--- a/kintex7/segbits_rioi3_tbytesrc.origin_info.db
+++ b/kintex7/segbits_rioi3_tbytesrc.origin_info.db

@@ -40,6 +40,7 @@
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+RIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 RIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 RIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+RIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 RIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 RIOI3_TBYTESRC.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 RIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 RIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 RIOI3_TBYTESRC.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 RIOI3_TBYTESRC.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 RIOI3_TBYTESRC.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+RIOI3_TBYTESRC.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+RIOI3_TBYTESRC.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 RIOI3_TBYTESRC.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 RIOI3_TBYTESRC.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+RIOI3_TBYTESRC.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 RIOI3_TBYTESRC.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 RIOI3_TBYTESRC.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 RIOI3_TBYTESRC.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+RIOI3_TBYTESRC.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+RIOI3_TBYTESRC.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 RIOI3_TBYTESRC.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 RIOI3_TBYTESRC.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+RIOI3_TBYTESRC.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/kintex7/segbits_rioi3_tbyteterm.db b/kintex7/segbits_rioi3_tbyteterm.db
index bafc348..95901a8 100644
--- a/kintex7/segbits_rioi3_tbyteterm.db
+++ b/kintex7/segbits_rioi3_tbyteterm.db

@@ -40,6 +40,7 @@
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+RIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 RIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 29_101
 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 RIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+RIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 RIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 RIOI3_TBYTETERM.OLOGIC_Y0.IS_D7_INVERTED 31_118
 RIOI3_TBYTETERM.OLOGIC_Y0.IS_D8_INVERTED 30_125
 RIOI3_TBYTETERM.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+RIOI3_TBYTETERM.OLOGIC_Y0.ODDR.SRUSED 32_112
+RIOI3_TBYTETERM.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 RIOI3_TBYTETERM.OLOGIC_Y0.OMUX.D1 33_111
 RIOI3_TBYTETERM.OLOGIC_Y0.OQUSED 31_86
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE 33_73
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+RIOI3_TBYTETERM.OLOGIC_Y0.TDDR.SRUSED 33_89
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_OQ 33_97
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_TQ 30_75
-RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK 31_90
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T1 30_67
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T2 30_71
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 RIOI3_TBYTETERM.OLOGIC_Y1.IS_D7_INVERTED 30_09
 RIOI3_TBYTETERM.OLOGIC_Y1.IS_D8_INVERTED 31_02
 RIOI3_TBYTETERM.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+RIOI3_TBYTETERM.OLOGIC_Y1.ODDR.SRUSED 33_15
+RIOI3_TBYTETERM.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 RIOI3_TBYTETERM.OLOGIC_Y1.OMUX.D1 32_16
 RIOI3_TBYTETERM.OLOGIC_Y1.OQUSED 30_41
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE 32_54
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+RIOI3_TBYTETERM.OLOGIC_Y1.TDDR.SRUSED 32_38
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_OQ 32_30
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_TQ 31_52
-RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK 30_37
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T1 31_60
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T2 31_56
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/kintex7/segbits_rioi3_tbyteterm.origin_info.db b/kintex7/segbits_rioi3_tbyteterm.origin_info.db
index 106e4ad..d2489b9 100644
--- a/kintex7/segbits_rioi3_tbyteterm.origin_info.db
+++ b/kintex7/segbits_rioi3_tbyteterm.origin_info.db

@@ -40,6 +40,7 @@
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+RIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 RIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 RIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+RIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 RIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 RIOI3_TBYTETERM.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 RIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 RIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 RIOI3_TBYTETERM.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 RIOI3_TBYTETERM.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 RIOI3_TBYTETERM.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+RIOI3_TBYTETERM.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+RIOI3_TBYTETERM.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 RIOI3_TBYTETERM.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 RIOI3_TBYTETERM.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+RIOI3_TBYTETERM.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 RIOI3_TBYTETERM.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 RIOI3_TBYTETERM.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 RIOI3_TBYTETERM.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+RIOI3_TBYTETERM.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+RIOI3_TBYTETERM.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 RIOI3_TBYTETERM.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 RIOI3_TBYTETERM.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+RIOI3_TBYTETERM.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/kintex7/xc7k70tfbg676-2/tilegrid.json b/kintex7/xc7k70tfbg676-2/tilegrid.json
index 79a826f..0b70b71 100644
--- a/kintex7/xc7k70tfbg676-2/tilegrid.json
+++ b/kintex7/xc7k70tfbg676-2/tilegrid.json

@@ -116616,7 +116616,7 @@
                 "baseaddr": "0x00421500",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y0",
@@ -116635,7 +116635,7 @@
                 "baseaddr": "0x00401500",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X1Y1",
@@ -116717,8 +116717,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00421500",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y0",
@@ -116736,8 +116736,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00401500",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y1",
@@ -116756,7 +116756,7 @@
                 "baseaddr": "0x00420080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y0",
@@ -116775,7 +116775,7 @@
                 "baseaddr": "0x00400080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y1",
@@ -116794,7 +116794,7 @@
                 "baseaddr": "0x00000080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y2",
@@ -116813,7 +116813,7 @@
                 "baseaddr": "0x00020080",
                 "frames": 30,
                 "offset": 0,
-                "words": 101
+                "words": 49
             }
         },
         "clock_region": "X0Y3",
@@ -116959,8 +116959,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00420080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y0",
@@ -116978,8 +116978,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00400080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y1",
@@ -116997,8 +116997,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00000080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y2",
@@ -117016,8 +117016,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00020080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y3",

diff --git a/zynq7/mask_clbll_l.db b/zynq7/mask_clbll_l.db
index aee22a3..bc31d2b 100644
--- a/zynq7/mask_clbll_l.db
+++ b/zynq7/mask_clbll_l.db

@@ -2139,7 +2139,6 @@
 bit 34_12
 bit 34_13
 bit 34_14
-bit 34_15
 bit 34_16
 bit 34_17
 bit 34_18
@@ -2155,7 +2154,6 @@
 bit 34_28
 bit 34_29
 bit 34_30
-bit 34_31
 bit 34_32
 bit 34_33
 bit 34_34
@@ -2171,7 +2169,6 @@
 bit 34_44
 bit 34_45
 bit 34_46
-bit 34_47
 bit 34_48
 bit 34_49
 bit 34_50
@@ -2187,7 +2184,6 @@
 bit 34_60
 bit 34_61
 bit 34_62
-bit 34_63
 bit 35_00
 bit 35_01
 bit 35_02

diff --git a/zynq7/mask_clbll_r.db b/zynq7/mask_clbll_r.db
index aee22a3..bc31d2b 100644
--- a/zynq7/mask_clbll_r.db
+++ b/zynq7/mask_clbll_r.db

@@ -2139,7 +2139,6 @@
 bit 34_12
 bit 34_13
 bit 34_14
-bit 34_15
 bit 34_16
 bit 34_17
 bit 34_18
@@ -2155,7 +2154,6 @@
 bit 34_28
 bit 34_29
 bit 34_30
-bit 34_31
 bit 34_32
 bit 34_33
 bit 34_34
@@ -2171,7 +2169,6 @@
 bit 34_44
 bit 34_45
 bit 34_46
-bit 34_47
 bit 34_48
 bit 34_49
 bit 34_50
@@ -2187,7 +2184,6 @@
 bit 34_60
 bit 34_61
 bit 34_62
-bit 34_63
 bit 35_00
 bit 35_01
 bit 35_02

diff --git a/zynq7/mask_clblm_l.db b/zynq7/mask_clblm_l.db
index 1426eb6..07cd8b5 100644
--- a/zynq7/mask_clblm_l.db
+++ b/zynq7/mask_clblm_l.db

@@ -2149,7 +2149,6 @@
 bit 34_12
 bit 34_13
 bit 34_14
-bit 34_15
 bit 34_16
 bit 34_17
 bit 34_18
@@ -2165,7 +2164,6 @@
 bit 34_28
 bit 34_29
 bit 34_30
-bit 34_31
 bit 34_32
 bit 34_33
 bit 34_34
@@ -2181,7 +2179,6 @@
 bit 34_44
 bit 34_45
 bit 34_46
-bit 34_47
 bit 34_48
 bit 34_49
 bit 34_50
@@ -2197,7 +2194,6 @@
 bit 34_60
 bit 34_61
 bit 34_62
-bit 34_63
 bit 35_00
 bit 35_01
 bit 35_02

diff --git a/zynq7/mask_clblm_r.db b/zynq7/mask_clblm_r.db
index 1426eb6..07cd8b5 100644
--- a/zynq7/mask_clblm_r.db
+++ b/zynq7/mask_clblm_r.db

@@ -2149,7 +2149,6 @@
 bit 34_12
 bit 34_13
 bit 34_14
-bit 34_15
 bit 34_16
 bit 34_17
 bit 34_18
@@ -2165,7 +2164,6 @@
 bit 34_28
 bit 34_29
 bit 34_30
-bit 34_31
 bit 34_32
 bit 34_33
 bit 34_34
@@ -2181,7 +2179,6 @@
 bit 34_44
 bit 34_45
 bit 34_46
-bit 34_47
 bit 34_48
 bit 34_49
 bit 34_50
@@ -2197,7 +2194,6 @@
 bit 34_60
 bit 34_61
 bit 34_62
-bit 34_63
 bit 35_00
 bit 35_01
 bit 35_02

diff --git a/zynq7/mask_lioi3.db b/zynq7/mask_lioi3.db
index 4a5f68d..11df0a4 100644
--- a/zynq7/mask_lioi3.db
+++ b/zynq7/mask_lioi3.db

@@ -1,4 +1,5 @@
 bit 25_07
+bit 25_08
 bit 25_16
 bit 25_20
 bit 25_21

diff --git a/zynq7/mask_lioi3_tbytesrc.db b/zynq7/mask_lioi3_tbytesrc.db
index 4a5f68d..11df0a4 100644
--- a/zynq7/mask_lioi3_tbytesrc.db
+++ b/zynq7/mask_lioi3_tbytesrc.db

@@ -1,4 +1,5 @@
 bit 25_07
+bit 25_08
 bit 25_16
 bit 25_20
 bit 25_21

diff --git a/zynq7/mask_lioi3_tbyteterm.db b/zynq7/mask_lioi3_tbyteterm.db
index 4a5f68d..11df0a4 100644
--- a/zynq7/mask_lioi3_tbyteterm.db
+++ b/zynq7/mask_lioi3_tbyteterm.db

@@ -1,4 +1,5 @@
 bit 25_07
+bit 25_08
 bit 25_16
 bit 25_20
 bit 25_21

diff --git a/zynq7/mask_rioi3.db b/zynq7/mask_rioi3.db
index 4a5f68d..11df0a4 100644
--- a/zynq7/mask_rioi3.db
+++ b/zynq7/mask_rioi3.db

@@ -1,4 +1,5 @@
 bit 25_07
+bit 25_08
 bit 25_16
 bit 25_20
 bit 25_21

diff --git a/zynq7/mask_rioi3_tbytesrc.db b/zynq7/mask_rioi3_tbytesrc.db
index 4a5f68d..11df0a4 100644
--- a/zynq7/mask_rioi3_tbytesrc.db
+++ b/zynq7/mask_rioi3_tbytesrc.db

@@ -1,4 +1,5 @@
 bit 25_07
+bit 25_08
 bit 25_16
 bit 25_20
 bit 25_21

diff --git a/zynq7/mask_rioi3_tbyteterm.db b/zynq7/mask_rioi3_tbyteterm.db
index 4a5f68d..11df0a4 100644
--- a/zynq7/mask_rioi3_tbyteterm.db
+++ b/zynq7/mask_rioi3_tbyteterm.db

@@ -1,4 +1,5 @@
 bit 25_07
+bit 25_08
 bit 25_16
 bit 25_20
 bit 25_21

diff --git a/zynq7/segbits_clk_bufg_bot_r.origin_info.db b/zynq7/segbits_clk_bufg_bot_r.origin_info.db
index f18cf2e..f679954 100644
--- a/zynq7/segbits_clk_bufg_bot_r.origin_info.db
+++ b/zynq7/segbits_clk_bufg_bot_r.origin_info.db

@@ -178,159 +178,159 @@
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_08 26_07 27_06
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_08 !27_06 26_07
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_07 !26_08 27_06
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_07 !26_08 !27_06
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_07 !26_08 !27_06
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_BOT_R_CK_MUXED1 origin:046-clk-bufg-muxed-pips !26_05 !27_05 26_04
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_04 26_05 27_05
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_04 !26_05 27_05
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_04 !27_05 26_05
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_04 !26_05 !27_05
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_04 !26_05 !27_05
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_BOT_R_CK_MUXED2 origin:046-clk-bufg-muxed-pips !26_23 !27_22 26_24
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_24 !27_22 26_23
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_24 26_23 27_22
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_23 !26_24 27_22
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_23 !26_24 !27_22
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_23 !26_24 !27_22
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_BOT_R_CK_MUXED3 origin:046-clk-bufg-muxed-pips !26_21 !27_21 26_20
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_20 !26_21 27_21
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_20 26_21 27_21
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_20 !27_21 26_21
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_20 !26_21 !27_21
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_20 !26_21 !27_21
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_BOT_R_CK_MUXED4 origin:046-clk-bufg-muxed-pips !26_39 !27_38 26_40
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_40 !27_38 26_39
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_40 26_39 27_38
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_39 !26_40 27_38
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_39 !26_40 !27_38
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_39 !26_40 !27_38
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_BOT_R_CK_MUXED5 origin:046-clk-bufg-muxed-pips !26_37 !27_37 26_36
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_36 !26_37 27_37
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_36 26_37 27_37
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_36 !27_37 26_37
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_36 !26_37 !27_37
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_36 !26_37 !27_37
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_BOT_R_CK_MUXED6 origin:046-clk-bufg-muxed-pips !26_55 !27_54 26_56
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_56 !27_54 26_55
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_56 26_55 27_54
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_55 !26_56 27_54
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_55 !26_56 !27_54
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_55 !26_56 !27_54
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_BOT_R_CK_MUXED7 origin:046-clk-bufg-muxed-pips !26_53 !27_53 26_52
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_52 !26_53 27_53
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_52 26_53 27_53
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_52 !27_53 26_53
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_52 !26_53 !27_53
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_52 !26_53 !27_53
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_BOT_R_CK_MUXED8 origin:046-clk-bufg-muxed-pips !26_71 !27_70 26_72
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_72 !27_70 26_71
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_72 26_71 27_70
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_71 !26_72 27_70
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_71 !26_72 !27_70
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_71 !26_72 !27_70
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_BOT_R_CK_MUXED9 origin:046-clk-bufg-muxed-pips !26_69 !27_69 26_68
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_68 !26_69 27_69
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_68 26_69 27_69
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_68 !27_69 26_69
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_68 !26_69 !27_69
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_68 !26_69 !27_69
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_BOT_R_CK_MUXED10 origin:046-clk-bufg-muxed-pips !26_87 !27_86 26_88
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_88 !27_86 26_87
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_88 26_87 27_86
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_87 !26_88 27_86
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_87 !26_88 !27_86
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_87 !26_88 !27_86
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_BOT_R_CK_MUXED11 origin:046-clk-bufg-muxed-pips !26_85 !27_85 26_84
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_84 !26_85 27_85
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_84 26_85 27_85
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_84 !27_85 26_85
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_84 !26_85 !27_85
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_84 !26_85 !27_85
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_BOT_R_CK_MUXED12 origin:046-clk-bufg-muxed-pips !26_103 !27_102 26_104
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_104 !27_102 26_103
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_104 26_103 27_102
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_103 !26_104 27_102
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_103 !26_104 !27_102
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_103 !26_104 !27_102
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_BOT_R_CK_MUXED13 origin:046-clk-bufg-muxed-pips !26_101 !27_101 26_100
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_100 !26_101 27_101
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_100 26_101 27_101
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_100 !27_101 26_101
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_100 !26_101 !27_101
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_100 !26_101 !27_101
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_BOT_R_CK_MUXED14 origin:046-clk-bufg-muxed-pips !26_119 !27_118 26_120
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_120 !27_118 26_119
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_120 26_119 27_118
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_119 !26_120 27_118
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_119 !26_120 !27_118
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_119 !26_120 !27_118
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_BOT_R_CK_MUXED15 origin:046-clk-bufg-muxed-pips !26_117 !27_117 26_116
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_116 !26_117 27_117
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_116 26_117 27_117
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_116 !27_117 26_117
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_116 !26_117 !27_117
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_116 !26_117 !27_117
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_BOT_R_CK_MUXED16 origin:046-clk-bufg-muxed-pips !26_135 !27_134 26_136
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_136 !27_134 26_135
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_136 26_135 27_134
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_135 !26_136 27_134
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_135 !26_136 !27_134
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_135 !26_136 !27_134
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_BOT_R_CK_MUXED17 origin:046-clk-bufg-muxed-pips !26_133 !27_133 26_132
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_132 !26_133 27_133
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_132 26_133 27_133
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_132 !27_133 26_133
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_132 !26_133 !27_133
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_132 !26_133 !27_133
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_BOT_R_CK_MUXED18 origin:046-clk-bufg-muxed-pips !26_151 !27_150 26_152
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_152 !27_150 26_151
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_152 26_151 27_150
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_151 !26_152 27_150
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_151 !26_152 !27_150
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_151 !26_152 !27_150
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_BOT_R_CK_MUXED19 origin:046-clk-bufg-muxed-pips !26_149 !27_149 26_148
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_148 !26_149 27_149
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_148 26_149 27_149
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_148 !27_149 26_149
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_148 !26_149 !27_149
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_148 !26_149 !27_149
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_BOT_R_CK_MUXED20 origin:046-clk-bufg-muxed-pips !26_167 !27_166 26_168
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_168 !27_166 26_167
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_168 26_167 27_166
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_167 !26_168 27_166
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_167 !26_168 !27_166
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_167 !26_168 !27_166
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_BOT_R_CK_MUXED21 origin:046-clk-bufg-muxed-pips !26_165 !27_165 26_164
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_164 !26_165 27_165
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_164 26_165 27_165
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_164 !27_165 26_165
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_164 !26_165 !27_165
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_164 !26_165 !27_165
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_BOT_R_CK_MUXED22 origin:046-clk-bufg-muxed-pips !26_183 !27_182 26_184
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_184 !27_182 26_183
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_184 26_183 27_182
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_183 !26_184 27_182
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_183 !26_184 !27_182
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_183 !26_184 !27_182
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_BOT_R_CK_MUXED23 origin:046-clk-bufg-muxed-pips !26_181 !27_181 26_180
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_180 !26_181 27_181
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_180 26_181 27_181
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_180 !27_181 26_181
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_180 !26_181 !27_181
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_180 !26_181 !27_181
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_BOT_R_CK_MUXED24 origin:046-clk-bufg-muxed-pips !26_199 !27_198 26_200
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_200 !27_198 26_199
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_200 26_199 27_198
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_199 !26_200 27_198
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_199 !26_200 !27_198
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_199 !26_200 !27_198
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_BOT_R_CK_MUXED25 origin:046-clk-bufg-muxed-pips !26_197 !27_197 26_196
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_196 !26_197 27_197
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_196 26_197 27_197
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_196 !27_197 26_197
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_196 !26_197 !27_197
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_196 !26_197 !27_197
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_BOT_R_CK_MUXED26 origin:046-clk-bufg-muxed-pips !26_215 !27_214 26_216
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_216 !27_214 26_215
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_216 26_215 27_214
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_215 !26_216 27_214
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_215 !26_216 !27_214
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_215 !26_216 !27_214
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_BOT_R_CK_MUXED27 origin:046-clk-bufg-muxed-pips !26_213 !27_213 26_212
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_212 !26_213 27_213
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_212 26_213 27_213
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_212 !27_213 26_213
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_212 !26_213 !27_213
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_212 !26_213 !27_213
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_BOT_R_CK_MUXED28 origin:046-clk-bufg-muxed-pips !26_231 !27_230 26_232
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_232 !27_230 26_231
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_232 26_231 27_230
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_231 !26_232 27_230
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_231 !26_232 !27_230
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_231 !26_232 !27_230
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_BOT_R_CK_MUXED29 origin:046-clk-bufg-muxed-pips !26_229 !27_229 26_228
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_228 !26_229 27_229
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_228 26_229 27_229
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_228 !27_229 26_229
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_228 !26_229 !27_229
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_228 !26_229 !27_229
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_BOT_R_CK_MUXED30 origin:046-clk-bufg-muxed-pips !26_247 !27_246 26_248
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_248 26_247 27_246
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_248 !27_246 26_247
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_247 !26_248 27_246
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_247 !26_248 !27_246
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_247 !26_248 !27_246
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_BOT_R_CK_MUXED31 origin:046-clk-bufg-muxed-pips !26_245 !27_245 26_244
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_244 26_245 27_245
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_244 !26_245 27_245
 CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_244 !27_245 26_245
-CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_244 !26_245 !27_245
+CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_244 !26_245 !27_245

diff --git a/zynq7/segbits_clk_bufg_top_r.origin_info.db b/zynq7/segbits_clk_bufg_top_r.origin_info.db
index b23f2e4..ddcc016 100644
--- a/zynq7/segbits_clk_bufg_top_r.origin_info.db
+++ b/zynq7/segbits_clk_bufg_top_r.origin_info.db

@@ -178,159 +178,159 @@
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_08 !27_06 26_07
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0 origin:046-clk-bufg-muxed-pips !26_07 !27_06 26_08
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_07 !26_08 27_06
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_07 !26_08 !27_06
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_07 !26_08 !27_06
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_04 26_05 27_05
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_04 !26_05 27_05
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_TOP_R_CK_MUXED1 origin:046-clk-bufg-muxed-pips !26_05 !27_05 26_04
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_04 !27_05 26_05
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_04 !26_05 !27_05
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_04 !26_05 !27_05
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_24 !27_22 26_23
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_24 26_23 27_22
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_TOP_R_CK_MUXED2 origin:046-clk-bufg-muxed-pips !26_23 !27_22 26_24
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_23 !26_24 27_22
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_23 !26_24 !27_22
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_23 !26_24 !27_22
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_20 !26_21 27_21
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_20 26_21 27_21
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_TOP_R_CK_MUXED3 origin:046-clk-bufg-muxed-pips !26_21 !27_21 26_20
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_20 !27_21 26_21
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_20 !26_21 !27_21
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_20 !26_21 !27_21
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_40 !27_38 26_39
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_40 26_39 27_38
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_TOP_R_CK_MUXED4 origin:046-clk-bufg-muxed-pips !26_39 !27_38 26_40
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_39 !26_40 27_38
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_39 !26_40 !27_38
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_39 !26_40 !27_38
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_36 !26_37 27_37
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_36 26_37 27_37
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_TOP_R_CK_MUXED5 origin:046-clk-bufg-muxed-pips !26_37 !27_37 26_36
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_36 !27_37 26_37
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_36 !26_37 !27_37
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_36 !26_37 !27_37
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_56 !27_54 26_55
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_56 26_55 27_54
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_TOP_R_CK_MUXED6 origin:046-clk-bufg-muxed-pips !26_55 !27_54 26_56
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_55 !26_56 27_54
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_55 !26_56 !27_54
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_55 !26_56 !27_54
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_52 !26_53 27_53
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_52 26_53 27_53
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_TOP_R_CK_MUXED7 origin:046-clk-bufg-muxed-pips !26_53 !27_53 26_52
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_52 !27_53 26_53
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_52 !26_53 !27_53
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_52 !26_53 !27_53
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_72 !27_70 26_71
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_72 26_71 27_70
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_TOP_R_CK_MUXED8 origin:046-clk-bufg-muxed-pips !26_71 !27_70 26_72
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_71 !26_72 27_70
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_71 !26_72 !27_70
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_71 !26_72 !27_70
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_68 !26_69 27_69
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_68 26_69 27_69
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_TOP_R_CK_MUXED9 origin:046-clk-bufg-muxed-pips !26_69 !27_69 26_68
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_68 !27_69 26_69
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_68 !26_69 !27_69
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_68 !26_69 !27_69
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_88 !27_86 26_87
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_88 26_87 27_86
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_TOP_R_CK_MUXED10 origin:046-clk-bufg-muxed-pips !26_87 !27_86 26_88
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_87 !26_88 27_86
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_87 !26_88 !27_86
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_87 !26_88 !27_86
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_84 !26_85 27_85
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_84 26_85 27_85
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_TOP_R_CK_MUXED11 origin:046-clk-bufg-muxed-pips !26_85 !27_85 26_84
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_84 !27_85 26_85
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_84 !26_85 !27_85
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_84 !26_85 !27_85
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_104 !27_102 26_103
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_104 26_103 27_102
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_TOP_R_CK_MUXED12 origin:046-clk-bufg-muxed-pips !26_103 !27_102 26_104
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_103 !26_104 27_102
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_103 !26_104 !27_102
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_103 !26_104 !27_102
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_100 !26_101 27_101
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_100 26_101 27_101
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_TOP_R_CK_MUXED13 origin:046-clk-bufg-muxed-pips !26_101 !27_101 26_100
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_100 !27_101 26_101
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_100 !26_101 !27_101
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_100 !26_101 !27_101
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_120 !27_118 26_119
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_120 26_119 27_118
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_TOP_R_CK_MUXED14 origin:046-clk-bufg-muxed-pips !26_119 !27_118 26_120
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_119 !26_120 27_118
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_119 !26_120 !27_118
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_119 !26_120 !27_118
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_116 !26_117 27_117
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_116 26_117 27_117
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_TOP_R_CK_MUXED15 origin:046-clk-bufg-muxed-pips !26_117 !27_117 26_116
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_116 !27_117 26_117
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_116 !26_117 !27_117
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_116 !26_117 !27_117
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_136 !27_134 26_135
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_136 26_135 27_134
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_TOP_R_CK_MUXED16 origin:046-clk-bufg-muxed-pips !26_135 !27_134 26_136
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_135 !26_136 27_134
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_135 !26_136 !27_134
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_135 !26_136 !27_134
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_132 !26_133 27_133
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_132 26_133 27_133
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_TOP_R_CK_MUXED17 origin:046-clk-bufg-muxed-pips !26_133 !27_133 26_132
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_132 !27_133 26_133
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_132 !26_133 !27_133
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_132 !26_133 !27_133
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_152 !27_150 26_151
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_152 26_151 27_150
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_TOP_R_CK_MUXED18 origin:046-clk-bufg-muxed-pips !26_151 !27_150 26_152
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_151 !26_152 27_150
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_151 !26_152 !27_150
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_151 !26_152 !27_150
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_148 !26_149 27_149
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_148 26_149 27_149
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_TOP_R_CK_MUXED19 origin:046-clk-bufg-muxed-pips !26_149 !27_149 26_148
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_148 !27_149 26_149
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_148 !26_149 !27_149
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_148 !26_149 !27_149
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_168 !27_166 26_167
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_168 26_167 27_166
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_TOP_R_CK_MUXED20 origin:046-clk-bufg-muxed-pips !26_167 !27_166 26_168
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_167 !26_168 27_166
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_167 !26_168 !27_166
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_167 !26_168 !27_166
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_164 !26_165 27_165
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_164 26_165 27_165
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_TOP_R_CK_MUXED21 origin:046-clk-bufg-muxed-pips !26_165 !27_165 26_164
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_164 !27_165 26_165
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_164 !26_165 !27_165
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_164 !26_165 !27_165
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_184 !27_182 26_183
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_184 26_183 27_182
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_TOP_R_CK_MUXED22 origin:046-clk-bufg-muxed-pips !26_183 !27_182 26_184
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_183 !26_184 27_182
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_183 !26_184 !27_182
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_183 !26_184 !27_182
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_180 !26_181 27_181
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_180 26_181 27_181
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_TOP_R_CK_MUXED23 origin:046-clk-bufg-muxed-pips !26_181 !27_181 26_180
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_180 !27_181 26_181
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_180 !26_181 !27_181
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_180 !26_181 !27_181
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_200 !27_198 26_199
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_200 26_199 27_198
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_TOP_R_CK_MUXED24 origin:046-clk-bufg-muxed-pips !26_199 !27_198 26_200
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_199 !26_200 27_198
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_199 !26_200 !27_198
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_199 !26_200 !27_198
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_196 !26_197 27_197
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_196 26_197 27_197
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_TOP_R_CK_MUXED25 origin:046-clk-bufg-muxed-pips !26_197 !27_197 26_196
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_196 !27_197 26_197
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_196 !26_197 !27_197
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_196 !26_197 !27_197
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_216 !27_214 26_215
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_216 26_215 27_214
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_TOP_R_CK_MUXED26 origin:046-clk-bufg-muxed-pips !26_215 !27_214 26_216
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_215 !26_216 27_214
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_215 !26_216 !27_214
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_215 !26_216 !27_214
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_212 !26_213 27_213
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_212 26_213 27_213
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_TOP_R_CK_MUXED27 origin:046-clk-bufg-muxed-pips !26_213 !27_213 26_212
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_212 !27_213 26_213
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_212 !26_213 !27_213
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_212 !26_213 !27_213
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_232 !27_230 26_231
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_232 26_231 27_230
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_TOP_R_CK_MUXED28 origin:046-clk-bufg-muxed-pips !26_231 !27_230 26_232
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_231 !26_232 27_230
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_231 !26_232 !27_230
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_231 !26_232 !27_230
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_228 !26_229 27_229
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_228 26_229 27_229
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_TOP_R_CK_MUXED29 origin:046-clk-bufg-muxed-pips !26_229 !27_229 26_228
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_228 !27_229 26_229
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_228 !26_229 !27_229
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_228 !26_229 !27_229
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_248 26_247 27_246
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_248 !27_246 26_247
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_TOP_R_CK_MUXED30 origin:046-clk-bufg-muxed-pips !26_247 !27_246 26_248
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_247 !26_248 27_246
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_247 !26_248 !27_246
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_247 !26_248 !27_246
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_244 26_245 27_245
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_244 !26_245 27_245
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_TOP_R_CK_MUXED31 origin:046-clk-bufg-muxed-pips !26_245 !27_245 26_244
 CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_244 !27_245 26_245
-CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_244 !26_245 !27_245
+CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:046-clk-bufg-muxed-pips,044-clk-bufg-pips !26_244 !26_245 !27_245

diff --git a/zynq7/segbits_cmt_top_l_lower_b.db b/zynq7/segbits_cmt_top_l_lower_b.db
new file mode 100644
index 0000000..4eda515
--- /dev/null
+++ b/zynq7/segbits_cmt_top_l_lower_b.db

@@ -0,0 +1,396 @@
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB0 !28_1012 28_1013 29_979 29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB1 !28_1012 !28_1013 29_979 29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB2 !28_1012 28_1013 29_979 !29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB3 !28_1012 !28_1013 29_979 !29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_IN3_HCLK 28_1012 !28_1013 29_979 !29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_IN3_INT 28_1012 28_1013 29_979 !29_1012
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_LR_LOWER_B_CLKFBOUT2IN 28_980 28_981 29_980
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB0 28_1014 28_1015 !29_1013 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB1 28_1014 !28_1015 !29_1013 !29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB2 !28_1014 !28_1015 !29_1013 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB3 !28_1014 !28_1015 !29_1013 !29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_IN1_HCLK !28_1014 !28_1015 29_1013 !29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_IN1_INT !28_1014 !28_1015 29_1013 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB0 !28_1015 28_1016 29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB1 !28_1015 !28_1016 29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB2 !28_1015 28_1016 !29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB3 !28_1015 !28_1016 !29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_IN2_HCLK 28_1015 !28_1016 !29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_IN2_INT 28_1015 28_1016 !29_1015
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS0_ACTIVE 28_1066 28_1074 29_1056
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS1_ACTIVE 28_1057 28_1067 28_1075
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840
+CMT_TOP_L_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_110 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 28_1015 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_110 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1013 29_1018
+CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL 29_109
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] 29_823
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] 28_823
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] 29_822
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] 28_822
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] 29_821
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] 28_821
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] 29_820
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] 28_820
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] 29_819
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] 28_819
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] 29_815
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] 28_815
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] 29_814
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] 28_814
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] 29_813
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] 28_813
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] 29_812
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] 28_812
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] 29_811
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] 28_811
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] 29_831
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] 28_831
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] 29_830
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] 28_830
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] 29_829
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] 28_829
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] 29_828
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] 28_828
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] 29_827
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] 28_827
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] 29_818
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] 28_818
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] 29_817
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] 28_817
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] 29_816
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] 29_810
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] 28_810
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] 29_809
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] 28_809
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] 29_808
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696
+CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT 29_94
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] 29_389
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] 28_388
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] 29_387
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] 28_386
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] 29_385
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] 28_384
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] 29_395
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] 28_394
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] 29_393
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] 28_392
+CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN 28_111
+CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST 29_111
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808

diff --git a/zynq7/segbits_cmt_top_l_lower_b.origin_info.db b/zynq7/segbits_cmt_top_l_lower_b.origin_info.db
new file mode 100644
index 0000000..02d9b6a
--- /dev/null
+++ b/zynq7/segbits_cmt_top_l_lower_b.origin_info.db

@@ -0,0 +1,396 @@
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !28_1012 28_1013 29_1012 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !28_1012 !28_1013 29_1012 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1012 !29_1012 28_1013 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1012 !28_1013 !29_1012 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_IN3_HCLK origin:034b-cmt-mmcm-pips !28_1013 !29_1012 28_1012 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_L_LOWER_B_CLK_IN3_INT origin:034b-cmt-mmcm-pips !29_1012 28_1012 28_1013 29_979
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_LR_LOWER_B_CLKFBOUT2IN origin:034b-cmt-mmcm-pips 28_980 28_981 29_980
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !29_1013 28_1014 28_1015 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !28_1015 !29_1013 !29_1014 28_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1014 !28_1015 !29_1013 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1014 !28_1015 !29_1013 !29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_IN1_HCLK origin:034b-cmt-mmcm-pips !28_1014 !28_1015 !29_1014 29_1013
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_L_LOWER_B_CLK_IN1_INT origin:034b-cmt-mmcm-pips !28_1014 !28_1015 29_1013 29_1014
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !28_1015 28_1016 29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !28_1015 !28_1016 29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1015 !29_1015 28_1016
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1015 !28_1016 !29_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_IN2_HCLK origin:034b-cmt-mmcm-pips !28_1016 !29_1015 28_1015
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_L_LOWER_B_CLK_IN2_INT origin:034b-cmt-mmcm-pips !29_1015 28_1015 28_1016
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS0_ACTIVE origin:034b-cmt-mmcm-pips 28_1066 28_1074 29_1056
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS1_ACTIVE origin:034b-cmt-mmcm-pips 28_1057 28_1067 28_1075
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068 28_1076 29_1057
+CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
+CMT_TOP_L_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
+CMT_TOP_L_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
+CMT_TOP_L_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_1015 28_110 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1013 29_1018 29_110 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
+CMT_TOP_L_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809
+CMT_TOP_L_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
+CMT_TOP_L_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
+CMT_TOP_L_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393
+CMT_TOP_L_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392
+CMT_TOP_L_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
+CMT_TOP_L_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
+CMT_TOP_L_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
+CMT_TOP_L_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
+CMT_TOP_L_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808

diff --git a/zynq7/segbits_cmt_top_l_upper_t.db b/zynq7/segbits_cmt_top_l_upper_t.db
index 8d3b53d..4859101 100644
--- a/zynq7/segbits_cmt_top_l_upper_t.db
+++ b/zynq7/segbits_cmt_top_l_upper_t.db

@@ -1,362 +1,366 @@
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN !28_11 28_43 !28_44 !29_10 !29_11 29_42 29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN !28_11 !28_43 28_44 !29_10 29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT !28_11 !28_43 28_44 29_10 29_11 !29_42 !29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_09 !28_10 !29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 28_09 !28_10 !29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 !28_09 !28_10 29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 28_09 !28_10 29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 !28_09 28_10 !29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_09 28_10 !29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_08 !29_07 !29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_08 29_07 !29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 28_08 !29_07 !29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 28_08 29_07 !29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 !28_08 !29_07 29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT !28_08 29_07 29_08
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175
-CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44
-CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_41 29_04
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183
-CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_05 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
-CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_722
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_200
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_200
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_201
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_201
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_202
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_202
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_203
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_203
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_204
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_204
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_208
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_208
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_209
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_209
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_210
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_210
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_211
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_211
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_212
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_212
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_192
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_192
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_193
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_193
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_194
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_194
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_195
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_195
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_196
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_196
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_205
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_205
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_206
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_206
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_207
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_213
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_213
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_214
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_214
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_215
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327
-CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_737
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_634
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_635
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_636
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_637
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_638
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_639
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_628
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_629
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_630
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_631
-CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_720
-CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_720
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN !28_43 28_75 !28_76 !29_42 !29_43 29_74 29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN !28_43 !28_75 28_76 !29_42 29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_43 !28_75 28_76 !29_42 !29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_43 !28_75 28_76 29_42 !29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 28_43 !28_75 28_76 !29_42 !29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 28_43 !28_75 28_76 29_42 !29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT !28_43 !28_75 28_76 29_42 29_43 !29_74 !29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_41 !28_42 !29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 28_41 !28_42 !29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 !28_41 !28_42 29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 28_41 !28_42 29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 !28_41 28_42 !29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_41 28_42 !29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_40 !29_39 !29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_40 29_39 !29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 28_40 !29_39 !29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 28_40 29_39 !29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 !28_40 !29_39 29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT !28_40 29_39 29_40
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
+CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
+CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215
+CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
+CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_754
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_232
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_232
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_233
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_233
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_234
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_234
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_235
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_235
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_236
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_236
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_240
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_240
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_241
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_241
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_242
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_242
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_243
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_243
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_244
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_244
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_224
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_224
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_225
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_225
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_226
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_226
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_227
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_227
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_228
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_228
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_237
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_237
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_238
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_238
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_239
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_245
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_245
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_246
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_246
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_247
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359
+CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_769
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_666
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_667
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_668
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_669
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_670
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_671
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_660
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_661
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_662
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_663
+CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_752
+CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_752
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247

diff --git a/zynq7/segbits_cmt_top_l_upper_t.origin_info.db b/zynq7/segbits_cmt_top_l_upper_t.origin_info.db
index 31fb3df..bfa0faf 100644
--- a/zynq7/segbits_cmt_top_l_upper_t.origin_info.db
+++ b/zynq7/segbits_cmt_top_l_upper_t.origin_info.db

@@ -1,362 +1,366 @@
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN origin:034-cmt-pll-pips !28_11 !28_44 !29_10 !29_11 28_43 29_42 29_43
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_42 !29_43 28_44 29_11
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_11 !29_42 !29_43 28_44
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_11 !28_43 !29_11 !29_42 !29_43 28_44 29_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_43 !29_10 !29_11 !29_42 !29_43 28_11 28_44
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_43 !29_11 !29_42 !29_43 28_11 28_44 29_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_11 !28_43 !29_42 !29_43 28_44 29_10 29_11
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_09 !28_10 !29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_10 !29_09 28_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_09 !28_10 29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_10 28_09 29_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_09 !29_09 28_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !29_09 28_09 28_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_08 !29_07 !29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_08 !29_08 29_07
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !29_07 !29_08 28_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !29_08 28_08 29_07
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_08 !29_07 29_08
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_08 29_07 29_08
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
-CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
-CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44
-CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_41 29_04
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183
-CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183
-CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
-CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214
-CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327
-CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327
-CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630
-CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631
-CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720
-CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59
-CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638
-CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207
-CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN origin:034-cmt-pll-pips !28_43 !28_76 !29_42 !29_43 28_75 29_74 29_75
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_43 !28_75 !29_42 !29_74 !29_75 28_76 29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_43 !28_75 !29_42 !29_43 !29_74 !29_75 28_76
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_43 !28_75 !29_43 !29_74 !29_75 28_76 29_42
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_75 !29_42 !29_43 !29_74 !29_75 28_43 28_76
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_75 !29_43 !29_74 !29_75 28_43 28_76 29_42
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_43 !28_75 !29_74 !29_75 28_76 29_42 29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_41 !28_42 !29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_42 !29_41 28_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_41 !28_42 29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_42 28_41 29_41
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_41 !29_41 28_42
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !29_41 28_41 28_42
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_40 !29_39 !29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_40 !29_40 29_39
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !29_39 !29_40 28_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !29_40 28_40 29_39
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_40 !29_39 29_40
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_40 29_39 29_40
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09 29_17
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
+CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
+CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
+CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
+CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
+CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
+CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246
+CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
+CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
+CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662
+CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663
+CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752
+CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
+CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
+CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
+CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247

diff --git a/zynq7/segbits_cmt_top_r_lower_b.db b/zynq7/segbits_cmt_top_r_lower_b.db
new file mode 100644
index 0000000..b57e543
--- /dev/null
+++ b/zynq7/segbits_cmt_top_r_lower_b.db

@@ -0,0 +1,396 @@
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_LR_LOWER_B_CLKFBOUT2IN 28_980 28_981 29_980
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB0 !28_1012 28_1013 29_979 29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB1 !28_1012 !28_1013 29_979 29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB2 !28_1012 28_1013 29_979 !29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB3 !28_1012 !28_1013 29_979 !29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_IN3_HCLK 28_1012 !28_1013 29_979 !29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_IN3_INT 28_1012 28_1013 29_979 !29_1012
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB0 28_1014 28_1015 !29_1013 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB1 28_1014 !28_1015 !29_1013 !29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB2 !28_1014 !28_1015 !29_1013 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB3 !28_1014 !28_1015 !29_1013 !29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_IN1_HCLK !28_1014 !28_1015 29_1013 !29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_IN1_INT !28_1014 !28_1015 29_1013 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB0 !28_1015 28_1016 29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB1 !28_1015 !28_1016 29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB2 !28_1015 28_1016 !29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB3 !28_1015 !28_1016 !29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_IN2_HCLK 28_1015 !28_1016 !29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_IN2_INT 28_1015 28_1016 !29_1015
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS0_ACTIVE 28_1066 28_1074 29_1056
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS1_ACTIVE 28_1057 28_1067 28_1075
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE 28_1068 28_1076 29_1057
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE 28_1058 28_1069 28_1077
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 29_860
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 28_860
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 29_859
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 28_859
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 29_858
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 28_858
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 29_863
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 28_863
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 29_862
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 28_862
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 29_861
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 28_861
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 29_857
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 28_857
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 29_856
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 28_856
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 29_855
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 28_855
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 29_854
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 28_854
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 29_853
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 28_853
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] 28_852
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] 29_849
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] 28_849
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] 29_848
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 28_850
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 29_850
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] 29_851
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] 28_851
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 29_852
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] 28_848
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] 28_841
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] 29_844
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] 28_844
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] 29_843
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] 28_843
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] 29_842
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] 28_842
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] 29_847
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] 28_847
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] 29_846
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] 28_846
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] 29_845
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] 28_845
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] 29_841
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] 29_840
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] 28_840
+CMT_TOP_R_LOWER_B.MMCME2.IN_USE 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_44 28_46 28_47 28_48 28_49 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_78 28_110 28_428 28_429 28_430 28_433 28_434 28_466 28_488 28_492 28_772 28_773 28_774 28_787 28_976 28_978 28_989 28_991 28_1007 28_1015 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_44 29_45 29_46 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_78 29_95 29_110 29_427 29_428 29_431 29_432 29_433 29_463 29_771 29_772 29_775 29_789 29_833 29_836 29_839 29_977 29_981 29_987 29_990 29_991 29_1007 29_1013 29_1018
+CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL 29_109
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] 29_823
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] 28_823
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] 29_822
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] 28_822
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] 29_821
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] 28_821
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] 29_820
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] 28_820
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] 29_819
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] 28_819
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] 29_815
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] 28_815
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] 29_814
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] 28_814
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] 29_813
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] 28_813
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] 29_812
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] 28_812
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] 29_811
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] 28_811
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] 29_831
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] 28_831
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] 29_830
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] 28_830
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] 29_829
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] 28_829
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] 29_828
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] 28_828
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] 29_827
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] 28_827
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] 29_818
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] 28_818
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] 29_817
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] 28_817
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] 29_816
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] 29_810
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] 28_810
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] 29_809
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] 28_809
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] 29_808
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] 29_703
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] 28_703
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] 29_702
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] 28_702
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] 29_701
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] 28_701
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] 29_700
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] 28_700
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] 29_699
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] 28_699
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] 29_698
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] 28_698
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] 29_697
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] 28_697
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] 29_696
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] 28_696
+CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT 29_94
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] 29_389
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] 28_388
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] 29_387
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] 28_386
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] 29_385
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] 28_384
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] 29_395
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] 28_394
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] 29_393
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] 28_392
+CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN 28_111
+CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST 29_111
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 29_956
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 28_956
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 29_955
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 28_955
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 29_954
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 28_954
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] 29_959
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] 28_959
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] 29_958
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] 28_958
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] 29_957
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] 28_957
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 29_953
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 28_953
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 29_952
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 28_952
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 29_951
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 28_951
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 29_950
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 28_950
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 29_949
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 28_949
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] 28_948
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] 29_945
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] 28_945
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] 29_944
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] 28_946
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 29_946
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] 29_947
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] 28_947
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] 29_948
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] 28_944
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 29_940
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 28_940
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 29_939
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 28_939
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 29_938
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 28_938
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] 29_943
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] 28_943
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] 29_942
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] 28_942
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] 29_941
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] 28_941
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 29_937
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 28_937
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 29_936
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 28_936
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 29_935
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 28_935
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 29_934
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 28_934
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 29_933
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 28_933
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] 28_932
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] 29_929
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] 28_929
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] 29_928
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] 28_930
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 29_930
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] 29_931
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] 28_931
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] 29_932
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] 28_928
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 29_924
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 28_924
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 29_923
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 28_923
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 29_922
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 28_922
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] 29_927
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] 28_927
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] 29_926
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] 28_926
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] 29_925
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] 28_925
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 29_921
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 28_921
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 29_920
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 28_920
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 29_919
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 28_919
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 29_918
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 28_918
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 29_917
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 28_917
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] 28_916
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] 29_913
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] 28_913
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] 29_912
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] 28_914
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 29_914
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] 29_915
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] 28_915
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] 29_916
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] 28_912
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 29_908
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 28_908
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 29_907
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 28_907
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 29_906
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 28_906
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] 29_911
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] 28_911
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] 29_910
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] 28_910
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] 29_909
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] 28_909
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 29_905
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 28_905
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 29_904
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 28_904
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 29_903
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 28_903
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 29_902
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 28_902
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 29_901
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 28_901
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] 28_900
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] 29_897
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] 28_897
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] 29_896
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] 28_898
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 29_898
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] 29_899
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] 28_899
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] 29_900
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] 28_896
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 29_892
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 28_892
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 29_891
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 28_891
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 29_890
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 28_890
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] 29_895
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] 28_895
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] 29_894
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] 28_894
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] 29_893
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] 28_893
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 29_889
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 28_889
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 29_888
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 28_888
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 29_887
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 28_887
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 29_886
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 28_886
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 29_885
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 28_885
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] 28_884
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] 29_881
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] 28_881
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] 29_880
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] 28_882
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 29_882
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] 29_883
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] 28_883
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] 29_884
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] 28_880
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 29_972
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 28_972
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 29_971
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 28_971
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 29_970
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 28_970
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] 29_975
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] 28_975
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] 29_974
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] 28_974
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] 29_973
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] 28_973
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 29_969
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 28_969
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 29_968
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 28_968
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_967
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_967
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_966
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_966
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_965
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_965
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] 28_964
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_962
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] 29_963
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] 28_963
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_964
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_962
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_961
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_961
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] 29_960
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] 28_960
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] 29_876
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] 28_876
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] 29_875
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] 28_875
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] 29_874
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] 28_874
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] 29_879
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] 28_879
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] 29_878
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] 28_878
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] 29_877
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] 28_877
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] 29_873
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] 28_873
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] 29_872
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] 28_872
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] 29_871
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] 28_871
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] 29_870
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] 28_870
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] 29_869
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] 28_869
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] 28_868
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] 29_866
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] 29_867
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] 28_867
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] 29_868
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] 28_866
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] 29_865
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] 28_865
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] 29_864
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] 28_864
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] 29_399
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] 28_399
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] 29_398
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] 28_398
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] 29_397
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] 28_397
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] 29_396
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] 28_396
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] 28_395
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] 29_394
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] 28_393
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] 29_392
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] 29_391
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] 28_391
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] 29_390
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] 28_390
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] 28_389
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] 29_388
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] 28_387
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] 29_386
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] 28_385
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] 29_384
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] 29_826
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] 28_826
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] 29_825
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] 28_825
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] 29_824
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] 28_824
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] 28_816
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] 28_808

diff --git a/zynq7/segbits_cmt_top_r_lower_b.origin_info.db b/zynq7/segbits_cmt_top_r_lower_b.origin_info.db
new file mode 100644
index 0000000..6483e35
--- /dev/null
+++ b/zynq7/segbits_cmt_top_r_lower_b.origin_info.db

@@ -0,0 +1,396 @@
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_LR_LOWER_B_CLKFBOUT2IN origin:034b-cmt-mmcm-pips 28_980 28_981 29_980
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !28_1012 28_1013 29_1012 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !28_1012 !28_1013 29_1012 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1012 !29_1012 28_1013 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1012 !28_1013 !29_1012 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_IN3_HCLK origin:034b-cmt-mmcm-pips !28_1013 !29_1012 28_1012 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBIN.CMT_R_LOWER_B_CLK_IN3_INT origin:034b-cmt-mmcm-pips !29_1012 28_1012 28_1013 29_979
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !29_1013 28_1014 28_1015 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !28_1015 !29_1013 !29_1014 28_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1014 !28_1015 !29_1013 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1014 !28_1015 !29_1013 !29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_IN1_HCLK origin:034b-cmt-mmcm-pips !28_1014 !28_1015 !29_1014 29_1013
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN1.CMT_R_LOWER_B_CLK_IN1_INT origin:034b-cmt-mmcm-pips !28_1014 !28_1015 29_1013 29_1014
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB0 origin:034b-cmt-mmcm-pips !28_1015 28_1016 29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB1 origin:034b-cmt-mmcm-pips !28_1015 !28_1016 29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB2 origin:034b-cmt-mmcm-pips !28_1015 !29_1015 28_1016
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_FREQ_BB3 origin:034b-cmt-mmcm-pips !28_1015 !28_1016 !29_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_IN2_HCLK origin:034b-cmt-mmcm-pips !28_1016 !29_1015 28_1015
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKIN2.CMT_R_LOWER_B_CLK_IN2_INT origin:034b-cmt-mmcm-pips !29_1015 28_1015 28_1016
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS0_ACTIVE origin:034b-cmt-mmcm-pips 28_1066 28_1074 29_1056
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS1_ACTIVE origin:034b-cmt-mmcm-pips 28_1057 28_1067 28_1075
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2_ACTIVE origin:034b-cmt-mmcm-pips 28_1068 28_1076 29_1057
+CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3_ACTIVE origin:034b-cmt-mmcm-pips 28_1058 28_1069 28_1077
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_860
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_860
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_859
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_859
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_858
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_858
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_863
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_863
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_862
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_862
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_861
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_861
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_857
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_857
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_856
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_856
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_855
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_855
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_854
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_854
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_853
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_853
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_852
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_849
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_849
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_848
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_850
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_850
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_851
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_851
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_852
+CMT_TOP_R_LOWER_B.MMCME2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_848
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_EDGE[0] origin:031-cmt-mmcm 28_841
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:031-cmt-mmcm 29_844
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:031-cmt-mmcm 28_844
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:031-cmt-mmcm 29_843
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:031-cmt-mmcm 28_843
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:031-cmt-mmcm 29_842
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:031-cmt-mmcm 28_842
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[0] origin:031-cmt-mmcm 29_847
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[1] origin:031-cmt-mmcm 28_847
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[2] origin:031-cmt-mmcm 29_846
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[3] origin:031-cmt-mmcm 28_846
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[4] origin:031-cmt-mmcm 29_845
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_LOW_TIME[5] origin:031-cmt-mmcm 28_845
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_NO_COUNT[0] origin:031-cmt-mmcm 29_841
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[0] origin:031-cmt-mmcm 29_840
+CMT_TOP_R_LOWER_B.MMCME2.DIVCLK_DIVCLK_RESERVED[1] origin:031-cmt-mmcm 28_840
+CMT_TOP_R_LOWER_B.MMCME2.IN_USE origin:031-cmt-mmcm 28_1007 28_1015 28_110 28_18 28_21 28_22 28_23 28_24 28_25 28_27 28_28 28_31 28_32 28_33 28_34 28_36 28_37 28_38 28_39 28_40 28_428 28_429 28_430 28_433 28_434 28_44 28_46 28_466 28_47 28_48 28_488 28_49 28_492 28_50 28_51 28_52 28_54 28_63 28_65 28_66 28_70 28_72 28_73 28_75 28_77 28_772 28_773 28_774 28_78 28_787 28_976 28_978 28_989 28_991 29_1007 29_1013 29_1018 29_110 29_16 29_18 29_22 29_25 29_28 29_31 29_34 29_35 29_36 29_37 29_39 29_40 29_41 29_42 29_427 29_428 29_431 29_432 29_433 29_44 29_45 29_46 29_463 29_47 29_48 29_51 29_52 29_56 29_57 29_60 29_64 29_65 29_66 29_67 29_68 29_70 29_71 29_72 29_73 29_75 29_76 29_77 29_771 29_772 29_775 29_78 29_789 29_833 29_836 29_839 29_95 29_977 29_981 29_987 29_990 29_991
+CMT_TOP_R_LOWER_B.MMCME2.INV_CLKINSEL origin:031-cmt-mmcm 29_109
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[0] origin:031-cmt-mmcm 29_823
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[1] origin:031-cmt-mmcm 28_823
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[2] origin:031-cmt-mmcm 29_822
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[3] origin:031-cmt-mmcm 28_822
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[4] origin:031-cmt-mmcm 29_821
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[5] origin:031-cmt-mmcm 28_821
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[6] origin:031-cmt-mmcm 29_820
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[7] origin:031-cmt-mmcm 28_820
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[8] origin:031-cmt-mmcm 29_819
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[9] origin:031-cmt-mmcm 28_819
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[10] origin:031-cmt-mmcm 29_815
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[11] origin:031-cmt-mmcm 28_815
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[12] origin:031-cmt-mmcm 29_814
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[13] origin:031-cmt-mmcm 28_814
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[14] origin:031-cmt-mmcm 29_813
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[15] origin:031-cmt-mmcm 28_813
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[16] origin:031-cmt-mmcm 29_812
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[17] origin:031-cmt-mmcm 28_812
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[18] origin:031-cmt-mmcm 29_811
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[19] origin:031-cmt-mmcm 28_811
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[20] origin:031-cmt-mmcm 29_831
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[21] origin:031-cmt-mmcm 28_831
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[22] origin:031-cmt-mmcm 29_830
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[23] origin:031-cmt-mmcm 28_830
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[24] origin:031-cmt-mmcm 29_829
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[25] origin:031-cmt-mmcm 28_829
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[26] origin:031-cmt-mmcm 29_828
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[27] origin:031-cmt-mmcm 28_828
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[28] origin:031-cmt-mmcm 29_827
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[29] origin:031-cmt-mmcm 28_827
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[30] origin:031-cmt-mmcm 29_818
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[31] origin:031-cmt-mmcm 28_818
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[32] origin:031-cmt-mmcm 29_817
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[33] origin:031-cmt-mmcm 28_817
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[34] origin:031-cmt-mmcm 29_816
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[35] origin:031-cmt-mmcm 29_810
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[36] origin:031-cmt-mmcm 28_810
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[37] origin:031-cmt-mmcm 29_809
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[38] origin:031-cmt-mmcm 28_809
+CMT_TOP_R_LOWER_B.MMCME2.LKTABLE[39] origin:031-cmt-mmcm 29_808
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[0] origin:031-cmt-mmcm 29_703
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[1] origin:031-cmt-mmcm 28_703
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[2] origin:031-cmt-mmcm 29_702
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[3] origin:031-cmt-mmcm 28_702
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[4] origin:031-cmt-mmcm 29_701
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[5] origin:031-cmt-mmcm 28_701
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[6] origin:031-cmt-mmcm 29_700
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[7] origin:031-cmt-mmcm 28_700
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[8] origin:031-cmt-mmcm 29_699
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[9] origin:031-cmt-mmcm 28_699
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[10] origin:031-cmt-mmcm 29_698
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[11] origin:031-cmt-mmcm 28_698
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[12] origin:031-cmt-mmcm 29_697
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[13] origin:031-cmt-mmcm 28_697
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[14] origin:031-cmt-mmcm 29_696
+CMT_TOP_R_LOWER_B.MMCME2.POWER_REG_POWER_REG_POWER_REG[15] origin:031-cmt-mmcm 28_696
+CMT_TOP_R_LOWER_B.MMCME2.STARTUP_WAIT origin:031-cmt-mmcm 29_94
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[0] origin:031-cmt-mmcm 29_389
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[1] origin:031-cmt-mmcm 28_388
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[2] origin:031-cmt-mmcm 29_387
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[3] origin:031-cmt-mmcm 28_386
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[4] origin:031-cmt-mmcm 29_385
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[5] origin:031-cmt-mmcm 28_384
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[6] origin:031-cmt-mmcm 29_395
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[7] origin:031-cmt-mmcm 28_394
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[8] origin:031-cmt-mmcm 29_393
+CMT_TOP_R_LOWER_B.MMCME2.TABLE[9] origin:031-cmt-mmcm 28_392
+CMT_TOP_R_LOWER_B.MMCME2.ZINV_PWRDWN origin:031-cmt-mmcm 28_111
+CMT_TOP_R_LOWER_B.MMCME2.ZINV_RST origin:031-cmt-mmcm 29_111
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_956
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_956
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_955
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_955
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_954
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_954
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_959
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_959
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_958
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_958
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_957
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_957
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_953
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_953
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_952
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_952
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_951
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_951
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_950
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_950
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_949
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_949
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_948
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_945
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_945
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_944
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_946
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_946
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_947
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_947
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_948
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT0_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_944
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_940
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_940
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_939
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_939
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_938
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_938
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_943
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_943
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_942
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_942
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_941
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_941
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_937
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_937
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_936
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_936
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_935
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_935
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_934
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_934
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_933
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_933
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_932
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_929
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_929
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_928
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_930
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_930
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_931
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_931
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_932
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT1_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_928
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_924
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_924
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_923
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_923
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_922
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_922
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_927
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_927
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_926
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_926
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_925
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_925
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_921
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_921
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_920
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_920
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_919
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_919
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_918
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_918
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_917
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_917
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_916
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_913
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_913
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_912
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_914
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_914
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_915
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_915
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_916
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT2_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_912
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_908
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_908
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_907
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_907
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_906
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_906
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_911
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_911
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_910
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_910
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_909
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_909
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_905
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_905
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_904
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_904
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_903
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_903
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_902
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_902
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_901
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_901
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_900
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_897
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_897
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_896
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_898
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_898
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_899
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_899
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_900
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT3_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_896
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_892
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_892
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_891
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_891
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_890
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_890
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_895
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_895
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_894
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_894
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_893
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_893
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_889
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_889
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_888
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_888
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:031-cmt-mmcm 29_887
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:031-cmt-mmcm 28_887
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:031-cmt-mmcm 29_886
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:031-cmt-mmcm 28_886
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:031-cmt-mmcm 29_885
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:031-cmt-mmcm 28_885
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_EDGE[0] origin:031-cmt-mmcm 28_884
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[0] origin:031-cmt-mmcm 29_881
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[1] origin:031-cmt-mmcm 28_881
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC[2] origin:031-cmt-mmcm 29_880
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:031-cmt-mmcm 28_882
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:031-cmt-mmcm 29_882
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[0] origin:031-cmt-mmcm 29_883
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_MX[1] origin:031-cmt-mmcm 28_883
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:031-cmt-mmcm 29_884
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT4_CLKOUT2_RESERVED[0] origin:031-cmt-mmcm 28_880
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_972
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_972
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_971
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_971
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_970
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_970
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_975
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_975
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_974
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_974
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_973
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_973
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_969
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_969
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_968
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_968
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_967
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_967
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_966
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_966
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_965
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_965
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_964
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_962
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_963
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_963
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_964
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_962
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_961
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_961
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_960
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT5_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_960
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[0] origin:031-cmt-mmcm 29_876
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[1] origin:031-cmt-mmcm 28_876
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[2] origin:031-cmt-mmcm 29_875
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[3] origin:031-cmt-mmcm 28_875
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[4] origin:031-cmt-mmcm 29_874
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_HIGH_TIME[5] origin:031-cmt-mmcm 28_874
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[0] origin:031-cmt-mmcm 29_879
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[1] origin:031-cmt-mmcm 28_879
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[2] origin:031-cmt-mmcm 29_878
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[3] origin:031-cmt-mmcm 28_878
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[4] origin:031-cmt-mmcm 29_877
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_LOW_TIME[5] origin:031-cmt-mmcm 28_877
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_OUTPUT_ENABLE[0] origin:031-cmt-mmcm 29_873
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[0] origin:031-cmt-mmcm 28_873
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[1] origin:031-cmt-mmcm 29_872
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT1_PHASE_MUX[2] origin:031-cmt-mmcm 28_872
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[0] origin:031-cmt-mmcm 29_871
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[1] origin:031-cmt-mmcm 28_871
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[2] origin:031-cmt-mmcm 29_870
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[3] origin:031-cmt-mmcm 28_870
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[4] origin:031-cmt-mmcm 29_869
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME[5] origin:031-cmt-mmcm 28_869
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE[0] origin:031-cmt-mmcm 28_868
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F[0] origin:031-cmt-mmcm 29_866
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[0] origin:031-cmt-mmcm 29_867
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_MX[1] origin:031-cmt-mmcm 28_867
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT[0] origin:031-cmt-mmcm 29_868
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[0] origin:031-cmt-mmcm 28_866
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[1] origin:031-cmt-mmcm 29_865
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F[2] origin:031-cmt-mmcm 28_865
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[0] origin:031-cmt-mmcm 29_864
+CMT_TOP_R_LOWER_B.MMCME2.CLKOUT6_CLKOUT2_FRACTIONAL_RESERVED[1] origin:031-cmt-mmcm 28_864
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[0] origin:031-cmt-mmcm 29_399
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[1] origin:031-cmt-mmcm 28_399
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[2] origin:031-cmt-mmcm 29_398
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[3] origin:031-cmt-mmcm 28_398
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[4] origin:031-cmt-mmcm 29_397
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[5] origin:031-cmt-mmcm 28_397
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[6] origin:031-cmt-mmcm 29_396
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[7] origin:031-cmt-mmcm 28_396
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[8] origin:031-cmt-mmcm 28_395
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[9] origin:031-cmt-mmcm 29_394
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[10] origin:031-cmt-mmcm 28_393
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG1_RESERVED[11] origin:031-cmt-mmcm 29_392
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[0] origin:031-cmt-mmcm 29_391
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[1] origin:031-cmt-mmcm 28_391
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[2] origin:031-cmt-mmcm 29_390
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[3] origin:031-cmt-mmcm 28_390
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[4] origin:031-cmt-mmcm 28_389
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[5] origin:031-cmt-mmcm 29_388
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[6] origin:031-cmt-mmcm 28_387
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[7] origin:031-cmt-mmcm 29_386
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[8] origin:031-cmt-mmcm 28_385
+CMT_TOP_R_LOWER_B.MMCME2.FILTREG2_RESERVED[9] origin:031-cmt-mmcm 29_384
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[0] origin:031-cmt-mmcm 29_826
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[1] origin:031-cmt-mmcm 28_826
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[2] origin:031-cmt-mmcm 29_825
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[3] origin:031-cmt-mmcm 28_825
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[4] origin:031-cmt-mmcm 29_824
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG1_RESERVED[5] origin:031-cmt-mmcm 28_824
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG2_RESERVED[0] origin:031-cmt-mmcm 28_816
+CMT_TOP_R_LOWER_B.MMCME2.LOCKREG3_RESERVED[0] origin:031-cmt-mmcm 28_808

diff --git a/zynq7/segbits_cmt_top_r_upper_t.db b/zynq7/segbits_cmt_top_r_upper_t.db
index 315be13..0e40593 100644
--- a/zynq7/segbits_cmt_top_r_upper_t.db
+++ b/zynq7/segbits_cmt_top_r_upper_t.db

@@ -1,362 +1,366 @@
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN !28_11 28_43 !28_44 !29_10 !29_11 29_42 29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN !28_11 !28_43 28_44 !29_10 29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 !28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT !28_11 !28_43 28_44 29_10 29_11 !29_42 !29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_09 !28_10 !29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 28_09 !28_10 !29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 !28_09 !28_10 29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 28_09 !28_10 29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 !28_09 28_10 !29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT 28_09 28_10 !29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_08 !29_07 !29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 !28_08 29_07 !29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 28_08 !29_07 !29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 28_08 29_07 !29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 !28_08 !29_07 29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT !28_08 29_07 29_08
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175
-CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44
-CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_41 29_04
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183
-CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_05 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
-CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_722
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_200
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_200
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_201
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_201
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_202
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_202
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_203
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_203
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_204
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_204
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_208
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_208
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_209
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_209
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_210
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_210
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_211
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_211
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_212
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_212
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_192
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_192
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_193
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_193
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_194
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_194
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_195
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_195
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_196
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_196
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_205
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_205
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_206
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_206
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_207
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_213
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_213
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_214
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_214
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_215
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327
-CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_737
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_634
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_635
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_636
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_637
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_638
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_639
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_628
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_629
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_630
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_631
-CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_720
-CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_720
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN !28_01 !28_02 !28_43 28_75 !28_76 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_42 !29_43 29_74 29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN !28_01 !28_02 !28_43 !28_75 28_76 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_42 29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_01 !28_02 !28_43 !28_75 28_76 29_00 !29_01 29_09 !29_10 !29_11 !29_12 29_17 !29_18 !29_19 !29_20 !29_42 !29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 28_01 !28_02 !28_43 !28_75 28_76 !29_00 !29_01 !29_09 29_10 !29_11 !29_12 !29_17 29_18 !29_19 !29_20 29_42 !29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 !28_01 !28_02 28_43 !28_75 28_76 !29_00 29_01 !29_09 !29_10 29_11 !29_12 !29_17 !29_18 29_19 !29_20 !29_42 !29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 !28_01 28_02 28_43 !28_75 28_76 !29_00 !29_01 !29_09 !29_10 !29_11 29_12 !29_17 !29_18 !29_19 29_20 29_42 !29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT !28_01 !28_02 !28_43 !28_75 28_76 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 29_42 29_43 !29_74 !29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_01 !28_02 !28_41 !28_42 29_00 !29_01 29_09 !29_10 !29_11 !29_12 29_17 !29_18 !29_19 !29_20 !29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 28_01 !28_02 28_41 !28_42 !29_00 !29_01 !29_09 29_10 !29_11 !29_12 !29_17 29_18 !29_19 !29_20 !29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 !28_01 !28_02 !28_41 !28_42 !29_00 29_01 !29_09 !29_10 29_11 !29_12 !29_17 !29_18 29_19 !29_20 29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 !28_01 28_02 28_41 !28_42 !29_00 !29_01 !29_09 !29_10 !29_11 29_12 !29_17 !29_18 !29_19 29_20 29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 !28_01 !28_02 !28_41 28_42 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT !28_01 !28_02 28_41 28_42 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_01 !28_02 !28_40 29_00 !29_01 29_09 !29_10 !29_11 !29_12 29_17 !29_18 !29_19 !29_20 !29_39 !29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 28_01 !28_02 !28_40 !29_00 !29_01 !29_09 29_10 !29_11 !29_12 !29_17 29_18 !29_19 !29_20 29_39 !29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 !28_01 !28_02 28_40 !29_00 29_01 !29_09 !29_10 29_11 !29_12 !29_17 !29_18 29_19 !29_20 !29_39 !29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 !28_01 28_02 28_40 !29_00 !29_01 !29_09 !29_10 !29_11 29_12 !29_17 !29_18 !29_19 29_20 29_39 !29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 !28_01 !28_02 !28_40 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_39 29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT !28_01 !28_02 !28_40 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 29_39 29_40
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE 29_00 29_09 29_17
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE 28_01 29_10 29_18
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE 29_01 29_11 29_19
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE 28_02 29_12 29_20
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_195
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_195
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_196
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_196
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_197
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_197
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_192
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_192
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_193
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_193
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_194
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_194
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_198
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_198
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_199
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_199
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_200
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_200
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_201
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_201
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_202
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_202
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_203
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_206
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_206
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_207
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_205
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_205
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_204
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_204
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_203
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_207
+CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_35 29_76
+CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_73 29_36
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_214
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_211
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_211
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_212
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_212
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_213
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_213
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_208
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_208
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_209
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_209
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_210
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_210
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_214
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_215
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_215
+CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_37 28_48 28_74 28_78 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_592 28_622 28_623 28_624 28_627 28_628 28_768 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_48 29_77 29_78 29_79 29_268 29_281 29_282 29_283 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_785 29_786 29_788 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
+CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_754
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_232
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_232
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_233
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_233
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_234
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_234
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_235
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_235
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_236
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_236
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_240
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_240
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_241
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_241
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_242
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_242
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_243
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_243
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_244
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_244
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_224
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_224
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_225
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_225
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_226
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_226
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_227
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_227
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_228
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_228
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_237
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_237
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_238
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_238
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_239
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_245
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_245
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_246
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_246
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_247
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_352
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_352
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_353
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_353
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_354
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_354
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_355
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_355
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_356
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_356
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_357
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_357
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_358
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_358
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_359
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_359
+CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_769
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_666
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_667
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_668
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_669
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_670
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_671
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_660
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_661
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_662
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_663
+CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_752
+CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_752
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_99
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_99
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_100
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_100
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_101
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_101
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_96
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_96
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_97
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_97
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_98
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_98
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_102
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_102
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_103
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_103
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_104
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_104
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_105
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_105
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_106
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_106
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_107
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_110
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_110
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_111
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_109
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_109
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_108
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_108
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_107
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_111
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_115
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_115
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_116
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_116
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_117
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_117
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_112
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_112
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_113
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_113
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_114
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_114
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_118
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_118
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_119
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_119
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_120
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_120
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_121
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_121
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_122
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_122
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_123
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_126
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_126
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_127
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_125
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_125
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_124
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_124
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_123
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_127
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_131
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_131
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_132
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_132
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_133
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_133
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_128
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_128
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_129
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_129
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_130
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_130
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_134
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_134
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_135
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_135
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_136
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_136
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_137
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_137
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_138
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_138
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_139
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_142
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_142
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_143
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_141
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_141
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_140
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_140
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_139
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_143
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_147
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_147
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_148
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_148
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_149
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_149
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_144
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_144
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_145
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_145
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_146
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_146
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_150
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_150
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_151
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_151
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_152
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_152
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_153
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_153
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_154
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_154
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_155
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_158
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_158
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_159
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_157
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_157
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_156
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_156
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_155
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_159
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_163
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_163
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_164
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_164
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_165
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_165
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_160
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_160
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_161
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_161
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_162
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_162
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_166
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_166
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_167
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_167
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_168
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_168
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_169
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_169
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_170
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_170
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_171
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_174
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_174
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_175
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_173
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_173
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_172
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_172
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_171
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_175
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_83
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_83
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_84
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_84
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_85
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_85
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_80
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_80
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_81
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_81
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_82
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_82
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_86
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_86
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_87
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_87
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_88
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_88
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_89
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_89
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_90
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_90
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_91
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_94
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_94
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_95
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_93
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_93
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_92
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_92
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_91
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_95
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_656
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_656
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_657
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_657
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_658
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_658
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_659
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_659
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_660
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_661
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_662
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_663
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_664
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_664
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_665
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_665
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_666
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_667
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_668
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_669
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_670
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_671
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_229
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_229
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_230
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_230
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_231
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_231
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_239
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_247

diff --git a/zynq7/segbits_cmt_top_r_upper_t.origin_info.db b/zynq7/segbits_cmt_top_r_upper_t.origin_info.db
index f571184..6ee0558 100644
--- a/zynq7/segbits_cmt_top_r_upper_t.origin_info.db
+++ b/zynq7/segbits_cmt_top_r_upper_t.origin_info.db

@@ -1,362 +1,366 @@
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN origin:034-cmt-pll-pips !28_11 !28_44 !29_10 !29_11 28_43 29_42 29_43
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_42 !29_43 28_44 29_11
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_11 !29_42 !29_43 28_44
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_11 !28_43 !29_11 !29_42 !29_43 28_44 29_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_43 !29_10 !29_11 !29_42 !29_43 28_11 28_44
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_43 !29_11 !29_42 !29_43 28_11 28_44 29_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_11 !28_43 !29_42 !29_43 28_44 29_10 29_11
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_09 !28_10 !29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_10 !29_09 28_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_09 !28_10 29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_10 28_09 29_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_09 !29_09 28_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !29_09 28_09 28_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_08 !29_07 !29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_08 !29_08 29_07
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !29_07 !29_08 28_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !29_08 28_08 29_07
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_08 !29_07 29_08
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_08 29_07 29_08
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
-CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
-CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44
-CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_41 29_04
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183
-CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183
-CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813
-CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214
-CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327
-CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327
-CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630
-CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631
-CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720
-CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59
-CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638
-CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207
-CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN origin:034-cmt-pll-pips !28_01 !28_02 !28_43 !28_76 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_42 !29_43 28_75 29_74 29_75
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_01 !28_02 !28_43 !28_75 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_42 !29_74 !29_75 28_76 29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_01 !28_02 !28_43 !28_75 !29_01 !29_10 !29_11 !29_12 !29_18 !29_19 !29_20 !29_42 !29_43 !29_74 !29_75 28_76 29_00 29_09 29_17
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_02 !28_43 !28_75 !29_00 !29_01 !29_09 !29_11 !29_12 !29_17 !29_19 !29_20 !29_43 !29_74 !29_75 28_01 28_76 29_10 29_18 29_42
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_01 !28_02 !28_75 !29_00 !29_09 !29_10 !29_12 !29_17 !29_18 !29_20 !29_42 !29_43 !29_74 !29_75 28_43 28_76 29_01 29_11 29_19
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_01 !28_75 !29_00 !29_01 !29_09 !29_10 !29_11 !29_17 !29_18 !29_19 !29_43 !29_74 !29_75 28_02 28_43 28_76 29_12 29_20 29_42
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_01 !28_02 !28_43 !28_75 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_74 !29_75 28_76 29_42 29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_01 !28_02 !28_41 !28_42 !29_01 !29_10 !29_11 !29_12 !29_18 !29_19 !29_20 !29_41 29_00 29_09 29_17
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_02 !28_42 !29_00 !29_01 !29_09 !29_11 !29_12 !29_17 !29_19 !29_20 !29_41 28_01 28_41 29_10 29_18
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_01 !28_02 !28_41 !28_42 !29_00 !29_09 !29_10 !29_12 !29_17 !29_18 !29_20 29_01 29_11 29_19 29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_01 !28_42 !29_00 !29_01 !29_09 !29_10 !29_11 !29_17 !29_18 !29_19 28_02 28_41 29_12 29_20 29_41
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_01 !28_02 !28_41 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_41 28_42
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !28_01 !28_02 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_41 28_41 28_42
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_01 !28_02 !28_40 !29_01 !29_10 !29_11 !29_12 !29_18 !29_19 !29_20 !29_39 !29_40 29_00 29_09 29_17
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_02 !28_40 !29_00 !29_01 !29_09 !29_11 !29_12 !29_17 !29_19 !29_20 !29_40 28_01 29_10 29_18 29_39
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_01 !28_02 !29_00 !29_09 !29_10 !29_12 !29_17 !29_18 !29_20 !29_39 !29_40 28_40 29_01 29_11 29_19
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_01 !29_00 !29_01 !29_09 !29_10 !29_11 !29_17 !29_18 !29_19 !29_40 28_02 28_40 29_12 29_20 29_39
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_01 !28_02 !28_40 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 !29_39 29_40
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_01 !28_02 !28_40 !29_00 !29_01 !29_09 !29_10 !29_11 !29_12 !29_17 !29_18 !29_19 !29_20 29_39 29_40
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS_ACTIVE origin:034-cmt-pll-pips 29_00 29_09 29_17
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS_ACTIVE origin:034-cmt-pll-pips 28_01 29_10 29_18
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS_ACTIVE origin:034-cmt-pll-pips 29_01 29_11 29_19
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS_ACTIVE origin:034-cmt-pll-pips 28_02 29_12 29_20
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_195
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_195
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_196
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_196
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_197
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_197
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_192
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_192
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_193
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_193
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_194
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_194
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_198
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_198
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_199
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_199
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_200
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_200
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_201
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_201
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_202
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_202
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_203
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_206
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_206
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_207
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_205
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_205
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_204
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_204
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_203
+CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_207
+CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_35 29_76
+CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_73 29_36
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_214
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_211
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_211
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_212
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_212
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_213
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_213
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_208
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_208
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_209
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_209
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_210
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_210
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_214
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_215
+CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_215
+CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_216 28_219 28_222 28_266 28_280 28_283 28_284 28_37 28_48 28_592 28_622 28_623 28_624 28_627 28_628 28_74 28_768 28_78 28_785 28_786 28_787 28_788 28_790 28_791 28_792 28_793 28_795 28_796 28_797 28_798 28_799 28_803 28_806 28_807 28_811 28_812 28_815 28_816 28_817 28_818 28_819 28_821 28_822 28_823 28_824 28_826 28_827 28_828 28_829 28_832 28_835 28_838 28_841 28_845 28_847 29_268 29_281 29_282 29_283 29_48 29_563 29_567 29_589 29_621 29_622 29_625 29_626 29_627 29_77 29_78 29_785 29_786 29_788 29_79 29_790 29_791 29_793 29_797 29_798 29_800 29_809 29_811 29_812 29_813 29_814 29_815 29_816 29_817 29_819 29_823 29_824 29_825 29_826 29_827 29_829 29_830 29_831 29_832 29_835 29_836 29_838 29_839 29_840 29_841 29_842 29_845
+CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_754
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_232
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_232
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_233
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_233
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_234
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_234
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_235
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_235
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_236
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_236
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_240
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_240
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_241
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_241
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_242
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_242
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_243
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_243
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_244
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_244
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_224
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_224
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_225
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_225
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_226
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_226
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_227
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_227
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_228
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_228
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_237
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_237
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_238
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_238
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_239
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_245
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_245
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_246
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_246
+CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_247
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_352
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_352
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_353
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_353
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_354
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_354
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_355
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_355
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_356
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_356
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_357
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_357
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_358
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_358
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_359
+CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_359
+CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_769
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_666
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_667
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_668
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_669
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_670
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_671
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_660
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_661
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_662
+CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_663
+CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_752
+CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_752
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_108
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_108
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_124
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_124
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_140
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_140
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_147
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_147
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_148
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_148
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_149
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_149
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_144
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_144
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_145
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_145
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_146
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_146
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_150
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_150
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_151
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_151
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_152
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_152
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_153
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_153
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_154
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_154
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_155
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_158
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_158
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_159
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_157
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_157
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_156
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_156
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_155
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_159
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_172
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_172
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_92
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_92
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91
+CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_656
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_656
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_657
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_657
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_658
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_658
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_659
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_659
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_660
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_661
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_662
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_663
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_664
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_664
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_665
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_665
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_666
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_667
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_668
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_669
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_670
+CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_671
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_229
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_229
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_230
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_230
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_231
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_231
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_239
+CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_247

diff --git a/zynq7/segbits_int_l.origin_info.db b/zynq7/segbits_int_l.origin_info.db
index adb181a..51fc51a 100644
--- a/zynq7/segbits_int_l.origin_info.db
+++ b/zynq7/segbits_int_l.origin_info.db

@@ -1897,7 +1897,7 @@
 INT_L.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
 INT_L.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
 INT_L.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
-INT_L.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
+INT_L.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
 INT_L.EE4BEG2.LOGIC_OUTS_L2 origin:050-pip-seed 02_41 04_42
 INT_L.EE4BEG2.LOGIC_OUTS_L6 origin:050-pip-seed 02_41 07_41
 INT_L.EE4BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_40 07_41
@@ -1917,7 +1917,7 @@
 INT_L.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
 INT_L.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
 INT_L.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
-INT_L.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
+INT_L.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
 INT_L.EE4BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_57 07_57
 INT_L.EE4BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_57 04_58
 INT_L.EE4BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_56 04_58
@@ -1937,7 +1937,7 @@
 INT_L.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
 INT_L.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
 INT_L.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_L.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
+INT_L.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
 INT_L.EL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_20 14_21
 INT_L.EL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_21 14_21
 INT_L.EL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_21 13_21
@@ -2273,7 +2273,7 @@
 INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
 INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
 INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
+INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
 INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17
 INT_L.NL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_17 14_17
 INT_L.NL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_17 13_17
@@ -2662,7 +2662,7 @@
 INT_L.NW6BEG0.LOGIC_OUTS_L22 origin:050-pip-seed 06_02 07_03
 INT_L.NW6BEG0.LV_L0 origin:056-pip-rem 04_03 06_02
 INT_L.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00
-INT_L.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03
+INT_L.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03
 INT_L.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00
 INT_L.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03
 INT_L.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03
@@ -3302,7 +3302,7 @@
 INT_L.SW6BEG1.LOGIC_OUTS_L23 origin:050-pip-seed 04_30 06_28
 INT_L.SW6BEG1.LV_L9 origin:056-pip-rem 04_30 05_28
 INT_L.SW6BEG1.EE2END1 origin:050-pip-seed 03_28 04_29
-INT_L.SW6BEG1.EE4END1 origin:056-pip-rem 04_29 05_28
+INT_L.SW6BEG1.EE4END1 origin:050-pip-seed 04_29 05_28
 INT_L.SW6BEG1.LH6 origin:056-pip-rem 05_28 07_29
 INT_L.SW6BEG1.NW2END2 origin:050-pip-seed 02_29 05_31
 INT_L.SW6BEG1.NW6END2 origin:050-pip-seed 05_31 06_28
@@ -3603,7 +3603,7 @@
 INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
 INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
 INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
-INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
+INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
 INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
 INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
 INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33

diff --git a/zynq7/segbits_int_r.origin_info.db b/zynq7/segbits_int_r.origin_info.db
index 8537d1c..816ece8 100644
--- a/zynq7/segbits_int_r.origin_info.db
+++ b/zynq7/segbits_int_r.origin_info.db

@@ -237,7 +237,7 @@
 INT_R.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
 INT_R.FAN_ALT0.LOGIC_OUTS0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
 INT_R.FAN_ALT0.LOGIC_OUTS12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
-INT_R.FAN_ALT0.LOGIC_OUTS22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
+INT_R.FAN_ALT0.LOGIC_OUTS22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
 INT_R.FAN_ALT0.SR1END_N3_3 origin:050-pip-seed !23_00 19_01 22_00 24_00 25_00
 INT_R.FAN_ALT0.SS2END_N0_3 origin:050-pip-seed !22_00 !23_00 !24_00 17_00 25_00
 INT_R.FAN_ALT0.SW2END_N0_3 origin:050-pip-seed !22_00 !23_00 !25_00 17_00 24_00
@@ -332,7 +332,7 @@
 INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
-INT_R.FAN_ALT4.LOGIC_OUTS18 origin:056-pip-rem !22_08 !23_08 !25_08 21_08 24_08
+INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
 INT_R.FAN_ALT4.SR1BEG_S0 origin:050-pip-seed !23_08 19_09 22_08 24_08 25_08
 INT_R.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
 INT_R.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
@@ -685,7 +685,7 @@
 INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
 INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
 INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
-INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
+INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
 INT_R.EE4BEG2.LOGIC_OUTS2 origin:050-pip-seed 02_41 04_42
 INT_R.EE4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_41 07_41
 INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
@@ -2273,7 +2273,7 @@
 INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
 INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
 INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
+INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
 INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17
 INT_R.NL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_17 14_17
 INT_R.NL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_17 13_17
@@ -2471,7 +2471,7 @@
 INT_R.NN6BEG2.NW2END2 origin:050-pip-seed 03_38 04_36
 INT_R.NN6BEG2.NW6END2 origin:050-pip-seed 04_36 07_39
 INT_R.NN6BEG2.SE2END2 origin:050-pip-seed 03_38 05_38
-INT_R.NN6BEG2.SE6END2 origin:056-pip-rem 05_38 07_39
+INT_R.NN6BEG2.SE6END2 origin:050-pip-seed 05_38 07_39
 INT_R.NN6BEG2.WW2END1 origin:050-pip-seed 02_39 04_36
 INT_R.NN6BEG2.WW4END2 origin:050-pip-seed 04_36 04_39
 INT_R.NN6BEG3.LOGIC_OUTS3 origin:050-pip-seed 03_54 06_54
@@ -2491,7 +2491,7 @@
 INT_R.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
 INT_R.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
 INT_R.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
-INT_R.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
+INT_R.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
 INT_R.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
 INT_R.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
 INT_R.NR1BEG0.LOGIC_OUTS0 origin:050-pip-seed 11_07 14_07
@@ -3321,7 +3321,7 @@
 INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
 INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
 INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
 INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
 INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
 INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
@@ -3568,7 +3568,7 @@
 INT_R.WW4BEG0.LH12 origin:056-pip-rem 05_00 07_01
 INT_R.WW4BEG0.LV0 origin:056-pip-rem 04_02 05_00
 INT_R.WW4BEG0.NE2END0 origin:050-pip-seed 02_01 05_03
-INT_R.WW4BEG0.NE6END0 origin:056-pip-rem 05_00 05_03
+INT_R.WW4BEG0.NE6END0 origin:050-pip-seed 05_00 05_03
 INT_R.WW4BEG0.NN2END0 origin:050-pip-seed 03_00 05_03
 INT_R.WW4BEG0.NN6END0 origin:050-pip-seed 05_03 06_00
 INT_R.WW4BEG0.NW2END0 origin:050-pip-seed 02_01 03_01
@@ -3603,7 +3603,7 @@
 INT_R.WW4BEG2.LVB0 origin:056-pip-rem 04_34 05_32
 INT_R.WW4BEG2.LVB12 origin:056-pip-rem 05_32 07_33
 INT_R.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
-INT_R.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
+INT_R.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
 INT_R.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
 INT_R.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
 INT_R.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33

diff --git a/zynq7/segbits_liob33.origin_info.db b/zynq7/segbits_liob33.origin_info.db
index c0a134f..0490cb8 100644
--- a/zynq7/segbits_liob33.origin_info.db
+++ b/zynq7/segbits_liob33.origin_info.db

@@ -37,10 +37,10 @@
 LIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87
 LIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST origin:030-iob !38_106 38_110 39_105 39_107 39_109 39_111
 LIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45
-LIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_4 !38_6 !39_5 !39_7
-LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_4 38_6 39_5 39_7
-LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_6 38_4 39_5 39_7
-LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_6 !39_5 38_4 39_7
+LIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_04 !38_06 !39_05 !39_07
+LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07
+LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07
+LIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07
 LIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
 LIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63
 LIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35

diff --git a/zynq7/segbits_lioi3.db b/zynq7/segbits_lioi3.db
index f781c22..465ab9b 100644
--- a/zynq7/segbits_lioi3.db
+++ b/zynq7/segbits_lioi3.db

@@ -40,6 +40,7 @@
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+LIOI3.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 LIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 LIOI3.ILOGIC_Y0.IDELMUXE3.P0 29_101
 LIOI3.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 LIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+LIOI3.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 LIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 LIOI3.OLOGIC_Y0.IS_D7_INVERTED 31_118
 LIOI3.OLOGIC_Y0.IS_D8_INVERTED 30_125
 LIOI3.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+LIOI3.OLOGIC_Y0.ODDR.SRUSED 32_112
+LIOI3.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 LIOI3.OLOGIC_Y0.OMUX.D1 33_111
 LIOI3.OLOGIC_Y0.OQUSED 31_86
 LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-LIOI3.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3.OLOGIC_Y0.OSERDES.IN_USE 33_73
 LIOI3.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 LIOI3.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 LIOI3.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 LIOI3.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+LIOI3.OLOGIC_Y0.TDDR.SRUSED 33_89
 LIOI3.OLOGIC_Y0.ZINIT_OQ 33_97
 LIOI3.OLOGIC_Y0.ZINIT_TQ 30_75
-LIOI3.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+LIOI3.OLOGIC_Y0.ZINV_CLK 31_90
 LIOI3.OLOGIC_Y0.ZINV_T1 30_67
 LIOI3.OLOGIC_Y0.ZINV_T2 30_71
 LIOI3.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 LIOI3.OLOGIC_Y1.IS_D7_INVERTED 30_09
 LIOI3.OLOGIC_Y1.IS_D8_INVERTED 31_02
 LIOI3.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+LIOI3.OLOGIC_Y1.ODDR.SRUSED 33_15
+LIOI3.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 LIOI3.OLOGIC_Y1.OMUX.D1 32_16
 LIOI3.OLOGIC_Y1.OQUSED 30_41
 LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-LIOI3.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3.OLOGIC_Y1.OSERDES.IN_USE 32_54
 LIOI3.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 LIOI3.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 LIOI3.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 LIOI3.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+LIOI3.OLOGIC_Y1.TDDR.SRUSED 32_38
 LIOI3.OLOGIC_Y1.ZINIT_OQ 32_30
 LIOI3.OLOGIC_Y1.ZINIT_TQ 31_52
-LIOI3.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+LIOI3.OLOGIC_Y1.ZINV_CLK 30_37
 LIOI3.OLOGIC_Y1.ZINV_T1 31_60
 LIOI3.OLOGIC_Y1.ZINV_T2 31_56
 LIOI3.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/zynq7/segbits_lioi3.origin_info.db b/zynq7/segbits_lioi3.origin_info.db
index a80d11c..e7e201c 100644
--- a/zynq7/segbits_lioi3.origin_info.db
+++ b/zynq7/segbits_lioi3.origin_info.db

@@ -40,6 +40,7 @@
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 LIOI3.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+LIOI3.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 LIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 LIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 LIOI3.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 LIOI3.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 LIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+LIOI3.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 LIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 LIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 LIOI3.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 LIOI3.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 LIOI3.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-LIOI3.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 LIOI3.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 LIOI3.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 LIOI3.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 LIOI3.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 LIOI3.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 LIOI3.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-LIOI3.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+LIOI3.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 LIOI3.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 LIOI3.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 LIOI3.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 LIOI3.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 LIOI3.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 LIOI3.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+LIOI3.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+LIOI3.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 LIOI3.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 LIOI3.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-LIOI3.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+LIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+LIOI3.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 LIOI3.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 LIOI3.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 LIOI3.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 LIOI3.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+LIOI3.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 LIOI3.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 LIOI3.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-LIOI3.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+LIOI3.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 LIOI3.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 LIOI3.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 LIOI3.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 LIOI3.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 LIOI3.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 LIOI3.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+LIOI3.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+LIOI3.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 LIOI3.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 LIOI3.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-LIOI3.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+LIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+LIOI3.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 LIOI3.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 LIOI3.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 LIOI3.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 LIOI3.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+LIOI3.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 LIOI3.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 LIOI3.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-LIOI3.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+LIOI3.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 LIOI3.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 LIOI3.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 LIOI3.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/zynq7/segbits_lioi3_tbytesrc.db b/zynq7/segbits_lioi3_tbytesrc.db
index 304a60b..f58db14 100644
--- a/zynq7/segbits_lioi3_tbytesrc.db
+++ b/zynq7/segbits_lioi3_tbytesrc.db

@@ -40,6 +40,7 @@
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+LIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 LIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 29_101
 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 LIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+LIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 LIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 LIOI3_TBYTESRC.OLOGIC_Y0.IS_D7_INVERTED 31_118
 LIOI3_TBYTESRC.OLOGIC_Y0.IS_D8_INVERTED 30_125
 LIOI3_TBYTESRC.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+LIOI3_TBYTESRC.OLOGIC_Y0.ODDR.SRUSED 32_112
+LIOI3_TBYTESRC.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 LIOI3_TBYTESRC.OLOGIC_Y0.OMUX.D1 33_111
 LIOI3_TBYTESRC.OLOGIC_Y0.OQUSED 31_86
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE 33_73
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+LIOI3_TBYTESRC.OLOGIC_Y0.TDDR.SRUSED 33_89
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_OQ 33_97
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_TQ 30_75
-LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK 31_90
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T1 30_67
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T2 30_71
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 LIOI3_TBYTESRC.OLOGIC_Y1.IS_D7_INVERTED 30_09
 LIOI3_TBYTESRC.OLOGIC_Y1.IS_D8_INVERTED 31_02
 LIOI3_TBYTESRC.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+LIOI3_TBYTESRC.OLOGIC_Y1.ODDR.SRUSED 33_15
+LIOI3_TBYTESRC.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 LIOI3_TBYTESRC.OLOGIC_Y1.OMUX.D1 32_16
 LIOI3_TBYTESRC.OLOGIC_Y1.OQUSED 30_41
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE 32_54
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+LIOI3_TBYTESRC.OLOGIC_Y1.TDDR.SRUSED 32_38
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_OQ 32_30
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_TQ 31_52
-LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK 30_37
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T1 31_60
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T2 31_56
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/zynq7/segbits_lioi3_tbytesrc.origin_info.db b/zynq7/segbits_lioi3_tbytesrc.origin_info.db
index 8d0ae06..2ac3c07 100644
--- a/zynq7/segbits_lioi3_tbytesrc.origin_info.db
+++ b/zynq7/segbits_lioi3_tbytesrc.origin_info.db

@@ -40,6 +40,7 @@
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 LIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+LIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 LIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 LIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 LIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 LIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+LIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 LIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 LIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+LIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 LIOI3_TBYTESRC.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 LIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 LIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 LIOI3_TBYTESRC.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 LIOI3_TBYTESRC.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 LIOI3_TBYTESRC.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+LIOI3_TBYTESRC.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+LIOI3_TBYTESRC.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 LIOI3_TBYTESRC.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 LIOI3_TBYTESRC.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 LIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+LIOI3_TBYTESRC.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 LIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 LIOI3_TBYTESRC.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 LIOI3_TBYTESRC.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 LIOI3_TBYTESRC.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+LIOI3_TBYTESRC.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+LIOI3_TBYTESRC.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 LIOI3_TBYTESRC.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 LIOI3_TBYTESRC.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 LIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+LIOI3_TBYTESRC.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 LIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/zynq7/segbits_lioi3_tbyteterm.db b/zynq7/segbits_lioi3_tbyteterm.db
index d60dde9..0c20c4d 100644
--- a/zynq7/segbits_lioi3_tbyteterm.db
+++ b/zynq7/segbits_lioi3_tbyteterm.db

@@ -40,6 +40,7 @@
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+LIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 LIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 29_101
 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 LIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+LIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 LIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 LIOI3_TBYTETERM.OLOGIC_Y0.IS_D7_INVERTED 31_118
 LIOI3_TBYTETERM.OLOGIC_Y0.IS_D8_INVERTED 30_125
 LIOI3_TBYTETERM.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+LIOI3_TBYTETERM.OLOGIC_Y0.ODDR.SRUSED 32_112
+LIOI3_TBYTETERM.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 LIOI3_TBYTETERM.OLOGIC_Y0.OMUX.D1 33_111
 LIOI3_TBYTETERM.OLOGIC_Y0.OQUSED 31_86
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE 33_73
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+LIOI3_TBYTETERM.OLOGIC_Y0.TDDR.SRUSED 33_89
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_OQ 33_97
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_TQ 30_75
-LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK 31_90
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T1 30_67
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T2 30_71
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 LIOI3_TBYTETERM.OLOGIC_Y1.IS_D7_INVERTED 30_09
 LIOI3_TBYTETERM.OLOGIC_Y1.IS_D8_INVERTED 31_02
 LIOI3_TBYTETERM.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+LIOI3_TBYTETERM.OLOGIC_Y1.ODDR.SRUSED 33_15
+LIOI3_TBYTETERM.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 LIOI3_TBYTETERM.OLOGIC_Y1.OMUX.D1 32_16
 LIOI3_TBYTETERM.OLOGIC_Y1.OQUSED 30_41
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE 32_54
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+LIOI3_TBYTETERM.OLOGIC_Y1.TDDR.SRUSED 32_38
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_OQ 32_30
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_TQ 31_52
-LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK 30_37
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T1 31_60
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T2 31_56
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/zynq7/segbits_lioi3_tbyteterm.origin_info.db b/zynq7/segbits_lioi3_tbyteterm.origin_info.db
index e72ab0e..8559928 100644
--- a/zynq7/segbits_lioi3_tbyteterm.origin_info.db
+++ b/zynq7/segbits_lioi3_tbyteterm.origin_info.db

@@ -40,6 +40,7 @@
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 LIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+LIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 LIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 LIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 LIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 LIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+LIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 LIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 LIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+LIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 LIOI3_TBYTETERM.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 LIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 LIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 LIOI3_TBYTETERM.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 LIOI3_TBYTETERM.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 LIOI3_TBYTETERM.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+LIOI3_TBYTETERM.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+LIOI3_TBYTETERM.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 LIOI3_TBYTETERM.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 LIOI3_TBYTETERM.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 LIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+LIOI3_TBYTETERM.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 LIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 LIOI3_TBYTETERM.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 LIOI3_TBYTETERM.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 LIOI3_TBYTETERM.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+LIOI3_TBYTETERM.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+LIOI3_TBYTETERM.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 LIOI3_TBYTETERM.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 LIOI3_TBYTETERM.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 LIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+LIOI3_TBYTETERM.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 LIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/zynq7/segbits_riob33.origin_info.db b/zynq7/segbits_riob33.origin_info.db
index a6d64c5..8db23c8 100644
--- a/zynq7/segbits_riob33.origin_info.db
+++ b/zynq7/segbits_riob33.origin_info.db

@@ -37,10 +37,10 @@
 RIOB33.IOB_Y0.SSTL135_SSTL15.IN_DIFF origin:030-iob !39_85 38_86 39_87
 RIOB33.IOB_Y0.SSTL135_SSTL15.SLEW.FAST origin:030-iob !38_106 38_110 39_105 39_107 39_109 39_111
 RIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45
-RIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_4 !38_6 !39_5 !39_7
-RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_4 38_6 39_5 39_7
-RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_6 38_4 39_5 39_7
-RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_6 !39_5 38_4 39_7
+RIOB33.IOB_Y1.IN_TERM.NONE origin:030-iob !38_04 !38_06 !39_05 !39_07
+RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_40 origin:030-iob 38_04 38_06 39_05 39_07
+RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_50 origin:030-iob !38_06 38_04 39_05 39_07
+RIOB33.IOB_Y1.IN_TERM.UNTUNED_SPLIT_60 origin:030-iob !38_06 !39_05 38_04 39_07
 RIOB33.IOB_Y1.INTERMDISABLE.I origin:030-iob 38_38
 RIOB33.IOB_Y1.LVTTL.DRIVE.I24 origin:030-iob !38_00 !38_02 !39_09 !39_15 38_08 38_10 38_62 39_01 39_63
 RIOB33.IOB_Y1.PULLTYPE.KEEPER origin:030-iob !38_34 39_33 39_35

diff --git a/zynq7/segbits_rioi3.db b/zynq7/segbits_rioi3.db
index 852f46e..8d44a45 100644
--- a/zynq7/segbits_rioi3.db
+++ b/zynq7/segbits_rioi3.db

@@ -40,6 +40,7 @@
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+RIOI3.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 RIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 RIOI3.ILOGIC_Y0.IDELMUXE3.P0 29_101
 RIOI3.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 RIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+RIOI3.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 RIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 RIOI3.OLOGIC_Y0.IS_D7_INVERTED 31_118
 RIOI3.OLOGIC_Y0.IS_D8_INVERTED 30_125
 RIOI3.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+RIOI3.OLOGIC_Y0.ODDR.SRUSED 32_112
+RIOI3.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 RIOI3.OLOGIC_Y0.OMUX.D1 33_111
 RIOI3.OLOGIC_Y0.OQUSED 31_86
 RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-RIOI3.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3.OLOGIC_Y0.OSERDES.IN_USE 33_73
 RIOI3.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 RIOI3.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 RIOI3.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 RIOI3.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+RIOI3.OLOGIC_Y0.TDDR.SRUSED 33_89
 RIOI3.OLOGIC_Y0.ZINIT_OQ 33_97
 RIOI3.OLOGIC_Y0.ZINIT_TQ 30_75
-RIOI3.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+RIOI3.OLOGIC_Y0.ZINV_CLK 31_90
 RIOI3.OLOGIC_Y0.ZINV_T1 30_67
 RIOI3.OLOGIC_Y0.ZINV_T2 30_71
 RIOI3.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 RIOI3.OLOGIC_Y1.IS_D7_INVERTED 30_09
 RIOI3.OLOGIC_Y1.IS_D8_INVERTED 31_02
 RIOI3.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+RIOI3.OLOGIC_Y1.ODDR.SRUSED 33_15
+RIOI3.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 RIOI3.OLOGIC_Y1.OMUX.D1 32_16
 RIOI3.OLOGIC_Y1.OQUSED 30_41
 RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-RIOI3.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3.OLOGIC_Y1.OSERDES.IN_USE 32_54
 RIOI3.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 RIOI3.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 RIOI3.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 RIOI3.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+RIOI3.OLOGIC_Y1.TDDR.SRUSED 32_38
 RIOI3.OLOGIC_Y1.ZINIT_OQ 32_30
 RIOI3.OLOGIC_Y1.ZINIT_TQ 31_52
-RIOI3.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+RIOI3.OLOGIC_Y1.ZINV_CLK 30_37
 RIOI3.OLOGIC_Y1.ZINV_T1 31_60
 RIOI3.OLOGIC_Y1.ZINV_T2 31_56
 RIOI3.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/zynq7/segbits_rioi3.origin_info.db b/zynq7/segbits_rioi3.origin_info.db
index 5c6e73b..a796d38 100644
--- a/zynq7/segbits_rioi3.origin_info.db
+++ b/zynq7/segbits_rioi3.origin_info.db

@@ -40,6 +40,7 @@
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 RIOI3.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+RIOI3.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 RIOI3.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 RIOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 RIOI3.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 RIOI3.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 RIOI3.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+RIOI3.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 RIOI3.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 RIOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 RIOI3.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 RIOI3.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 RIOI3.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-RIOI3.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 RIOI3.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 RIOI3.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 RIOI3.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 RIOI3.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 RIOI3.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 RIOI3.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-RIOI3.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+RIOI3.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 RIOI3.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 RIOI3.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 RIOI3.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 RIOI3.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 RIOI3.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 RIOI3.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+RIOI3.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+RIOI3.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 RIOI3.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 RIOI3.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-RIOI3.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+RIOI3.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+RIOI3.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 RIOI3.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 RIOI3.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 RIOI3.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 RIOI3.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+RIOI3.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 RIOI3.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 RIOI3.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-RIOI3.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+RIOI3.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 RIOI3.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 RIOI3.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 RIOI3.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 RIOI3.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 RIOI3.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 RIOI3.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+RIOI3.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+RIOI3.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 RIOI3.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 RIOI3.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-RIOI3.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+RIOI3.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+RIOI3.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 RIOI3.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 RIOI3.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 RIOI3.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 RIOI3.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+RIOI3.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 RIOI3.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 RIOI3.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-RIOI3.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+RIOI3.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 RIOI3.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 RIOI3.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 RIOI3.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/zynq7/segbits_rioi3_tbytesrc.db b/zynq7/segbits_rioi3_tbytesrc.db
index c2b6214..87be7f7 100644
--- a/zynq7/segbits_rioi3_tbytesrc.db
+++ b/zynq7/segbits_rioi3_tbytesrc.db

@@ -40,6 +40,7 @@
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+RIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 RIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 29_101
 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 RIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+RIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 RIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 RIOI3_TBYTESRC.OLOGIC_Y0.IS_D7_INVERTED 31_118
 RIOI3_TBYTESRC.OLOGIC_Y0.IS_D8_INVERTED 30_125
 RIOI3_TBYTESRC.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+RIOI3_TBYTESRC.OLOGIC_Y0.ODDR.SRUSED 32_112
+RIOI3_TBYTESRC.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 RIOI3_TBYTESRC.OLOGIC_Y0.OMUX.D1 33_111
 RIOI3_TBYTESRC.OLOGIC_Y0.OQUSED 31_86
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE 33_73
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+RIOI3_TBYTESRC.OLOGIC_Y0.TDDR.SRUSED 33_89
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_OQ 33_97
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_TQ 30_75
-RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK 31_90
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T1 30_67
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T2 30_71
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 RIOI3_TBYTESRC.OLOGIC_Y1.IS_D7_INVERTED 30_09
 RIOI3_TBYTESRC.OLOGIC_Y1.IS_D8_INVERTED 31_02
 RIOI3_TBYTESRC.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+RIOI3_TBYTESRC.OLOGIC_Y1.ODDR.SRUSED 33_15
+RIOI3_TBYTESRC.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 RIOI3_TBYTESRC.OLOGIC_Y1.OMUX.D1 32_16
 RIOI3_TBYTESRC.OLOGIC_Y1.OQUSED 30_41
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE 32_54
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+RIOI3_TBYTESRC.OLOGIC_Y1.TDDR.SRUSED 32_38
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_OQ 32_30
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_TQ 31_52
-RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK 30_37
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T1 31_60
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T2 31_56
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/zynq7/segbits_rioi3_tbytesrc.origin_info.db b/zynq7/segbits_rioi3_tbytesrc.origin_info.db
index 440fa78..23c8e8e 100644
--- a/zynq7/segbits_rioi3_tbytesrc.origin_info.db
+++ b/zynq7/segbits_rioi3_tbytesrc.origin_info.db

@@ -40,6 +40,7 @@
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 RIOI3_TBYTESRC.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+RIOI3_TBYTESRC.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 RIOI3_TBYTESRC.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 RIOI3_TBYTESRC.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 RIOI3_TBYTESRC.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 RIOI3_TBYTESRC.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+RIOI3_TBYTESRC.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 RIOI3_TBYTESRC.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 RIOI3_TBYTESRC.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+RIOI3_TBYTESRC.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 RIOI3_TBYTESRC.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 RIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 RIOI3_TBYTESRC.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 RIOI3_TBYTESRC.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 RIOI3_TBYTESRC.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 RIOI3_TBYTESRC.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+RIOI3_TBYTESRC.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+RIOI3_TBYTESRC.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 RIOI3_TBYTESRC.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 RIOI3_TBYTESRC.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 RIOI3_TBYTESRC.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+RIOI3_TBYTESRC.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 RIOI3_TBYTESRC.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 RIOI3_TBYTESRC.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 RIOI3_TBYTESRC.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 RIOI3_TBYTESRC.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+RIOI3_TBYTESRC.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+RIOI3_TBYTESRC.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 RIOI3_TBYTESRC.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 RIOI3_TBYTESRC.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 RIOI3_TBYTESRC.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+RIOI3_TBYTESRC.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 RIOI3_TBYTESRC.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/zynq7/segbits_rioi3_tbyteterm.db b/zynq7/segbits_rioi3_tbyteterm.db
index bafc348..95901a8 100644
--- a/zynq7/segbits_rioi3_tbyteterm.db
+++ b/zynq7/segbits_rioi3_tbyteterm.db

@@ -40,6 +40,7 @@
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[2] !35_17 35_19
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[3] !35_25 35_27
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[4] !35_31 35_33
+RIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE 26_71 26_121 27_70
 RIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE 26_71 27_70
 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE !26_99 27_98
 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 !27_98
@@ -84,6 +85,7 @@
 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 29_101
 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 !29_101
 RIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 28_116
+RIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE 26_57 27_06 27_56
 RIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE 26_57 27_56
 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 !27_28
 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE !26_29 27_28
@@ -282,30 +284,34 @@
 RIOI3_TBYTETERM.OLOGIC_Y0.IS_D7_INVERTED 31_118
 RIOI3_TBYTETERM.OLOGIC_Y0.IS_D8_INVERTED 30_125
 RIOI3_TBYTETERM.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92
+RIOI3_TBYTETERM.OLOGIC_Y0.ODDR.SRUSED 32_112
+RIOI3_TBYTETERM.OLOGIC_Y0.ODDR_TDDR.IN_USE 31_83
 RIOI3_TBYTETERM.OLOGIC_Y0.OMUX.D1 33_111
 RIOI3_TBYTETERM.OLOGIC_Y0.OQUSED 31_86
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR 33_91 !33_93
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR !33_91 33_93
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR 32_70
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR 33_69
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 30_95
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 30_99
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 !30_121 !30_123 30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 !30_121 !30_123 !30_127 !31_116 !31_120 31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 30_121 !30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 !30_121 !30_123 !30_127 !31_116 31_120 !31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 !30_121 30_123 !30_127 !31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 !30_121 !30_123 !30_127 31_116 !31_120 !31_124 !31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE 32_112 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF 32_66 !32_70 !33_69
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR !32_66 32_70 !33_69
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR !32_66 !32_70 33_69
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 !30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 31_120 !31_124 !31_126 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 30_95 30_99 !30_121 !30_123 !30_127 !31_100 31_116 !31_120 !31_124 !31_126 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 !30_95 30_99 !30_121 !30_123 30_127 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 30_95 !30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_124 31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 30_95 30_99 !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 !30_95 30_99 30_121 !30_123 !30_127 31_98 !31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 !30_95 30_99 !30_121 !30_123 !30_127 31_98 31_100 !31_116 31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 !30_95 !30_99 !30_121 30_123 !30_127 31_98 31_100 !31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 !30_95 !30_99 !30_121 !30_123 !30_127 31_98 31_100 31_116 !31_120 !31_124 !31_126 33_73 !33_91 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE 33_73
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE 33_83
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SRTYPE.SYNC 32_94
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 32_90
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC 32_72
+RIOI3_TBYTETERM.OLOGIC_Y0.TDDR.SRUSED 33_89
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_OQ 33_97
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_TQ 30_75
-RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK 31_90 31_92
+RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK 31_90
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T1 30_67
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T2 30_71
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T3 31_76
@@ -322,30 +328,34 @@
 RIOI3_TBYTETERM.OLOGIC_Y1.IS_D7_INVERTED 30_09
 RIOI3_TBYTETERM.OLOGIC_Y1.IS_D8_INVERTED 31_02
 RIOI3_TBYTETERM.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
+RIOI3_TBYTETERM.OLOGIC_Y1.ODDR.SRUSED 33_15
+RIOI3_TBYTETERM.OLOGIC_Y1.ODDR_TDDR.IN_USE 30_44
 RIOI3_TBYTETERM.OLOGIC_Y1.OMUX.D1 32_16
 RIOI3_TBYTETERM.OLOGIC_Y1.OQUSED 30_41
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR !32_34 32_36
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR 32_34 !32_36
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF 33_61
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR 33_57
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 31_32
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 31_28
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 !30_01 !30_03 !30_07 !30_11 31_00 !31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 30_01 !30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 !30_01 30_03 !30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 !30_01 !30_03 30_07 !30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 !30_01 !30_03 !30_07 !30_11 !31_00 31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 !30_01 !30_03 !30_07 30_11 !31_00 !31_04 !31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE 32_54 33_15
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF !32_58 !33_57 33_61
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR !32_58 33_57 !33_61
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR 32_58 !33_57 !33_61
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 !30_01 !30_03 30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 !30_01 !30_03 !30_07 30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 !30_01 30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 31_28 31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 !30_01 !30_03 !30_07 !30_11 !30_27 30_29 !31_00 !31_04 31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 !30_01 !30_03 30_07 !30_11 30_27 30_29 !31_00 !31_04 !31_06 31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 !30_01 !30_03 !30_07 !30_11 30_27 30_29 !31_00 31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 !30_01 !30_03 !30_07 30_11 30_27 30_29 !31_00 !31_04 !31_06 !31_28 !31_32 32_34 !32_36 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE 32_54
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE 32_44
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SRTYPE.SYNC 33_33
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 33_37
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC 33_55
+RIOI3_TBYTETERM.OLOGIC_Y1.TDDR.SRUSED 32_38
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_OQ 32_30
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_TQ 31_52
-RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK 30_35 30_37
+RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK 30_37
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T1 31_60
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T2 31_56
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T3 30_51

diff --git a/zynq7/segbits_rioi3_tbyteterm.origin_info.db b/zynq7/segbits_rioi3_tbyteterm.origin_info.db
index 106e4ad..d2489b9 100644
--- a/zynq7/segbits_rioi3_tbyteterm.origin_info.db
+++ b/zynq7/segbits_rioi3_tbyteterm.origin_info.db

@@ -40,6 +40,7 @@
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[2] origin:035a-iob-idelay !35_17 35_19
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[3] origin:035a-iob-idelay !35_25 35_27
 RIOI3_TBYTETERM.IDELAY_Y1.ZIDELAY_VALUE[4] origin:035a-iob-idelay !35_31 35_33
+RIOI3_TBYTETERM.ILOGIC_Y0.IDDR.IN_USE origin:035b-iob-iserdes 26_121 26_71 27_70
 RIOI3_TBYTETERM.ILOGIC_Y0.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_71 27_70
 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !26_99 27_98
 RIOI3_TBYTETERM.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !27_98 26_99
@@ -84,6 +85,7 @@
 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P0 origin:035-iob-ilogic 29_101
 RIOI3_TBYTETERM.ILOGIC_Y0.IDELMUXE3.P1 origin:035-iob-ilogic !29_101
 RIOI3_TBYTETERM.ILOGIC_Y0.IFFDELMUXE3.P0 origin:035-iob-ilogic 28_116
+RIOI3_TBYTETERM.ILOGIC_Y1.IDDR.IN_USE origin:035b-iob-iserdes 26_57 27_06 27_56
 RIOI3_TBYTETERM.ILOGIC_Y1.IDDR_OR_ISERDES.IN_USE origin:035b-iob-iserdes 26_57 27_56
 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic !27_28 26_29
 RIOI3_TBYTETERM.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic !26_29 27_28
@@ -103,27 +105,27 @@
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.DYN_CLK_INV_EN origin:035b-iob-iserdes 28_00
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.DYN_CLKDIV_INV_EN origin:035b-iob-iserdes 26_09
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.IN_USE origin:035b-iob-iserdes 26_25 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 !27_6 26_17 26_25 26_29 26_57 27_56 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 27_6 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_06 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_20 !27_26 26_17 26_25 26_29 26_57 27_06 27_56 28_60 29_17
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.W4 origin:035b-iob-iserdes 26_17 26_25 26_29 26_57 27_06 27_10 27_26 27_56 28_60 29_17
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MODE.MASTER origin:035b-iob-iserdes !26_21
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.MODE.SLAVE origin:035b-iob-iserdes 26_21
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_16 27_18 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_16 27_20 27_56 27_6 28_60 29_17
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_18 27_20 27_56 27_6 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_16 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_18 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_16 !27_26 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 origin:035b-iob-iserdes !26_15 !26_17 !26_19 !27_12 !27_26 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 origin:035b-iob-iserdes !26_15 !26_19 !27_12 !27_26 26_17 26_25 26_29 26_57 27_06 27_16 27_18 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_18 !27_26 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 origin:035b-iob-iserdes !26_17 !27_12 !27_18 !27_26 26_15 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 origin:035b-iob-iserdes !26_15 !27_12 !27_16 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 origin:035b-iob-iserdes !27_12 !27_16 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 origin:035b-iob-iserdes !26_15 !27_12 !27_18 !27_26 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 origin:035b-iob-iserdes !27_12 !27_18 !27_26 26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_16 27_20 27_56 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 origin:035b-iob-iserdes !26_15 !26_17 !27_12 !27_16 !27_26 26_19 26_25 26_29 26_57 27_06 27_18 27_20 27_56 28_60 29_17
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NUM_CE.N1 origin:035b-iob-iserdes !26_47
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.NUM_CE.N2 origin:035b-iob-iserdes 26_47
 RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OFB_USED origin:035b-iob-iserdes 28_14 28_24
-RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_12 27_20 27_26 27_56 27_6 28_60 29_17
+RIOI3_TBYTETERM.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 origin:035b-iob-iserdes !26_15 !26_19 !27_16 !27_18 26_17 26_25 26_29 26_57 27_06 27_12 27_20 27_26 27_56 28_60 29_17
 RIOI3_TBYTETERM.ILOGIC_Y1.ZINV_D origin:035-iob-ilogic 28_18
 RIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P0 origin:035-iob-ilogic 28_26
 RIOI3_TBYTETERM.ILOGIC_Y1.IDELMUXE3.P1 origin:035-iob-ilogic !28_26
@@ -282,30 +284,34 @@
 RIOI3_TBYTETERM.OLOGIC_Y0.IS_D7_INVERTED origin:036-iob-ologic 31_118
 RIOI3_TBYTETERM.OLOGIC_Y0.IS_D8_INVERTED origin:036-iob-ologic 30_125
 RIOI3_TBYTETERM.OLOGIC_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92
+RIOI3_TBYTETERM.OLOGIC_Y0.ODDR.SRUSED origin:036-iob-ologic 32_112
+RIOI3_TBYTETERM.OLOGIC_Y0.ODDR_TDDR.IN_USE origin:036-iob-ologic 31_83
 RIOI3_TBYTETERM.OLOGIC_Y0.OMUX.D1 origin:036-iob-ologic 33_111
 RIOI3_TBYTETERM.OLOGIC_Y0.OQUSED origin:036-iob-ologic 31_86
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !33_93 33_91
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !33_91 33_93
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 30_95
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 30_99
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_121 !30_123 !31_116 !31_120 !31_124 !31_126 30_127
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_124 31_126
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_120 !31_126 31_124
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_123 !30_127 !31_116 !31_120 !31_124 !31_126 30_121
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_116 !31_124 !31_126 31_120
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_121 !30_127 !31_116 !31_120 !31_124 !31_126 30_123
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_120 !31_124 !31_126 31_116
-RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 32_112 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_70 !33_69 32_66
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_66 !33_69 32_70
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !32_66 !32_70 33_69
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_126 30_99 31_124 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_124 !31_126 30_95 31_120 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_120 !31_124 !31_126 30_95 30_99 31_116 33_73
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_121 !30_123 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_127 30_99 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_99 !31_100 !31_116 !31_120 !31_124 !33_91 30_95 31_126 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_121 !30_123 !30_127 !31_100 !31_116 !31_120 !31_126 !33_91 30_95 30_99 31_124 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_123 !30_127 !30_95 !31_100 !31_116 !31_120 !31_124 !31_126 !33_91 30_121 30_99 31_98 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !31_116 !31_124 !31_126 !33_91 30_99 31_100 31_120 31_98 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_121 !30_127 !30_95 !30_99 !31_116 !31_120 !31_124 !31_126 !33_91 30_123 31_100 31_98 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_121 !30_123 !30_127 !30_95 !30_99 !31_120 !31_124 !31_126 !33_91 31_100 31_116 31_98 33_73 33_93
+RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.IN_USE origin:036-iob-ologic 33_73
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 33_83
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 32_94
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 32_90
 RIOI3_TBYTETERM.OLOGIC_Y0.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 32_72
+RIOI3_TBYTETERM.OLOGIC_Y0.TDDR.SRUSED origin:036-iob-ologic 33_89
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_OQ origin:036-iob-ologic 33_97
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINIT_TQ origin:036-iob-ologic 30_75
-RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90 31_92
+RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_CLK origin:036-iob-ologic 31_90
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T1 origin:036-iob-ologic 30_67
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T2 origin:036-iob-ologic 30_71
 RIOI3_TBYTETERM.OLOGIC_Y0.ZINV_T3 origin:036-iob-ologic 31_76
@@ -322,30 +328,34 @@
 RIOI3_TBYTETERM.OLOGIC_Y1.IS_D7_INVERTED origin:036-iob-ologic 30_09
 RIOI3_TBYTETERM.OLOGIC_Y1.IS_D8_INVERTED origin:036-iob-ologic 31_02
 RIOI3_TBYTETERM.OLOGIC_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35
+RIOI3_TBYTETERM.OLOGIC_Y1.ODDR.SRUSED origin:036-iob-ologic 33_15
+RIOI3_TBYTETERM.OLOGIC_Y1.ODDR_TDDR.IN_USE origin:036-iob-ologic 30_44
 RIOI3_TBYTETERM.OLOGIC_Y1.OMUX.D1 origin:036-iob-ologic 32_16
 RIOI3_TBYTETERM.OLOGIC_Y1.OQUSED origin:036-iob-ologic 30_41
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.DDR origin:036-iob-ologic !32_34 32_36
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_OQ.SDR origin:036-iob-ologic !32_36 32_34
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic 33_61
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic 33_57
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6_8 origin:036-iob-ologic 31_32
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2_4_5_6 origin:036-iob-ologic 31_28
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_04 !31_06 31_00
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !31_00 !31_04 !31_06 30_01
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !31_00 !31_04 !31_06 30_03
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_04 31_06
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 30_07
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 31_04
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 30_11
-RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54 33_15
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.BUF origin:036-iob-ologic !32_58 !33_57 33_61
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.DDR origin:036-iob-ologic !32_58 !33_61 33_57
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_RATE_TQ.SDR origin:036-iob-ologic !33_57 !33_61 32_58
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_32 30_03 31_28 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 30_07 31_32 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.DDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_27 !30_29 !31_00 !31_04 !31_06 30_11 31_28 31_32 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W2 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !30_29 !31_04 !31_06 !31_32 !32_36 31_00 31_28 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W3 origin:036-iob-ologic !30_03 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !31_28 !32_36 30_01 31_32 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W4 origin:036-iob-ologic !30_01 !30_07 !30_11 !30_27 !30_29 !31_00 !31_04 !31_06 !32_36 30_03 31_28 31_32 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W5 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !30_27 !31_00 !31_04 !31_32 !32_36 30_29 31_06 31_28 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W6 origin:036-iob-ologic !30_01 !30_03 !30_11 !31_00 !31_04 !31_06 !31_32 !32_36 30_07 30_27 30_29 31_28 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W7 origin:036-iob-ologic !30_01 !30_03 !30_07 !30_11 !31_00 !31_06 !31_28 !31_32 !32_36 30_27 30_29 31_04 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.DATA_WIDTH.SDR.W8 origin:036-iob-ologic !30_01 !30_03 !30_07 !31_00 !31_04 !31_06 !31_28 !31_32 !32_36 30_11 30_27 30_29 32_34 32_54
+RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.IN_USE origin:036-iob-ologic 32_54
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SERDES_MODE.SLAVE origin:036-iob-ologic 32_44
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.SRTYPE.SYNC origin:036-iob-ologic 33_33
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TRISTATE_WIDTH.W4 origin:036-iob-ologic 33_37
 RIOI3_TBYTETERM.OLOGIC_Y1.OSERDES.TSRTYPE.SYNC origin:036-iob-ologic 33_55
+RIOI3_TBYTETERM.OLOGIC_Y1.TDDR.SRUSED origin:036-iob-ologic 32_38
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_OQ origin:036-iob-ologic 32_30
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINIT_TQ origin:036-iob-ologic 31_52
-RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_35 30_37
+RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_CLK origin:036-iob-ologic 30_37
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T1 origin:036-iob-ologic 31_60
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T2 origin:036-iob-ologic 31_56
 RIOI3_TBYTETERM.OLOGIC_Y1.ZINV_T3 origin:036-iob-ologic 30_51

diff --git a/zynq7/timings/LIOB33.sdf b/zynq7/timings/LIOB33.sdf
index 43ad6e0..bfd9395 100644
--- a/zynq7/timings/LIOB33.sdf
+++ b/zynq7/timings/LIOB33.sdf

@@ -4,11 +4,11 @@
     (TIMESCALE 1ns)
 
     (CELL
-        (CELLTYPE "IOB33M_INBUF_ENIOB33_IOBM_INBUF_EN")
+        (CELLTYPE "IOB33_INBUF_ENIOB33_IOB_INBUF_EN")
         (INSTANCE IOB33M)
         (DELAY
             (ABSOLUTE
-                (IOPATH IBUFDISABLE OUT (0.339::0.390)(1.016::1.169))
+                (IOPATH IBUFDISABLE OUT (0.339::0.390)(1.027::1.182))
             )
         )
     )

diff --git a/zynq7/xc7z010clg400-1/tilegrid.json b/zynq7/xc7z010clg400-1/tilegrid.json
index b6536b6..4c6fc69 100644
--- a/zynq7/xc7z010clg400-1/tilegrid.json
+++ b/zynq7/xc7z010clg400-1/tilegrid.json

@@ -50573,7 +50573,14 @@
         "type": "CMT_PMV_L"
     },
     "CMT_TOP_L_LOWER_B_X119Y9": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00401B00",
+                "frames": 30,
+                "offset": 0,
+                "words": 49
+            }
+        },
         "clock_region": "X1Y0",
         "grid_x": 119,
         "grid_y": 95,
@@ -50585,7 +50592,14 @@
         "type": "CMT_TOP_L_LOWER_B"
     },
     "CMT_TOP_L_LOWER_B_X119Y61": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00001B00",
+                "frames": 30,
+                "offset": 0,
+                "words": 49
+            }
+        },
         "clock_region": "X1Y1",
         "grid_x": 119,
         "grid_y": 43,
@@ -50665,8 +50679,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00401B00",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y0",
@@ -50684,8 +50698,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00001B00",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y1",

diff --git a/zynq7/xc7z020clg400-1/tilegrid.json b/zynq7/xc7z020clg400-1/tilegrid.json
index 87f8ad6..bc05457 100644
--- a/zynq7/xc7z020clg400-1/tilegrid.json
+++ b/zynq7/xc7z020clg400-1/tilegrid.json

@@ -147455,7 +147455,14 @@
         "type": "CMT_PMV"
     },
     "CMT_TOP_L_LOWER_B_X178Y9": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00422400",
+                "frames": 30,
+                "offset": 0,
+                "words": 49
+            }
+        },
         "clock_region": "X1Y0",
         "grid_x": 178,
         "grid_y": 147,
@@ -147467,7 +147474,14 @@
         "type": "CMT_TOP_L_LOWER_B"
     },
     "CMT_TOP_L_LOWER_B_X178Y61": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00402400",
+                "frames": 30,
+                "offset": 0,
+                "words": 49
+            }
+        },
         "clock_region": "X1Y1",
         "grid_x": 178,
         "grid_y": 95,
@@ -147479,7 +147493,14 @@
         "type": "CMT_TOP_L_LOWER_B"
     },
     "CMT_TOP_L_LOWER_B_X178Y113": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00002400",
+                "frames": 30,
+                "offset": 0,
+                "words": 49
+            }
+        },
         "clock_region": "X1Y2",
         "grid_x": 178,
         "grid_y": 43,
@@ -147591,8 +147612,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00422400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y0",
@@ -147610,8 +147631,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00402400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y1",
@@ -147629,8 +147650,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00002400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y2",
@@ -147644,7 +147665,14 @@
         "type": "CMT_TOP_L_UPPER_T"
     },
     "CMT_TOP_R_LOWER_B_X8Y9": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00420080",
+                "frames": 30,
+                "offset": 0,
+                "words": 49
+            }
+        },
         "clock_region": "X0Y0",
         "grid_x": 8,
         "grid_y": 147,
@@ -147692,8 +147720,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00420080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y0",

diff --git a/zynq7/xc7z020clg484-1/tilegrid.json b/zynq7/xc7z020clg484-1/tilegrid.json
index 87f8ad6..bc05457 100644
--- a/zynq7/xc7z020clg484-1/tilegrid.json
+++ b/zynq7/xc7z020clg484-1/tilegrid.json

@@ -147455,7 +147455,14 @@
         "type": "CMT_PMV"
     },
     "CMT_TOP_L_LOWER_B_X178Y9": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00422400",
+                "frames": 30,
+                "offset": 0,
+                "words": 49
+            }
+        },
         "clock_region": "X1Y0",
         "grid_x": 178,
         "grid_y": 147,
@@ -147467,7 +147474,14 @@
         "type": "CMT_TOP_L_LOWER_B"
     },
     "CMT_TOP_L_LOWER_B_X178Y61": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00402400",
+                "frames": 30,
+                "offset": 0,
+                "words": 49
+            }
+        },
         "clock_region": "X1Y1",
         "grid_x": 178,
         "grid_y": 95,
@@ -147479,7 +147493,14 @@
         "type": "CMT_TOP_L_LOWER_B"
     },
     "CMT_TOP_L_LOWER_B_X178Y113": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00002400",
+                "frames": 30,
+                "offset": 0,
+                "words": 49
+            }
+        },
         "clock_region": "X1Y2",
         "grid_x": 178,
         "grid_y": 43,
@@ -147591,8 +147612,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00422400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y0",
@@ -147610,8 +147631,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00402400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y1",
@@ -147629,8 +147650,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00002400",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X1Y2",
@@ -147644,7 +147665,14 @@
         "type": "CMT_TOP_L_UPPER_T"
     },
     "CMT_TOP_R_LOWER_B_X8Y9": {
-        "bits": {},
+        "bits": {
+            "CLB_IO_CLK": {
+                "baseaddr": "0x00420080",
+                "frames": 30,
+                "offset": 0,
+                "words": 49
+            }
+        },
         "clock_region": "X0Y0",
         "grid_x": 8,
         "grid_y": 147,
@@ -147692,8 +147720,8 @@
             "CLB_IO_CLK": {
                 "baseaddr": "0x00420080",
                 "frames": 30,
-                "offset": 75,
-                "words": 26
+                "offset": 74,
+                "words": 27
             }
         },
         "clock_region": "X0Y0",
commit	76ef27c727f1b8e4d8c0ee681f71c4f4d4eab3c9	[log] [tgz]
author	Tim 'mithro' Ansell <me@mith.ro>	Wed Oct 21 12:04:33 2020 -0700
committer	Tim 'mithro' Ansell <me@mith.ro>	Wed Oct 21 12:05:08 2020 -0700
tree	ca62fbb8ec6f315ce123bab91772d0380b8d8edd
parent	303a61d8bc552f7a533b91b17448c59e908aa391 [diff]