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        "type": "BRAM_L"
    },
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                "offset": 40,
                "words": 10
            },
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        },
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        },
        "type": "BRAM_L"
    },
    "BRAM_L_X30Y75": {
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        },
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        },
        "type": "BRAM_L"
    },
    "BRAM_L_X30Y80": {
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        },
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        },
        "type": "BRAM_L"
    },
    "BRAM_L_X30Y85": {
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                "words": 10
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        },
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        },
        "type": "BRAM_L"
    },
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                "words": 10
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        },
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        "type": "BRAM_L"
    },
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        },
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        "type": "BRAM_L"
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    "BRAM_L_X6Y0": {
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        },
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        "type": "BRAM_L"
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        },
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        "type": "BRAM_L"
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        },
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        "type": "BRAM_L"
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                "words": 10
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        },
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        "type": "BRAM_L"
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        },
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                "words": 10
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                "words": 10
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                "offset": 0,
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                "words": 10
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    "BRAM_L_X6Y65": {
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                "words": 10
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        "type": "BRAM_L"
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                "words": 10
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        },
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        "type": "BRAM_L"
    },
    "BRAM_L_X6Y75": {
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                "offset": 51,
                "words": 10
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        "sites": {
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        "type": "BRAM_L"
    },
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                "offset": 61,
                "words": 10
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                "offset": 61,
                "words": 10
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        },
        "grid_x": 19,
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        "sites": {
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        "type": "BRAM_L"
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    "BRAM_L_X6Y85": {
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                "offset": 71,
                "words": 10
            },
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                "offset": 71,
                "words": 10
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        },
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        "sites": {
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        "type": "BRAM_L"
    },
    "BRAM_L_X6Y90": {
        "bits": {
            "BLOCK_RAM": {
                "baseaddr": "0x00800000",
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                "offset": 81,
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    "CLK_HROW_BOT_R_X60Y26": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00400B80",
                "frames": 30,
                "offset": 42,
                "words": 18
            }
        },
        "grid_x": 60,
        "grid_y": 130,
        "sites": {
            "BUFHCE_X0Y0": "BUFHCE",
            "BUFHCE_X0Y1": "BUFHCE",
            "BUFHCE_X0Y10": "BUFHCE",
            "BUFHCE_X0Y11": "BUFHCE",
            "BUFHCE_X0Y2": "BUFHCE",
            "BUFHCE_X0Y3": "BUFHCE",
            "BUFHCE_X0Y4": "BUFHCE",
            "BUFHCE_X0Y5": "BUFHCE",
            "BUFHCE_X0Y6": "BUFHCE",
            "BUFHCE_X0Y7": "BUFHCE",
            "BUFHCE_X0Y8": "BUFHCE",
            "BUFHCE_X0Y9": "BUFHCE",
            "BUFHCE_X1Y0": "BUFHCE",
            "BUFHCE_X1Y1": "BUFHCE",
            "BUFHCE_X1Y10": "BUFHCE",
            "BUFHCE_X1Y11": "BUFHCE",
            "BUFHCE_X1Y2": "BUFHCE",
            "BUFHCE_X1Y3": "BUFHCE",
            "BUFHCE_X1Y4": "BUFHCE",
            "BUFHCE_X1Y5": "BUFHCE",
            "BUFHCE_X1Y6": "BUFHCE",
            "BUFHCE_X1Y7": "BUFHCE",
            "BUFHCE_X1Y8": "BUFHCE",
            "BUFHCE_X1Y9": "BUFHCE"
        },
        "type": "CLK_HROW_BOT_R"
    },
    "CLK_HROW_TOP_R_X60Y130": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00020B80",
                "frames": 30,
                "offset": 42,
                "words": 18
            }
        },
        "grid_x": 60,
        "grid_y": 26,
        "sites": {
            "BUFHCE_X0Y24": "BUFHCE",
            "BUFHCE_X0Y25": "BUFHCE",
            "BUFHCE_X0Y26": "BUFHCE",
            "BUFHCE_X0Y27": "BUFHCE",
            "BUFHCE_X0Y28": "BUFHCE",
            "BUFHCE_X0Y29": "BUFHCE",
            "BUFHCE_X0Y30": "BUFHCE",
            "BUFHCE_X0Y31": "BUFHCE",
            "BUFHCE_X0Y32": "BUFHCE",
            "BUFHCE_X0Y33": "BUFHCE",
            "BUFHCE_X0Y34": "BUFHCE",
            "BUFHCE_X0Y35": "BUFHCE",
            "BUFHCE_X1Y24": "BUFHCE",
            "BUFHCE_X1Y25": "BUFHCE",
            "BUFHCE_X1Y26": "BUFHCE",
            "BUFHCE_X1Y27": "BUFHCE",
            "BUFHCE_X1Y28": "BUFHCE",
            "BUFHCE_X1Y29": "BUFHCE",
            "BUFHCE_X1Y30": "BUFHCE",
            "BUFHCE_X1Y31": "BUFHCE",
            "BUFHCE_X1Y32": "BUFHCE",
            "BUFHCE_X1Y33": "BUFHCE",
            "BUFHCE_X1Y34": "BUFHCE",
            "BUFHCE_X1Y35": "BUFHCE"
        },
        "type": "CLK_HROW_TOP_R"
    },
    "CLK_HROW_TOP_R_X60Y78": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00000B80",
                "frames": 30,
                "offset": 42,
                "words": 18
            }
        },
        "grid_x": 60,
        "grid_y": 78,
        "sites": {
            "BUFHCE_X0Y12": "BUFHCE",
            "BUFHCE_X0Y13": "BUFHCE",
            "BUFHCE_X0Y14": "BUFHCE",
            "BUFHCE_X0Y15": "BUFHCE",
            "BUFHCE_X0Y16": "BUFHCE",
            "BUFHCE_X0Y17": "BUFHCE",
            "BUFHCE_X0Y18": "BUFHCE",
            "BUFHCE_X0Y19": "BUFHCE",
            "BUFHCE_X0Y20": "BUFHCE",
            "BUFHCE_X0Y21": "BUFHCE",
            "BUFHCE_X0Y22": "BUFHCE",
            "BUFHCE_X0Y23": "BUFHCE",
            "BUFHCE_X1Y12": "BUFHCE",
            "BUFHCE_X1Y13": "BUFHCE",
            "BUFHCE_X1Y14": "BUFHCE",
            "BUFHCE_X1Y15": "BUFHCE",
            "BUFHCE_X1Y16": "BUFHCE",
            "BUFHCE_X1Y17": "BUFHCE",
            "BUFHCE_X1Y18": "BUFHCE",
            "BUFHCE_X1Y19": "BUFHCE",
            "BUFHCE_X1Y20": "BUFHCE",
            "BUFHCE_X1Y21": "BUFHCE",
            "BUFHCE_X1Y22": "BUFHCE",
            "BUFHCE_X1Y23": "BUFHCE"
        },
        "type": "CLK_HROW_TOP_R"
    },
    "CLK_MTBF2_X60Y47": {
        "bits": {},
        "grid_x": 60,
        "grid_y": 109,
        "sites": {},
        "type": "CLK_MTBF2"
    },
    "CLK_PMV2_SVT_X60Y34": {
        "bits": {},
        "grid_x": 60,
        "grid_y": 122,
        "sites": {},
        "type": "CLK_PMV2_SVT"
    },
    "CLK_PMV2_X60Y43": {
        "bits": {},
        "grid_x": 60,
        "grid_y": 113,
        "sites": {
            "PMV_X0Y2": "PMV2"
        },
        "type": "CLK_PMV2"
    },
    "CLK_PMVIOB_X60Y18": {
        "bits": {},
        "grid_x": 60,
        "grid_y": 138,
        "sites": {},
        "type": "CLK_PMVIOB"
    },
    "CLK_PMV_X60Y2": {
        "bits": {},
        "grid_x": 60,
        "grid_y": 154,
        "sites": {},
        "type": "CLK_PMV"
    },
    "CLK_TERM_X60Y0": {
        "bits": {},
        "grid_x": 60,
        "grid_y": 156,
        "sites": {},
        "type": "CLK_TERM"
    },
    "CLK_TERM_X60Y156": {
        "bits": {},
        "grid_x": 60,
        "grid_y": 0,
        "sites": {},
        "type": "CLK_TERM"
    },
    "CMT_FIFO_L_X107Y20": {
        "bits": {},
        "grid_x": 107,
        "grid_y": 136,
        "sites": {
            "IN_FIFO_X1Y1": "IN_FIFO",
            "OUT_FIFO_X1Y1": "OUT_FIFO"
        },
        "type": "CMT_FIFO_L"
    },
    "CMT_FIFO_L_X107Y33": {
        "bits": {},
        "grid_x": 107,
        "grid_y": 123,
        "sites": {
            "IN_FIFO_X1Y2": "IN_FIFO",
            "OUT_FIFO_X1Y2": "OUT_FIFO"
        },
        "type": "CMT_FIFO_L"
    },
    "CMT_FIFO_L_X107Y45": {
        "bits": {},
        "grid_x": 107,
        "grid_y": 111,
        "sites": {
            "IN_FIFO_X1Y3": "IN_FIFO",
            "OUT_FIFO_X1Y3": "OUT_FIFO"
        },
        "type": "CMT_FIFO_L"
    },
    "CMT_FIFO_L_X107Y60": {
        "bits": {},
        "grid_x": 107,
        "grid_y": 96,
        "sites": {
            "IN_FIFO_X1Y4": "IN_FIFO",
            "OUT_FIFO_X1Y4": "OUT_FIFO"
        },
        "type": "CMT_FIFO_L"
    },
    "CMT_FIFO_L_X107Y72": {
        "bits": {},
        "grid_x": 107,
        "grid_y": 84,
        "sites": {
            "IN_FIFO_X1Y5": "IN_FIFO",
            "OUT_FIFO_X1Y5": "OUT_FIFO"
        },
        "type": "CMT_FIFO_L"
    },
    "CMT_FIFO_L_X107Y8": {
        "bits": {},
        "grid_x": 107,
        "grid_y": 148,
        "sites": {
            "IN_FIFO_X1Y0": "IN_FIFO",
            "OUT_FIFO_X1Y0": "OUT_FIFO"
        },
        "type": "CMT_FIFO_L"
    },
    "CMT_FIFO_L_X107Y85": {
        "bits": {},
        "grid_x": 107,
        "grid_y": 71,
        "sites": {
            "IN_FIFO_X1Y6": "IN_FIFO",
            "OUT_FIFO_X1Y6": "OUT_FIFO"
        },
        "type": "CMT_FIFO_L"
    },
    "CMT_FIFO_L_X107Y97": {
        "bits": {},
        "grid_x": 107,
        "grid_y": 59,
        "sites": {
            "IN_FIFO_X1Y7": "IN_FIFO",
            "OUT_FIFO_X1Y7": "OUT_FIFO"
        },
        "type": "CMT_FIFO_L"
    },
    "CMT_FIFO_R_X7Y112": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 44,
        "sites": {
            "IN_FIFO_X0Y8": "IN_FIFO",
            "OUT_FIFO_X0Y8": "OUT_FIFO"
        },
        "type": "CMT_FIFO_R"
    },
    "CMT_FIFO_R_X7Y124": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 32,
        "sites": {
            "IN_FIFO_X0Y9": "IN_FIFO",
            "OUT_FIFO_X0Y9": "OUT_FIFO"
        },
        "type": "CMT_FIFO_R"
    },
    "CMT_FIFO_R_X7Y137": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 19,
        "sites": {
            "IN_FIFO_X0Y10": "IN_FIFO",
            "OUT_FIFO_X0Y10": "OUT_FIFO"
        },
        "type": "CMT_FIFO_R"
    },
    "CMT_FIFO_R_X7Y149": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 7,
        "sites": {
            "IN_FIFO_X0Y11": "IN_FIFO",
            "OUT_FIFO_X0Y11": "OUT_FIFO"
        },
        "type": "CMT_FIFO_R"
    },
    "CMT_FIFO_R_X7Y20": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 136,
        "sites": {
            "IN_FIFO_X0Y1": "IN_FIFO",
            "OUT_FIFO_X0Y1": "OUT_FIFO"
        },
        "type": "CMT_FIFO_R"
    },
    "CMT_FIFO_R_X7Y33": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 123,
        "sites": {
            "IN_FIFO_X0Y2": "IN_FIFO",
            "OUT_FIFO_X0Y2": "OUT_FIFO"
        },
        "type": "CMT_FIFO_R"
    },
    "CMT_FIFO_R_X7Y45": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 111,
        "sites": {
            "IN_FIFO_X0Y3": "IN_FIFO",
            "OUT_FIFO_X0Y3": "OUT_FIFO"
        },
        "type": "CMT_FIFO_R"
    },
    "CMT_FIFO_R_X7Y60": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 96,
        "sites": {
            "IN_FIFO_X0Y4": "IN_FIFO",
            "OUT_FIFO_X0Y4": "OUT_FIFO"
        },
        "type": "CMT_FIFO_R"
    },
    "CMT_FIFO_R_X7Y72": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 84,
        "sites": {
            "IN_FIFO_X0Y5": "IN_FIFO",
            "OUT_FIFO_X0Y5": "OUT_FIFO"
        },
        "type": "CMT_FIFO_R"
    },
    "CMT_FIFO_R_X7Y8": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 148,
        "sites": {
            "IN_FIFO_X0Y0": "IN_FIFO",
            "OUT_FIFO_X0Y0": "OUT_FIFO"
        },
        "type": "CMT_FIFO_R"
    },
    "CMT_FIFO_R_X7Y85": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 71,
        "sites": {
            "IN_FIFO_X0Y6": "IN_FIFO",
            "OUT_FIFO_X0Y6": "OUT_FIFO"
        },
        "type": "CMT_FIFO_R"
    },
    "CMT_FIFO_R_X7Y97": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 59,
        "sites": {
            "IN_FIFO_X0Y7": "IN_FIFO",
            "OUT_FIFO_X0Y7": "OUT_FIFO"
        },
        "type": "CMT_FIFO_R"
    },
    "CMT_PMV_L_X107Y1": {
        "bits": {},
        "grid_x": 107,
        "grid_y": 155,
        "sites": {},
        "type": "CMT_PMV_L"
    },
    "CMT_PMV_L_X107Y103": {
        "bits": {},
        "grid_x": 107,
        "grid_y": 53,
        "sites": {},
        "type": "CMT_PMV_L"
    },
    "CMT_PMV_L_X107Y51": {
        "bits": {},
        "grid_x": 107,
        "grid_y": 105,
        "sites": {},
        "type": "CMT_PMV_L"
    },
    "CMT_PMV_L_X107Y53": {
        "bits": {},
        "grid_x": 107,
        "grid_y": 103,
        "sites": {},
        "type": "CMT_PMV_L"
    },
    "CMT_PMV_X7Y1": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 155,
        "sites": {},
        "type": "CMT_PMV"
    },
    "CMT_PMV_X7Y103": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 53,
        "sites": {},
        "type": "CMT_PMV"
    },
    "CMT_PMV_X7Y105": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 51,
        "sites": {},
        "type": "CMT_PMV"
    },
    "CMT_PMV_X7Y155": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 1,
        "sites": {},
        "type": "CMT_PMV"
    },
    "CMT_PMV_X7Y51": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 105,
        "sites": {},
        "type": "CMT_PMV"
    },
    "CMT_PMV_X7Y53": {
        "bits": {},
        "grid_x": 7,
        "grid_y": 103,
        "sites": {},
        "type": "CMT_PMV"
    },
    "CMT_TOP_L_LOWER_B_X106Y61": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00020080",
                "frames": 30,
                "offset": 0,
                "words": 101
            }
        },
        "grid_x": 106,
        "grid_y": 95,
        "sites": {
            "MMCME2_ADV_X1Y1": "MMCME2_ADV"
        },
        "type": "CMT_TOP_L_LOWER_B"
    },
    "CMT_TOP_L_LOWER_B_X106Y9": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00000080",
                "frames": 30,
                "offset": 0,
                "words": 101
            }
        },
        "grid_x": 106,
        "grid_y": 147,
        "sites": {
            "MMCME2_ADV_X1Y0": "MMCME2_ADV"
        },
        "type": "CMT_TOP_L_LOWER_B"
    },
    "CMT_TOP_L_LOWER_T_X106Y18": {
        "bits": {},
        "grid_x": 106,
        "grid_y": 138,
        "sites": {
            "PHASER_IN_PHY_X1Y0": "PHASER_IN_PHY",
            "PHASER_IN_PHY_X1Y1": "PHASER_IN_PHY",
            "PHASER_OUT_PHY_X1Y0": "PHASER_OUT_PHY",
            "PHASER_OUT_PHY_X1Y1": "PHASER_OUT_PHY"
        },
        "type": "CMT_TOP_L_LOWER_T"
    },
    "CMT_TOP_L_LOWER_T_X106Y70": {
        "bits": {},
        "grid_x": 106,
        "grid_y": 86,
        "sites": {
            "PHASER_IN_PHY_X1Y4": "PHASER_IN_PHY",
            "PHASER_IN_PHY_X1Y5": "PHASER_IN_PHY",
            "PHASER_OUT_PHY_X1Y4": "PHASER_OUT_PHY",
            "PHASER_OUT_PHY_X1Y5": "PHASER_OUT_PHY"
        },
        "type": "CMT_TOP_L_LOWER_T"
    },
    "CMT_TOP_L_UPPER_B_X106Y31": {
        "bits": {},
        "grid_x": 106,
        "grid_y": 125,
        "sites": {
            "PHASER_IN_PHY_X1Y2": "PHASER_IN_PHY",
            "PHASER_IN_PHY_X1Y3": "PHASER_IN_PHY",
            "PHASER_OUT_PHY_X1Y2": "PHASER_OUT_PHY",
            "PHASER_OUT_PHY_X1Y3": "PHASER_OUT_PHY",
            "PHASER_REF_X1Y0": "PHASER_REF",
            "PHY_CONTROL_X1Y0": "PHY_CONTROL"
        },
        "type": "CMT_TOP_L_UPPER_B"
    },
    "CMT_TOP_L_UPPER_B_X106Y83": {
        "bits": {},
        "grid_x": 106,
        "grid_y": 73,
        "sites": {
            "PHASER_IN_PHY_X1Y6": "PHASER_IN_PHY",
            "PHASER_IN_PHY_X1Y7": "PHASER_IN_PHY",
            "PHASER_OUT_PHY_X1Y6": "PHASER_OUT_PHY",
            "PHASER_OUT_PHY_X1Y7": "PHASER_OUT_PHY",
            "PHASER_REF_X1Y1": "PHASER_REF",
            "PHY_CONTROL_X1Y1": "PHY_CONTROL"
        },
        "type": "CMT_TOP_L_UPPER_B"
    },
    "CMT_TOP_L_UPPER_T_X106Y44": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00401500",
                "frames": 30,
                "offset": 0,
                "words": 101
            }
        },
        "grid_x": 106,
        "grid_y": 112,
        "sites": {
            "PLLE2_ADV_X1Y0": "PLLE2_ADV"
        },
        "type": "CMT_TOP_L_UPPER_T"
    },
    "CMT_TOP_L_UPPER_T_X106Y96": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00001500",
                "frames": 30,
                "offset": 0,
                "words": 101
            }
        },
        "grid_x": 106,
        "grid_y": 60,
        "sites": {
            "PLLE2_ADV_X1Y1": "PLLE2_ADV"
        },
        "type": "CMT_TOP_L_UPPER_T"
    },
    "CMT_TOP_R_LOWER_B_X8Y113": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00001500",
                "frames": 30,
                "offset": 0,
                "words": 101
            }
        },
        "grid_x": 8,
        "grid_y": 43,
        "sites": {
            "MMCME2_ADV_X0Y2": "MMCME2_ADV"
        },
        "type": "CMT_TOP_R_LOWER_B"
    },
    "CMT_TOP_R_LOWER_B_X8Y61": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00400080",
                "frames": 30,
                "offset": 0,
                "words": 101
            }
        },
        "grid_x": 8,
        "grid_y": 95,
        "sites": {
            "MMCME2_ADV_X0Y1": "MMCME2_ADV"
        },
        "type": "CMT_TOP_R_LOWER_B"
    },
    "CMT_TOP_R_LOWER_B_X8Y9": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00401500",
                "frames": 30,
                "offset": 0,
                "words": 101
            }
        },
        "grid_x": 8,
        "grid_y": 147,
        "sites": {
            "MMCME2_ADV_X0Y0": "MMCME2_ADV"
        },
        "type": "CMT_TOP_R_LOWER_B"
    },
    "CMT_TOP_R_LOWER_T_X8Y122": {
        "bits": {},
        "grid_x": 8,
        "grid_y": 34,
        "sites": {
            "PHASER_IN_PHY_X0Y8": "PHASER_IN_PHY",
            "PHASER_IN_PHY_X0Y9": "PHASER_IN_PHY",
            "PHASER_OUT_PHY_X0Y8": "PHASER_OUT_PHY",
            "PHASER_OUT_PHY_X0Y9": "PHASER_OUT_PHY"
        },
        "type": "CMT_TOP_R_LOWER_T"
    },
    "CMT_TOP_R_LOWER_T_X8Y18": {
        "bits": {},
        "grid_x": 8,
        "grid_y": 138,
        "sites": {
            "PHASER_IN_PHY_X0Y0": "PHASER_IN_PHY",
            "PHASER_IN_PHY_X0Y1": "PHASER_IN_PHY",
            "PHASER_OUT_PHY_X0Y0": "PHASER_OUT_PHY",
            "PHASER_OUT_PHY_X0Y1": "PHASER_OUT_PHY"
        },
        "type": "CMT_TOP_R_LOWER_T"
    },
    "CMT_TOP_R_LOWER_T_X8Y70": {
        "bits": {},
        "grid_x": 8,
        "grid_y": 86,
        "sites": {
            "PHASER_IN_PHY_X0Y4": "PHASER_IN_PHY",
            "PHASER_IN_PHY_X0Y5": "PHASER_IN_PHY",
            "PHASER_OUT_PHY_X0Y4": "PHASER_OUT_PHY",
            "PHASER_OUT_PHY_X0Y5": "PHASER_OUT_PHY"
        },
        "type": "CMT_TOP_R_LOWER_T"
    },
    "CMT_TOP_R_UPPER_B_X8Y135": {
        "bits": {},
        "grid_x": 8,
        "grid_y": 21,
        "sites": {
            "PHASER_IN_PHY_X0Y10": "PHASER_IN_PHY",
            "PHASER_IN_PHY_X0Y11": "PHASER_IN_PHY",
            "PHASER_OUT_PHY_X0Y10": "PHASER_OUT_PHY",
            "PHASER_OUT_PHY_X0Y11": "PHASER_OUT_PHY",
            "PHASER_REF_X0Y2": "PHASER_REF",
            "PHY_CONTROL_X0Y2": "PHY_CONTROL"
        },
        "type": "CMT_TOP_R_UPPER_B"
    },
    "CMT_TOP_R_UPPER_B_X8Y31": {
        "bits": {},
        "grid_x": 8,
        "grid_y": 125,
        "sites": {
            "PHASER_IN_PHY_X0Y2": "PHASER_IN_PHY",
            "PHASER_IN_PHY_X0Y3": "PHASER_IN_PHY",
            "PHASER_OUT_PHY_X0Y2": "PHASER_OUT_PHY",
            "PHASER_OUT_PHY_X0Y3": "PHASER_OUT_PHY",
            "PHASER_REF_X0Y0": "PHASER_REF",
            "PHY_CONTROL_X0Y0": "PHY_CONTROL"
        },
        "type": "CMT_TOP_R_UPPER_B"
    },
    "CMT_TOP_R_UPPER_B_X8Y83": {
        "bits": {},
        "grid_x": 8,
        "grid_y": 73,
        "sites": {
            "PHASER_IN_PHY_X0Y6": "PHASER_IN_PHY",
            "PHASER_IN_PHY_X0Y7": "PHASER_IN_PHY",
            "PHASER_OUT_PHY_X0Y6": "PHASER_OUT_PHY",
            "PHASER_OUT_PHY_X0Y7": "PHASER_OUT_PHY",
            "PHASER_REF_X0Y1": "PHASER_REF",
            "PHY_CONTROL_X0Y1": "PHY_CONTROL"
        },
        "type": "CMT_TOP_R_UPPER_B"
    },
    "CMT_TOP_R_UPPER_T_X8Y148": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00020080",
                "frames": 30,
                "offset": 0,
                "words": 101
            }
        },
        "grid_x": 8,
        "grid_y": 8,
        "sites": {
            "PLLE2_ADV_X0Y2": "PLLE2_ADV"
        },
        "type": "CMT_TOP_R_UPPER_T"
    },
    "CMT_TOP_R_UPPER_T_X8Y44": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00400080",
                "frames": 30,
                "offset": 0,
                "words": 101
            }
        },
        "grid_x": 8,
        "grid_y": 112,
        "sites": {
            "PLLE2_ADV_X0Y0": "PLLE2_ADV"
        },
        "type": "CMT_TOP_R_UPPER_T"
    },
    "CMT_TOP_R_UPPER_T_X8Y96": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00000080",
                "frames": 30,
                "offset": 0,
                "words": 101
            }
        },
        "grid_x": 8,
        "grid_y": 60,
        "sites": {
            "PLLE2_ADV_X0Y1": "PLLE2_ADV"
        },
        "type": "CMT_TOP_R_UPPER_T"
    },
    "DSP_L_X34Y0": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00401100",
                "frames": 28,
                "offset": 0,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 155,
        "sites": {
            "DSP48_X1Y0": "DSP48E1",
            "DSP48_X1Y1": "DSP48E1",
            "TIEOFF_X35Y0": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y10": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00401100",
                "frames": 28,
                "offset": 20,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 145,
        "sites": {
            "DSP48_X1Y4": "DSP48E1",
            "DSP48_X1Y5": "DSP48E1",
            "TIEOFF_X35Y10": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y100": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00021100",
                "frames": 28,
                "offset": 0,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 51,
        "sites": {
            "DSP48_X1Y40": "DSP48E1",
            "DSP48_X1Y41": "DSP48E1",
            "TIEOFF_X35Y100": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y105": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00021100",
                "frames": 28,
                "offset": 10,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 46,
        "sites": {
            "DSP48_X1Y42": "DSP48E1",
            "DSP48_X1Y43": "DSP48E1",
            "TIEOFF_X35Y105": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y110": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00021100",
                "frames": 28,
                "offset": 20,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 41,
        "sites": {
            "DSP48_X1Y44": "DSP48E1",
            "DSP48_X1Y45": "DSP48E1",
            "TIEOFF_X35Y110": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y115": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00021100",
                "frames": 28,
                "offset": 30,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 36,
        "sites": {
            "DSP48_X1Y46": "DSP48E1",
            "DSP48_X1Y47": "DSP48E1",
            "TIEOFF_X35Y115": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y120": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00021100",
                "frames": 28,
                "offset": 40,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 31,
        "sites": {
            "DSP48_X1Y48": "DSP48E1",
            "DSP48_X1Y49": "DSP48E1",
            "TIEOFF_X35Y120": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y125": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00021100",
                "frames": 28,
                "offset": 51,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 25,
        "sites": {
            "DSP48_X1Y50": "DSP48E1",
            "DSP48_X1Y51": "DSP48E1",
            "TIEOFF_X35Y125": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y130": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00021100",
                "frames": 28,
                "offset": 61,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 20,
        "sites": {
            "DSP48_X1Y52": "DSP48E1",
            "DSP48_X1Y53": "DSP48E1",
            "TIEOFF_X35Y130": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y135": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00021100",
                "frames": 28,
                "offset": 71,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 15,
        "sites": {
            "DSP48_X1Y54": "DSP48E1",
            "DSP48_X1Y55": "DSP48E1",
            "TIEOFF_X35Y135": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y140": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00021100",
                "frames": 28,
                "offset": 81,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 10,
        "sites": {
            "DSP48_X1Y56": "DSP48E1",
            "DSP48_X1Y57": "DSP48E1",
            "TIEOFF_X35Y140": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y145": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00021100",
                "frames": 28,
                "offset": 91,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 5,
        "sites": {
            "DSP48_X1Y58": "DSP48E1",
            "DSP48_X1Y59": "DSP48E1",
            "TIEOFF_X35Y145": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y15": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00401100",
                "frames": 28,
                "offset": 30,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 140,
        "sites": {
            "DSP48_X1Y6": "DSP48E1",
            "DSP48_X1Y7": "DSP48E1",
            "TIEOFF_X35Y15": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y20": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00401100",
                "frames": 28,
                "offset": 40,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 135,
        "sites": {
            "DSP48_X1Y8": "DSP48E1",
            "DSP48_X1Y9": "DSP48E1",
            "TIEOFF_X35Y20": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y25": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00401100",
                "frames": 28,
                "offset": 51,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 129,
        "sites": {
            "DSP48_X1Y10": "DSP48E1",
            "DSP48_X1Y11": "DSP48E1",
            "TIEOFF_X35Y25": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y30": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00401100",
                "frames": 28,
                "offset": 61,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 124,
        "sites": {
            "DSP48_X1Y12": "DSP48E1",
            "DSP48_X1Y13": "DSP48E1",
            "TIEOFF_X35Y30": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y35": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00401100",
                "frames": 28,
                "offset": 71,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 119,
        "sites": {
            "DSP48_X1Y14": "DSP48E1",
            "DSP48_X1Y15": "DSP48E1",
            "TIEOFF_X35Y35": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y40": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00401100",
                "frames": 28,
                "offset": 81,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 114,
        "sites": {
            "DSP48_X1Y16": "DSP48E1",
            "DSP48_X1Y17": "DSP48E1",
            "TIEOFF_X35Y40": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y45": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00401100",
                "frames": 28,
                "offset": 91,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 109,
        "sites": {
            "DSP48_X1Y18": "DSP48E1",
            "DSP48_X1Y19": "DSP48E1",
            "TIEOFF_X35Y45": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y5": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00401100",
                "frames": 28,
                "offset": 10,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 150,
        "sites": {
            "DSP48_X1Y2": "DSP48E1",
            "DSP48_X1Y3": "DSP48E1",
            "TIEOFF_X35Y5": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y50": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00001100",
                "frames": 28,
                "offset": 0,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 103,
        "sites": {
            "DSP48_X1Y20": "DSP48E1",
            "DSP48_X1Y21": "DSP48E1",
            "TIEOFF_X35Y50": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y55": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00001100",
                "frames": 28,
                "offset": 10,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 98,
        "sites": {
            "DSP48_X1Y22": "DSP48E1",
            "DSP48_X1Y23": "DSP48E1",
            "TIEOFF_X35Y55": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y60": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00001100",
                "frames": 28,
                "offset": 20,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 93,
        "sites": {
            "DSP48_X1Y24": "DSP48E1",
            "DSP48_X1Y25": "DSP48E1",
            "TIEOFF_X35Y60": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y65": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00001100",
                "frames": 28,
                "offset": 30,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 88,
        "sites": {
            "DSP48_X1Y26": "DSP48E1",
            "DSP48_X1Y27": "DSP48E1",
            "TIEOFF_X35Y65": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y70": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00001100",
                "frames": 28,
                "offset": 40,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 83,
        "sites": {
            "DSP48_X1Y28": "DSP48E1",
            "DSP48_X1Y29": "DSP48E1",
            "TIEOFF_X35Y70": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y75": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00001100",
                "frames": 28,
                "offset": 51,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 77,
        "sites": {
            "DSP48_X1Y30": "DSP48E1",
            "DSP48_X1Y31": "DSP48E1",
            "TIEOFF_X35Y75": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y80": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00001100",
                "frames": 28,
                "offset": 61,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 72,
        "sites": {
            "DSP48_X1Y32": "DSP48E1",
            "DSP48_X1Y33": "DSP48E1",
            "TIEOFF_X35Y80": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y85": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00001100",
                "frames": 28,
                "offset": 71,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 67,
        "sites": {
            "DSP48_X1Y34": "DSP48E1",
            "DSP48_X1Y35": "DSP48E1",
            "TIEOFF_X35Y85": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y90": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00001100",
                "frames": 28,
                "offset": 81,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 62,
        "sites": {
            "DSP48_X1Y36": "DSP48E1",
            "DSP48_X1Y37": "DSP48E1",
            "TIEOFF_X35Y90": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_L_X34Y95": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00001100",
                "frames": 28,
                "offset": 91,
                "words": 10
            }
        },
        "grid_x": 86,
        "grid_y": 57,
        "sites": {
            "DSP48_X1Y38": "DSP48E1",
            "DSP48_X1Y39": "DSP48E1",
            "TIEOFF_X35Y95": "TIEOFF"
        },
        "type": "DSP_L"
    },
    "DSP_R_X9Y0": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00400480",
                "frames": 28,
                "offset": 0,
                "words": 10
            }
        },
        "grid_x": 28,
        "grid_y": 155,
        "sites": {
            "DSP48_X0Y0": "DSP48E1",
            "DSP48_X0Y1": "DSP48E1",
            "TIEOFF_X10Y0": "TIEOFF"
        },
        "type": "DSP_R"
    },
    "DSP_R_X9Y10": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00400480",
                "frames": 28,
                "offset": 20,
                "words": 10
            }
        },
        "grid_x": 28,
        "grid_y": 145,
        "sites": {
            "DSP48_X0Y4": "DSP48E1",
            "DSP48_X0Y5": "DSP48E1",
            "TIEOFF_X10Y10": "TIEOFF"
        },
        "type": "DSP_R"
    },
    "DSP_R_X9Y100": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00020480",
                "frames": 28,
                "offset": 0,
                "words": 10
            }
        },
        "grid_x": 28,
        "grid_y": 51,
        "sites": {
            "DSP48_X0Y40": "DSP48E1",
            "DSP48_X0Y41": "DSP48E1",
            "TIEOFF_X10Y100": "TIEOFF"
        },
        "type": "DSP_R"
    },
    "DSP_R_X9Y105": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00020480",
                "frames": 28,
                "offset": 10,
                "words": 10
            }
        },
        "grid_x": 28,
        "grid_y": 46,
        "sites": {
            "DSP48_X0Y42": "DSP48E1",
            "DSP48_X0Y43": "DSP48E1",
            "TIEOFF_X10Y105": "TIEOFF"
        },
        "type": "DSP_R"
    },
    "DSP_R_X9Y110": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00020480",
                "frames": 28,
                "offset": 20,
                "words": 10
            }
        },
        "grid_x": 28,
        "grid_y": 41,
        "sites": {
            "DSP48_X0Y44": "DSP48E1",
            "DSP48_X0Y45": "DSP48E1",
            "TIEOFF_X10Y110": "TIEOFF"
        },
        "type": "DSP_R"
    },
    "DSP_R_X9Y115": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00020480",
                "frames": 28,
                "offset": 30,
                "words": 10
            }
        },
        "grid_x": 28,
        "grid_y": 36,
        "sites": {
            "DSP48_X0Y46": "DSP48E1",
            "DSP48_X0Y47": "DSP48E1",
            "TIEOFF_X10Y115": "TIEOFF"
        },
        "type": "DSP_R"
    },
    "DSP_R_X9Y120": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00020480",
                "frames": 28,
                "offset": 40,
                "words": 10
            }
        },
        "grid_x": 28,
        "grid_y": 31,
        "sites": {
            "DSP48_X0Y48": "DSP48E1",
            "DSP48_X0Y49": "DSP48E1",
            "TIEOFF_X10Y120": "TIEOFF"
        },
        "type": "DSP_R"
    },
    "DSP_R_X9Y125": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00020480",
                "frames": 28,
                "offset": 51,
                "words": 10
            }
        },
        "grid_x": 28,
        "grid_y": 25,
        "sites": {
            "DSP48_X0Y50": "DSP48E1",
            "DSP48_X0Y51": "DSP48E1",
            "TIEOFF_X10Y125": "TIEOFF"
        },
        "type": "DSP_R"
    },
    "DSP_R_X9Y130": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00020480",
                "frames": 28,
                "offset": 61,
                "words": 10
            }
        },
        "grid_x": 28,
        "grid_y": 20,
        "sites": {
            "DSP48_X0Y52": "DSP48E1",
            "DSP48_X0Y53": "DSP48E1",
            "TIEOFF_X10Y130": "TIEOFF"
        },
        "type": "DSP_R"
    },
    "DSP_R_X9Y135": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00020480",
                "frames": 28,
                "offset": 71,
                "words": 10
            }
        },
        "grid_x": 28,
        "grid_y": 15,
        "sites": {
            "DSP48_X0Y54": "DSP48E1",
            "DSP48_X0Y55": "DSP48E1",
            "TIEOFF_X10Y135": "TIEOFF"
        },
        "type": "DSP_R"
    },
    "DSP_R_X9Y140": {
        "bits": {
            "CLB_IO_CLK": {
                "baseaddr": "0x00020480",
                "frames": 28,
                "offset": 81,
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