diff --git a/Info.md b/Info.md
index f509feb..a8ccf42 100644
--- a/Info.md
+++ b/Info.md
@@ -37,7 +37,7 @@
 
 # Details
 
-Last updated on Fri 09 Aug 2019 10:49:28 PM UTC (2019-08-09T22:49:28+00:00).
+Last updated on Fri 09 Aug 2019 11:31:49 PM UTC (2019-08-09T23:31:49+00:00).
 
 Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [e10b7c8](https://github.com/SymbiFlow/prjxray/commit/e10b7c8ff59b0865c8bfd5af4841b90405c1f813).
 
@@ -97,21 +97,21 @@
  * [`8c6097166bf4b43969c49894dc464d1202f19683d7287a63ec709bc867d97105  ./artix7/element_counts.csv`](./artix7/element_counts.csv)
  * [`6864d8edcef442cb129f83b9c5cd27be85d1b4bded8007bbeadcfc70717f8c48  ./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt`](./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt)
  * [`2b18b3806f0e58024469eac1fe11749d04c6b035d2c2eafa7d2f30bf57173fa9  ./artix7/harness/README.md`](./artix7/harness/README.md)
- * [`189a65a8ccea8f891a6eb11024636c57ef76824629fbc70f08173caa21de05c0  ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit)
- * [`5cdb00acf930a418c544ef7d18fd41b0a42808284fcf5e4332923c6a012dfa0a  ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp)
- * [`39236ffb06698077ee3f06edd6d64c0167793cefab4acda71f219a5cf3a20f76  ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
+ * [`d08f84342532952c3f5ec432a194f3ee0631c68f94479b8c1ffbd17a36b1ee89  ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit)
+ * [`1719fd18deb28d3e5015636e773c7f862fddc9ff2ab1f25d91c2308642bb692d  ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp)
+ * [`2dc51404a29d236de3a15000f0f70856fc5a532f4aec92d95304a1ddc55879cd  ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
  * [`fb90ad5fe10750f33d5802e1409ebc2406f7b0adab4bf6ef12b53c0e100b43ea  ./artix7/harness/arty-a7/pmod/design.txt`](./artix7/harness/arty-a7/pmod/design.txt)
- * [`94a9cd37523ad06463f5eeffcac01bc90078fba44ba2a321bad81ec858b46854  ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit)
- * [`dfc8063e0ec0c55d47010c0c2b9eab04f0524cda27c1d4e6c4ede63a1d4b9490  ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp)
- * [`944dcf3cdecc2c0d0a88b14d86e8de13c86a3430bbadc711359fa7939a2ab747  ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
+ * [`ca5bf2cfc9d4cdecdcc947366fb86a473e941055fb309a62df4b844348955f62  ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit)
+ * [`212f49d332cac74c042bfddc9bda1e6ad47ef3307124714d21cb4dce702f2dc2  ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp)
+ * [`69fabcf0457fdc0f79a80f088ba830c8f59719e97609f993198cbf73c90301f9  ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
  * [`884af447661ff1cb653cd8280602c2348435366b35bf2627e2221af34899d191  ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt)
- * [`07957c1776d7cd95382181d955726dbd07e7065364722d905bb671f25d6a3adc  ./artix7/harness/arty-a7/uart/design.bit`](./artix7/harness/arty-a7/uart/design.bit)
- * [`6f548987f5e1539c8b1ef662b84ad960b628fe20983630fd6db7ca20842ca5fb  ./artix7/harness/arty-a7/uart/design.dcp`](./artix7/harness/arty-a7/uart/design.dcp)
- * [`62586079b9ffd917ff5a5d4edcae802b161a7ed4f6af1c776731dcd10c87d096  ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json)
+ * [`87bb1877c43352d47c0e57408b6da49a85a56faf8c371bcb1759de7f2574a6cd  ./artix7/harness/arty-a7/uart/design.bit`](./artix7/harness/arty-a7/uart/design.bit)
+ * [`90c66d89d1b6e221a04e2965a9b2dbc7c8cdab4b76d1c042d9d173712f7ef17a  ./artix7/harness/arty-a7/uart/design.dcp`](./artix7/harness/arty-a7/uart/design.dcp)
+ * [`559876ebf78b9a26fd75533f10080f7f897a637e5610ddef4b6fc8336bdb4704  ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json)
  * [`0583aa7502ee7a0303510c524f5500d8e1b9598aa26016d3d0e4e9623bf8ab8d  ./artix7/harness/arty-a7/uart/design.txt`](./artix7/harness/arty-a7/uart/design.txt)
- * [`4f590875a7851c6d036ab171421b12100f517af74229ad47d8e21fdb6e09b09e  ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
- * [`0e48014931ae9a6010d6023b2a6e07e13ecf206be1076197b881161e67ced596  ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
- * [`9bc42fedabb2f8ca69d0431b5e9c22f20c09b8fa5313dd252d0c32c32b6ad80b  ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
+ * [`b5b4d788d492d465add3f64d772055e6d6050f09b70be25a02aef1463457bb23  ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
+ * [`9999fedf8801ba549238c7d3baf6244693a34d1f7e77a308a6b4cc1195b4ffbb  ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
+ * [`7f97aec3d4804cd11a1e46a51e1f5da8cf4107701deb0708da1132369bda583c  ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
  * [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689  ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt)
  * [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d  ./artix7/mask_bram_l.block_ram.db`](./artix7/mask_bram_l.block_ram.db)
  * [`30b4cfe8b60ccde4423a0bd0d7ad5242bea58d54abf5d15601dd3f390465e821  ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)
diff --git a/artix7/harness/arty-a7/pmod/design.bit b/artix7/harness/arty-a7/pmod/design.bit
index 2b1a531..0901074 100644
--- a/artix7/harness/arty-a7/pmod/design.bit
+++ b/artix7/harness/arty-a7/pmod/design.bit
Binary files differ
diff --git a/artix7/harness/arty-a7/pmod/design.dcp b/artix7/harness/arty-a7/pmod/design.dcp
index 1a35df9..7d4ad1c 100644
--- a/artix7/harness/arty-a7/pmod/design.dcp
+++ b/artix7/harness/arty-a7/pmod/design.dcp
Binary files differ
diff --git a/artix7/harness/arty-a7/pmod/design.json b/artix7/harness/arty-a7/pmod/design.json
index cdbcec2..c2fca1c 100644
--- a/artix7/harness/arty-a7/pmod/design.json
+++ b/artix7/harness/arty-a7/pmod/design.json
@@ -887,7 +887,7 @@
         "CLK_HROW_TOP_R_X60Y130.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_R_CK_GCLK0",
         "CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK0_ACTIVE",
         "CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK0_ACTIVE",
-        "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_ACTIVE",
+        "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_USED",
         "INT_L_X0Y10.IMUX_L34.SS2END1",
         "INT_L_X0Y10.SL1BEG1.SR1END1",
         "INT_L_X0Y100.LVB_L0.LV_L18",
@@ -1060,107 +1060,121 @@
         "INT_R_X1Y112.WR1BEG_S0.NE6END3",
         "INT_R_X1Y116.WW2BEG2.NN6END3",
         "INT_R_X23Y46.IMUX24.SE2END0",
-        "LIOB33_SING_X0Y99.IOB_Y1.IN_ONLY",
+        "LIOB33_SING_X0Y99.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_SING_X0Y99.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_SING_X0Y99.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_SING_X0Y99.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_SING_X0Y99.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_SING_X0Y99.IOB_Y1.SLEW.FAST",
-        "LIOB33_SING_X0Y99.IOB_Y1.ZINV_D",
+        "LIOB33_X0Y3.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y3.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y3.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y3.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y3.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y3.IOB_Y0.SLEW.SLOW",
+        "LIOB33_X0Y3.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y3.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y3.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y3.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y3.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y3.IOB_Y1.SLEW.SLOW",
-        "LIOB33_X0Y43.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP",
-        "LIOB33_X0Y43.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "LIOB33_X0Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "LIOB33_X0Y43.IOB_Y1.PULLTYPE.PULLDOWN",
-        "LIOB33_X0Y43.IOB_Y1.SLEW.FAST",
+        "LIOB33_X0Y5.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y5.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y5.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y5.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y5.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y5.IOB_Y0.SLEW.SLOW",
+        "LIOB33_X0Y5.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y5.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y5.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y5.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y5.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y5.IOB_Y1.SLEW.SLOW",
-        "LIOB33_X0Y51.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y51.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y51.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y51.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y51.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y51.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y51.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y51.IOB_Y0.ZINV_D",
-        "LIOB33_X0Y51.IOB_Y1.IN_ONLY",
+        "LIOB33_X0Y51.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y51.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y51.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y51.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y51.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y51.IOB_Y1.SLEW.FAST",
-        "LIOB33_X0Y51.IOB_Y1.ZINV_D",
-        "LIOB33_X0Y53.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y53.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y53.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y53.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y53.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y53.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y53.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y53.IOB_Y0.ZINV_D",
-        "LIOB33_X0Y53.IOB_Y1.IN_ONLY",
+        "LIOB33_X0Y53.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y53.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y53.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y53.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y53.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y53.IOB_Y1.SLEW.FAST",
-        "LIOB33_X0Y53.IOB_Y1.ZINV_D",
+        "LIOB33_X0Y7.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y7.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y7.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y7.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y7.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y7.IOB_Y0.SLEW.SLOW",
+        "LIOB33_X0Y7.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y7.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y7.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y7.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y7.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y7.IOB_Y1.SLEW.SLOW",
-        "LIOB33_X0Y75.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y75.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y75.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y75.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y75.IOB_Y0.ZINV_D",
-        "LIOB33_X0Y75.IOB_Y1.IN_ONLY",
+        "LIOB33_X0Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y75.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y75.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y75.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y75.IOB_Y1.SLEW.FAST",
-        "LIOB33_X0Y75.IOB_Y1.ZINV_D",
-        "LIOB33_X0Y77.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y77.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y77.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y77.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y77.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y77.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y77.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y77.IOB_Y0.ZINV_D",
-        "LIOB33_X0Y77.IOB_Y1.IN_ONLY",
+        "LIOB33_X0Y77.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y77.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y77.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y77.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y77.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y77.IOB_Y1.SLEW.FAST",
-        "LIOB33_X0Y77.IOB_Y1.ZINV_D",
+        "LIOB33_X0Y9.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y9.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y9.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y9.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y9.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y9.IOB_Y0.SLEW.SLOW",
+        "LIOB33_X0Y9.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y9.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y9.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y9.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y9.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y9.IOB_Y1.SLEW.SLOW"
+        "LIOI3_SING_X0Y99.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_SING_X0Y99.ILOGIC_Y1.ZINV_D",
+        "LIOI3_TBYTESRC_X0Y7.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_TBYTESRC_X0Y7.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_TBYTESRC_X0Y7.OLOGIC_Y0.OMUX.D1",
+        "LIOI3_TBYTESRC_X0Y7.OLOGIC_Y0.OQUSED",
+        "LIOI3_TBYTESRC_X0Y7.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_TBYTESRC_X0Y7.OLOGIC_Y1.OMUX.D1",
+        "LIOI3_TBYTESRC_X0Y7.OLOGIC_Y1.OQUSED",
+        "LIOI3_TBYTESRC_X0Y7.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y3.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y3.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y3.OLOGIC_Y0.OMUX.D1",
+        "LIOI3_X0Y3.OLOGIC_Y0.OQUSED",
+        "LIOI3_X0Y3.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y3.OLOGIC_Y1.OMUX.D1",
+        "LIOI3_X0Y3.OLOGIC_Y1.OQUSED",
+        "LIOI3_X0Y3.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y5.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y5.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y5.OLOGIC_Y0.OMUX.D1",
+        "LIOI3_X0Y5.OLOGIC_Y0.OQUSED",
+        "LIOI3_X0Y5.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y5.OLOGIC_Y1.OMUX.D1",
+        "LIOI3_X0Y5.OLOGIC_Y1.OQUSED",
+        "LIOI3_X0Y5.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y51.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y51.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y51.ILOGIC_Y0.ZINV_D",
+        "LIOI3_X0Y51.ILOGIC_Y1.ZINV_D",
+        "LIOI3_X0Y53.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y53.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y53.ILOGIC_Y0.ZINV_D",
+        "LIOI3_X0Y53.ILOGIC_Y1.ZINV_D",
+        "LIOI3_X0Y75.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y75.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y75.ILOGIC_Y0.ZINV_D",
+        "LIOI3_X0Y75.ILOGIC_Y1.ZINV_D",
+        "LIOI3_X0Y77.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y77.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y77.ILOGIC_Y0.ZINV_D",
+        "LIOI3_X0Y77.ILOGIC_Y1.ZINV_D",
+        "LIOI3_X0Y9.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y9.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y9.OLOGIC_Y0.OMUX.D1",
+        "LIOI3_X0Y9.OLOGIC_Y0.OQUSED",
+        "LIOI3_X0Y9.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y9.OLOGIC_Y1.OMUX.D1",
+        "LIOI3_X0Y9.OLOGIC_Y1.OQUSED",
+        "LIOI3_X0Y9.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF"
     ]
 }
diff --git a/artix7/harness/arty-a7/swbut/design.bit b/artix7/harness/arty-a7/swbut/design.bit
index c187ad7..2d48da1 100644
--- a/artix7/harness/arty-a7/swbut/design.bit
+++ b/artix7/harness/arty-a7/swbut/design.bit
Binary files differ
diff --git a/artix7/harness/arty-a7/swbut/design.dcp b/artix7/harness/arty-a7/swbut/design.dcp
index 21cc5af..603e070 100644
--- a/artix7/harness/arty-a7/swbut/design.dcp
+++ b/artix7/harness/arty-a7/swbut/design.dcp
Binary files differ
diff --git a/artix7/harness/arty-a7/swbut/design.json b/artix7/harness/arty-a7/swbut/design.json
index 14f632f..e37e72e 100644
--- a/artix7/harness/arty-a7/swbut/design.json
+++ b/artix7/harness/arty-a7/swbut/design.json
@@ -721,8 +721,9 @@
         "CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK16_ACTIVE",
         "CLK_HROW_TOP_R_X60Y78.CLK_HROW_TOP_R_CK_BUFG_CASCO0.CLK_HROW_CK_IN_R0",
         "HCLK_CMT_L_X106Y78.HCLK_CMT_CCIO0_ACTIVE",
+        "HCLK_CMT_L_X106Y78.HCLK_CMT_CCIO0_USED",
         "HCLK_CMT_L_X106Y78.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0",
-        "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_ACTIVE",
+        "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_USED",
         "INT_L_X0Y1.IMUX_L34.SL1END1",
         "INT_L_X0Y102.NN2BEG2.NN6END2",
         "INT_L_X0Y104.EE2BEG2.NN2END2",
@@ -844,125 +845,139 @@
         "INT_R_X43Y61.IMUX34.SR1BEG_S0",
         "INT_R_X43Y61.SR1BEG_S0.WW4END_S0_0",
         "INT_R_X43Y63.SS6BEG0.SE6END0",
+        "LIOB33_X0Y1.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y1.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y1.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y1.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y1.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y1.IOB_Y0.SLEW.SLOW",
+        "LIOB33_X0Y1.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y1.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y1.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y1.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y1.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y1.IOB_Y1.SLEW.SLOW",
-        "LIOB33_X0Y121.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y121.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y121.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y121.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y121.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y121.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y121.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y121.IOB_Y0.ZINV_D",
-        "LIOB33_X0Y121.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "LIOB33_X0Y121.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "LIOB33_X0Y121.IOB_Y1.PULLTYPE.PULLDOWN",
-        "LIOB33_X0Y121.IOB_Y1.SLEW.FAST",
-        "LIOB33_X0Y123.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y123.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y123.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y123.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y123.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y123.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y123.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y123.IOB_Y0.ZINV_D",
-        "LIOB33_X0Y123.IOB_Y1.IN_ONLY",
+        "LIOB33_X0Y123.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y123.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y123.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y123.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y123.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y123.IOB_Y1.SLEW.FAST",
-        "LIOB33_X0Y123.IOB_Y1.ZINV_D",
-        "LIOB33_X0Y125.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y125.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y125.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y125.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y125.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y125.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y125.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y125.IOB_Y0.ZINV_D",
-        "LIOB33_X0Y125.IOB_Y1.IN_ONLY",
+        "LIOB33_X0Y125.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y125.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y125.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y125.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y125.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y125.IOB_Y1.SLEW.FAST",
-        "LIOB33_X0Y125.IOB_Y1.ZINV_D",
-        "LIOB33_X0Y127.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y127.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y127.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y127.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y127.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y127.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y127.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y127.IOB_Y0.ZINV_D",
-        "LIOB33_X0Y127.IOB_Y1.IN_ONLY",
+        "LIOB33_X0Y127.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y127.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y127.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y127.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y127.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y127.IOB_Y1.SLEW.FAST",
-        "LIOB33_X0Y127.IOB_Y1.ZINV_D",
-        "LIOB33_X0Y137.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "LIOB33_X0Y137.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "LIOB33_X0Y137.IOB_Y0.PULLTYPE.PULLDOWN",
-        "LIOB33_X0Y137.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y137.IOB_Y1.IN_ONLY",
+        "LIOB33_X0Y137.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y137.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y137.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y137.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y137.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y137.IOB_Y1.SLEW.FAST",
-        "LIOB33_X0Y137.IOB_Y1.ZINV_D",
-        "LIOB33_X0Y43.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP",
-        "LIOB33_X0Y43.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "LIOB33_X0Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "LIOB33_X0Y43.IOB_Y1.PULLTYPE.PULLDOWN",
-        "LIOB33_X0Y43.IOB_Y1.SLEW.FAST",
+        "LIOI3_TBYTETERM_X0Y137.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_TBYTETERM_X0Y137.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_TBYTETERM_X0Y137.ILOGIC_Y1.ZINV_D",
+        "LIOI3_X0Y1.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y1.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y1.OLOGIC_Y0.OMUX.D1",
+        "LIOI3_X0Y1.OLOGIC_Y0.OQUSED",
+        "LIOI3_X0Y1.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y1.OLOGIC_Y1.OMUX.D1",
+        "LIOI3_X0Y1.OLOGIC_Y1.OQUSED",
+        "LIOI3_X0Y1.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y121.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y121.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y121.ILOGIC_Y0.ZINV_D",
+        "LIOI3_X0Y123.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y123.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y123.ILOGIC_Y0.ZINV_D",
+        "LIOI3_X0Y123.ILOGIC_Y1.ZINV_D",
+        "LIOI3_X0Y125.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y125.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y125.ILOGIC_Y0.ZINV_D",
+        "LIOI3_X0Y125.ILOGIC_Y1.ZINV_D",
+        "LIOI3_X0Y127.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y127.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y127.ILOGIC_Y0.ZINV_D",
+        "LIOI3_X0Y127.ILOGIC_Y1.ZINV_D",
+        "RIOB33_SING_X43Y50.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "RIOB33_SING_X43Y50.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "RIOB33_SING_X43Y50.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "RIOB33_SING_X43Y50.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "RIOB33_SING_X43Y50.IOB_Y0.PULLTYPE.NONE",
-        "RIOB33_SING_X43Y50.IOB_Y0.SLEW.SLOW",
+        "RIOB33_X43Y51.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "RIOB33_X43Y51.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "RIOB33_X43Y51.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "RIOB33_X43Y51.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "RIOB33_X43Y51.IOB_Y0.PULLTYPE.NONE",
-        "RIOB33_X43Y51.IOB_Y0.SLEW.SLOW",
+        "RIOB33_X43Y51.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "RIOB33_X43Y51.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "RIOB33_X43Y51.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "RIOB33_X43Y51.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "RIOB33_X43Y51.IOB_Y1.PULLTYPE.NONE",
-        "RIOB33_X43Y51.IOB_Y1.SLEW.SLOW",
-        "RIOB33_X43Y55.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "RIOB33_X43Y55.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "RIOB33_X43Y55.IOB_Y0.PULLTYPE.PULLDOWN",
-        "RIOB33_X43Y55.IOB_Y0.SLEW.FAST",
+        "RIOB33_X43Y55.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "RIOB33_X43Y55.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "RIOB33_X43Y55.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "RIOB33_X43Y55.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "RIOB33_X43Y55.IOB_Y1.PULLTYPE.NONE",
-        "RIOB33_X43Y55.IOB_Y1.SLEW.SLOW",
+        "RIOB33_X43Y57.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "RIOB33_X43Y57.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "RIOB33_X43Y57.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "RIOB33_X43Y57.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "RIOB33_X43Y57.IOB_Y0.PULLTYPE.NONE",
-        "RIOB33_X43Y57.IOB_Y0.SLEW.SLOW",
-        "RIOB33_X43Y57.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "RIOB33_X43Y57.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "RIOB33_X43Y57.IOB_Y1.PULLTYPE.PULLDOWN",
-        "RIOB33_X43Y57.IOB_Y1.SLEW.FAST",
-        "RIOB33_X43Y61.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "RIOB33_X43Y61.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "RIOB33_X43Y61.IOB_Y0.PULLTYPE.PULLDOWN",
-        "RIOB33_X43Y61.IOB_Y0.SLEW.FAST",
+        "RIOB33_X43Y61.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "RIOB33_X43Y61.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "RIOB33_X43Y61.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "RIOB33_X43Y61.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "RIOB33_X43Y61.IOB_Y1.PULLTYPE.NONE",
-        "RIOB33_X43Y61.IOB_Y1.SLEW.SLOW",
-        "RIOB33_X43Y75.IOB_Y0.IN_ONLY",
+        "RIOB33_X43Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "RIOB33_X43Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "RIOB33_X43Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "RIOB33_X43Y75.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "RIOB33_X43Y75.IOB_Y0.PULLTYPE.NONE",
-        "RIOB33_X43Y75.IOB_Y0.SLEW.FAST",
-        "RIOB33_X43Y75.IOB_Y0.ZINV_D",
-        "RIOB33_X43Y75.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "RIOB33_X43Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "RIOB33_X43Y75.IOB_Y1.PULLTYPE.PULLDOWN",
-        "RIOB33_X43Y75.IOB_Y1.SLEW.FAST"
+        "RIOI3_SING_X43Y50.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_SING_X43Y50.OLOGIC_Y0.OMUX.D1",
+        "RIOI3_SING_X43Y50.OLOGIC_Y0.OQUSED",
+        "RIOI3_SING_X43Y50.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "RIOI3_TBYTESRC_X43Y57.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_TBYTESRC_X43Y57.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_TBYTESRC_X43Y57.OLOGIC_Y0.OMUX.D1",
+        "RIOI3_TBYTESRC_X43Y57.OLOGIC_Y0.OQUSED",
+        "RIOI3_TBYTESRC_X43Y57.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "RIOI3_X43Y51.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y51.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y51.OLOGIC_Y0.OMUX.D1",
+        "RIOI3_X43Y51.OLOGIC_Y0.OQUSED",
+        "RIOI3_X43Y51.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "RIOI3_X43Y51.OLOGIC_Y1.OMUX.D1",
+        "RIOI3_X43Y51.OLOGIC_Y1.OQUSED",
+        "RIOI3_X43Y51.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "RIOI3_X43Y55.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y55.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y55.OLOGIC_Y1.OMUX.D1",
+        "RIOI3_X43Y55.OLOGIC_Y1.OQUSED",
+        "RIOI3_X43Y55.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "RIOI3_X43Y61.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y61.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y61.OLOGIC_Y1.OMUX.D1",
+        "RIOI3_X43Y61.OLOGIC_Y1.OQUSED",
+        "RIOI3_X43Y61.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "RIOI3_X43Y75.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y75.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y75.ILOGIC_Y0.ZINV_D"
     ]
 }
diff --git a/artix7/harness/arty-a7/uart/design.bit b/artix7/harness/arty-a7/uart/design.bit
index a7182fe..c1f3543 100644
--- a/artix7/harness/arty-a7/uart/design.bit
+++ b/artix7/harness/arty-a7/uart/design.bit
Binary files differ
diff --git a/artix7/harness/arty-a7/uart/design.dcp b/artix7/harness/arty-a7/uart/design.dcp
index 0236696..14f9477 100644
--- a/artix7/harness/arty-a7/uart/design.dcp
+++ b/artix7/harness/arty-a7/uart/design.dcp
Binary files differ
diff --git a/artix7/harness/arty-a7/uart/design.json b/artix7/harness/arty-a7/uart/design.json
index 70ef5f0..5c6d939 100644
--- a/artix7/harness/arty-a7/uart/design.json
+++ b/artix7/harness/arty-a7/uart/design.json
@@ -304,8 +304,9 @@
         "CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK16_ACTIVE",
         "CLK_HROW_TOP_R_X60Y78.CLK_HROW_TOP_R_CK_BUFG_CASCO0.CLK_HROW_CK_IN_R0",
         "HCLK_CMT_L_X106Y78.HCLK_CMT_CCIO0_ACTIVE",
+        "HCLK_CMT_L_X106Y78.HCLK_CMT_CCIO0_USED",
         "HCLK_CMT_L_X106Y78.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0",
-        "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_ACTIVE",
+        "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_USED",
         "INT_L_X0Y1.IMUX_L34.SL1END1",
         "INT_L_X0Y102.EE2BEG2.SE2END2",
         "INT_L_X0Y103.SW2BEG2.SE6END2",
@@ -339,56 +340,58 @@
         "INT_R_X43Y68.NR1BEG0.LOGIC_OUTS18",
         "INT_R_X43Y69.LV0.NR1END0",
         "INT_R_X43Y87.LH0.LV18",
-        "LIOB33_X0Y1.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "LIOB33_X0Y1.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "LIOB33_X0Y1.IOB_Y0.PULLTYPE.PULLDOWN",
-        "LIOB33_X0Y1.IOB_Y0.SLEW.FAST",
+        "LIOB33_X0Y1.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y1.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y1.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y1.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y1.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y1.IOB_Y1.SLEW.SLOW",
-        "LIOB33_X0Y111.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "LIOB33_X0Y111.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "LIOB33_X0Y111.IOB_Y0.PULLTYPE.PULLDOWN",
-        "LIOB33_X0Y111.IOB_Y0.SLEW.FAST",
+        "LIOB33_X0Y111.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y111.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y111.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y111.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y111.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y111.IOB_Y1.SLEW.SLOW",
-        "LIOB33_X0Y121.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "LIOB33_X0Y121.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "LIOB33_X0Y121.IOB_Y0.PULLTYPE.PULLDOWN",
-        "LIOB33_X0Y121.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y121.IOB_Y1.IN_ONLY",
+        "LIOB33_X0Y121.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y121.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y121.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y121.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y121.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y121.IOB_Y1.SLEW.FAST",
-        "LIOB33_X0Y121.IOB_Y1.ZINV_D",
-        "LIOB33_X0Y43.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP",
-        "LIOB33_X0Y43.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "LIOB33_X0Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "LIOB33_X0Y43.IOB_Y1.PULLTYPE.PULLDOWN",
-        "LIOB33_X0Y43.IOB_Y1.SLEW.FAST",
-        "RIOB33_X43Y67.IOB_Y0.IN_ONLY",
+        "LIOI3_X0Y1.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y1.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y1.OLOGIC_Y1.OMUX.D1",
+        "LIOI3_X0Y1.OLOGIC_Y1.OQUSED",
+        "LIOI3_X0Y1.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y111.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y111.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y111.OLOGIC_Y1.OMUX.D1",
+        "LIOI3_X0Y111.OLOGIC_Y1.OQUSED",
+        "LIOI3_X0Y111.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y121.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y121.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y121.ILOGIC_Y1.ZINV_D",
+        "RIOB33_X43Y67.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "RIOB33_X43Y67.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "RIOB33_X43Y67.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "RIOB33_X43Y67.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "RIOB33_X43Y67.IOB_Y0.PULLTYPE.NONE",
-        "RIOB33_X43Y67.IOB_Y0.SLEW.FAST",
-        "RIOB33_X43Y67.IOB_Y0.ZINV_D",
-        "RIOB33_X43Y67.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "RIOB33_X43Y67.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "RIOB33_X43Y67.IOB_Y1.PULLTYPE.PULLDOWN",
-        "RIOB33_X43Y67.IOB_Y1.SLEW.FAST",
-        "RIOB33_X43Y75.IOB_Y0.IN_ONLY",
+        "RIOB33_X43Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "RIOB33_X43Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "RIOB33_X43Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "RIOB33_X43Y75.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "RIOB33_X43Y75.IOB_Y0.PULLTYPE.NONE",
-        "RIOB33_X43Y75.IOB_Y0.SLEW.FAST",
-        "RIOB33_X43Y75.IOB_Y0.ZINV_D",
-        "RIOB33_X43Y75.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "RIOB33_X43Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "RIOB33_X43Y75.IOB_Y1.PULLTYPE.PULLDOWN",
-        "RIOB33_X43Y75.IOB_Y1.SLEW.FAST"
+        "RIOI3_X43Y67.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y67.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y67.ILOGIC_Y0.ZINV_D",
+        "RIOI3_X43Y75.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y75.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y75.ILOGIC_Y0.ZINV_D"
     ]
 }
diff --git a/artix7/harness/basys3/swbut/design.bit b/artix7/harness/basys3/swbut/design.bit
index 5e186b6..9d18ca2 100644
--- a/artix7/harness/basys3/swbut/design.bit
+++ b/artix7/harness/basys3/swbut/design.bit
Binary files differ
diff --git a/artix7/harness/basys3/swbut/design.dcp b/artix7/harness/basys3/swbut/design.dcp
index 59ed01a..40dea1b 100644
--- a/artix7/harness/basys3/swbut/design.dcp
+++ b/artix7/harness/basys3/swbut/design.dcp
Binary files differ
diff --git a/artix7/harness/basys3/swbut/design.json b/artix7/harness/basys3/swbut/design.json
index 7856957..ae6598a 100644
--- a/artix7/harness/basys3/swbut/design.json
+++ b/artix7/harness/basys3/swbut/design.json
@@ -3117,8 +3117,9 @@
         "CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK0_ACTIVE",
         "CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK0_ACTIVE",
         "HCLK_CMT_L_X106Y26.HCLK_CMT_CCIO0_ACTIVE",
+        "HCLK_CMT_L_X106Y26.HCLK_CMT_CCIO0_USED",
         "HCLK_CMT_L_X106Y26.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0",
-        "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_ACTIVE",
+        "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_USED",
         "INT_L_X0Y0.IMUX_L34.SS2END1",
         "INT_L_X0Y1.IMUX_L34.WW2END0",
         "INT_L_X0Y10.LV_L0.NR1END0",
@@ -3470,218 +3471,252 @@
         "INT_R_X43Y76.SL1BEG1.ER1END1",
         "INT_R_X43Y87.ER1BEG1.SE6END0",
         "INT_R_X43Y87.IMUX34.WR1END1",
+        "LIOB33_SING_X0Y0.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_SING_X0Y0.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_SING_X0Y0.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_SING_X0Y0.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_SING_X0Y0.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_SING_X0Y0.IOB_Y0.SLEW.SLOW",
+        "LIOB33_X0Y1.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y1.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y1.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y1.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y1.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y1.IOB_Y0.SLEW.SLOW",
+        "LIOB33_X0Y1.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y1.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y1.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y1.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y1.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y1.IOB_Y1.SLEW.SLOW",
-        "LIOB33_X0Y11.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y11.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y11.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y11.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y11.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y11.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y11.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y11.IOB_Y0.ZINV_D",
-        "LIOB33_X0Y11.IOB_Y1.IN_ONLY",
+        "LIOB33_X0Y11.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y11.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y11.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y11.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y11.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y11.IOB_Y1.SLEW.FAST",
-        "LIOB33_X0Y11.IOB_Y1.ZINV_D",
-        "LIOB33_X0Y111.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y111.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y111.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y111.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y111.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y111.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y111.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y111.IOB_Y0.ZINV_D",
+        "LIOB33_X0Y111.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y111.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y111.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y111.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y111.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y111.IOB_Y1.SLEW.SLOW",
+        "LIOB33_X0Y17.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y17.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y17.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y17.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y17.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y17.IOB_Y0.SLEW.SLOW",
-        "LIOB33_X0Y17.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "LIOB33_X0Y17.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "LIOB33_X0Y17.IOB_Y1.PULLTYPE.PULLDOWN",
-        "LIOB33_X0Y17.IOB_Y1.SLEW.FAST",
+        "LIOB33_X0Y19.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y19.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y19.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y19.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y19.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y19.IOB_Y0.SLEW.SLOW",
+        "LIOB33_X0Y19.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y19.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y19.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y19.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y19.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y19.IOB_Y1.SLEW.SLOW",
+        "LIOB33_X0Y3.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y3.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y3.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y3.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y3.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y3.IOB_Y0.SLEW.SLOW",
+        "LIOB33_X0Y3.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y3.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y3.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y3.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y3.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y3.IOB_Y1.SLEW.SLOW",
-        "LIOB33_X0Y43.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP",
-        "LIOB33_X0Y43.IOB_Y0.SLEW.FAST",
+        "LIOB33_X0Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "LIOB33_X0Y43.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "LIOB33_X0Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "LIOB33_X0Y43.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "LIOB33_X0Y43.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y43.IOB_Y1.SLEW.SLOW",
-        "LIOB33_X0Y5.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y5.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y5.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y5.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y5.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y5.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y5.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y5.IOB_Y0.ZINV_D",
-        "LIOB33_X0Y5.IOB_Y1.IN_ONLY",
+        "LIOB33_X0Y5.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y5.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y5.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y5.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y5.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y5.IOB_Y1.SLEW.FAST",
-        "LIOB33_X0Y5.IOB_Y1.ZINV_D",
-        "LIOB33_X0Y7.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y7.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y7.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y7.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y7.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y7.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y7.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y7.IOB_Y0.ZINV_D",
-        "LIOB33_X0Y7.IOB_Y1.IN_ONLY",
+        "LIOB33_X0Y7.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y7.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y7.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y7.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y7.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y7.IOB_Y1.SLEW.FAST",
-        "LIOB33_X0Y7.IOB_Y1.ZINV_D",
-        "LIOB33_X0Y9.IOB_Y0.IN_ONLY",
+        "LIOB33_X0Y9.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y9.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y9.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y9.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y9.IOB_Y0.PULLTYPE.NONE",
-        "LIOB33_X0Y9.IOB_Y0.SLEW.FAST",
-        "LIOB33_X0Y9.IOB_Y0.ZINV_D",
-        "LIOB33_X0Y9.IOB_Y1.IN_ONLY",
+        "LIOB33_X0Y9.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "LIOB33_X0Y9.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "LIOB33_X0Y9.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "LIOB33_X0Y9.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "LIOB33_X0Y9.IOB_Y1.PULLTYPE.NONE",
-        "LIOB33_X0Y9.IOB_Y1.SLEW.FAST",
-        "LIOB33_X0Y9.IOB_Y1.ZINV_D",
-        "RIOB33_X43Y25.IOB_Y0.IN_ONLY",
+        "LIOI3_SING_X0Y0.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_SING_X0Y0.OLOGIC_Y0.OMUX.D1",
+        "LIOI3_SING_X0Y0.OLOGIC_Y0.OQUSED",
+        "LIOI3_SING_X0Y0.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_TBYTESRC_X0Y19.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_TBYTESRC_X0Y19.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_TBYTESRC_X0Y19.OLOGIC_Y0.OMUX.D1",
+        "LIOI3_TBYTESRC_X0Y19.OLOGIC_Y0.OQUSED",
+        "LIOI3_TBYTESRC_X0Y19.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_TBYTESRC_X0Y19.OLOGIC_Y1.OMUX.D1",
+        "LIOI3_TBYTESRC_X0Y19.OLOGIC_Y1.OQUSED",
+        "LIOI3_TBYTESRC_X0Y19.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_TBYTESRC_X0Y43.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_TBYTESRC_X0Y43.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_TBYTESRC_X0Y43.OLOGIC_Y1.OMUX.D1",
+        "LIOI3_TBYTESRC_X0Y43.OLOGIC_Y1.OQUSED",
+        "LIOI3_TBYTESRC_X0Y43.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_TBYTESRC_X0Y7.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_TBYTESRC_X0Y7.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_TBYTESRC_X0Y7.ILOGIC_Y0.ZINV_D",
+        "LIOI3_TBYTESRC_X0Y7.ILOGIC_Y1.ZINV_D",
+        "LIOI3_X0Y1.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y1.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y1.OLOGIC_Y0.OMUX.D1",
+        "LIOI3_X0Y1.OLOGIC_Y0.OQUSED",
+        "LIOI3_X0Y1.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y1.OLOGIC_Y1.OMUX.D1",
+        "LIOI3_X0Y1.OLOGIC_Y1.OQUSED",
+        "LIOI3_X0Y1.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y11.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y11.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y11.ILOGIC_Y0.ZINV_D",
+        "LIOI3_X0Y11.ILOGIC_Y1.ZINV_D",
+        "LIOI3_X0Y111.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y111.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y111.ILOGIC_Y0.ZINV_D",
+        "LIOI3_X0Y111.OLOGIC_Y1.OMUX.D1",
+        "LIOI3_X0Y111.OLOGIC_Y1.OQUSED",
+        "LIOI3_X0Y111.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y17.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y17.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y17.OLOGIC_Y0.OMUX.D1",
+        "LIOI3_X0Y17.OLOGIC_Y0.OQUSED",
+        "LIOI3_X0Y17.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y3.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y3.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y3.OLOGIC_Y0.OMUX.D1",
+        "LIOI3_X0Y3.OLOGIC_Y0.OQUSED",
+        "LIOI3_X0Y3.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y3.OLOGIC_Y1.OMUX.D1",
+        "LIOI3_X0Y3.OLOGIC_Y1.OQUSED",
+        "LIOI3_X0Y3.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "LIOI3_X0Y5.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y5.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y5.ILOGIC_Y0.ZINV_D",
+        "LIOI3_X0Y5.ILOGIC_Y1.ZINV_D",
+        "LIOI3_X0Y9.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y9.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "LIOI3_X0Y9.ILOGIC_Y0.ZINV_D",
+        "LIOI3_X0Y9.ILOGIC_Y1.ZINV_D",
+        "RIOB33_X43Y25.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "RIOB33_X43Y25.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "RIOB33_X43Y25.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "RIOB33_X43Y25.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "RIOB33_X43Y25.IOB_Y0.PULLTYPE.NONE",
-        "RIOB33_X43Y25.IOB_Y0.SLEW.FAST",
-        "RIOB33_X43Y25.IOB_Y0.ZINV_D",
-        "RIOB33_X43Y25.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "RIOB33_X43Y25.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "RIOB33_X43Y25.IOB_Y1.PULLTYPE.PULLDOWN",
-        "RIOB33_X43Y25.IOB_Y1.SLEW.FAST",
+        "RIOB33_X43Y31.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "RIOB33_X43Y31.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "RIOB33_X43Y31.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "RIOB33_X43Y31.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "RIOB33_X43Y31.IOB_Y0.PULLTYPE.NONE",
-        "RIOB33_X43Y31.IOB_Y0.SLEW.SLOW",
-        "RIOB33_X43Y31.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "RIOB33_X43Y31.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "RIOB33_X43Y31.IOB_Y1.PULLTYPE.PULLDOWN",
-        "RIOB33_X43Y31.IOB_Y1.SLEW.FAST",
+        "RIOB33_X43Y37.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "RIOB33_X43Y37.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "RIOB33_X43Y37.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "RIOB33_X43Y37.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "RIOB33_X43Y37.IOB_Y0.PULLTYPE.NONE",
-        "RIOB33_X43Y37.IOB_Y0.SLEW.SLOW",
+        "RIOB33_X43Y37.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "RIOB33_X43Y37.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "RIOB33_X43Y37.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "RIOB33_X43Y37.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "RIOB33_X43Y37.IOB_Y1.PULLTYPE.NONE",
-        "RIOB33_X43Y37.IOB_Y1.SLEW.SLOW",
-        "RIOB33_X43Y39.IOB_Y0.IN_ONLY",
+        "RIOB33_X43Y39.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "RIOB33_X43Y39.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "RIOB33_X43Y39.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "RIOB33_X43Y39.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "RIOB33_X43Y39.IOB_Y0.PULLTYPE.NONE",
-        "RIOB33_X43Y39.IOB_Y0.SLEW.FAST",
-        "RIOB33_X43Y39.IOB_Y0.ZINV_D",
-        "RIOB33_X43Y39.IOB_Y1.IN_ONLY",
+        "RIOB33_X43Y39.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "RIOB33_X43Y39.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "RIOB33_X43Y39.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "RIOB33_X43Y39.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "RIOB33_X43Y39.IOB_Y1.PULLTYPE.NONE",
-        "RIOB33_X43Y39.IOB_Y1.SLEW.FAST",
-        "RIOB33_X43Y39.IOB_Y1.ZINV_D",
-        "RIOB33_X43Y43.IOB_Y0.IN_ONLY",
+        "RIOB33_X43Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "RIOB33_X43Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "RIOB33_X43Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "RIOB33_X43Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "RIOB33_X43Y43.IOB_Y0.PULLTYPE.NONE",
-        "RIOB33_X43Y43.IOB_Y0.SLEW.FAST",
-        "RIOB33_X43Y43.IOB_Y0.ZINV_D",
-        "RIOB33_X43Y43.IOB_Y1.IN_ONLY",
+        "RIOB33_X43Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "RIOB33_X43Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "RIOB33_X43Y43.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "RIOB33_X43Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "RIOB33_X43Y43.IOB_Y1.PULLTYPE.NONE",
-        "RIOB33_X43Y43.IOB_Y1.SLEW.FAST",
-        "RIOB33_X43Y43.IOB_Y1.ZINV_D",
-        "RIOB33_X43Y45.IOB_Y0.IN_ONLY",
+        "RIOB33_X43Y45.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "RIOB33_X43Y45.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "RIOB33_X43Y45.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "RIOB33_X43Y45.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "RIOB33_X43Y45.IOB_Y0.PULLTYPE.NONE",
-        "RIOB33_X43Y45.IOB_Y0.SLEW.FAST",
-        "RIOB33_X43Y45.IOB_Y0.ZINV_D",
-        "RIOB33_X43Y45.IOB_Y1.IN_ONLY",
+        "RIOB33_X43Y45.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "RIOB33_X43Y45.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "RIOB33_X43Y45.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "RIOB33_X43Y45.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "RIOB33_X43Y45.IOB_Y1.PULLTYPE.NONE",
-        "RIOB33_X43Y45.IOB_Y1.SLEW.FAST",
-        "RIOB33_X43Y45.IOB_Y1.ZINV_D",
-        "RIOB33_X43Y47.IOB_Y0.IN_ONLY",
+        "RIOB33_X43Y47.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "RIOB33_X43Y47.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "RIOB33_X43Y47.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "RIOB33_X43Y47.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "RIOB33_X43Y47.IOB_Y0.PULLTYPE.NONE",
-        "RIOB33_X43Y47.IOB_Y0.SLEW.FAST",
-        "RIOB33_X43Y47.IOB_Y0.ZINV_D",
-        "RIOB33_X43Y47.IOB_Y1.IN_ONLY",
+        "RIOB33_X43Y47.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+        "RIOB33_X43Y47.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
         "RIOB33_X43Y47.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
-        "RIOB33_X43Y47.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
         "RIOB33_X43Y47.IOB_Y1.PULLTYPE.NONE",
-        "RIOB33_X43Y47.IOB_Y1.SLEW.FAST",
-        "RIOB33_X43Y47.IOB_Y1.ZINV_D",
-        "RIOB33_X43Y61.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "RIOB33_X43Y61.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "RIOB33_X43Y61.IOB_Y0.PULLTYPE.PULLDOWN",
-        "RIOB33_X43Y61.IOB_Y0.SLEW.FAST",
+        "RIOB33_X43Y61.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "RIOB33_X43Y61.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "RIOB33_X43Y61.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "RIOB33_X43Y61.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "RIOB33_X43Y61.IOB_Y1.PULLTYPE.NONE",
-        "RIOB33_X43Y61.IOB_Y1.SLEW.SLOW",
+        "RIOB33_X43Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "RIOB33_X43Y75.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "RIOB33_X43Y75.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "RIOB33_X43Y75.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
         "RIOB33_X43Y75.IOB_Y0.PULLTYPE.NONE",
-        "RIOB33_X43Y75.IOB_Y0.SLEW.SLOW",
+        "RIOB33_X43Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "RIOB33_X43Y75.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "RIOB33_X43Y75.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "RIOB33_X43Y75.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "RIOB33_X43Y75.IOB_Y1.PULLTYPE.NONE",
-        "RIOB33_X43Y75.IOB_Y1.SLEW.SLOW",
-        "RIOB33_X43Y87.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+        "RIOB33_X43Y87.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
         "RIOB33_X43Y87.IOB_Y0.PULLTYPE.PULLDOWN",
-        "RIOB33_X43Y87.IOB_Y0.SLEW.FAST",
+        "RIOB33_X43Y87.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
         "RIOB33_X43Y87.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
-        "RIOB33_X43Y87.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
-        "RIOB33_X43Y87.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
         "RIOB33_X43Y87.IOB_Y1.PULLTYPE.NONE",
-        "RIOB33_X43Y87.IOB_Y1.SLEW.SLOW"
+        "RIOI3_TBYTESRC_X43Y31.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_TBYTESRC_X43Y31.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_TBYTESRC_X43Y31.OLOGIC_Y0.OMUX.D1",
+        "RIOI3_TBYTESRC_X43Y31.OLOGIC_Y0.OQUSED",
+        "RIOI3_TBYTESRC_X43Y31.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "RIOI3_TBYTESRC_X43Y43.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_TBYTESRC_X43Y43.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_TBYTESRC_X43Y43.ILOGIC_Y0.ZINV_D",
+        "RIOI3_TBYTESRC_X43Y43.ILOGIC_Y1.ZINV_D",
+        "RIOI3_TBYTETERM_X43Y37.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_TBYTETERM_X43Y37.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_TBYTETERM_X43Y37.OLOGIC_Y0.OMUX.D1",
+        "RIOI3_TBYTETERM_X43Y37.OLOGIC_Y0.OQUSED",
+        "RIOI3_TBYTETERM_X43Y37.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "RIOI3_TBYTETERM_X43Y37.OLOGIC_Y1.OMUX.D1",
+        "RIOI3_TBYTETERM_X43Y37.OLOGIC_Y1.OQUSED",
+        "RIOI3_TBYTETERM_X43Y37.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "RIOI3_TBYTETERM_X43Y87.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_TBYTETERM_X43Y87.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_TBYTETERM_X43Y87.OLOGIC_Y1.OMUX.D1",
+        "RIOI3_TBYTETERM_X43Y87.OLOGIC_Y1.OQUSED",
+        "RIOI3_TBYTETERM_X43Y87.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "RIOI3_X43Y25.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y25.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y25.ILOGIC_Y0.ZINV_D",
+        "RIOI3_X43Y39.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y39.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y39.ILOGIC_Y0.ZINV_D",
+        "RIOI3_X43Y39.ILOGIC_Y1.ZINV_D",
+        "RIOI3_X43Y45.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y45.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y45.ILOGIC_Y0.ZINV_D",
+        "RIOI3_X43Y45.ILOGIC_Y1.ZINV_D",
+        "RIOI3_X43Y47.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y47.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y47.ILOGIC_Y0.ZINV_D",
+        "RIOI3_X43Y47.ILOGIC_Y1.ZINV_D",
+        "RIOI3_X43Y61.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y61.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y61.OLOGIC_Y1.OMUX.D1",
+        "RIOI3_X43Y61.OLOGIC_Y1.OQUSED",
+        "RIOI3_X43Y61.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+        "RIOI3_X43Y75.IDELAY_Y0.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y75.IDELAY_Y1.IDELAY_TYPE_FIXED",
+        "RIOI3_X43Y75.OLOGIC_Y0.OMUX.D1",
+        "RIOI3_X43Y75.OLOGIC_Y0.OQUSED",
+        "RIOI3_X43Y75.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+        "RIOI3_X43Y75.OLOGIC_Y1.OMUX.D1",
+        "RIOI3_X43Y75.OLOGIC_Y1.OQUSED",
+        "RIOI3_X43Y75.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF"
     ]
 }