diff --git a/Info.md b/Info.md
index 51eafbe..faf54c0 100644
--- a/Info.md
+++ b/Info.md
@@ -37,7 +37,7 @@
 
 # Details
 
-Last updated on Wed Mar 13 21:42:34 UTC 2019 (2019-03-13T21:42:34+00:00).
+Last updated on Wed Mar 13 22:16:59 UTC 2019 (2019-03-13T22:16:59+00:00).
 
 Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [45a8af8](https://github.com/SymbiFlow/prjxray/commit/45a8af8d71c285e7115112c564e5d46b6c81dd97).
 
@@ -96,7 +96,7 @@
 
  * [`8c6097166bf4b43969c49894dc464d1202f19683d7287a63ec709bc867d97105  ./artix7/element_counts.csv`](./artix7/element_counts.csv)
  * [`6864d8edcef442cb129f83b9c5cd27be85d1b4bded8007bbeadcfc70717f8c48  ./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt`](./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt)
- * [`4c0a815ab8943181331f7aa9ac77655a0a640d9a409a602e4f24f8feb5f905e9  ./artix7/harness/README.md`](./artix7/harness/README.md)
+ * [`3aacff527ff9389f20510c56014b7bc2c54116d9d0d3199216743cfbdd09664d  ./artix7/harness/README.md`](./artix7/harness/README.md)
  * [`8416e8eef29e5defebbd3e45f60baa15cbcc22d66647a8da62ec7c42eff8b521  ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit)
  * [`c98eefb677a5cd469b75223d6ceb0e95f5d331de00291193caed008f33ee746c  ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp)
  * [`13382ee7fffcd88636892517929e7c60a6e82bb63324a4e48414bb16eb81174b  ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
@@ -631,6 +631,11 @@
 Results have checksums;
 
  * [`389d7501980b8d12b5fe58af98158372ac3eaa1f557434f6ad96b7610c1ad378  ./zynq7/element_counts.csv`](./zynq7/element_counts.csv)
+ * [`bfd74012f2b02547e824bac877b790ce12b84694b375205e26cb96b5f517672d  ./zynq7/harness/README.md`](./zynq7/harness/README.md)
+ * [`ef169ec1d698b4f8a6675b33b600af8f7c481f61ebb663deed1ad5923e4a438c  ./zynq7/harness/zybo/swbut/design.bit`](./zynq7/harness/zybo/swbut/design.bit)
+ * [`e0e4b94719fdd010522da34d18ab9466f2938e6a14871696e94f48a5818a31e4  ./zynq7/harness/zybo/swbut/design.dcp`](./zynq7/harness/zybo/swbut/design.dcp)
+ * [`785faee1524045b220751675a2ac5d9c29fb5718a44e854dfd512014ace97e24  ./zynq7/harness/zybo/swbut/design.json`](./zynq7/harness/zybo/swbut/design.json)
+ * [`9315fdbbd691414d1cd31b798b080f53bcfe7fefc735f86f9b4d5f013d14c168  ./zynq7/harness/zybo/swbut/design.txt`](./zynq7/harness/zybo/swbut/design.txt)
  * [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d  ./zynq7/mask_bram_l.block_ram.db`](./zynq7/mask_bram_l.block_ram.db)
  * [`3adab1bc4365599535597dd6366028004dd056a17a3349d328965b23a6a4064a  ./zynq7/mask_bram_l.db`](./zynq7/mask_bram_l.db)
  * [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d  ./zynq7/mask_bram_r.block_ram.db`](./zynq7/mask_bram_r.block_ram.db)
diff --git a/artix7/harness/README.md b/artix7/harness/README.md
index 25ea43b..a13f3b8 100644
--- a/artix7/harness/README.md
+++ b/artix7/harness/README.md
@@ -1,4 +1,4 @@
-# [Harnesses](.)
+# [Artix 7 Harnesses](.)
 
 Current using Project X-Ray requires a bitstream "harness" which connects IO
 into the ROI.
@@ -73,7 +73,7 @@
 Supported boards;
  * [Arty A7-35T](#Arty%20A7-35T)
  * [Basys 3](#Basys%203)
-
+ * [Zybo Z7-10](../../zynq7/harness/README.md#Zybo%2Z7-10)
 
 ## PMOD
 
diff --git a/zynq7/harness/README.md b/zynq7/harness/README.md
new file mode 100644
index 0000000..810d9b4
--- /dev/null
+++ b/zynq7/harness/README.md
@@ -0,0 +1,73 @@
+# [Zynq Harnesses](.)
+
+Current using Project X-Ray requires a bitstream "harness" which connects IO
+into the ROI.
+
+Once you have the "harness" bitstream, you can place and route designs using
+only open source tools despite Project X-Ray still not understand how to
+configure the complete bitstream and IO tiles.
+
+---
+
+# Boards
+
+Currently supported boards are listed below, they are;
+ * [Zybo Z7-10](#Zybo%2Z7-10)
+
+## [Zybo Z7-10](zybo)
+
+ * FPGA Part: `XC7Z010-1CLG400C`
+ * Cost: $USD 199.00
+ * [Buy Zybo Z7 from Digilent](https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board/)
+
+**Only** the Zybo Z7-10 version of the board is currently supported. 
+
+Both the original Zybo and the Zybo Z7-20 are **not** supported.
+
+
+Description from the [Digilent website](https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board/);
+> The Zybo Z7 is a feature-rich, ready-to-use embedded software and digital
+> circuit development board built around the Xilinx Zynq-7000 family. This is
+> the second generation update to the popular Zybo that was released in 2012.
+> The Zynq family is based on the Xilinx All Programmable System-on-Chip (AP
+> SoC) architecture, which tightly integrates a dual-core ARM Cortex-A9
+> processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic.
+> The Zybo Z7 surrounds the Zynq with a rich set of multimedia and connectivity
+> peripherals to create a formidable single-board computer, even before
+> considering the flexibility and power added by the FPGA. The Zybo Z7's
+> video-capable feature set, including a MIPI CSI-2 compatible Pcam connector,
+> HDMI input, HDMI output, and high DDR3L bandwidth, was chosen to make it an
+> affordable solution for the high end embedded vision applications that Xilinx
+> FPGAs are popular for. Attaching additional hardware is made easy by the Zybo
+> Z7's Pmod connectors, allowing access to Digilent's catalog of over 70 Pmod
+> peripheral boards, including motor controllers, sensors, displays, and more.
+
+Supported harness configurations;
+ * [SWBUT](#swbut)
+
+---
+
+# Configurations
+
+Currently supported boards are listed below, they are;
+ * [SWBUT](#swbut)
+ * [PMOD](#pmod)
+
+## SWBUT
+
+Harness which maps a board's switches, buttons and LEDs into the region of
+interest (plus clock).
+
+Supported boards;
+ * [Arty A7-35T](../../artix7/harness/README.md#Arty%20A7-35T)
+ * [Basys 3](../../artix7/harness/README.md#Basys%203)
+ * [Zybo Z7-10](#Zybo%2Z7-10)
+
+## PMOD
+
+Harness which maps a board's PMOD connectors into the region of interest (plus
+a clock).
+
+Supported boards;
+ * [Arty A7-35T](../../artix7/harness/README.md#Arty%20A7-35T)
+
diff --git a/zynq7/harness/zybo/swbut/design.bit b/zynq7/harness/zybo/swbut/design.bit
new file mode 100644
index 0000000..22fb633
--- /dev/null
+++ b/zynq7/harness/zybo/swbut/design.bit
Binary files differ
diff --git a/zynq7/harness/zybo/swbut/design.dcp b/zynq7/harness/zybo/swbut/design.dcp
new file mode 100644
index 0000000..81cb48d
--- /dev/null
+++ b/zynq7/harness/zybo/swbut/design.dcp
Binary files differ
diff --git a/zynq7/harness/zybo/swbut/design.json b/zynq7/harness/zybo/swbut/design.json
new file mode 100644
index 0000000..f8fa73e
--- /dev/null
+++ b/zynq7/harness/zybo/swbut/design.json
@@ -0,0 +1,296 @@
+{
+    "info": {
+        "GRID_X_MAX": 118,
+        "GRID_X_MIN": 83,
+        "GRID_Y_MAX": 51,
+        "GRID_Y_MIN": 0
+    },
+    "ports": [
+        {
+            "name": "clk",
+            "node": "CLK_HROW_TOP_R_X82Y78/CLK_HROW_CK_BUFHCLK_R0",
+            "pin": "K17",
+            "wire": "HCLK_VBRK_X83Y78/HCLK_VBRK_CK_BUFHCLK0"
+        },
+        {
+            "name": "din[0]",
+            "node": "INT_R_X31Y53/WW2BEG1",
+            "pin": "J15",
+            "wire": "VBRK_X118Y56/VBRK_WW2END1",
+            "wires_outside_roi": [
+                "CMT_FIFO_L_X120Y60/CMT_FIFO_WW2END1_2",
+                "CMT_TOP_L_LOWER_B_X119Y61/CMT_TOP_WW2END1_3",
+                "INT_INTERFACE_L_X30Y53/INT_INTERFACE_WW2END1",
+                "INT_L_X30Y50/NE6BEG1",
+                "INT_L_X30Y50/WW2END0",
+                "INT_L_X30Y53/WW2A1",
+                "INT_R_X31Y50/EE2BEG0",
+                "INT_R_X31Y50/LOGIC_OUTS18",
+                "INT_R_X31Y50/NE6A1",
+                "INT_R_X31Y50/WW2A0",
+                "INT_R_X31Y51/NE6B1",
+                "INT_R_X31Y52/NE6C1",
+                "INT_R_X31Y53/NE6D1",
+                "INT_R_X31Y53/SR1END1",
+                "INT_R_X31Y53/WW2BEG1",
+                "INT_R_X31Y54/NE6E1",
+                "INT_R_X31Y54/NW6END1",
+                "INT_R_X31Y54/SR1BEG1",
+                "IO_INT_INTERFACE_R_X31Y50/INT_INTERFACE_EE2BEG0",
+                "IO_INT_INTERFACE_R_X31Y50/INT_INTERFACE_LOGIC_OUTS18",
+                "IO_INT_INTERFACE_R_X31Y50/INT_INTERFACE_LOGIC_OUTS_B18",
+                "IO_INT_INTERFACE_R_X31Y50/INT_INTERFACE_WW2A0",
+                "IO_INT_INTERFACE_R_X31Y54/INT_INTERFACE_NE4C1",
+                "IO_INT_INTERFACE_R_X31Y54/INT_INTERFACE_NW4END1",
+                "RIOB33_SING_X31Y50/IOB_IBUF0",
+                "RIOI3_SING_X31Y50/IOI_ILOGIC0_O",
+                "RIOI3_SING_X31Y50/IOI_LOGIC_OUTS18_0",
+                "RIOI3_SING_X31Y50/RIOI_I0",
+                "RIOI3_SING_X31Y50/RIOI_IBUF0",
+                "RIOI3_SING_X31Y50/RIOI_ILOGIC0_D",
+                "R_TERM_INT_X125Y53/R_TERM_INT_WW2A0",
+                "R_TERM_INT_X125Y53/TERM_INT_LOGIC_OUTS_L_B18",
+                "R_TERM_INT_X125Y57/R_TERM_INT_NW4END1"
+            ]
+        },
+        {
+            "name": "din[1]",
+            "node": "INT_R_X31Y56/WW2BEG1",
+            "pin": "G15",
+            "wire": "VBRK_X118Y59/VBRK_WW2END1",
+            "wires_outside_roi": [
+                "CMT_FIFO_L_X120Y60/CMT_FIFO_WW2END1_5",
+                "CMT_TOP_L_LOWER_B_X119Y61/CMT_TOP_WW2END1_6",
+                "INT_INTERFACE_L_X30Y56/INT_INTERFACE_WW2END1",
+                "INT_L_X30Y56/WW2A1",
+                "INT_L_X30Y57/ER1BEG1",
+                "INT_L_X30Y57/SW6END0",
+                "INT_R_X31Y56/SL1END1",
+                "INT_R_X31Y56/WW2BEG1",
+                "INT_R_X31Y57/ER1END1",
+                "INT_R_X31Y57/SL1BEG1",
+                "INT_R_X31Y57/SW6E0",
+                "INT_R_X31Y58/SW6D0",
+                "INT_R_X31Y59/SW6C0",
+                "INT_R_X31Y60/SW6B0",
+                "INT_R_X31Y61/LOGIC_OUTS18",
+                "INT_R_X31Y61/SE6BEG0",
+                "INT_R_X31Y61/SW6A0",
+                "IO_INT_INTERFACE_R_X31Y61/INT_INTERFACE_LOGIC_OUTS18",
+                "IO_INT_INTERFACE_R_X31Y61/INT_INTERFACE_LOGIC_OUTS_B18",
+                "IO_INT_INTERFACE_R_X31Y61/INT_INTERFACE_SE4BEG0",
+                "IO_INT_INTERFACE_R_X31Y61/INT_INTERFACE_SW4A0",
+                "RIOB33_X31Y61/IOB_IBUF1",
+                "RIOI3_X31Y61/IOI_ILOGIC1_O",
+                "RIOI3_X31Y61/IOI_LOGIC_OUTS18_0",
+                "RIOI3_X31Y61/RIOI_I1",
+                "RIOI3_X31Y61/RIOI_IBUF1",
+                "RIOI3_X31Y61/RIOI_ILOGIC1_D",
+                "R_TERM_INT_X125Y64/R_TERM_INT_SW4A0",
+                "R_TERM_INT_X125Y64/TERM_INT_LOGIC_OUTS_L_B18"
+            ]
+        },
+        {
+            "name": "din[2]",
+            "node": "INT_R_X31Y59/WW2BEG1",
+            "pin": "K18",
+            "wire": "VBRK_X118Y62/VBRK_WW2END1",
+            "wires_outside_roi": [
+                "CMT_FIFO_L_X120Y60/CMT_FIFO_WW2END1_8",
+                "CMT_TOP_L_LOWER_B_X119Y61/CMT_TOP_WW2END1_9",
+                "HCLK_R_X123Y78/HCLK_LV16",
+                "INT_INTERFACE_L_X30Y59/INT_INTERFACE_WW2END1",
+                "INT_L_X30Y59/WW2A1",
+                "INT_R_X31Y58/LV0",
+                "INT_R_X31Y59/LV1",
+                "INT_R_X31Y59/SS2END1",
+                "INT_R_X31Y59/WW2BEG1",
+                "INT_R_X31Y60/LV2",
+                "INT_R_X31Y60/SS2A1",
+                "INT_R_X31Y61/LV3",
+                "INT_R_X31Y61/SS2BEG1",
+                "INT_R_X31Y61/SS6END1",
+                "INT_R_X31Y62/LV4",
+                "INT_R_X31Y62/SS6E1",
+                "INT_R_X31Y63/LV5",
+                "INT_R_X31Y63/SS6D1",
+                "INT_R_X31Y64/LV6",
+                "INT_R_X31Y64/SS6C1",
+                "INT_R_X31Y65/LV7",
+                "INT_R_X31Y65/SS6B1",
+                "INT_R_X31Y66/LV8",
+                "INT_R_X31Y66/SS6A1",
+                "INT_R_X31Y67/LV9",
+                "INT_R_X31Y67/SS6BEG1",
+                "INT_R_X31Y68/LV10",
+                "INT_R_X31Y69/LV11",
+                "INT_R_X31Y70/LV12",
+                "INT_R_X31Y71/LV13",
+                "INT_R_X31Y72/LV14",
+                "INT_R_X31Y73/LV15",
+                "INT_R_X31Y74/LV16",
+                "INT_R_X31Y75/LOGIC_OUTS18",
+                "INT_R_X31Y75/LV17",
+                "INT_R_X31Y75/NR1BEG0",
+                "INT_R_X31Y76/LV18",
+                "INT_R_X31Y76/NR1END0",
+                "IO_INT_INTERFACE_R_X31Y75/INT_INTERFACE_LOGIC_OUTS18",
+                "IO_INT_INTERFACE_R_X31Y75/INT_INTERFACE_LOGIC_OUTS_B18",
+                "RIOB33_X31Y75/IOB_IBUF1",
+                "RIOI3_X31Y75/IOI_ILOGIC1_O",
+                "RIOI3_X31Y75/IOI_LOGIC_OUTS18_0",
+                "RIOI3_X31Y75/RIOI_I1",
+                "RIOI3_X31Y75/RIOI_IBUF1",
+                "RIOI3_X31Y75/RIOI_ILOGIC1_D",
+                "R_TERM_INT_X125Y79/TERM_INT_LOGIC_OUTS_L_B18"
+            ]
+        },
+        {
+            "name": "din[3]",
+            "node": "INT_R_X31Y62/WW2BEG1",
+            "pin": "K19",
+            "wire": "VBRK_X118Y65/VBRK_WW2END1",
+            "wires_outside_roi": [
+                "CMT_FIFO_L_X120Y60/CMT_FIFO_WW2END1_11",
+                "CMT_TOP_L_LOWER_B_X119Y61/CMT_TOP_WW2END1_12",
+                "HCLK_L_X122Y78/HCLK_LV16",
+                "INT_INTERFACE_L_X30Y62/INT_INTERFACE_WW2END1",
+                "INT_L_X30Y58/LV_L0",
+                "INT_L_X30Y59/LV_L1",
+                "INT_L_X30Y60/LV_L2",
+                "INT_L_X30Y61/LV_L3",
+                "INT_L_X30Y62/LV_L4",
+                "INT_L_X30Y62/WW2A1",
+                "INT_L_X30Y63/LV_L5",
+                "INT_L_X30Y64/LV_L6",
+                "INT_L_X30Y65/LV_L7",
+                "INT_L_X30Y66/LV_L8",
+                "INT_L_X30Y67/LV_L9",
+                "INT_L_X30Y67/SE6BEG1",
+                "INT_L_X30Y68/LV_L10",
+                "INT_L_X30Y69/LV_L11",
+                "INT_L_X30Y70/LV_L12",
+                "INT_L_X30Y71/LV_L13",
+                "INT_L_X30Y72/LV_L14",
+                "INT_L_X30Y73/LV_L15",
+                "INT_L_X30Y74/LV_L16",
+                "INT_L_X30Y75/LV_L17",
+                "INT_L_X30Y76/LV_L18",
+                "INT_L_X30Y76/SW6END0",
+                "INT_R_X31Y62/SL1END1",
+                "INT_R_X31Y62/WW2BEG1",
+                "INT_R_X31Y63/SE6E1",
+                "INT_R_X31Y63/SL1BEG1",
+                "INT_R_X31Y63/SW6END1",
+                "INT_R_X31Y64/SE6D1",
+                "INT_R_X31Y65/SE6C1",
+                "INT_R_X31Y66/SE6B1",
+                "INT_R_X31Y67/SE6A1",
+                "INT_R_X31Y76/SW6E0",
+                "INT_R_X31Y77/SW6D0",
+                "INT_R_X31Y78/SW6C0",
+                "INT_R_X31Y79/SW6B0",
+                "INT_R_X31Y80/LOGIC_OUTS18",
+                "INT_R_X31Y80/SE6BEG0",
+                "INT_R_X31Y80/SW6A0",
+                "IO_INT_INTERFACE_R_X31Y63/INT_INTERFACE_SE4C1",
+                "IO_INT_INTERFACE_R_X31Y63/INT_INTERFACE_SW4END1",
+                "IO_INT_INTERFACE_R_X31Y80/INT_INTERFACE_LOGIC_OUTS18",
+                "IO_INT_INTERFACE_R_X31Y80/INT_INTERFACE_LOGIC_OUTS_B18",
+                "IO_INT_INTERFACE_R_X31Y80/INT_INTERFACE_SE4BEG0",
+                "IO_INT_INTERFACE_R_X31Y80/INT_INTERFACE_SW4A0",
+                "RIOB33_X31Y79/IOB_IBUF0",
+                "RIOI3_X31Y79/IOI_ILOGIC0_O",
+                "RIOI3_X31Y79/IOI_LOGIC_OUTS18_1",
+                "RIOI3_X31Y79/RIOI_I0",
+                "RIOI3_X31Y79/RIOI_IBUF0",
+                "RIOI3_X31Y79/RIOI_ILOGIC0_D",
+                "R_TERM_INT_X125Y66/R_TERM_INT_SW4END1",
+                "R_TERM_INT_X125Y84/R_TERM_INT_SW4A0",
+                "R_TERM_INT_X125Y84/TERM_INT_LOGIC_OUTS_L_B18"
+            ]
+        },
+        {
+            "name": "dout[0]",
+            "node": "INT_R_X29Y81/EE2BEG0",
+            "pin": "H15",
+            "wire": "VBRK_X118Y85/VBRK_EE2BEG0",
+            "wires_outside_roi": [
+                "CMT_FIFO_L_X120Y85/CMT_FIFO_EE2BEG0_6",
+                "CMT_TOP_L_UPPER_B_X119Y83/CMT_TOP_EE2BEG0_6",
+                "INT_INTERFACE_L_X30Y81/INT_INTERFACE_EE2BEG0",
+                "INT_L_X30Y81/EE2A0",
+                "INT_R_X31Y81/EE2END0"
+            ]
+        },
+        {
+            "name": "dout[1]",
+            "node": "INT_R_X29Y84/EE2BEG0",
+            "pin": "E17",
+            "wire": "VBRK_X118Y88/VBRK_EE2BEG0",
+            "wires_outside_roi": [
+                "CMT_FIFO_L_X120Y85/CMT_FIFO_EE2BEG0_9",
+                "CMT_TOP_L_UPPER_B_X119Y83/CMT_TOP_EE2BEG0_9",
+                "INT_INTERFACE_L_X30Y84/INT_INTERFACE_EE2BEG0",
+                "INT_L_X30Y84/EE2A0",
+                "INT_R_X31Y84/EE2END0"
+            ]
+        },
+        {
+            "name": "dout[2]",
+            "node": "INT_R_X29Y87/EE2BEG0",
+            "pin": "M14",
+            "wire": "VBRK_X118Y91/VBRK_EE2BEG0",
+            "wires_outside_roi": [
+                "CMT_FIFO_L_X120Y97/CMT_FIFO_EE2BEG0_0",
+                "CMT_TOP_L_UPPER_T_X119Y96/CMT_TOP_EE2BEG0_0",
+                "INT_INTERFACE_L_X30Y87/INT_INTERFACE_EE2BEG0",
+                "INT_L_X30Y87/EE2A0",
+                "INT_R_X31Y87/EE2END0"
+            ]
+        },
+        {
+            "name": "dout[3]",
+            "node": "INT_R_X29Y90/EE2BEG0",
+            "pin": "M15",
+            "wire": "VBRK_X118Y94/VBRK_EE2BEG0",
+            "wires_outside_roi": [
+                "CMT_FIFO_L_X120Y97/CMT_FIFO_EE2BEG0_3",
+                "CMT_TOP_L_UPPER_T_X119Y96/CMT_TOP_EE2BEG0_3",
+                "INT_INTERFACE_L_X30Y90/INT_INTERFACE_EE2BEG0",
+                "INT_L_X30Y90/EE2A0",
+                "INT_R_X31Y90/EE2END0"
+            ]
+        },
+        {
+            "name": "dout[4]",
+            "node": "INT_R_X29Y93/EE2BEG0",
+            "pin": "D18",
+            "wire": "VBRK_X118Y97/VBRK_EE2BEG0",
+            "wires_outside_roi": [
+                "CMT_FIFO_L_X120Y97/CMT_FIFO_EE2BEG0_6",
+                "CMT_TOP_L_UPPER_T_X119Y96/CMT_TOP_EE2BEG0_6",
+                "INT_INTERFACE_L_X30Y93/INT_INTERFACE_EE2BEG0",
+                "INT_L_X30Y93/EE2A0",
+                "INT_R_X31Y93/EE2END0"
+            ]
+        },
+        {
+            "name": "dout[5]",
+            "node": "INT_R_X29Y96/EE2BEG0",
+            "pin": "G14",
+            "wire": "VBRK_X118Y100/VBRK_EE2BEG0",
+            "wires_outside_roi": [
+                "CMT_FIFO_L_X120Y97/CMT_FIFO_EE2BEG0_9",
+                "CMT_TOP_L_UPPER_T_X119Y96/CMT_TOP_EE2BEG0_9",
+                "INT_INTERFACE_L_X30Y96/INT_INTERFACE_EE2BEG0",
+                "INT_L_X30Y96/EE2A0",
+                "INT_R_X31Y96/EE2END0"
+            ]
+        }
+    ],
+    "required_features": [
+        "",
+        ""
+    ]
+}
diff --git a/zynq7/harness/zybo/swbut/design.txt b/zynq7/harness/zybo/swbut/design.txt
new file mode 100644
index 0000000..7366226
--- /dev/null
+++ b/zynq7/harness/zybo/swbut/design.txt
@@ -0,0 +1,12 @@
+name node pin wire
+clk CLK_HROW_TOP_R_X82Y78/CLK_HROW_CK_BUFHCLK_R0 K17 HCLK_VBRK_X83Y78/HCLK_VBRK_CK_BUFHCLK0
+din[0] INT_R_X31Y53/WW2BEG1 J15 VBRK_X118Y56/VBRK_WW2END1
+din[1] INT_R_X31Y56/WW2BEG1 G15 VBRK_X118Y59/VBRK_WW2END1
+din[2] INT_R_X31Y59/WW2BEG1 K18 VBRK_X118Y62/VBRK_WW2END1
+din[3] INT_R_X31Y62/WW2BEG1 K19 VBRK_X118Y65/VBRK_WW2END1
+dout[0] INT_R_X29Y81/EE2BEG0 H15 VBRK_X118Y85/VBRK_EE2BEG0
+dout[1] INT_R_X29Y84/EE2BEG0 E17 VBRK_X118Y88/VBRK_EE2BEG0
+dout[2] INT_R_X29Y87/EE2BEG0 M14 VBRK_X118Y91/VBRK_EE2BEG0
+dout[3] INT_R_X29Y90/EE2BEG0 M15 VBRK_X118Y94/VBRK_EE2BEG0
+dout[4] INT_R_X29Y93/EE2BEG0 D18 VBRK_X118Y97/VBRK_EE2BEG0
+dout[5] INT_R_X29Y96/EE2BEG0 G14 VBRK_X118Y100/VBRK_EE2BEG0