Updating harness for Artix and Zynq parts based on "Merge pull request #1047 from antmicro/oserdes_minitest".
See [Info File](Info.md) for details.
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
diff --git a/Info.md b/Info.md
index b062bab..a4ec48a 100644
--- a/Info.md
+++ b/Info.md
@@ -37,7 +37,7 @@
# Details
-Last updated on Wed 11 Sep 2019 11:52:52 PM UTC (2019-09-11T23:52:52+00:00).
+Last updated on Thu 12 Sep 2019 01:36:47 AM UTC (2019-09-12T01:36:47+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [6d21194b](https://github.com/SymbiFlow/prjxray/commit/6d21194b569b2e320d7b1c4fe87c8db814a823b1).
@@ -97,24 +97,24 @@
* [`8c6097166bf4b43969c49894dc464d1202f19683d7287a63ec709bc867d97105 ./artix7/element_counts.csv`](./artix7/element_counts.csv)
* [`6864d8edcef442cb129f83b9c5cd27be85d1b4bded8007bbeadcfc70717f8c48 ./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt`](./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt)
* [`2b18b3806f0e58024469eac1fe11749d04c6b035d2c2eafa7d2f30bf57173fa9 ./artix7/harness/README.md`](./artix7/harness/README.md)
- * [`d08f84342532952c3f5ec432a194f3ee0631c68f94479b8c1ffbd17a36b1ee89 ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit)
- * [`1719fd18deb28d3e5015636e773c7f862fddc9ff2ab1f25d91c2308642bb692d ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp)
+ * [`560f255b569fd4798989f45104d4a511b51380418d4ca6fc53201141b36b20aa ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit)
+ * [`1d8a121c3aa3bca7893429cfb08a8748206134271432daa52cdc9d3f5593bda0 ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp)
* [`2dc51404a29d236de3a15000f0f70856fc5a532f4aec92d95304a1ddc55879cd ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
* [`fb90ad5fe10750f33d5802e1409ebc2406f7b0adab4bf6ef12b53c0e100b43ea ./artix7/harness/arty-a7/pmod/design.txt`](./artix7/harness/arty-a7/pmod/design.txt)
- * [`ca5bf2cfc9d4cdecdcc947366fb86a473e941055fb309a62df4b844348955f62 ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit)
- * [`212f49d332cac74c042bfddc9bda1e6ad47ef3307124714d21cb4dce702f2dc2 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp)
+ * [`931c1598b75005a8a8e5b2225cc7454c2c7be451cb907bc4c047cb04db99772d ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit)
+ * [`5d06132c788097344a9bca7040a08dd0e1632e177ed8def1d7445132020cc768 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp)
* [`69fabcf0457fdc0f79a80f088ba830c8f59719e97609f993198cbf73c90301f9 ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
* [`884af447661ff1cb653cd8280602c2348435366b35bf2627e2221af34899d191 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt)
- * [`87bb1877c43352d47c0e57408b6da49a85a56faf8c371bcb1759de7f2574a6cd ./artix7/harness/arty-a7/uart/design.bit`](./artix7/harness/arty-a7/uart/design.bit)
- * [`90c66d89d1b6e221a04e2965a9b2dbc7c8cdab4b76d1c042d9d173712f7ef17a ./artix7/harness/arty-a7/uart/design.dcp`](./artix7/harness/arty-a7/uart/design.dcp)
+ * [`128e73ee026cf2238a35c7e993b845e3551919c90fc77b277635bc5098d59741 ./artix7/harness/arty-a7/uart/design.bit`](./artix7/harness/arty-a7/uart/design.bit)
+ * [`955daed70c5728c13865eddc9bd7001d93183a50c560559a7b6628aa85b1fbbe ./artix7/harness/arty-a7/uart/design.dcp`](./artix7/harness/arty-a7/uart/design.dcp)
* [`559876ebf78b9a26fd75533f10080f7f897a637e5610ddef4b6fc8336bdb4704 ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json)
* [`0583aa7502ee7a0303510c524f5500d8e1b9598aa26016d3d0e4e9623bf8ab8d ./artix7/harness/arty-a7/uart/design.txt`](./artix7/harness/arty-a7/uart/design.txt)
- * [`b5b4d788d492d465add3f64d772055e6d6050f09b70be25a02aef1463457bb23 ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
- * [`9999fedf8801ba549238c7d3baf6244693a34d1f7e77a308a6b4cc1195b4ffbb ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
+ * [`d3109010f8fced3be08e720741a157d08b7042359e84d04bbe677f50cbf10a04 ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
+ * [`abedfa7f2ee5a4dbc51b582ebae62dd20489f745a4a239e49b18ba3e02be019f ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
* [`7f97aec3d4804cd11a1e46a51e1f5da8cf4107701deb0708da1132369bda583c ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
* [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689 ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt)
- * [`29f314aad5ec0a152bf8acecd54583f829a52003051e754c20f8ee8957187cd7 ./artix7/harness/basys3/swbut_50/design.bit`](./artix7/harness/basys3/swbut_50/design.bit)
- * [`c6d41209251db99c2752eef72efec012f1dd41061a4973d89ef69d3d22cbb468 ./artix7/harness/basys3/swbut_50/design.dcp`](./artix7/harness/basys3/swbut_50/design.dcp)
+ * [`3ad62b024991225f1565e84159f2eb59d08e9fc6cf2577ea1698952b5dc0e4ec ./artix7/harness/basys3/swbut_50/design.bit`](./artix7/harness/basys3/swbut_50/design.bit)
+ * [`773fe43b4974ab353bde87e544abb6b541cdcb280de40df76afa96f7fa23db46 ./artix7/harness/basys3/swbut_50/design.dcp`](./artix7/harness/basys3/swbut_50/design.dcp)
* [`3614288b4365a562631a035d9897b58b17755ac477c261598e4eca7fd9e5acda ./artix7/harness/basys3/swbut_50/design.json`](./artix7/harness/basys3/swbut_50/design.json)
* [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689 ./artix7/harness/basys3/swbut_50/design.txt`](./artix7/harness/basys3/swbut_50/design.txt)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./artix7/mask_bram_l.block_ram.db`](./artix7/mask_bram_l.block_ram.db)
@@ -880,9 +880,9 @@
* [`389d7501980b8d12b5fe58af98158372ac3eaa1f557434f6ad96b7610c1ad378 ./zynq7/element_counts.csv`](./zynq7/element_counts.csv)
* [`bfd74012f2b02547e824bac877b790ce12b84694b375205e26cb96b5f517672d ./zynq7/harness/README.md`](./zynq7/harness/README.md)
- * [`ef169ec1d698b4f8a6675b33b600af8f7c481f61ebb663deed1ad5923e4a438c ./zynq7/harness/zybo/swbut/design.bit`](./zynq7/harness/zybo/swbut/design.bit)
- * [`e0e4b94719fdd010522da34d18ab9466f2938e6a14871696e94f48a5818a31e4 ./zynq7/harness/zybo/swbut/design.dcp`](./zynq7/harness/zybo/swbut/design.dcp)
- * [`785faee1524045b220751675a2ac5d9c29fb5718a44e854dfd512014ace97e24 ./zynq7/harness/zybo/swbut/design.json`](./zynq7/harness/zybo/swbut/design.json)
+ * [`71c89f2ff630726ef4daba9c3f7c2e15bd8e6d07dc576bfabdafdde72488a0da ./zynq7/harness/zybo/swbut/design.bit`](./zynq7/harness/zybo/swbut/design.bit)
+ * [`0ffc8577fbaf5ff4db2c3379c2a41b7860056f8dffba2a718d62896f7e7ebb8f ./zynq7/harness/zybo/swbut/design.dcp`](./zynq7/harness/zybo/swbut/design.dcp)
+ * [`329f324b12fc74c14f52f618e37a4e498edf7e3e2c62946152ad1051080530d1 ./zynq7/harness/zybo/swbut/design.json`](./zynq7/harness/zybo/swbut/design.json)
* [`9315fdbbd691414d1cd31b798b080f53bcfe7fefc735f86f9b4d5f013d14c168 ./zynq7/harness/zybo/swbut/design.txt`](./zynq7/harness/zybo/swbut/design.txt)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./zynq7/mask_bram_l.block_ram.db`](./zynq7/mask_bram_l.block_ram.db)
* [`3adab1bc4365599535597dd6366028004dd056a17a3349d328965b23a6a4064a ./zynq7/mask_bram_l.db`](./zynq7/mask_bram_l.db)
diff --git a/artix7/harness/arty-a7/pmod/design.bit b/artix7/harness/arty-a7/pmod/design.bit
index 0901074..a799aeb 100644
--- a/artix7/harness/arty-a7/pmod/design.bit
+++ b/artix7/harness/arty-a7/pmod/design.bit
Binary files differ
diff --git a/artix7/harness/arty-a7/pmod/design.dcp b/artix7/harness/arty-a7/pmod/design.dcp
index 7d4ad1c..ab9b2f6 100644
--- a/artix7/harness/arty-a7/pmod/design.dcp
+++ b/artix7/harness/arty-a7/pmod/design.dcp
Binary files differ
diff --git a/artix7/harness/arty-a7/swbut/design.bit b/artix7/harness/arty-a7/swbut/design.bit
index 2d48da1..e62546e 100644
--- a/artix7/harness/arty-a7/swbut/design.bit
+++ b/artix7/harness/arty-a7/swbut/design.bit
Binary files differ
diff --git a/artix7/harness/arty-a7/swbut/design.dcp b/artix7/harness/arty-a7/swbut/design.dcp
index 603e070..19e7a51 100644
--- a/artix7/harness/arty-a7/swbut/design.dcp
+++ b/artix7/harness/arty-a7/swbut/design.dcp
Binary files differ
diff --git a/artix7/harness/arty-a7/uart/design.bit b/artix7/harness/arty-a7/uart/design.bit
index c1f3543..d1910f4 100644
--- a/artix7/harness/arty-a7/uart/design.bit
+++ b/artix7/harness/arty-a7/uart/design.bit
Binary files differ
diff --git a/artix7/harness/arty-a7/uart/design.dcp b/artix7/harness/arty-a7/uart/design.dcp
index 14f9477..6665f4a 100644
--- a/artix7/harness/arty-a7/uart/design.dcp
+++ b/artix7/harness/arty-a7/uart/design.dcp
Binary files differ
diff --git a/artix7/harness/basys3/swbut/design.bit b/artix7/harness/basys3/swbut/design.bit
index 9d18ca2..0feb5bc 100644
--- a/artix7/harness/basys3/swbut/design.bit
+++ b/artix7/harness/basys3/swbut/design.bit
Binary files differ
diff --git a/artix7/harness/basys3/swbut/design.dcp b/artix7/harness/basys3/swbut/design.dcp
index 40dea1b..705cfe0 100644
--- a/artix7/harness/basys3/swbut/design.dcp
+++ b/artix7/harness/basys3/swbut/design.dcp
Binary files differ
diff --git a/artix7/harness/basys3/swbut_50/design.bit b/artix7/harness/basys3/swbut_50/design.bit
index c571138..17f0697 100644
--- a/artix7/harness/basys3/swbut_50/design.bit
+++ b/artix7/harness/basys3/swbut_50/design.bit
Binary files differ
diff --git a/artix7/harness/basys3/swbut_50/design.dcp b/artix7/harness/basys3/swbut_50/design.dcp
index d75fe02..51d7e15 100644
--- a/artix7/harness/basys3/swbut_50/design.dcp
+++ b/artix7/harness/basys3/swbut_50/design.dcp
Binary files differ
diff --git a/zynq7/harness/zybo/swbut/design.bit b/zynq7/harness/zybo/swbut/design.bit
index 22fb633..e59cc86 100644
--- a/zynq7/harness/zybo/swbut/design.bit
+++ b/zynq7/harness/zybo/swbut/design.bit
Binary files differ
diff --git a/zynq7/harness/zybo/swbut/design.dcp b/zynq7/harness/zybo/swbut/design.dcp
index 81cb48d..e5484bb 100644
--- a/zynq7/harness/zybo/swbut/design.dcp
+++ b/zynq7/harness/zybo/swbut/design.dcp
Binary files differ
diff --git a/zynq7/harness/zybo/swbut/design.json b/zynq7/harness/zybo/swbut/design.json
index f8fa73e..0ecf79f 100644
--- a/zynq7/harness/zybo/swbut/design.json
+++ b/zynq7/harness/zybo/swbut/design.json
@@ -291,6 +291,193 @@
],
"required_features": [
"",
- ""
+ "CFG_CENTER_MID_X67Y32.ALWAYS_ON_PROP1",
+ "CFG_CENTER_MID_X67Y32.ALWAYS_ON_PROP2",
+ "CFG_CENTER_MID_X67Y32.ALWAYS_ON_PROP3",
+ "CLK_BUFG_REBUF_X82Y38.GCLK16_ENABLE_BELOW",
+ "CLK_BUFG_REBUF_X82Y65.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT",
+ "CLK_BUFG_REBUF_X82Y65.GCLK16_ENABLE_ABOVE",
+ "CLK_BUFG_REBUF_X82Y65.GCLK16_ENABLE_BELOW",
+ "CLK_BUFG_REBUF_X82Y90.GCLK16_ENABLE_ABOVE",
+ "CLK_BUFG_TOP_R_X82Y53.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE",
+ "CLK_BUFG_TOP_R_X82Y53.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED",
+ "CLK_BUFG_TOP_R_X82Y53.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0",
+ "CLK_BUFG_TOP_R_X82Y53.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2",
+ "CLK_BUFG_TOP_R_X82Y53.CLK_BUFG_CK_GCLK16.CLK_BUFG_BUFGCTRL0_O",
+ "CLK_HROW_TOP_R_X82Y78.BUFHCE.BUFHCE_X1Y0.IN_USE",
+ "CLK_HROW_TOP_R_X82Y78.BUFHCE.BUFHCE_X1Y0.ZINV_CE",
+ "CLK_HROW_TOP_R_X82Y78.CLK_HROW_CK_IN_R0_ACTIVE",
+ "CLK_HROW_TOP_R_X82Y78.CLK_HROW_CK_MUX_OUT_R0.CLK_HROW_R_CK_GCLK16",
+ "CLK_HROW_TOP_R_X82Y78.CLK_HROW_R_CK_GCLK16_ACTIVE",
+ "CLK_HROW_TOP_R_X82Y78.CLK_HROW_TOP_R_CK_BUFG_CASCO0.CLK_HROW_CK_IN_R0",
+ "HCLK_CMT_L_X119Y78.HCLK_CMT_CCIO0_ACTIVE",
+ "HCLK_CMT_L_X119Y78.HCLK_CMT_CCIO0_USED",
+ "HCLK_CMT_L_X119Y78.HCLK_CMT_CK_BUFHCLK0_USED",
+ "HCLK_CMT_L_X119Y78.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0",
+ "INT_L_X30Y50.NE6BEG1.WW2END0",
+ "INT_L_X30Y53.ER1BEG1.SW2END0",
+ "INT_L_X30Y54.ER1BEG1.SW2END0",
+ "INT_L_X30Y57.ER1BEG1.SW6END0",
+ "INT_L_X30Y62.ER1BEG1.SW2END0",
+ "INT_L_X30Y67.SE6BEG1.LV_L9",
+ "INT_L_X30Y76.LV_L18.SW6END0",
+ "INT_L_X30Y88.NN6BEG0.NW6END0",
+ "INT_L_X30Y94.EE2BEG0.NN6END0",
+ "INT_R_X31Y50.EE2BEG0.LOGIC_OUTS18",
+ "INT_R_X31Y53.IMUX34.ER1END1",
+ "INT_R_X31Y53.WW2BEG1.SR1END1",
+ "INT_R_X31Y54.IMUX34.ER1END1",
+ "INT_R_X31Y54.SR1BEG1.NW6END1",
+ "INT_R_X31Y54.SW2BEG0.SS6END0",
+ "INT_R_X31Y55.SW2BEG0.SS6END0",
+ "INT_R_X31Y56.WW2BEG1.SL1END1",
+ "INT_R_X31Y57.SL1BEG1.ER1END1",
+ "INT_R_X31Y59.WW2BEG1.SS2END1",
+ "INT_R_X31Y60.SS6BEG0.SS6END0",
+ "INT_R_X31Y61.SE6BEG0.LOGIC_OUTS18",
+ "INT_R_X31Y61.SS2BEG1.SS6END1",
+ "INT_R_X31Y61.SS6BEG0.SS6END0",
+ "INT_R_X31Y62.IMUX34.ER1END1",
+ "INT_R_X31Y62.WW2BEG1.SL1END1",
+ "INT_R_X31Y63.SL1BEG1.SW6END1",
+ "INT_R_X31Y63.SW2BEG0.SS6END0",
+ "INT_R_X31Y66.SS6BEG0.SS6END0",
+ "INT_R_X31Y67.SS6BEG0.SS6END0",
+ "INT_R_X31Y67.SS6BEG1.LV9",
+ "INT_R_X31Y69.SS6BEG0.SS6END0",
+ "INT_R_X31Y72.SS6BEG0.SS6END0",
+ "INT_R_X31Y73.SS6BEG0.SS6END0",
+ "INT_R_X31Y75.NR1BEG0.LOGIC_OUTS18",
+ "INT_R_X31Y75.SS6BEG0.SS6END0",
+ "INT_R_X31Y76.LV18.NR1END0",
+ "INT_R_X31Y78.SS6BEG0.SS6END0",
+ "INT_R_X31Y79.SS6BEG0.SS6END0",
+ "INT_R_X31Y80.SE6BEG0.LOGIC_OUTS18",
+ "INT_R_X31Y81.SS6BEG0.EE2END0",
+ "INT_R_X31Y84.NE6BEG0.EE2END0",
+ "INT_R_X31Y84.SS6BEG0.SS6END0",
+ "INT_R_X31Y85.SS6BEG0.SS2END0",
+ "INT_R_X31Y87.SS2BEG0.EE2END0",
+ "INT_R_X31Y90.SS6BEG0.EE2END0",
+ "INT_R_X31Y93.BYP_ALT0.EE2END0",
+ "INT_R_X31Y93.IMUX34.BYP_BOUNCE0",
+ "INT_R_X31Y94.IMUX34.WW2END0",
+ "INT_R_X31Y96.NN2BEG0.EE2END0",
+ "INT_R_X31Y98.NN2BEG0.NN2END0",
+ "INT_R_X31Y99.IMUX34.SR1BEG_S0",
+ "INT_R_X31Y99.SR1BEG_S0.SS2END3",
+ "RIOB33_SING_X31Y50.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+ "RIOB33_SING_X31Y50.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
+ "RIOB33_SING_X31Y50.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_SING_X31Y50.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_SING_X31Y99.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
+ "RIOB33_SING_X31Y99.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_SING_X31Y99.IOB_Y1.PULLTYPE.NONE",
+ "RIOB33_X31Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+ "RIOB33_X31Y43.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
+ "RIOB33_X31Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X31Y43.IOB_Y0.PULLTYPE.PULLUP",
+ "RIOB33_X31Y43.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+ "RIOB33_X31Y43.IOB_Y1.PULLTYPE.PULLDOWN",
+ "RIOB33_X31Y53.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
+ "RIOB33_X31Y53.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X31Y53.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X31Y53.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
+ "RIOB33_X31Y53.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X31Y53.IOB_Y1.PULLTYPE.NONE",
+ "RIOB33_X31Y61.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
+ "RIOB33_X31Y61.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X31Y61.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X31Y61.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+ "RIOB33_X31Y61.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
+ "RIOB33_X31Y61.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X31Y61.IOB_Y1.PULLTYPE.NONE",
+ "RIOB33_X31Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+ "RIOB33_X31Y75.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
+ "RIOB33_X31Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X31Y75.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X31Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+ "RIOB33_X31Y75.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
+ "RIOB33_X31Y75.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X31Y75.IOB_Y1.PULLTYPE.NONE",
+ "RIOB33_X31Y79.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+ "RIOB33_X31Y79.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY",
+ "RIOB33_X31Y79.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X31Y79.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X31Y79.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST",
+ "RIOB33_X31Y79.IOB_Y1.PULLTYPE.PULLDOWN",
+ "RIOB33_X31Y93.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
+ "RIOB33_X31Y93.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X31Y93.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X31Y93.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.SLEW.SLOW",
+ "RIOB33_X31Y93.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X31Y93.IOB_Y1.PULLTYPE.NONE",
+ "RIOI3_SING_X31Y50.IDELAY_Y0.IDELAY_TYPE_FIXED",
+ "RIOI3_SING_X31Y50.ILOGIC_Y0.ZINV_D",
+ "RIOI3_SING_X31Y99.IDELAY_Y1.IDELAY_TYPE_FIXED",
+ "RIOI3_SING_X31Y99.OLOGIC_Y1.OMUX.D1",
+ "RIOI3_SING_X31Y99.OLOGIC_Y1.OQUSED",
+ "RIOI3_SING_X31Y99.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOI3_TBYTESRC_X31Y93.IDELAY_Y0.IDELAY_TYPE_FIXED",
+ "RIOI3_TBYTESRC_X31Y93.IDELAY_Y1.IDELAY_TYPE_FIXED",
+ "RIOI3_TBYTESRC_X31Y93.OLOGIC_Y0.OMUX.D1",
+ "RIOI3_TBYTESRC_X31Y93.OLOGIC_Y0.OQUSED",
+ "RIOI3_TBYTESRC_X31Y93.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOI3_TBYTESRC_X31Y93.OLOGIC_Y1.OMUX.D1",
+ "RIOI3_TBYTESRC_X31Y93.OLOGIC_Y1.OQUSED",
+ "RIOI3_TBYTESRC_X31Y93.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOI3_X31Y53.IDELAY_Y0.IDELAY_TYPE_FIXED",
+ "RIOI3_X31Y53.IDELAY_Y1.IDELAY_TYPE_FIXED",
+ "RIOI3_X31Y53.OLOGIC_Y0.OMUX.D1",
+ "RIOI3_X31Y53.OLOGIC_Y0.OQUSED",
+ "RIOI3_X31Y53.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOI3_X31Y53.OLOGIC_Y1.OMUX.D1",
+ "RIOI3_X31Y53.OLOGIC_Y1.OQUSED",
+ "RIOI3_X31Y53.OLOGIC_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOI3_X31Y61.IDELAY_Y0.IDELAY_TYPE_FIXED",
+ "RIOI3_X31Y61.IDELAY_Y1.IDELAY_TYPE_FIXED",
+ "RIOI3_X31Y61.ILOGIC_Y1.ZINV_D",
+ "RIOI3_X31Y61.OLOGIC_Y0.OMUX.D1",
+ "RIOI3_X31Y61.OLOGIC_Y0.OQUSED",
+ "RIOI3_X31Y61.OLOGIC_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOI3_X31Y75.IDELAY_Y0.IDELAY_TYPE_FIXED",
+ "RIOI3_X31Y75.IDELAY_Y1.IDELAY_TYPE_FIXED",
+ "RIOI3_X31Y75.ILOGIC_Y0.ZINV_D",
+ "RIOI3_X31Y75.ILOGIC_Y1.ZINV_D",
+ "RIOI3_X31Y79.IDELAY_Y0.IDELAY_TYPE_FIXED",
+ "RIOI3_X31Y79.IDELAY_Y1.IDELAY_TYPE_FIXED",
+ "RIOI3_X31Y79.ILOGIC_Y0.ZINV_D"
]
}
