Updating all based on "Merge pull request #1562 from dnltz/WIP/dnltz/new_parts"
See [Info File](Info.md) for details.
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
diff --git a/Info.md b/Info.md
index 222d9bd..39282df 100644
--- a/Info.md
+++ b/Info.md
@@ -37,20 +37,20 @@
# Details
-Last updated on Thu 11 Mar 2021 07:29:56 PM UTC (2021-03-11T19:29:56+00:00).
+Last updated on Sat 20 Mar 2021 10:41:40 PM UTC (2021-03-20T22:41:40+00:00).
-Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [0d9418a9](https://github.com/SymbiFlow/prjxray/commit/0d9418a908dafecae1d38418d3a0e2d2b2416ea0).
+Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [086f9a17](https://github.com/SymbiFlow/prjxray/commit/086f9a1714e96323947d7c2526f5e4b97063e79f).
Latest commit was;
```
-commit 0d9418a908dafecae1d38418d3a0e2d2b2416ea0
-Merge: 0ddf03b8 2ccada20
+commit 086f9a1714e96323947d7c2526f5e4b97063e79f
+Merge: a0dbca4d 772c4280
Author: litghost <537074+litghost@users.noreply.github.com>
-Date: Wed Mar 10 09:07:49 2021 -0800
+Date: Thu Mar 18 13:07:02 2021 -0700
- Merge pull request #1614 from antmicro/add-gtp-ports-attrs-file
+ Merge pull request #1562 from dnltz/WIP/dnltz/new_parts
- gtp: generate attributes and ports files to add to the db
+ Populate all parts
```
@@ -59,7 +59,7 @@
### Settings
-Created using following [settings/artix7.sh (sha256: 00d45bf1672d3460e8d452cda8e747fa713eed629aa086b219162886452013e4)](https://github.com/SymbiFlow/prjxray/blob/0d9418a908dafecae1d38418d3a0e2d2b2416ea0/settings/artix7.sh)
+Created using following [settings/artix7.sh (sha256: 00d45bf1672d3460e8d452cda8e747fa713eed629aa086b219162886452013e4)](https://github.com/SymbiFlow/prjxray/blob/086f9a1714e96323947d7c2526f5e4b97063e79f/settings/artix7.sh)
```shell
#!/bin/bash
# Copyright (C) 2017-2020 The Project X-Ray Authors.
@@ -108,6 +108,8 @@
* [`962b9db76b9e6333b72880fc196a492756f4f5d37dae2fe727c7f6fb6db8e834 ./artix7/cells_data/gtpe2_channel_ports.json`](./artix7/cells_data/gtpe2_channel_ports.json)
* [`0928d105dc294cedc1f19bf61790f81f5adee62f03fcfe4a4d220546d99a2b40 ./artix7/cells_data/gtpe2_common_attrs.json`](./artix7/cells_data/gtpe2_common_attrs.json)
* [`b6c8fbd663d4c7410909f3b7cb0a473d82343e3240810a27e4323ac6220abeb5 ./artix7/cells_data/gtpe2_common_ports.json`](./artix7/cells_data/gtpe2_common_ports.json)
+ * [`5fb7bf32219a5c01b3506c589ef51d3f963762940953501f3382ecca287b96a7 ./artix7/cells_data/pcie_2_1_attrs.json`](./artix7/cells_data/pcie_2_1_attrs.json)
+ * [`83dc2fcb8193af23a4a0145f9d5e6ed836bdc0fca85ea9f0ac2666921da6d57d ./artix7/cells_data/pcie_2_1_ports.json`](./artix7/cells_data/pcie_2_1_ports.json)
* [`d7c598657e5d66095a732b74bfa559253fba959bf53706cfd464635f07ae6b9b ./artix7/element_counts.csv`](./artix7/element_counts.csv)
* [`b5a8a5e4aa788f9a8b17a0b0879814d9e8f38f6cbb65740fb537935fb028296a ./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt`](./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt)
* [`2b18b3806f0e58024469eac1fe11749d04c6b035d2c2eafa7d2f30bf57173fa9 ./artix7/harness/README.md`](./artix7/harness/README.md)
@@ -128,12 +130,12 @@
* [`ada2b826fc1b0c687ab4194f95b025460db0fbad8fe24a69ed600b1983b51ea8 ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
* [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689 ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt)
* [`e5ebd51966bcfddb9b04078203231810df64f5afd3e3a608a5fb8fdc7d3c3304 ./artix7/mapping/devices.yaml`](./artix7/mapping/devices.yaml)
- * [`9a63d519dcfee4016602553490a53c00a2fbc8cd0355ed201cfa3545650f6ce4 ./artix7/mapping/parts.yaml`](./artix7/mapping/parts.yaml)
+ * [`4c35219ab79439746b75f73482a8bfa1ad9b39315ad8838a7fbd22a4ff292db5 ./artix7/mapping/parts.yaml`](./artix7/mapping/parts.yaml)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./artix7/mask_bram_l.block_ram.db`](./artix7/mask_bram_l.block_ram.db)
- * [`6d74881ba45dd2b17f442764722e3bb570fc879b973f32a778d0cbd583b513e1 ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)
+ * [`c4781022ded947376e750b8e652f7b69009c3e07f246da17b2987d29b82b3890 ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_bram_l.origin_info.db`](./artix7/mask_bram_l.origin_info.db)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./artix7/mask_bram_r.block_ram.db`](./artix7/mask_bram_r.block_ram.db)
- * [`6d74881ba45dd2b17f442764722e3bb570fc879b973f32a778d0cbd583b513e1 ./artix7/mask_bram_r.db`](./artix7/mask_bram_r.db)
+ * [`c4781022ded947376e750b8e652f7b69009c3e07f246da17b2987d29b82b3890 ./artix7/mask_bram_r.db`](./artix7/mask_bram_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_bram_r.origin_info.db`](./artix7/mask_bram_r.origin_info.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./artix7/mask_clbll_l.db`](./artix7/mask_clbll_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_clbll_l.origin_info.db`](./artix7/mask_clbll_l.origin_info.db)
@@ -148,9 +150,9 @@
* [`82a9c646430a3ce5a1881c715b6396a2840bdf46514d8508e2f210003d0642f3 ./artix7/mask_clk_bufg_top_r.db`](./artix7/mask_clk_bufg_top_r.db)
* [`8065dd1943464a57b58323eb09fa9d34148e09a3cd0d7d750dc31166ac25164a ./artix7/mask_clk_hrow_bot_r.db`](./artix7/mask_clk_hrow_bot_r.db)
* [`8065dd1943464a57b58323eb09fa9d34148e09a3cd0d7d750dc31166ac25164a ./artix7/mask_clk_hrow_top_r.db`](./artix7/mask_clk_hrow_top_r.db)
- * [`dcaa8c88264f90fdf779f30ef36b4317d95f15de932ef1db94426835db2a3c72 ./artix7/mask_dsp_l.db`](./artix7/mask_dsp_l.db)
+ * [`4a97dd3f29a2459744d6c1adbbb4e987e3c078f7a72cfdc205f08dee54da2417 ./artix7/mask_dsp_l.db`](./artix7/mask_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_dsp_l.origin_info.db`](./artix7/mask_dsp_l.origin_info.db)
- * [`0ea9fc3ec271604c27b850f84ec3811fd366c0897dfb8728bdb96d7f170a8a27 ./artix7/mask_dsp_r.db`](./artix7/mask_dsp_r.db)
+ * [`4dfa6da23a38cad4cf2880126b4f498c0747393d5a33e1c78bd043be23a5b9ec ./artix7/mask_dsp_r.db`](./artix7/mask_dsp_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_dsp_r.origin_info.db`](./artix7/mask_dsp_r.origin_info.db)
* [`9e159b25b2f3eadcc2fa0bcd2f3c25dc3acf2083d3a57368968204d70d5f8ae4 ./artix7/mask_gtp_channel_0.db`](./artix7/mask_gtp_channel_0.db)
* [`d9ee40b7a46372b89ebc17de5800266a25489c6c2f3f9495d29f7916c3c6909c ./artix7/mask_gtp_channel_0_mid_left.db`](./artix7/mask_gtp_channel_0_mid_left.db)
@@ -348,9 +350,9 @@
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
* [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./artix7/segbits_hclk_r.origin_info.db`](./artix7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
- * [`c5e7dd396db511c4e0e8bf8b45e7632ae70a1589c028405f1e08e855314ffe53 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
+ * [`b22ca76720ece3dc6e248c248dae14c7dea0238be178be1de4633d47cd7e47b4 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
- * [`dc42429ae7563134fe7874b0aad2a563363496ff16a8423aa104321559fd82e0 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
+ * [`963e8ad2eaf35bf6cc10cf5114923a5341fb9e6599a5ba12c90d80e1e0e41564 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
* [`432e956da48016ba647631ff91975eb501f98e3961330bdaa35c686d780300d9 ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db)
* [`606867ace72307cf773d819f40696862301419fda3d6d748746d2bfc58579731 ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db)
* [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff ./artix7/segbits_lioi3.db`](./artix7/segbits_lioi3.db)
@@ -363,8 +365,8 @@
* [`f2a3c7410f318cb6906c49916104864894d0d2daba55a2173dc2033c8037bae7 ./artix7/segbits_pcie_bot.origin_info.db`](./artix7/segbits_pcie_bot.origin_info.db)
* [`0eb48fb48373d46d4ec033976696223e34fc16a000cad8e067e2bebf76f0a8df ./artix7/segbits_pcie_int_interface_l.db`](./artix7/segbits_pcie_int_interface_l.db)
* [`ed58243250118f8cb3e7378e04b9861aa580db4991b7026b3edc439e0cfe0a77 ./artix7/segbits_pcie_int_interface_l.origin_info.db`](./artix7/segbits_pcie_int_interface_l.origin_info.db)
- * [`0bc32fce572935289e5ac7b10c95fb96b78418270016546d42ab11276285343e ./artix7/segbits_pcie_int_interface_r.db`](./artix7/segbits_pcie_int_interface_r.db)
- * [`ad36811e5e38c911473f2c3a6b805e7bb1f6186408bb6740c0dd906754762e3b ./artix7/segbits_pcie_int_interface_r.origin_info.db`](./artix7/segbits_pcie_int_interface_r.origin_info.db)
+ * [`7b882f20ee52b683ba2330b06af4f94bce3ca19083ebd9018dd7d17295fc07c6 ./artix7/segbits_pcie_int_interface_r.db`](./artix7/segbits_pcie_int_interface_r.db)
+ * [`35f4243cc3f53193771a4d045e5df0370cd023d3722a995861c1881d924e30fe ./artix7/segbits_pcie_int_interface_r.origin_info.db`](./artix7/segbits_pcie_int_interface_r.origin_info.db)
* [`327992e6b38faaeb0ddf948e8b42b8ce082a662f83f0dac14ebac901b3aeb909 ./artix7/segbits_riob33.db`](./artix7/segbits_riob33.db)
* [`f5b3e67f5a0afcd5351a35efd5c3a9e74254347c4268259de6ef4fa9c7bbfaeb ./artix7/segbits_riob33.origin_info.db`](./artix7/segbits_riob33.origin_info.db)
* [`712cc4b66ff35ea6033cb76e41d8dde1225857836f4b799834925ab5c3e8575a ./artix7/segbits_rioi3.db`](./artix7/segbits_rioi3.db)
@@ -602,43 +604,280 @@
* [`3f202fefbd0f36761f08eb58737a42754c65c965968174421df0374198e31daa ./artix7/xc7a100tcsg324-1/package_pins.csv`](./artix7/xc7a100tcsg324-1/package_pins.csv)
* [`277906907e43846ac8a52115983cd0ece673b2310d8d10c9b2253d6537bf1a02 ./artix7/xc7a100tcsg324-1/part.json`](./artix7/xc7a100tcsg324-1/part.json)
* [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tcsg324-1/part.yaml`](./artix7/xc7a100tcsg324-1/part.yaml)
+ * [`3f202fefbd0f36761f08eb58737a42754c65c965968174421df0374198e31daa ./artix7/xc7a100tcsg324-2/package_pins.csv`](./artix7/xc7a100tcsg324-2/package_pins.csv)
+ * [`277906907e43846ac8a52115983cd0ece673b2310d8d10c9b2253d6537bf1a02 ./artix7/xc7a100tcsg324-2/part.json`](./artix7/xc7a100tcsg324-2/part.json)
+ * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tcsg324-2/part.yaml`](./artix7/xc7a100tcsg324-2/part.yaml)
+ * [`3f202fefbd0f36761f08eb58737a42754c65c965968174421df0374198e31daa ./artix7/xc7a100tcsg324-2L/package_pins.csv`](./artix7/xc7a100tcsg324-2L/package_pins.csv)
+ * [`277906907e43846ac8a52115983cd0ece673b2310d8d10c9b2253d6537bf1a02 ./artix7/xc7a100tcsg324-2L/part.json`](./artix7/xc7a100tcsg324-2L/part.json)
+ * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tcsg324-2L/part.yaml`](./artix7/xc7a100tcsg324-2L/part.yaml)
+ * [`3f202fefbd0f36761f08eb58737a42754c65c965968174421df0374198e31daa ./artix7/xc7a100tcsg324-3/package_pins.csv`](./artix7/xc7a100tcsg324-3/package_pins.csv)
+ * [`277906907e43846ac8a52115983cd0ece673b2310d8d10c9b2253d6537bf1a02 ./artix7/xc7a100tcsg324-3/part.json`](./artix7/xc7a100tcsg324-3/part.json)
+ * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tcsg324-3/part.yaml`](./artix7/xc7a100tcsg324-3/part.yaml)
+ * [`3e1de5edac7fdd8122041afb2b611902653f8c62dc2da1518b94ed6378e36f26 ./artix7/xc7a100tfgg484-1/package_pins.csv`](./artix7/xc7a100tfgg484-1/package_pins.csv)
+ * [`78909bda2084de19e6095258ab1b1ad549c2db376abdd8699235a7bdc3aa19fb ./artix7/xc7a100tfgg484-1/part.json`](./artix7/xc7a100tfgg484-1/part.json)
+ * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tfgg484-1/part.yaml`](./artix7/xc7a100tfgg484-1/part.yaml)
* [`3e1de5edac7fdd8122041afb2b611902653f8c62dc2da1518b94ed6378e36f26 ./artix7/xc7a100tfgg484-2/package_pins.csv`](./artix7/xc7a100tfgg484-2/package_pins.csv)
* [`78909bda2084de19e6095258ab1b1ad549c2db376abdd8699235a7bdc3aa19fb ./artix7/xc7a100tfgg484-2/part.json`](./artix7/xc7a100tfgg484-2/part.json)
* [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tfgg484-2/part.yaml`](./artix7/xc7a100tfgg484-2/part.yaml)
+ * [`3e1de5edac7fdd8122041afb2b611902653f8c62dc2da1518b94ed6378e36f26 ./artix7/xc7a100tfgg484-2L/package_pins.csv`](./artix7/xc7a100tfgg484-2L/package_pins.csv)
+ * [`78909bda2084de19e6095258ab1b1ad549c2db376abdd8699235a7bdc3aa19fb ./artix7/xc7a100tfgg484-2L/part.json`](./artix7/xc7a100tfgg484-2L/part.json)
+ * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tfgg484-2L/part.yaml`](./artix7/xc7a100tfgg484-2L/part.yaml)
+ * [`3e1de5edac7fdd8122041afb2b611902653f8c62dc2da1518b94ed6378e36f26 ./artix7/xc7a100tfgg484-3/package_pins.csv`](./artix7/xc7a100tfgg484-3/package_pins.csv)
+ * [`78909bda2084de19e6095258ab1b1ad549c2db376abdd8699235a7bdc3aa19fb ./artix7/xc7a100tfgg484-3/part.json`](./artix7/xc7a100tfgg484-3/part.json)
+ * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tfgg484-3/part.yaml`](./artix7/xc7a100tfgg484-3/part.yaml)
* [`bf25d62e58330960eb582f0b3b99196bd59df046db0d7de5330634b64cd397ad ./artix7/xc7a100tfgg676-1/package_pins.csv`](./artix7/xc7a100tfgg676-1/package_pins.csv)
* [`78909bda2084de19e6095258ab1b1ad549c2db376abdd8699235a7bdc3aa19fb ./artix7/xc7a100tfgg676-1/part.json`](./artix7/xc7a100tfgg676-1/part.json)
* [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tfgg676-1/part.yaml`](./artix7/xc7a100tfgg676-1/part.yaml)
+ * [`bf25d62e58330960eb582f0b3b99196bd59df046db0d7de5330634b64cd397ad ./artix7/xc7a100tfgg676-2/package_pins.csv`](./artix7/xc7a100tfgg676-2/package_pins.csv)
+ * [`78909bda2084de19e6095258ab1b1ad549c2db376abdd8699235a7bdc3aa19fb ./artix7/xc7a100tfgg676-2/part.json`](./artix7/xc7a100tfgg676-2/part.json)
+ * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tfgg676-2/part.yaml`](./artix7/xc7a100tfgg676-2/part.yaml)
+ * [`bf25d62e58330960eb582f0b3b99196bd59df046db0d7de5330634b64cd397ad ./artix7/xc7a100tfgg676-2L/package_pins.csv`](./artix7/xc7a100tfgg676-2L/package_pins.csv)
+ * [`78909bda2084de19e6095258ab1b1ad549c2db376abdd8699235a7bdc3aa19fb ./artix7/xc7a100tfgg676-2L/part.json`](./artix7/xc7a100tfgg676-2L/part.json)
+ * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tfgg676-2L/part.yaml`](./artix7/xc7a100tfgg676-2L/part.yaml)
+ * [`bf25d62e58330960eb582f0b3b99196bd59df046db0d7de5330634b64cd397ad ./artix7/xc7a100tfgg676-3/package_pins.csv`](./artix7/xc7a100tfgg676-3/package_pins.csv)
+ * [`78909bda2084de19e6095258ab1b1ad549c2db376abdd8699235a7bdc3aa19fb ./artix7/xc7a100tfgg676-3/part.json`](./artix7/xc7a100tfgg676-3/part.json)
+ * [`4e1f153303270ed3727ca40af3179020f74271ff63c4d771556020b1d3037b92 ./artix7/xc7a100tfgg676-3/part.yaml`](./artix7/xc7a100tfgg676-3/part.yaml)
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+ * [`12dd577bd32c19b80719bd9cc120e2069a372720cfdcb6c03ad7f2f3d6e88399 ./artix7/xc7a50tcpg236-3/part.json`](./artix7/xc7a50tcpg236-3/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tcpg236-3/part.yaml`](./artix7/xc7a50tcpg236-3/part.yaml)
+ * [`d656d80d3969b020050190034ddb573a320eeba76733b9fb850479902bb7b5c1 ./artix7/xc7a50tcsg324-1/package_pins.csv`](./artix7/xc7a50tcsg324-1/package_pins.csv)
+ * [`6f58dc1e7f454bb28592ecfc9b343541283593d596dba555d0088d0bff9ca1ae ./artix7/xc7a50tcsg324-1/part.json`](./artix7/xc7a50tcsg324-1/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tcsg324-1/part.yaml`](./artix7/xc7a50tcsg324-1/part.yaml)
+ * [`d656d80d3969b020050190034ddb573a320eeba76733b9fb850479902bb7b5c1 ./artix7/xc7a50tcsg324-2/package_pins.csv`](./artix7/xc7a50tcsg324-2/package_pins.csv)
+ * [`6f58dc1e7f454bb28592ecfc9b343541283593d596dba555d0088d0bff9ca1ae ./artix7/xc7a50tcsg324-2/part.json`](./artix7/xc7a50tcsg324-2/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tcsg324-2/part.yaml`](./artix7/xc7a50tcsg324-2/part.yaml)
+ * [`d656d80d3969b020050190034ddb573a320eeba76733b9fb850479902bb7b5c1 ./artix7/xc7a50tcsg324-2L/package_pins.csv`](./artix7/xc7a50tcsg324-2L/package_pins.csv)
+ * [`6f58dc1e7f454bb28592ecfc9b343541283593d596dba555d0088d0bff9ca1ae ./artix7/xc7a50tcsg324-2L/part.json`](./artix7/xc7a50tcsg324-2L/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tcsg324-2L/part.yaml`](./artix7/xc7a50tcsg324-2L/part.yaml)
+ * [`d656d80d3969b020050190034ddb573a320eeba76733b9fb850479902bb7b5c1 ./artix7/xc7a50tcsg324-3/package_pins.csv`](./artix7/xc7a50tcsg324-3/package_pins.csv)
+ * [`6f58dc1e7f454bb28592ecfc9b343541283593d596dba555d0088d0bff9ca1ae ./artix7/xc7a50tcsg324-3/part.json`](./artix7/xc7a50tcsg324-3/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tcsg324-3/part.yaml`](./artix7/xc7a50tcsg324-3/part.yaml)
+ * [`1540a3a76e80ef37cfd9ba3858a2208a0b953c8d1db7740b8ddf794d5ed63b38 ./artix7/xc7a50tcsg325-1/package_pins.csv`](./artix7/xc7a50tcsg325-1/package_pins.csv)
+ * [`5f610e82c79e85df8cda0c1f0eae0f6d59776eee5496c49e0afae27743384833 ./artix7/xc7a50tcsg325-1/part.json`](./artix7/xc7a50tcsg325-1/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tcsg325-1/part.yaml`](./artix7/xc7a50tcsg325-1/part.yaml)
+ * [`1540a3a76e80ef37cfd9ba3858a2208a0b953c8d1db7740b8ddf794d5ed63b38 ./artix7/xc7a50tcsg325-2/package_pins.csv`](./artix7/xc7a50tcsg325-2/package_pins.csv)
+ * [`5f610e82c79e85df8cda0c1f0eae0f6d59776eee5496c49e0afae27743384833 ./artix7/xc7a50tcsg325-2/part.json`](./artix7/xc7a50tcsg325-2/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tcsg325-2/part.yaml`](./artix7/xc7a50tcsg325-2/part.yaml)
+ * [`1540a3a76e80ef37cfd9ba3858a2208a0b953c8d1db7740b8ddf794d5ed63b38 ./artix7/xc7a50tcsg325-2L/package_pins.csv`](./artix7/xc7a50tcsg325-2L/package_pins.csv)
+ * [`5f610e82c79e85df8cda0c1f0eae0f6d59776eee5496c49e0afae27743384833 ./artix7/xc7a50tcsg325-2L/part.json`](./artix7/xc7a50tcsg325-2L/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tcsg325-2L/part.yaml`](./artix7/xc7a50tcsg325-2L/part.yaml)
+ * [`1540a3a76e80ef37cfd9ba3858a2208a0b953c8d1db7740b8ddf794d5ed63b38 ./artix7/xc7a50tcsg325-3/package_pins.csv`](./artix7/xc7a50tcsg325-3/package_pins.csv)
+ * [`5f610e82c79e85df8cda0c1f0eae0f6d59776eee5496c49e0afae27743384833 ./artix7/xc7a50tcsg325-3/part.json`](./artix7/xc7a50tcsg325-3/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tcsg325-3/part.yaml`](./artix7/xc7a50tcsg325-3/part.yaml)
* [`1b01a06e9bae479981698cdb89fff971c825c75266b3b529cd69cd54815ce805 ./artix7/xc7a50tfgg484-1/package_pins.csv`](./artix7/xc7a50tfgg484-1/package_pins.csv)
* [`6f58dc1e7f454bb28592ecfc9b343541283593d596dba555d0088d0bff9ca1ae ./artix7/xc7a50tfgg484-1/part.json`](./artix7/xc7a50tfgg484-1/part.json)
* [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tfgg484-1/part.yaml`](./artix7/xc7a50tfgg484-1/part.yaml)
+ * [`1b01a06e9bae479981698cdb89fff971c825c75266b3b529cd69cd54815ce805 ./artix7/xc7a50tfgg484-2/package_pins.csv`](./artix7/xc7a50tfgg484-2/package_pins.csv)
+ * [`6f58dc1e7f454bb28592ecfc9b343541283593d596dba555d0088d0bff9ca1ae ./artix7/xc7a50tfgg484-2/part.json`](./artix7/xc7a50tfgg484-2/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tfgg484-2/part.yaml`](./artix7/xc7a50tfgg484-2/part.yaml)
+ * [`1b01a06e9bae479981698cdb89fff971c825c75266b3b529cd69cd54815ce805 ./artix7/xc7a50tfgg484-2L/package_pins.csv`](./artix7/xc7a50tfgg484-2L/package_pins.csv)
+ * [`6f58dc1e7f454bb28592ecfc9b343541283593d596dba555d0088d0bff9ca1ae ./artix7/xc7a50tfgg484-2L/part.json`](./artix7/xc7a50tfgg484-2L/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tfgg484-2L/part.yaml`](./artix7/xc7a50tfgg484-2L/part.yaml)
+ * [`1b01a06e9bae479981698cdb89fff971c825c75266b3b529cd69cd54815ce805 ./artix7/xc7a50tfgg484-3/package_pins.csv`](./artix7/xc7a50tfgg484-3/package_pins.csv)
+ * [`6f58dc1e7f454bb28592ecfc9b343541283593d596dba555d0088d0bff9ca1ae ./artix7/xc7a50tfgg484-3/part.json`](./artix7/xc7a50tfgg484-3/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tfgg484-3/part.yaml`](./artix7/xc7a50tfgg484-3/part.yaml)
+ * [`48c715243411156182302fe04f461e6605d4f2008a4fb8fc40c7fa73948c2f2d ./artix7/xc7a50tftg256-1/package_pins.csv`](./artix7/xc7a50tftg256-1/package_pins.csv)
+ * [`fa45189af30b211aaf3f466fff9429826d4ee8c3ec82bd9bd0ea90313c061043 ./artix7/xc7a50tftg256-1/part.json`](./artix7/xc7a50tftg256-1/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tftg256-1/part.yaml`](./artix7/xc7a50tftg256-1/part.yaml)
+ * [`48c715243411156182302fe04f461e6605d4f2008a4fb8fc40c7fa73948c2f2d ./artix7/xc7a50tftg256-2/package_pins.csv`](./artix7/xc7a50tftg256-2/package_pins.csv)
+ * [`fa45189af30b211aaf3f466fff9429826d4ee8c3ec82bd9bd0ea90313c061043 ./artix7/xc7a50tftg256-2/part.json`](./artix7/xc7a50tftg256-2/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tftg256-2/part.yaml`](./artix7/xc7a50tftg256-2/part.yaml)
+ * [`48c715243411156182302fe04f461e6605d4f2008a4fb8fc40c7fa73948c2f2d ./artix7/xc7a50tftg256-2L/package_pins.csv`](./artix7/xc7a50tftg256-2L/package_pins.csv)
+ * [`fa45189af30b211aaf3f466fff9429826d4ee8c3ec82bd9bd0ea90313c061043 ./artix7/xc7a50tftg256-2L/part.json`](./artix7/xc7a50tftg256-2L/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tftg256-2L/part.yaml`](./artix7/xc7a50tftg256-2L/part.yaml)
+ * [`48c715243411156182302fe04f461e6605d4f2008a4fb8fc40c7fa73948c2f2d ./artix7/xc7a50tftg256-3/package_pins.csv`](./artix7/xc7a50tftg256-3/package_pins.csv)
+ * [`fa45189af30b211aaf3f466fff9429826d4ee8c3ec82bd9bd0ea90313c061043 ./artix7/xc7a50tftg256-3/part.json`](./artix7/xc7a50tftg256-3/part.json)
+ * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tftg256-3/part.yaml`](./artix7/xc7a50tftg256-3/part.yaml)
## Database for [kintex7](kintex7/)
### Settings
-Created using following [settings/kintex7.sh (sha256: f04c23dee2bff14bf48a04f60034d3f3d674bb3e40182cc88201265679ac42fb)](https://github.com/SymbiFlow/prjxray/blob/0d9418a908dafecae1d38418d3a0e2d2b2416ea0/settings/kintex7.sh)
+Created using following [settings/kintex7.sh (sha256: f04c23dee2bff14bf48a04f60034d3f3d674bb3e40182cc88201265679ac42fb)](https://github.com/SymbiFlow/prjxray/blob/086f9a1714e96323947d7c2526f5e4b97063e79f/settings/kintex7.sh)
```shell
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
@@ -679,12 +918,12 @@
* [`aef69bf4538841de972b7e905351f0699c137248ccc2c464f67a80e39fb0d330 ./kintex7/element_counts.csv`](./kintex7/element_counts.csv)
* [`749138de1b21b457f05ca05c863584ee70af1a44f7470d1400855760d43b3909 ./kintex7/mapping/devices.yaml`](./kintex7/mapping/devices.yaml)
- * [`db2141b86ba03b028a0d355c4a2ef6bed2b9c7667f0db47f29dd58887ab02679 ./kintex7/mapping/parts.yaml`](./kintex7/mapping/parts.yaml)
+ * [`90dc3ec4c918aed2d1ece9dc0053c51e492647b001c96f240dfe6e9531464c1d ./kintex7/mapping/parts.yaml`](./kintex7/mapping/parts.yaml)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./kintex7/mask_bram_l.block_ram.db`](./kintex7/mask_bram_l.block_ram.db)
- * [`0a946160b7cc00081d0a4f0b115bef85db44332b89e93ac5dc1f715a98f2272e ./kintex7/mask_bram_l.db`](./kintex7/mask_bram_l.db)
+ * [`faa400823ee94cd263cd0583f23bff0c2844cc6249a365682f5314303cad236f ./kintex7/mask_bram_l.db`](./kintex7/mask_bram_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/mask_bram_l.origin_info.db`](./kintex7/mask_bram_l.origin_info.db)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./kintex7/mask_bram_r.block_ram.db`](./kintex7/mask_bram_r.block_ram.db)
- * [`0a946160b7cc00081d0a4f0b115bef85db44332b89e93ac5dc1f715a98f2272e ./kintex7/mask_bram_r.db`](./kintex7/mask_bram_r.db)
+ * [`faa400823ee94cd263cd0583f23bff0c2844cc6249a365682f5314303cad236f ./kintex7/mask_bram_r.db`](./kintex7/mask_bram_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/mask_bram_r.origin_info.db`](./kintex7/mask_bram_r.origin_info.db)
* [`4f37a37c925f92956b6fc010034529a4cc37698ecb7dd263a0fe737ad600cde7 ./kintex7/mask_clbll_l.db`](./kintex7/mask_clbll_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/mask_clbll_l.origin_info.db`](./kintex7/mask_clbll_l.origin_info.db)
@@ -699,9 +938,9 @@
* [`6421d30c48f1ae5bdf1cdbf7aa205edb31059a018082125861d6a3c7d23e9327 ./kintex7/mask_clk_bufg_top_r.db`](./kintex7/mask_clk_bufg_top_r.db)
* [`82097a536f2fa952d7da31e5d6010d2d3952c6b096fe905b8ebc374a1d30c557 ./kintex7/mask_clk_hrow_bot_r.db`](./kintex7/mask_clk_hrow_bot_r.db)
* [`4d6eb3eb7c63fe5b22d6d6575a236119e3bce2e74fbaaf1733591aa4223cb416 ./kintex7/mask_clk_hrow_top_r.db`](./kintex7/mask_clk_hrow_top_r.db)
- * [`40e89c81f44480c96957a2c5d29cf365d5c859cce8e2bc7233e90eb4a2d490b0 ./kintex7/mask_dsp_l.db`](./kintex7/mask_dsp_l.db)
+ * [`2065c4a07269a355607f4862f055bf8d7c5b380b2d27f7193c8dc0a08c8f481c ./kintex7/mask_dsp_l.db`](./kintex7/mask_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/mask_dsp_l.origin_info.db`](./kintex7/mask_dsp_l.origin_info.db)
- * [`54ce9ba489d62d7ef53b5e234c8e51591f254b707475c176ab0515a09a352f32 ./kintex7/mask_dsp_r.db`](./kintex7/mask_dsp_r.db)
+ * [`b3c53663009d0c2e3ed74d758b39739a85541f48d801c8647b0b73ebc0563a4c ./kintex7/mask_dsp_r.db`](./kintex7/mask_dsp_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/mask_dsp_r.origin_info.db`](./kintex7/mask_dsp_r.origin_info.db)
* [`c714c25d06cc5d3b7947e638f55c5268b01792cb2d86320a5411d00387ada404 ./kintex7/mask_hclk_cmt.db`](./kintex7/mask_hclk_cmt.db)
* [`c714c25d06cc5d3b7947e638f55c5268b01792cb2d86320a5411d00387ada404 ./kintex7/mask_hclk_cmt_l.db`](./kintex7/mask_hclk_cmt_l.db)
@@ -825,9 +1064,9 @@
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db)
* [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./kintex7/segbits_hclk_r.origin_info.db`](./kintex7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
- * [`a8e4e0a62a4c109423a18d94aaf5a963f187c58ffe17e321088395dad6300b32 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
+ * [`82289cefac20bb56691b8c5b157b41828d4cb9f9916fdba13bcc79ea809350f0 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
- * [`be03541f8c9a9fce4375588fc0747427c1bbbe3ca4fc27a5ae5e594435401d3d ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
+ * [`2d48d3facbd085a85c86e196ea1aaa2ad79c75b84271fd4cf581a5fc0f1d39da ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db)
* [`432e956da48016ba647631ff91975eb501f98e3961330bdaa35c686d780300d9 ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db)
* [`606867ace72307cf773d819f40696862301419fda3d6d748746d2bfc58579731 ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db)
* [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff ./kintex7/segbits_lioi3.db`](./kintex7/segbits_lioi3.db)
@@ -1012,16 +1251,61 @@
* [`5b05a6f706a18184e00c2634a3423e86242244c622c1dbc09d1efec19315cd41 ./kintex7/xc7k70t/node_wires.json`](./kintex7/xc7k70t/node_wires.json)
* [`77985c4643b2984db517096deb4fc80ae992794089aea91c21b456d81fcbadd2 ./kintex7/xc7k70t/tileconn.json`](./kintex7/xc7k70t/tileconn.json)
* [`ad68c3cb4cac3846e55da96ab182a829a52372269a6a9b50c539e47252b66279 ./kintex7/xc7k70t/tilegrid.json`](./kintex7/xc7k70t/tilegrid.json)
+ * [`0c087483964aa070381911d940ad5793b57abc97c6f3a914f56d364c5a66c58b ./kintex7/xc7k70tfbg484-1/package_pins.csv`](./kintex7/xc7k70tfbg484-1/package_pins.csv)
+ * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbg484-1/part.json`](./kintex7/xc7k70tfbg484-1/part.json)
+ * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg484-1/part.yaml`](./kintex7/xc7k70tfbg484-1/part.yaml)
+ * [`0c087483964aa070381911d940ad5793b57abc97c6f3a914f56d364c5a66c58b ./kintex7/xc7k70tfbg484-2/package_pins.csv`](./kintex7/xc7k70tfbg484-2/package_pins.csv)
+ * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbg484-2/part.json`](./kintex7/xc7k70tfbg484-2/part.json)
+ * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg484-2/part.yaml`](./kintex7/xc7k70tfbg484-2/part.yaml)
+ * [`0c087483964aa070381911d940ad5793b57abc97c6f3a914f56d364c5a66c58b ./kintex7/xc7k70tfbg484-2L/package_pins.csv`](./kintex7/xc7k70tfbg484-2L/package_pins.csv)
+ * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbg484-2L/part.json`](./kintex7/xc7k70tfbg484-2L/part.json)
+ * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg484-2L/part.yaml`](./kintex7/xc7k70tfbg484-2L/part.yaml)
+ * [`0c087483964aa070381911d940ad5793b57abc97c6f3a914f56d364c5a66c58b ./kintex7/xc7k70tfbg484-3/package_pins.csv`](./kintex7/xc7k70tfbg484-3/package_pins.csv)
+ * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbg484-3/part.json`](./kintex7/xc7k70tfbg484-3/part.json)
+ * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg484-3/part.yaml`](./kintex7/xc7k70tfbg484-3/part.yaml)
+ * [`8b128900def98b91bc600d7476510024c569654b85d569d3b259a36195c2b287 ./kintex7/xc7k70tfbg676-1/package_pins.csv`](./kintex7/xc7k70tfbg676-1/package_pins.csv)
+ * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbg676-1/part.json`](./kintex7/xc7k70tfbg676-1/part.json)
+ * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg676-1/part.yaml`](./kintex7/xc7k70tfbg676-1/part.yaml)
* [`8b128900def98b91bc600d7476510024c569654b85d569d3b259a36195c2b287 ./kintex7/xc7k70tfbg676-2/package_pins.csv`](./kintex7/xc7k70tfbg676-2/package_pins.csv)
* [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbg676-2/part.json`](./kintex7/xc7k70tfbg676-2/part.json)
* [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg676-2/part.yaml`](./kintex7/xc7k70tfbg676-2/part.yaml)
+ * [`8b128900def98b91bc600d7476510024c569654b85d569d3b259a36195c2b287 ./kintex7/xc7k70tfbg676-2L/package_pins.csv`](./kintex7/xc7k70tfbg676-2L/package_pins.csv)
+ * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbg676-2L/part.json`](./kintex7/xc7k70tfbg676-2L/part.json)
+ * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg676-2L/part.yaml`](./kintex7/xc7k70tfbg676-2L/part.yaml)
+ * [`8b128900def98b91bc600d7476510024c569654b85d569d3b259a36195c2b287 ./kintex7/xc7k70tfbg676-3/package_pins.csv`](./kintex7/xc7k70tfbg676-3/package_pins.csv)
+ * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbg676-3/part.json`](./kintex7/xc7k70tfbg676-3/part.json)
+ * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg676-3/part.yaml`](./kintex7/xc7k70tfbg676-3/part.yaml)
+ * [`0c087483964aa070381911d940ad5793b57abc97c6f3a914f56d364c5a66c58b ./kintex7/xc7k70tfbv484-1/package_pins.csv`](./kintex7/xc7k70tfbv484-1/package_pins.csv)
+ * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbv484-1/part.json`](./kintex7/xc7k70tfbv484-1/part.json)
+ * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbv484-1/part.yaml`](./kintex7/xc7k70tfbv484-1/part.yaml)
+ * [`0c087483964aa070381911d940ad5793b57abc97c6f3a914f56d364c5a66c58b ./kintex7/xc7k70tfbv484-2/package_pins.csv`](./kintex7/xc7k70tfbv484-2/package_pins.csv)
+ * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbv484-2/part.json`](./kintex7/xc7k70tfbv484-2/part.json)
+ * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbv484-2/part.yaml`](./kintex7/xc7k70tfbv484-2/part.yaml)
+ * [`0c087483964aa070381911d940ad5793b57abc97c6f3a914f56d364c5a66c58b ./kintex7/xc7k70tfbv484-2L/package_pins.csv`](./kintex7/xc7k70tfbv484-2L/package_pins.csv)
+ * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbv484-2L/part.json`](./kintex7/xc7k70tfbv484-2L/part.json)
+ * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbv484-2L/part.yaml`](./kintex7/xc7k70tfbv484-2L/part.yaml)
+ * [`0c087483964aa070381911d940ad5793b57abc97c6f3a914f56d364c5a66c58b ./kintex7/xc7k70tfbv484-3/package_pins.csv`](./kintex7/xc7k70tfbv484-3/package_pins.csv)
+ * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbv484-3/part.json`](./kintex7/xc7k70tfbv484-3/part.json)
+ * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbv484-3/part.yaml`](./kintex7/xc7k70tfbv484-3/part.yaml)
+ * [`8b128900def98b91bc600d7476510024c569654b85d569d3b259a36195c2b287 ./kintex7/xc7k70tfbv676-1/package_pins.csv`](./kintex7/xc7k70tfbv676-1/package_pins.csv)
+ * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbv676-1/part.json`](./kintex7/xc7k70tfbv676-1/part.json)
+ * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbv676-1/part.yaml`](./kintex7/xc7k70tfbv676-1/part.yaml)
+ * [`8b128900def98b91bc600d7476510024c569654b85d569d3b259a36195c2b287 ./kintex7/xc7k70tfbv676-2/package_pins.csv`](./kintex7/xc7k70tfbv676-2/package_pins.csv)
+ * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbv676-2/part.json`](./kintex7/xc7k70tfbv676-2/part.json)
+ * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbv676-2/part.yaml`](./kintex7/xc7k70tfbv676-2/part.yaml)
+ * [`8b128900def98b91bc600d7476510024c569654b85d569d3b259a36195c2b287 ./kintex7/xc7k70tfbv676-2L/package_pins.csv`](./kintex7/xc7k70tfbv676-2L/package_pins.csv)
+ * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbv676-2L/part.json`](./kintex7/xc7k70tfbv676-2L/part.json)
+ * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbv676-2L/part.yaml`](./kintex7/xc7k70tfbv676-2L/part.yaml)
+ * [`8b128900def98b91bc600d7476510024c569654b85d569d3b259a36195c2b287 ./kintex7/xc7k70tfbv676-3/package_pins.csv`](./kintex7/xc7k70tfbv676-3/package_pins.csv)
+ * [`d86758840d59ef445b8889f62784cbdaed4c05f9f02128d733e6b2b1dd770966 ./kintex7/xc7k70tfbv676-3/part.json`](./kintex7/xc7k70tfbv676-3/part.json)
+ * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbv676-3/part.yaml`](./kintex7/xc7k70tfbv676-3/part.yaml)
## Database for [zynq7](zynq7/)
### Settings
-Created using following [settings/zynq7.sh (sha256: 241ebc54a73b6a3cb3eacea09b798fe9887d955ccdfe7b48994a9a10928837c2)](https://github.com/SymbiFlow/prjxray/blob/0d9418a908dafecae1d38418d3a0e2d2b2416ea0/settings/zynq7.sh)
+Created using following [settings/zynq7.sh (sha256: 241ebc54a73b6a3cb3eacea09b798fe9887d955ccdfe7b48994a9a10928837c2)](https://github.com/SymbiFlow/prjxray/blob/086f9a1714e96323947d7c2526f5e4b97063e79f/settings/zynq7.sh)
```shell
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
@@ -1063,13 +1347,13 @@
Results have checksums;
* [`c38e176a49188f55bcf4f092c5dc0ae22018d174573e3894ce8e8b882792c5ed ./zynq7/element_counts.csv`](./zynq7/element_counts.csv)
- * [`f7801492da30281313a79230964418196192a4ecbef8d79e183429a5ca8db0d5 ./zynq7/mapping/devices.yaml`](./zynq7/mapping/devices.yaml)
- * [`130554b91fe91a8166096fd5425c55c6b7fa1a9a1f44bf37cce431eb111d1639 ./zynq7/mapping/parts.yaml`](./zynq7/mapping/parts.yaml)
+ * [`e8a14fa95bebc6bb612a74d53afd2671cad0311890b570d9217f43a0a230f4e5 ./zynq7/mapping/devices.yaml`](./zynq7/mapping/devices.yaml)
+ * [`41e93442c88339163e8d66cb475c7d4009f9653b5c3ad74b720e480867615503 ./zynq7/mapping/parts.yaml`](./zynq7/mapping/parts.yaml)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./zynq7/mask_bram_l.block_ram.db`](./zynq7/mask_bram_l.block_ram.db)
- * [`bd011fe1a63f4f35366b266b6f3e1557fc021754e684e97cc2704f29f307e50c ./zynq7/mask_bram_l.db`](./zynq7/mask_bram_l.db)
+ * [`7a1c456d5ac3ef29a984aa4915e6d857161b14529649f8c4d2eb8e9beb7905b4 ./zynq7/mask_bram_l.db`](./zynq7/mask_bram_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_bram_l.origin_info.db`](./zynq7/mask_bram_l.origin_info.db)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./zynq7/mask_bram_r.block_ram.db`](./zynq7/mask_bram_r.block_ram.db)
- * [`bd011fe1a63f4f35366b266b6f3e1557fc021754e684e97cc2704f29f307e50c ./zynq7/mask_bram_r.db`](./zynq7/mask_bram_r.db)
+ * [`7a1c456d5ac3ef29a984aa4915e6d857161b14529649f8c4d2eb8e9beb7905b4 ./zynq7/mask_bram_r.db`](./zynq7/mask_bram_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_bram_r.origin_info.db`](./zynq7/mask_bram_r.origin_info.db)
* [`dae6bd639ae3cf0ddb9bbdf78e7d5f79bb9971573fa84d0a8c071bac79555120 ./zynq7/mask_clbll_l.db`](./zynq7/mask_clbll_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_clbll_l.origin_info.db`](./zynq7/mask_clbll_l.origin_info.db)
@@ -1084,9 +1368,9 @@
* [`9c35071320dd49be8a4820964b462a13945ca1fe88fd50daf59dd299b81233b3 ./zynq7/mask_clk_bufg_top_r.db`](./zynq7/mask_clk_bufg_top_r.db)
* [`492d7880ed2be3ce5479b397a88e012ea0c98e2ba667fa02d1d57acbdf10208f ./zynq7/mask_clk_hrow_bot_r.db`](./zynq7/mask_clk_hrow_bot_r.db)
* [`417f3c44478e40a864aa29db3dc92f4dda62646db2e69e7418af5c4f518095d5 ./zynq7/mask_clk_hrow_top_r.db`](./zynq7/mask_clk_hrow_top_r.db)
- * [`d1dbb0c4cb485755b168dacf45915daca0c03d9d564d8499a0ee8e443f2636fc ./zynq7/mask_dsp_l.db`](./zynq7/mask_dsp_l.db)
+ * [`3c51e6557a25778581e612d900e1be6183bac234bf4e6d7a58bf2506d87bd774 ./zynq7/mask_dsp_l.db`](./zynq7/mask_dsp_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_dsp_l.origin_info.db`](./zynq7/mask_dsp_l.origin_info.db)
- * [`737dd6a42bad544ae596da9e5be353e4cc39f20dff304f524c1c9ae4d62b9fb5 ./zynq7/mask_dsp_r.db`](./zynq7/mask_dsp_r.db)
+ * [`54a3952cc6878052567f637848e7e12ae6d4631ebc196dc945d7060d8b610bdd ./zynq7/mask_dsp_r.db`](./zynq7/mask_dsp_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_dsp_r.origin_info.db`](./zynq7/mask_dsp_r.origin_info.db)
* [`c714c25d06cc5d3b7947e638f55c5268b01792cb2d86320a5411d00387ada404 ./zynq7/mask_hclk_cmt.db`](./zynq7/mask_hclk_cmt.db)
* [`c714c25d06cc5d3b7947e638f55c5268b01792cb2d86320a5411d00387ada404 ./zynq7/mask_hclk_cmt_l.db`](./zynq7/mask_hclk_cmt_l.db)
@@ -1217,19 +1501,19 @@
* [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db)
* [`61d05145f3613042e8f0c1d97d63f6c185cfb66df609b621b44422ebb27c77a0 ./zynq7/segbits_hclk_r.origin_info.db`](./zynq7/segbits_hclk_r.origin_info.db)
* [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db)
- * [`66c9451631fbcde9a417fa19168a60a8bae3a991823d6773ffa1543396dde30e ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
+ * [`bcb8a2ec56e8a02191598e46606b90087130a8ff84ccca4b3a376f3e1e0d1b1d ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
* [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db)
- * [`578bb187f19d5a0dff2e5dccda6fde721e03b25abbe4287fb48d563f484e0866 ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
- * [`432e956da48016ba647631ff91975eb501f98e3961330bdaa35c686d780300d9 ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db)
- * [`606867ace72307cf773d819f40696862301419fda3d6d748746d2bfc58579731 ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db)
+ * [`bc0d59c5798b5b2d6491a8c1e31f2f0daf21303dc1b16fed39de0062b427d2f9 ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
+ * [`e0ba8ef08832a23ec1793e5fbf40d75734821489b4bd6b37866caf870e5f7d29 ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db)
+ * [`cd4f9c30eaa40cdd6b6d690371e88e53dbb78f19cfaa65e7590fcaf56eb19c9f ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db)
* [`d369c1e614ef6ab1a464c0ab01d07456f73e88ca5a0c3c0dc524bb3b4f4364ff ./zynq7/segbits_lioi3.db`](./zynq7/segbits_lioi3.db)
* [`4b1dd698dba50fdf44426b05641189c2faaff29a99d387543d1874983fd68a50 ./zynq7/segbits_lioi3.origin_info.db`](./zynq7/segbits_lioi3.origin_info.db)
* [`0fb3e4c3427cb3fe2426445f9e6ebd1a33a3a5900904f28c7aea339a5f71530e ./zynq7/segbits_lioi3_tbytesrc.db`](./zynq7/segbits_lioi3_tbytesrc.db)
* [`cbc24997471fa0a4cc59db46589a3daea9f59b4d599ca802a1f62b730090c89c ./zynq7/segbits_lioi3_tbytesrc.origin_info.db`](./zynq7/segbits_lioi3_tbytesrc.origin_info.db)
* [`e81ad6e17e179647d06b9dc193588c8297af448e8eb7bd6c4b807a832631e07b ./zynq7/segbits_lioi3_tbyteterm.db`](./zynq7/segbits_lioi3_tbyteterm.db)
* [`bf79280a339e566244220050232020c5d3b8dceed7bd80bcf23da7b4a53cb250 ./zynq7/segbits_lioi3_tbyteterm.origin_info.db`](./zynq7/segbits_lioi3_tbyteterm.origin_info.db)
- * [`327992e6b38faaeb0ddf948e8b42b8ce082a662f83f0dac14ebac901b3aeb909 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db)
- * [`f5b3e67f5a0afcd5351a35efd5c3a9e74254347c4268259de6ef4fa9c7bbfaeb ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db)
+ * [`c59b40b4582dc6215fd46746aa7837585e01f62418e4921d1aef62336df27f4a ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db)
+ * [`e471bd1c75d3e087051d4ed694ecc5bb01794cbbc3b5f148ee88e4e9c10a099e ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db)
* [`712cc4b66ff35ea6033cb76e41d8dde1225857836f4b799834925ab5c3e8575a ./zynq7/segbits_rioi3.db`](./zynq7/segbits_rioi3.db)
* [`4d0e9719c7016a0dece266060eabf4db7218b6cc982449cb93b87e7b2d0c755b ./zynq7/segbits_rioi3.origin_info.db`](./zynq7/segbits_rioi3.origin_info.db)
* [`6823106be1cdccae2cf0c1332c7a36ee11a1a86c31376100f16921b6b579ea19 ./zynq7/segbits_rioi3_tbytesrc.db`](./zynq7/segbits_rioi3_tbytesrc.db)
@@ -1430,20 +1714,47 @@
* [`626d9e188a1c4874f7ac657e82c64df8d52f819624e8ee4f9ed9e557d85ad3f2 ./zynq7/timings/carry4_slicem.sdf`](./zynq7/timings/carry4_slicem.sdf)
* [`fd31d66077f869d01f13d9fabbd0dcd38b4aab0322179ecf9ac190a3b70c5456 ./zynq7/timings/slicel.sdf`](./zynq7/timings/slicel.sdf)
* [`3d2da5714d8c81165fa51403fb719b3ddd9e7ea7ab79280ae4e157d11a29172e ./zynq7/timings/slicem.sdf`](./zynq7/timings/slicem.sdf)
+ * [`d99fd0da8cc6b38b4ce4b08182aefe8ed9259d46b3afddcd992c31d3893f8bba ./zynq7/xc7z010/node_wires.json`](./zynq7/xc7z010/node_wires.json)
+ * [`e6d0ebf9b27f60f4afdab85a357bff4d7cf2cd77c3a6c0f2d887022cda874066 ./zynq7/xc7z010/tileconn.json`](./zynq7/xc7z010/tileconn.json)
+ * [`db16874f2827fc05248ad4a7ef5769deaa8e70158a60c8dd40194c48713479ee ./zynq7/xc7z010/tilegrid.json`](./zynq7/xc7z010/tilegrid.json)
+ * [`c346a529adb6c62a4f18e3e04281df94d6a8861d6f8c34527d3b24150ee58a4a ./zynq7/xc7z010clg225-1/package_pins.csv`](./zynq7/xc7z010clg225-1/package_pins.csv)
+ * [`1754ec1c7a8e0447a116984505cc422819d3be06389527de96bf192c5175d095 ./zynq7/xc7z010clg225-1/part.json`](./zynq7/xc7z010clg225-1/part.json)
+ * [`43a136f26603c51bd97e9489d223bbc80f278fcc234225ed9fde404402f22683 ./zynq7/xc7z010clg225-1/part.yaml`](./zynq7/xc7z010clg225-1/part.yaml)
+ * [`c346a529adb6c62a4f18e3e04281df94d6a8861d6f8c34527d3b24150ee58a4a ./zynq7/xc7z010clg225-2/package_pins.csv`](./zynq7/xc7z010clg225-2/package_pins.csv)
+ * [`1754ec1c7a8e0447a116984505cc422819d3be06389527de96bf192c5175d095 ./zynq7/xc7z010clg225-2/part.json`](./zynq7/xc7z010clg225-2/part.json)
+ * [`43a136f26603c51bd97e9489d223bbc80f278fcc234225ed9fde404402f22683 ./zynq7/xc7z010clg225-2/part.yaml`](./zynq7/xc7z010clg225-2/part.yaml)
+ * [`c346a529adb6c62a4f18e3e04281df94d6a8861d6f8c34527d3b24150ee58a4a ./zynq7/xc7z010clg225-3/package_pins.csv`](./zynq7/xc7z010clg225-3/package_pins.csv)
+ * [`1754ec1c7a8e0447a116984505cc422819d3be06389527de96bf192c5175d095 ./zynq7/xc7z010clg225-3/part.json`](./zynq7/xc7z010clg225-3/part.json)
+ * [`43a136f26603c51bd97e9489d223bbc80f278fcc234225ed9fde404402f22683 ./zynq7/xc7z010clg225-3/part.yaml`](./zynq7/xc7z010clg225-3/part.yaml)
* [`2e714cd17c9768566a3a262edf9665a5bdb3e5bfa9d4756ac6d224b44f24a107 ./zynq7/xc7z010clg400-1/package_pins.csv`](./zynq7/xc7z010clg400-1/package_pins.csv)
* [`1754ec1c7a8e0447a116984505cc422819d3be06389527de96bf192c5175d095 ./zynq7/xc7z010clg400-1/part.json`](./zynq7/xc7z010clg400-1/part.json)
* [`43a136f26603c51bd97e9489d223bbc80f278fcc234225ed9fde404402f22683 ./zynq7/xc7z010clg400-1/part.yaml`](./zynq7/xc7z010clg400-1/part.yaml)
* [`899966167308aa91e3651f66bba8611ee465acaf8e58bd3ba87d5b1777c0f625 ./zynq7/xc7z010clg400-1/required_features.fasm`](./zynq7/xc7z010clg400-1/required_features.fasm)
- * [`d99fd0da8cc6b38b4ce4b08182aefe8ed9259d46b3afddcd992c31d3893f8bba ./zynq7/xc7z010s/node_wires.json`](./zynq7/xc7z010s/node_wires.json)
- * [`e6d0ebf9b27f60f4afdab85a357bff4d7cf2cd77c3a6c0f2d887022cda874066 ./zynq7/xc7z010s/tileconn.json`](./zynq7/xc7z010s/tileconn.json)
- * [`db16874f2827fc05248ad4a7ef5769deaa8e70158a60c8dd40194c48713479ee ./zynq7/xc7z010s/tilegrid.json`](./zynq7/xc7z010s/tilegrid.json)
+ * [`2e714cd17c9768566a3a262edf9665a5bdb3e5bfa9d4756ac6d224b44f24a107 ./zynq7/xc7z010clg400-2/package_pins.csv`](./zynq7/xc7z010clg400-2/package_pins.csv)
+ * [`1754ec1c7a8e0447a116984505cc422819d3be06389527de96bf192c5175d095 ./zynq7/xc7z010clg400-2/part.json`](./zynq7/xc7z010clg400-2/part.json)
+ * [`43a136f26603c51bd97e9489d223bbc80f278fcc234225ed9fde404402f22683 ./zynq7/xc7z010clg400-2/part.yaml`](./zynq7/xc7z010clg400-2/part.yaml)
+ * [`2e714cd17c9768566a3a262edf9665a5bdb3e5bfa9d4756ac6d224b44f24a107 ./zynq7/xc7z010clg400-3/package_pins.csv`](./zynq7/xc7z010clg400-3/package_pins.csv)
+ * [`1754ec1c7a8e0447a116984505cc422819d3be06389527de96bf192c5175d095 ./zynq7/xc7z010clg400-3/part.json`](./zynq7/xc7z010clg400-3/part.json)
+ * [`43a136f26603c51bd97e9489d223bbc80f278fcc234225ed9fde404402f22683 ./zynq7/xc7z010clg400-3/part.yaml`](./zynq7/xc7z010clg400-3/part.yaml)
+ * [`3a569badb9f777cc28a9d4f80234ef432fd202a5fbf40b17122286847a8188f3 ./zynq7/xc7z020/node_wires.json`](./zynq7/xc7z020/node_wires.json)
+ * [`8c3c23f987f1c0a2e55ab2a7467a9724f30762d1268e6cc5fce00eb65bf00ad3 ./zynq7/xc7z020/tileconn.json`](./zynq7/xc7z020/tileconn.json)
+ * [`c980c8eb552d50ef8c210a6709043c6c0355b95b695a36f99cfa9716d853c61d ./zynq7/xc7z020/tilegrid.json`](./zynq7/xc7z020/tilegrid.json)
* [`52eac7be98da1e8bda491fa07699ae84c0e7eca1e09cde8b308be1df2ab5590f ./zynq7/xc7z020clg400-1/package_pins.csv`](./zynq7/xc7z020clg400-1/package_pins.csv)
* [`40734e0dad409b7728403109f9eeb47adfbfcdcb8780414a8e81c04c44b96c49 ./zynq7/xc7z020clg400-1/part.json`](./zynq7/xc7z020clg400-1/part.json)
* [`a5e33398424d02770e3fdccc4d7fe41f0ba8b8440b79a62ad09b60cae6048174 ./zynq7/xc7z020clg400-1/part.yaml`](./zynq7/xc7z020clg400-1/part.yaml)
* [`aedbb30dc143aaec2ca2bc76597ca4ebe546aa7913f0e4de710cecf3e0f31f23 ./zynq7/xc7z020clg400-1/required_features.fasm`](./zynq7/xc7z020clg400-1/required_features.fasm)
+ * [`52eac7be98da1e8bda491fa07699ae84c0e7eca1e09cde8b308be1df2ab5590f ./zynq7/xc7z020clg400-2/package_pins.csv`](./zynq7/xc7z020clg400-2/package_pins.csv)
+ * [`40734e0dad409b7728403109f9eeb47adfbfcdcb8780414a8e81c04c44b96c49 ./zynq7/xc7z020clg400-2/part.json`](./zynq7/xc7z020clg400-2/part.json)
+ * [`a5e33398424d02770e3fdccc4d7fe41f0ba8b8440b79a62ad09b60cae6048174 ./zynq7/xc7z020clg400-2/part.yaml`](./zynq7/xc7z020clg400-2/part.yaml)
+ * [`52eac7be98da1e8bda491fa07699ae84c0e7eca1e09cde8b308be1df2ab5590f ./zynq7/xc7z020clg400-3/package_pins.csv`](./zynq7/xc7z020clg400-3/package_pins.csv)
+ * [`40734e0dad409b7728403109f9eeb47adfbfcdcb8780414a8e81c04c44b96c49 ./zynq7/xc7z020clg400-3/part.json`](./zynq7/xc7z020clg400-3/part.json)
+ * [`a5e33398424d02770e3fdccc4d7fe41f0ba8b8440b79a62ad09b60cae6048174 ./zynq7/xc7z020clg400-3/part.yaml`](./zynq7/xc7z020clg400-3/part.yaml)
* [`55a9a5d444f71774d8b072adb3de03338d68f78ba18f9c817ab1bf239613b1dc ./zynq7/xc7z020clg484-1/package_pins.csv`](./zynq7/xc7z020clg484-1/package_pins.csv)
* [`47d494b96865d61458ec9c5e0d720886bcd755d9eebcae46ca9045fd679d2f2d ./zynq7/xc7z020clg484-1/part.json`](./zynq7/xc7z020clg484-1/part.json)
* [`a5e33398424d02770e3fdccc4d7fe41f0ba8b8440b79a62ad09b60cae6048174 ./zynq7/xc7z020clg484-1/part.yaml`](./zynq7/xc7z020clg484-1/part.yaml)
- * [`3a569badb9f777cc28a9d4f80234ef432fd202a5fbf40b17122286847a8188f3 ./zynq7/xc7z020s/node_wires.json`](./zynq7/xc7z020s/node_wires.json)
- * [`8c3c23f987f1c0a2e55ab2a7467a9724f30762d1268e6cc5fce00eb65bf00ad3 ./zynq7/xc7z020s/tileconn.json`](./zynq7/xc7z020s/tileconn.json)
- * [`c980c8eb552d50ef8c210a6709043c6c0355b95b695a36f99cfa9716d853c61d ./zynq7/xc7z020s/tilegrid.json`](./zynq7/xc7z020s/tilegrid.json)
+ * [`55a9a5d444f71774d8b072adb3de03338d68f78ba18f9c817ab1bf239613b1dc ./zynq7/xc7z020clg484-2/package_pins.csv`](./zynq7/xc7z020clg484-2/package_pins.csv)
+ * [`47d494b96865d61458ec9c5e0d720886bcd755d9eebcae46ca9045fd679d2f2d ./zynq7/xc7z020clg484-2/part.json`](./zynq7/xc7z020clg484-2/part.json)
+ * [`a5e33398424d02770e3fdccc4d7fe41f0ba8b8440b79a62ad09b60cae6048174 ./zynq7/xc7z020clg484-2/part.yaml`](./zynq7/xc7z020clg484-2/part.yaml)
+ * [`55a9a5d444f71774d8b072adb3de03338d68f78ba18f9c817ab1bf239613b1dc ./zynq7/xc7z020clg484-3/package_pins.csv`](./zynq7/xc7z020clg484-3/package_pins.csv)
+ * [`47d494b96865d61458ec9c5e0d720886bcd755d9eebcae46ca9045fd679d2f2d ./zynq7/xc7z020clg484-3/part.json`](./zynq7/xc7z020clg484-3/part.json)
+ * [`a5e33398424d02770e3fdccc4d7fe41f0ba8b8440b79a62ad09b60cae6048174 ./zynq7/xc7z020clg484-3/part.yaml`](./zynq7/xc7z020clg484-3/part.yaml)
diff --git a/artix7/cells_data/pcie_2_1_attrs.json b/artix7/cells_data/pcie_2_1_attrs.json
new file mode 100644
index 0000000..a2ab5ae
--- /dev/null
+++ b/artix7/cells_data/pcie_2_1_attrs.json
@@ -0,0 +1,2086 @@
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+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "SLOT_CAP_NO_CMD_COMPLETED_SUPPORT": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "SLOT_CAP_PHYSICAL_SLOT_NUM": {
+ "digits": 13,
+ "type": "BIN",
+ "values": [
+ 8191
+ ]
+ },
+ "SLOT_CAP_POWER_CONTROLLER_PRESENT": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "SLOT_CAP_POWER_INDICATOR_PRESENT": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "SLOT_CAP_SLOT_POWER_LIMIT_SCALE": {
+ "digits": 2,
+ "type": "BIN",
+ "values": [
+ 3
+ ]
+ },
+ "SLOT_CAP_SLOT_POWER_LIMIT_VALUE": {
+ "digits": 8,
+ "type": "BIN",
+ "values": [
+ 255
+ ]
+ },
+ "SPARE_BIT0": {
+ "digits": 1,
+ "type": "BIN",
+ "values": [
+ 1
+ ]
+ },
+ "SPARE_BIT1": {
+ "digits": 1,
+ "type": "BIN",
+ "values": [
+ 1
+ ]
+ },
+ "SPARE_BIT2": {
+ "digits": 1,
+ "type": "BIN",
+ "values": [
+ 1
+ ]
+ },
+ "SPARE_BIT3": {
+ "digits": 1,
+ "type": "BIN",
+ "values": [
+ 1
+ ]
+ },
+ "SPARE_BIT4": {
+ "digits": 1,
+ "type": "BIN",
+ "values": [
+ 1
+ ]
+ },
+ "SPARE_BIT5": {
+ "digits": 1,
+ "type": "BIN",
+ "values": [
+ 1
+ ]
+ },
+ "SPARE_BIT6": {
+ "digits": 1,
+ "type": "BIN",
+ "values": [
+ 1
+ ]
+ },
+ "SPARE_BIT7": {
+ "digits": 1,
+ "type": "BIN",
+ "values": [
+ 1
+ ]
+ },
+ "SPARE_BIT8": {
+ "digits": 1,
+ "type": "BIN",
+ "values": [
+ 1
+ ]
+ },
+ "SPARE_BYTE0": {
+ "digits": 8,
+ "type": "BIN",
+ "values": [
+ 255
+ ]
+ },
+ "SPARE_BYTE1": {
+ "digits": 8,
+ "type": "BIN",
+ "values": [
+ 255
+ ]
+ },
+ "SPARE_BYTE2": {
+ "digits": 8,
+ "type": "BIN",
+ "values": [
+ 255
+ ]
+ },
+ "SPARE_BYTE3": {
+ "digits": 8,
+ "type": "BIN",
+ "values": [
+ 255
+ ]
+ },
+ "SPARE_WORD0": {
+ "digits": 32,
+ "type": "BIN",
+ "values": [
+ 4294967295
+ ]
+ },
+ "SPARE_WORD1": {
+ "digits": 32,
+ "type": "BIN",
+ "values": [
+ 4294967295
+ ]
+ },
+ "SPARE_WORD2": {
+ "digits": 32,
+ "type": "BIN",
+ "values": [
+ 4294967295
+ ]
+ },
+ "SPARE_WORD3": {
+ "digits": 32,
+ "type": "BIN",
+ "values": [
+ 4294967295
+ ]
+ },
+ "SSL_MESSAGE_AUTO": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "TECRC_EP_INV": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "TL_RBYPASS": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "TL_RX_RAM_RADDR_LATENCY": {
+ "digits": 1,
+ "type": "BIN",
+ "values": [
+ 1
+ ]
+ },
+ "TL_RX_RAM_RDATA_LATENCY": {
+ "digits": 2,
+ "type": "BIN",
+ "values": [
+ 3
+ ]
+ },
+ "TL_RX_RAM_WRITE_LATENCY": {
+ "digits": 1,
+ "type": "BIN",
+ "values": [
+ 1
+ ]
+ },
+ "TL_TFC_DISABLE": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "TL_TX_CHECKS_DISABLE": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "TL_TX_RAM_RADDR_LATENCY": {
+ "digits": 1,
+ "type": "BIN",
+ "values": [
+ 1
+ ]
+ },
+ "TL_TX_RAM_RDATA_LATENCY": {
+ "digits": 2,
+ "type": "BIN",
+ "values": [
+ 3
+ ]
+ },
+ "TL_TX_RAM_WRITE_LATENCY": {
+ "digits": 1,
+ "type": "BIN",
+ "values": [
+ 1
+ ]
+ },
+ "TRN_DW": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "TRN_NP_FC": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "UPCONFIG_CAPABLE": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "UPSTREAM_FACING": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "UR_ATOMIC": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "UR_CFG1": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "UR_INV_REQ": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "UR_PRS_RESPONSE": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "USER_CLK2_DIV2": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "USER_CLK_FREQ": {
+ "digits": 3,
+ "type": "BIN",
+ "values": [
+ 7
+ ]
+ },
+ "USE_RID_PINS": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "VC0_CPL_INFINITE": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "VC0_RX_RAM_LIMIT": {
+ "digits": 13,
+ "type": "BIN",
+ "values": [
+ 8191
+ ]
+ },
+ "VC0_TOTAL_CREDITS_CD": {
+ "digits": 11,
+ "type": "BIN",
+ "values": [
+ 2047
+ ]
+ },
+ "VC0_TOTAL_CREDITS_CH": {
+ "digits": 7,
+ "type": "BIN",
+ "values": [
+ 127
+ ]
+ },
+ "VC0_TOTAL_CREDITS_NPD": {
+ "digits": 11,
+ "type": "BIN",
+ "values": [
+ 2047
+ ]
+ },
+ "VC0_TOTAL_CREDITS_NPH": {
+ "digits": 7,
+ "type": "BIN",
+ "values": [
+ 127
+ ]
+ },
+ "VC0_TOTAL_CREDITS_PD": {
+ "digits": 11,
+ "type": "BIN",
+ "values": [
+ 2047
+ ]
+ },
+ "VC0_TOTAL_CREDITS_PH": {
+ "digits": 7,
+ "type": "BIN",
+ "values": [
+ 127
+ ]
+ },
+ "VC0_TX_LASTPACKET": {
+ "digits": 5,
+ "type": "BIN",
+ "values": [
+ 31
+ ]
+ },
+ "VC_BASE_PTR": {
+ "digits": 12,
+ "type": "BIN",
+ "values": [
+ 4095
+ ]
+ },
+ "VC_CAP_ID": {
+ "digits": 16,
+ "type": "BIN",
+ "values": [
+ 65535
+ ]
+ },
+ "VC_CAP_NEXTPTR": {
+ "digits": 12,
+ "type": "BIN",
+ "values": [
+ 4095
+ ]
+ },
+ "VC_CAP_ON": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "VC_CAP_REJECT_SNOOP_TRANSACTIONS": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "VC_CAP_VERSION": {
+ "digits": 4,
+ "type": "BIN",
+ "values": [
+ 15
+ ]
+ },
+ "VSEC_BASE_PTR": {
+ "digits": 12,
+ "type": "BIN",
+ "values": [
+ 4095
+ ]
+ },
+ "VSEC_CAP_HDR_ID": {
+ "digits": 16,
+ "type": "BIN",
+ "values": [
+ 65535
+ ]
+ },
+ "VSEC_CAP_HDR_LENGTH": {
+ "digits": 12,
+ "type": "BIN",
+ "values": [
+ 4095
+ ]
+ },
+ "VSEC_CAP_HDR_REVISION": {
+ "digits": 4,
+ "type": "BIN",
+ "values": [
+ 15
+ ]
+ },
+ "VSEC_CAP_ID": {
+ "digits": 16,
+ "type": "BIN",
+ "values": [
+ 65535
+ ]
+ },
+ "VSEC_CAP_IS_LINK_VISIBLE": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "VSEC_CAP_NEXTPTR": {
+ "digits": 12,
+ "type": "BIN",
+ "values": [
+ 4095
+ ]
+ },
+ "VSEC_CAP_ON": {
+ "digits": 1,
+ "type": "BOOL",
+ "values": [
+ "FALSE",
+ "TRUE"
+ ]
+ },
+ "VSEC_CAP_VERSION": {
+ "digits": 4,
+ "type": "BIN",
+ "values": [
+ 15
+ ]
+ }
+}
diff --git a/artix7/cells_data/pcie_2_1_ports.json b/artix7/cells_data/pcie_2_1_ports.json
new file mode 100644
index 0000000..c263c1d
--- /dev/null
+++ b/artix7/cells_data/pcie_2_1_ports.json
@@ -0,0 +1,1634 @@
+{
+ "CFGAERECRCCHECKEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGAERECRCGENEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGAERINTERRUPTMSGNUM": {
+ "direction": "input",
+ "width": 5
+ },
+ "CFGAERROOTERRCORRERRRECEIVED": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGAERROOTERRCORRERRREPORTINGEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGAERROOTERRFATALERRRECEIVED": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGAERROOTERRFATALERRREPORTINGEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGAERROOTERRNONFATALERRRECEIVED": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGAERROOTERRNONFATALERRREPORTINGEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGBRIDGESERREN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGCOMMANDBUSMASTERENABLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGCOMMANDINTERRUPTDISABLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGCOMMANDIOENABLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGCOMMANDMEMENABLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGCOMMANDSERREN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROL2ARIFORWARDEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROL2ATOMICEGRESSBLOCK": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROL2ATOMICREQUESTEREN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROL2CPLTIMEOUTDIS": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROL2CPLTIMEOUTVAL": {
+ "direction": "output",
+ "width": 4
+ },
+ "CFGDEVCONTROL2IDOCPLEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROL2IDOREQEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROL2LTREN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROL2TLPPREFIXBLOCK": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROLAUXPOWEREN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROLCORRERRREPORTINGEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROLENABLERO": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROLEXTTAGEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROLFATALERRREPORTINGEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROLMAXPAYLOAD": {
+ "direction": "output",
+ "width": 3
+ },
+ "CFGDEVCONTROLMAXREADREQ": {
+ "direction": "output",
+ "width": 3
+ },
+ "CFGDEVCONTROLNONFATALREPORTINGEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROLNOSNOOPEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROLPHANTOMEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVCONTROLURERRREPORTINGEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVID": {
+ "direction": "input",
+ "width": 16
+ },
+ "CFGDEVSTATUSCORRERRDETECTED": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVSTATUSFATALERRDETECTED": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVSTATUSNONFATALERRDETECTED": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDEVSTATUSURDETECTED": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGDSBUSNUMBER": {
+ "direction": "input",
+ "width": 8
+ },
+ "CFGDSDEVICENUMBER": {
+ "direction": "input",
+ "width": 5
+ },
+ "CFGDSFUNCTIONNUMBER": {
+ "direction": "input",
+ "width": 3
+ },
+ "CFGDSN": {
+ "direction": "input",
+ "width": 64
+ },
+ "CFGERRACSN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGERRAERHEADERLOG": {
+ "direction": "input",
+ "width": 128
+ },
+ "CFGERRAERHEADERLOGSETN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGERRATOMICEGRESSBLOCKEDN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGERRCORN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGERRCPLABORTN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGERRCPLRDYN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGERRCPLTIMEOUTN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGERRCPLUNEXPECTN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGERRECRCN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGERRINTERNALCORN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGERRINTERNALUNCORN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGERRLOCKEDN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGERRMALFORMEDN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGERRMCBLOCKEDN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGERRNORECOVERYN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGERRPOISONEDN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGERRPOSTEDN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGERRTLPCPLHEADER": {
+ "direction": "input",
+ "width": 48
+ },
+ "CFGERRURN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGFORCECOMMONCLOCKOFF": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGFORCEEXTENDEDSYNCON": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGFORCEMPS": {
+ "direction": "input",
+ "width": 3
+ },
+ "CFGINTERRUPTASSERTN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGINTERRUPTDI": {
+ "direction": "input",
+ "width": 8
+ },
+ "CFGINTERRUPTDO": {
+ "direction": "output",
+ "width": 8
+ },
+ "CFGINTERRUPTMMENABLE": {
+ "direction": "output",
+ "width": 3
+ },
+ "CFGINTERRUPTMSIENABLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGINTERRUPTMSIXENABLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGINTERRUPTMSIXFM": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGINTERRUPTN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGINTERRUPTRDYN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGINTERRUPTSTATN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGLINKCONTROLASPMCONTROL": {
+ "direction": "output",
+ "width": 2
+ },
+ "CFGLINKCONTROLAUTOBANDWIDTHINTEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGLINKCONTROLBANDWIDTHINTEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGLINKCONTROLCLOCKPMEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGLINKCONTROLCOMMONCLOCK": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGLINKCONTROLEXTENDEDSYNC": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGLINKCONTROLHWAUTOWIDTHDIS": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGLINKCONTROLLINKDISABLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGLINKCONTROLRCB": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGLINKCONTROLRETRAINLINK": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGLINKSTATUSAUTOBANDWIDTHSTATUS": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGLINKSTATUSBANDWIDTHSTATUS": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGLINKSTATUSCURRENTSPEED": {
+ "direction": "output",
+ "width": 2
+ },
+ "CFGLINKSTATUSDLLACTIVE": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGLINKSTATUSLINKTRAINING": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGLINKSTATUSNEGOTIATEDWIDTH": {
+ "direction": "output",
+ "width": 4
+ },
+ "CFGMGMTBYTEENN": {
+ "direction": "input",
+ "width": 4
+ },
+ "CFGMGMTDI": {
+ "direction": "input",
+ "width": 32
+ },
+ "CFGMGMTDO": {
+ "direction": "output",
+ "width": 32
+ },
+ "CFGMGMTDWADDR": {
+ "direction": "input",
+ "width": 10
+ },
+ "CFGMGMTRDENN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGMGMTRDWRDONEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMGMTWRENN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGMGMTWRREADONLYN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGMGMTWRRW1CASRWN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGMSGDATA": {
+ "direction": "output",
+ "width": 16
+ },
+ "CFGMSGRECEIVED": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDASSERTINTA": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDASSERTINTB": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDASSERTINTC": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDASSERTINTD": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDDEASSERTINTA": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDDEASSERTINTB": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDDEASSERTINTC": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDDEASSERTINTD": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDERRCOR": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDERRFATAL": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDERRNONFATAL": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDPMASNAK": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDPMETO": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDPMETOACK": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDPMPME": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDSETSLOTPOWERLIMIT": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGMSGRECEIVEDUNLOCK": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGPCIECAPINTERRUPTMSGNUM": {
+ "direction": "input",
+ "width": 5
+ },
+ "CFGPCIELINKSTATE": {
+ "direction": "output",
+ "width": 3
+ },
+ "CFGPMCSRPMEEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGPMCSRPMESTATUS": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGPMCSRPOWERSTATE": {
+ "direction": "output",
+ "width": 2
+ },
+ "CFGPMFORCESTATE": {
+ "direction": "input",
+ "width": 2
+ },
+ "CFGPMFORCESTATEENN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGPMHALTASPML0SN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGPMHALTASPML1N": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGPMRCVASREQL1N": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGPMRCVENTERL1N": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGPMRCVENTERL23N": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGPMRCVREQACKN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGPMSENDPMETON": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGPMTURNOFFOKN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGPMWAKEN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGPORTNUMBER": {
+ "direction": "input",
+ "width": 8
+ },
+ "CFGREVID": {
+ "direction": "input",
+ "width": 8
+ },
+ "CFGROOTCONTROLPMEINTEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGROOTCONTROLSYSERRCORRERREN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGROOTCONTROLSYSERRFATALERREN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGROOTCONTROLSYSERRNONFATALERREN": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGSLOTCONTROLELECTROMECHILCTLPULSE": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGSUBSYSID": {
+ "direction": "input",
+ "width": 16
+ },
+ "CFGSUBSYSVENDID": {
+ "direction": "input",
+ "width": 16
+ },
+ "CFGTRANSACTION": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGTRANSACTIONADDR": {
+ "direction": "output",
+ "width": 7
+ },
+ "CFGTRANSACTIONTYPE": {
+ "direction": "output",
+ "width": 1
+ },
+ "CFGTRNPENDINGN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CFGVCTCVCMAP": {
+ "direction": "output",
+ "width": 7
+ },
+ "CFGVENDID": {
+ "direction": "input",
+ "width": 16
+ },
+ "CMRSTN": {
+ "direction": "input",
+ "width": 1
+ },
+ "CMSTICKYRSTN": {
+ "direction": "input",
+ "width": 1
+ },
+ "DBGMODE": {
+ "direction": "input",
+ "width": 2
+ },
+ "DBGSCLRA": {
+ "direction": "output",
+ "width": 1
+ },
+ "DBGSCLRB": {
+ "direction": "output",
+ "width": 1
+ },
+ "DBGSCLRC": {
+ "direction": "output",
+ "width": 1
+ },
+ "DBGSCLRD": {
+ "direction": "output",
+ "width": 1
+ },
+ "DBGSCLRE": {
+ "direction": "output",
+ "width": 1
+ },
+ "DBGSCLRF": {
+ "direction": "output",
+ "width": 1
+ },
+ "DBGSCLRG": {
+ "direction": "output",
+ "width": 1
+ },
+ "DBGSCLRH": {
+ "direction": "output",
+ "width": 1
+ },
+ "DBGSCLRI": {
+ "direction": "output",
+ "width": 1
+ },
+ "DBGSCLRJ": {
+ "direction": "output",
+ "width": 1
+ },
+ "DBGSCLRK": {
+ "direction": "output",
+ "width": 1
+ },
+ "DBGSUBMODE": {
+ "direction": "input",
+ "width": 1
+ },
+ "DBGVECA": {
+ "direction": "output",
+ "width": 64
+ },
+ "DBGVECB": {
+ "direction": "output",
+ "width": 64
+ },
+ "DBGVECC": {
+ "direction": "output",
+ "width": 12
+ },
+ "DLRSTN": {
+ "direction": "input",
+ "width": 1
+ },
+ "DRPADDR": {
+ "direction": "input",
+ "width": 9
+ },
+ "DRPCLK": {
+ "direction": "input",
+ "width": 1
+ },
+ "DRPDI": {
+ "direction": "input",
+ "width": 16
+ },
+ "DRPDO": {
+ "direction": "output",
+ "width": 16
+ },
+ "DRPEN": {
+ "direction": "input",
+ "width": 1
+ },
+ "DRPRDY": {
+ "direction": "output",
+ "width": 1
+ },
+ "DRPWE": {
+ "direction": "input",
+ "width": 1
+ },
+ "FUNCLVLRSTN": {
+ "direction": "input",
+ "width": 1
+ },
+ "LL2BADDLLPERR": {
+ "direction": "output",
+ "width": 1
+ },
+ "LL2BADTLPERR": {
+ "direction": "output",
+ "width": 1
+ },
+ "LL2LINKSTATUS": {
+ "direction": "output",
+ "width": 5
+ },
+ "LL2PROTOCOLERR": {
+ "direction": "output",
+ "width": 1
+ },
+ "LL2RECEIVERERR": {
+ "direction": "output",
+ "width": 1
+ },
+ "LL2REPLAYROERR": {
+ "direction": "output",
+ "width": 1
+ },
+ "LL2REPLAYTOERR": {
+ "direction": "output",
+ "width": 1
+ },
+ "LL2SENDASREQL1": {
+ "direction": "input",
+ "width": 1
+ },
+ "LL2SENDENTERL1": {
+ "direction": "input",
+ "width": 1
+ },
+ "LL2SENDENTERL23": {
+ "direction": "input",
+ "width": 1
+ },
+ "LL2SENDPMACK": {
+ "direction": "input",
+ "width": 1
+ },
+ "LL2SUSPENDNOW": {
+ "direction": "input",
+ "width": 1
+ },
+ "LL2SUSPENDOK": {
+ "direction": "output",
+ "width": 1
+ },
+ "LL2TFCINIT1SEQ": {
+ "direction": "output",
+ "width": 1
+ },
+ "LL2TFCINIT2SEQ": {
+ "direction": "output",
+ "width": 1
+ },
+ "LL2TLPRCV": {
+ "direction": "input",
+ "width": 1
+ },
+ "LL2TXIDLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "LNKCLKEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "MIMRXRADDR": {
+ "direction": "output",
+ "width": 13
+ },
+ "MIMRXRDATA": {
+ "direction": "input",
+ "width": 68
+ },
+ "MIMRXREN": {
+ "direction": "output",
+ "width": 1
+ },
+ "MIMRXWADDR": {
+ "direction": "output",
+ "width": 13
+ },
+ "MIMRXWDATA": {
+ "direction": "output",
+ "width": 68
+ },
+ "MIMRXWEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "MIMTXRADDR": {
+ "direction": "output",
+ "width": 13
+ },
+ "MIMTXRDATA": {
+ "direction": "input",
+ "width": 69
+ },
+ "MIMTXREN": {
+ "direction": "output",
+ "width": 1
+ },
+ "MIMTXWADDR": {
+ "direction": "output",
+ "width": 13
+ },
+ "MIMTXWDATA": {
+ "direction": "output",
+ "width": 69
+ },
+ "MIMTXWEN": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPECLK": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX0CHANISALIGNED": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX0CHARISK": {
+ "direction": "input",
+ "width": 2
+ },
+ "PIPERX0DATA": {
+ "direction": "input",
+ "width": 16
+ },
+ "PIPERX0ELECIDLE": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX0PHYSTATUS": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX0POLARITY": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPERX0STATUS": {
+ "direction": "input",
+ "width": 3
+ },
+ "PIPERX0VALID": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX1CHANISALIGNED": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX1CHARISK": {
+ "direction": "input",
+ "width": 2
+ },
+ "PIPERX1DATA": {
+ "direction": "input",
+ "width": 16
+ },
+ "PIPERX1ELECIDLE": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX1PHYSTATUS": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX1POLARITY": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPERX1STATUS": {
+ "direction": "input",
+ "width": 3
+ },
+ "PIPERX1VALID": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX2CHANISALIGNED": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX2CHARISK": {
+ "direction": "input",
+ "width": 2
+ },
+ "PIPERX2DATA": {
+ "direction": "input",
+ "width": 16
+ },
+ "PIPERX2ELECIDLE": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX2PHYSTATUS": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX2POLARITY": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPERX2STATUS": {
+ "direction": "input",
+ "width": 3
+ },
+ "PIPERX2VALID": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX3CHANISALIGNED": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX3CHARISK": {
+ "direction": "input",
+ "width": 2
+ },
+ "PIPERX3DATA": {
+ "direction": "input",
+ "width": 16
+ },
+ "PIPERX3ELECIDLE": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX3PHYSTATUS": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX3POLARITY": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPERX3STATUS": {
+ "direction": "input",
+ "width": 3
+ },
+ "PIPERX3VALID": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX4CHANISALIGNED": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX4CHARISK": {
+ "direction": "input",
+ "width": 2
+ },
+ "PIPERX4DATA": {
+ "direction": "input",
+ "width": 16
+ },
+ "PIPERX4ELECIDLE": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX4PHYSTATUS": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX4POLARITY": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPERX4STATUS": {
+ "direction": "input",
+ "width": 3
+ },
+ "PIPERX4VALID": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX5CHANISALIGNED": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX5CHARISK": {
+ "direction": "input",
+ "width": 2
+ },
+ "PIPERX5DATA": {
+ "direction": "input",
+ "width": 16
+ },
+ "PIPERX5ELECIDLE": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX5PHYSTATUS": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX5POLARITY": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPERX5STATUS": {
+ "direction": "input",
+ "width": 3
+ },
+ "PIPERX5VALID": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX6CHANISALIGNED": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX6CHARISK": {
+ "direction": "input",
+ "width": 2
+ },
+ "PIPERX6DATA": {
+ "direction": "input",
+ "width": 16
+ },
+ "PIPERX6ELECIDLE": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX6PHYSTATUS": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX6POLARITY": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPERX6STATUS": {
+ "direction": "input",
+ "width": 3
+ },
+ "PIPERX6VALID": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX7CHANISALIGNED": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX7CHARISK": {
+ "direction": "input",
+ "width": 2
+ },
+ "PIPERX7DATA": {
+ "direction": "input",
+ "width": 16
+ },
+ "PIPERX7ELECIDLE": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX7PHYSTATUS": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPERX7POLARITY": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPERX7STATUS": {
+ "direction": "input",
+ "width": 3
+ },
+ "PIPERX7VALID": {
+ "direction": "input",
+ "width": 1
+ },
+ "PIPETX0CHARISK": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETX0COMPLIANCE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX0DATA": {
+ "direction": "output",
+ "width": 16
+ },
+ "PIPETX0ELECIDLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX0POWERDOWN": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETX1CHARISK": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETX1COMPLIANCE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX1DATA": {
+ "direction": "output",
+ "width": 16
+ },
+ "PIPETX1ELECIDLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX1POWERDOWN": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETX2CHARISK": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETX2COMPLIANCE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX2DATA": {
+ "direction": "output",
+ "width": 16
+ },
+ "PIPETX2ELECIDLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX2POWERDOWN": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETX3CHARISK": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETX3COMPLIANCE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX3DATA": {
+ "direction": "output",
+ "width": 16
+ },
+ "PIPETX3ELECIDLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX3POWERDOWN": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETX4CHARISK": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETX4COMPLIANCE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX4DATA": {
+ "direction": "output",
+ "width": 16
+ },
+ "PIPETX4ELECIDLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX4POWERDOWN": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETX5CHARISK": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETX5COMPLIANCE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX5DATA": {
+ "direction": "output",
+ "width": 16
+ },
+ "PIPETX5ELECIDLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX5POWERDOWN": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETX6CHARISK": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETX6COMPLIANCE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX6DATA": {
+ "direction": "output",
+ "width": 16
+ },
+ "PIPETX6ELECIDLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX6POWERDOWN": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETX7CHARISK": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETX7COMPLIANCE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX7DATA": {
+ "direction": "output",
+ "width": 16
+ },
+ "PIPETX7ELECIDLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETX7POWERDOWN": {
+ "direction": "output",
+ "width": 2
+ },
+ "PIPETXDEEMPH": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETXMARGIN": {
+ "direction": "output",
+ "width": 3
+ },
+ "PIPETXRATE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETXRCVRDET": {
+ "direction": "output",
+ "width": 1
+ },
+ "PIPETXRESET": {
+ "direction": "output",
+ "width": 1
+ },
+ "PL2DIRECTEDLSTATE": {
+ "direction": "input",
+ "width": 5
+ },
+ "PL2L0REQ": {
+ "direction": "output",
+ "width": 1
+ },
+ "PL2LINKUP": {
+ "direction": "output",
+ "width": 1
+ },
+ "PL2RECEIVERERR": {
+ "direction": "output",
+ "width": 1
+ },
+ "PL2RECOVERY": {
+ "direction": "output",
+ "width": 1
+ },
+ "PL2RXELECIDLE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PL2RXPMSTATE": {
+ "direction": "output",
+ "width": 2
+ },
+ "PL2SUSPENDOK": {
+ "direction": "output",
+ "width": 1
+ },
+ "PLDBGMODE": {
+ "direction": "input",
+ "width": 3
+ },
+ "PLDBGVEC": {
+ "direction": "output",
+ "width": 12
+ },
+ "PLDIRECTEDCHANGEDONE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PLDIRECTEDLINKAUTON": {
+ "direction": "input",
+ "width": 1
+ },
+ "PLDIRECTEDLINKCHANGE": {
+ "direction": "input",
+ "width": 2
+ },
+ "PLDIRECTEDLINKSPEED": {
+ "direction": "input",
+ "width": 1
+ },
+ "PLDIRECTEDLINKWIDTH": {
+ "direction": "input",
+ "width": 2
+ },
+ "PLDIRECTEDLTSSMNEW": {
+ "direction": "input",
+ "width": 6
+ },
+ "PLDIRECTEDLTSSMNEWVLD": {
+ "direction": "input",
+ "width": 1
+ },
+ "PLDIRECTEDLTSSMSTALL": {
+ "direction": "input",
+ "width": 1
+ },
+ "PLDOWNSTREAMDEEMPHSOURCE": {
+ "direction": "input",
+ "width": 1
+ },
+ "PLINITIALLINKWIDTH": {
+ "direction": "output",
+ "width": 3
+ },
+ "PLLANEREVERSALMODE": {
+ "direction": "output",
+ "width": 2
+ },
+ "PLLINKGEN2CAP": {
+ "direction": "output",
+ "width": 1
+ },
+ "PLLINKPARTNERGEN2SUPPORTED": {
+ "direction": "output",
+ "width": 1
+ },
+ "PLLINKUPCFGCAP": {
+ "direction": "output",
+ "width": 1
+ },
+ "PLLTSSMSTATE": {
+ "direction": "output",
+ "width": 6
+ },
+ "PLPHYLNKUPN": {
+ "direction": "output",
+ "width": 1
+ },
+ "PLRECEIVEDHOTRST": {
+ "direction": "output",
+ "width": 1
+ },
+ "PLRSTN": {
+ "direction": "input",
+ "width": 1
+ },
+ "PLRXPMSTATE": {
+ "direction": "output",
+ "width": 2
+ },
+ "PLSELLNKRATE": {
+ "direction": "output",
+ "width": 1
+ },
+ "PLSELLNKWIDTH": {
+ "direction": "output",
+ "width": 2
+ },
+ "PLTRANSMITHOTRST": {
+ "direction": "input",
+ "width": 1
+ },
+ "PLTXPMSTATE": {
+ "direction": "output",
+ "width": 3
+ },
+ "PLUPSTREAMPREFERDEEMPH": {
+ "direction": "input",
+ "width": 1
+ },
+ "RECEIVEDFUNCLVLRSTN": {
+ "direction": "output",
+ "width": 1
+ },
+ "SYSRSTN": {
+ "direction": "input",
+ "width": 1
+ },
+ "TL2ASPMSUSPENDCREDITCHECK": {
+ "direction": "input",
+ "width": 1
+ },
+ "TL2ASPMSUSPENDCREDITCHECKOK": {
+ "direction": "output",
+ "width": 1
+ },
+ "TL2ASPMSUSPENDREQ": {
+ "direction": "output",
+ "width": 1
+ },
+ "TL2ERRFCPE": {
+ "direction": "output",
+ "width": 1
+ },
+ "TL2ERRHDR": {
+ "direction": "output",
+ "width": 64
+ },
+ "TL2ERRMALFORMED": {
+ "direction": "output",
+ "width": 1
+ },
+ "TL2ERRRXOVERFLOW": {
+ "direction": "output",
+ "width": 1
+ },
+ "TL2PPMSUSPENDOK": {
+ "direction": "output",
+ "width": 1
+ },
+ "TL2PPMSUSPENDREQ": {
+ "direction": "input",
+ "width": 1
+ },
+ "TLRSTN": {
+ "direction": "input",
+ "width": 1
+ },
+ "TRNFCCPLD": {
+ "direction": "output",
+ "width": 12
+ },
+ "TRNFCCPLH": {
+ "direction": "output",
+ "width": 8
+ },
+ "TRNFCNPD": {
+ "direction": "output",
+ "width": 12
+ },
+ "TRNFCNPH": {
+ "direction": "output",
+ "width": 8
+ },
+ "TRNFCPD": {
+ "direction": "output",
+ "width": 12
+ },
+ "TRNFCPH": {
+ "direction": "output",
+ "width": 8
+ },
+ "TRNFCSEL": {
+ "direction": "input",
+ "width": 3
+ },
+ "TRNLNKUP": {
+ "direction": "output",
+ "width": 1
+ },
+ "TRNRBARHIT": {
+ "direction": "output",
+ "width": 8
+ },
+ "TRNRD": {
+ "direction": "output",
+ "width": 128
+ },
+ "TRNRDLLPDATA": {
+ "direction": "output",
+ "width": 64
+ },
+ "TRNRDLLPSRCRDY": {
+ "direction": "output",
+ "width": 2
+ },
+ "TRNRDSTRDY": {
+ "direction": "input",
+ "width": 1
+ },
+ "TRNRECRCERR": {
+ "direction": "output",
+ "width": 1
+ },
+ "TRNREOF": {
+ "direction": "output",
+ "width": 1
+ },
+ "TRNRERRFWD": {
+ "direction": "output",
+ "width": 1
+ },
+ "TRNRFCPRET": {
+ "direction": "input",
+ "width": 1
+ },
+ "TRNRNPOK": {
+ "direction": "input",
+ "width": 1
+ },
+ "TRNRNPREQ": {
+ "direction": "input",
+ "width": 1
+ },
+ "TRNRREM": {
+ "direction": "output",
+ "width": 2
+ },
+ "TRNRSOF": {
+ "direction": "output",
+ "width": 1
+ },
+ "TRNRSRCDSC": {
+ "direction": "output",
+ "width": 1
+ },
+ "TRNRSRCRDY": {
+ "direction": "output",
+ "width": 1
+ },
+ "TRNTBUFAV": {
+ "direction": "output",
+ "width": 6
+ },
+ "TRNTCFGGNT": {
+ "direction": "input",
+ "width": 1
+ },
+ "TRNTCFGREQ": {
+ "direction": "output",
+ "width": 1
+ },
+ "TRNTD": {
+ "direction": "input",
+ "width": 128
+ },
+ "TRNTDLLPDATA": {
+ "direction": "input",
+ "width": 32
+ },
+ "TRNTDLLPDSTRDY": {
+ "direction": "output",
+ "width": 1
+ },
+ "TRNTDLLPSRCRDY": {
+ "direction": "input",
+ "width": 1
+ },
+ "TRNTDSTRDY": {
+ "direction": "output",
+ "width": 4
+ },
+ "TRNTECRCGEN": {
+ "direction": "input",
+ "width": 1
+ },
+ "TRNTEOF": {
+ "direction": "input",
+ "width": 1
+ },
+ "TRNTERRDROP": {
+ "direction": "output",
+ "width": 1
+ },
+ "TRNTERRFWD": {
+ "direction": "input",
+ "width": 1
+ },
+ "TRNTREM": {
+ "direction": "input",
+ "width": 2
+ },
+ "TRNTSOF": {
+ "direction": "input",
+ "width": 1
+ },
+ "TRNTSRCDSC": {
+ "direction": "input",
+ "width": 1
+ },
+ "TRNTSRCRDY": {
+ "direction": "input",
+ "width": 1
+ },
+ "TRNTSTR": {
+ "direction": "input",
+ "width": 1
+ },
+ "USERCLK": {
+ "direction": "input",
+ "width": 1
+ },
+ "USERCLK2": {
+ "direction": "input",
+ "width": 1
+ },
+ "USERRSTN": {
+ "direction": "output",
+ "width": 1
+ }
+}
diff --git a/artix7/mapping/parts.yaml b/artix7/mapping/parts.yaml
index d37e7cc..e58356d 100644
--- a/artix7/mapping/parts.yaml
+++ b/artix7/mapping/parts.yaml
@@ -1,37 +1,352 @@
-# part number to device, package and speed grade mapping
-"xc7a200tffg1156-1":
- device: "xc7a200t"
- package: "ffg1156"
- speedgrade: "1"
-"xc7a200tsbg484-1":
- device: "xc7a200t"
- package: "sbg484"
- speedgrade: "1"
-"xc7a100tfgg676-1":
- device: "xc7a100t"
- package: "fgg676"
- speedgrade: "1"
-"xc7a100tfgg484-2":
- device: "xc7a100t"
- package: "fgg484"
- speedgrade: "2"
-"xc7a100tcsg324-1":
- device: "xc7a100t"
- package: "csg324"
- speedgrade: "1"
-"xc7a50tfgg484-1":
- device: "xc7a50t"
- package: "fgg484"
- speedgrade: "1"
-"xc7a35tcsg324-1":
- device: "xc7a35t"
- package: "csg324"
- speedgrade: "1"
-"xc7a35tftg256-1":
- device: "xc7a35t"
- package: "ftg256"
- speedgrade: "1"
-"xc7a35tcpg236-1":
- device: "xc7a35t"
- package: "cpg236"
- speedgrade: "1"
+xc7a100tcsg324-1:
+ device: xc7a100t
+ package: csg324
+ speedgrade: '1'
+xc7a100tcsg324-2:
+ device: xc7a100t
+ package: csg324
+ speedgrade: '2'
+xc7a100tcsg324-2L:
+ device: xc7a100t
+ package: csg324
+ speedgrade: 2L
+xc7a100tcsg324-3:
+ device: xc7a100t
+ package: csg324
+ speedgrade: '3'
+xc7a100tfgg484-1:
+ device: xc7a100t
+ package: fgg484
+ speedgrade: '1'
+xc7a100tfgg484-2:
+ device: xc7a100t
+ package: fgg484
+ speedgrade: '2'
+xc7a100tfgg484-2L:
+ device: xc7a100t
+ package: fgg484
+ speedgrade: 2L
+xc7a100tfgg484-3:
+ device: xc7a100t
+ package: fgg484
+ speedgrade: '3'
+xc7a100tfgg676-1:
+ device: xc7a100t
+ package: fgg676
+ speedgrade: '1'
+xc7a100tfgg676-2:
+ device: xc7a100t
+ package: fgg676
+ speedgrade: '2'
+xc7a100tfgg676-2L:
+ device: xc7a100t
+ package: fgg676
+ speedgrade: 2L
+xc7a100tfgg676-3:
+ device: xc7a100t
+ package: fgg676
+ speedgrade: '3'
+xc7a100tftg256-1:
+ device: xc7a100t
+ package: ftg256
+ speedgrade: '1'
+xc7a100tftg256-2:
+ device: xc7a100t
+ package: ftg256
+ speedgrade: '2'
+xc7a100tftg256-2L:
+ device: xc7a100t
+ package: ftg256
+ speedgrade: 2L
+xc7a100tftg256-3:
+ device: xc7a100t
+ package: ftg256
+ speedgrade: '3'
+xc7a200tfbg484-1:
+ device: xc7a200t
+ package: fbg484
+ speedgrade: '1'
+xc7a200tfbg484-2:
+ device: xc7a200t
+ package: fbg484
+ speedgrade: '2'
+xc7a200tfbg484-2L:
+ device: xc7a200t
+ package: fbg484
+ speedgrade: 2L
+xc7a200tfbg484-3:
+ device: xc7a200t
+ package: fbg484
+ speedgrade: '3'
+xc7a200tfbg676-1:
+ device: xc7a200t
+ package: fbg676
+ speedgrade: '1'
+xc7a200tfbg676-2:
+ device: xc7a200t
+ package: fbg676
+ speedgrade: '2'
+xc7a200tfbg676-2L:
+ device: xc7a200t
+ package: fbg676
+ speedgrade: 2L
+xc7a200tfbg676-3:
+ device: xc7a200t
+ package: fbg676
+ speedgrade: '3'
+xc7a200tfbv484-1:
+ device: xc7a200t
+ package: fbv484
+ speedgrade: '1'
+xc7a200tfbv484-2:
+ device: xc7a200t
+ package: fbv484
+ speedgrade: '2'
+xc7a200tfbv484-2L:
+ device: xc7a200t
+ package: fbv484
+ speedgrade: 2L
+xc7a200tfbv484-3:
+ device: xc7a200t
+ package: fbv484
+ speedgrade: '3'
+xc7a200tfbv676-1:
+ device: xc7a200t
+ package: fbv676
+ speedgrade: '1'
+xc7a200tfbv676-2:
+ device: xc7a200t
+ package: fbv676
+ speedgrade: '2'
+xc7a200tfbv676-2L:
+ device: xc7a200t
+ package: fbv676
+ speedgrade: 2L
+xc7a200tfbv676-3:
+ device: xc7a200t
+ package: fbv676
+ speedgrade: '3'
+xc7a200tffg1156-1:
+ device: xc7a200t
+ package: ffg1156
+ speedgrade: '1'
+xc7a200tffg1156-2:
+ device: xc7a200t
+ package: ffg1156
+ speedgrade: '2'
+xc7a200tffg1156-2L:
+ device: xc7a200t
+ package: ffg1156
+ speedgrade: 2L
+xc7a200tffg1156-3:
+ device: xc7a200t
+ package: ffg1156
+ speedgrade: '3'
+xc7a200tffv1156-1:
+ device: xc7a200t
+ package: ffv1156
+ speedgrade: '1'
+xc7a200tffv1156-2:
+ device: xc7a200t
+ package: ffv1156
+ speedgrade: '2'
+xc7a200tffv1156-2L:
+ device: xc7a200t
+ package: ffv1156
+ speedgrade: 2L
+xc7a200tffv1156-3:
+ device: xc7a200t
+ package: ffv1156
+ speedgrade: '3'
+xc7a200tsbg484-1:
+ device: xc7a200t
+ package: sbg484
+ speedgrade: '1'
+xc7a200tsbg484-2:
+ device: xc7a200t
+ package: sbg484
+ speedgrade: '2'
+xc7a200tsbg484-2L:
+ device: xc7a200t
+ package: sbg484
+ speedgrade: 2L
+xc7a200tsbg484-3:
+ device: xc7a200t
+ package: sbg484
+ speedgrade: '3'
+xc7a200tsbv484-1:
+ device: xc7a200t
+ package: sbv484
+ speedgrade: '1'
+xc7a200tsbv484-2:
+ device: xc7a200t
+ package: sbv484
+ speedgrade: '2'
+xc7a200tsbv484-2L:
+ device: xc7a200t
+ package: sbv484
+ speedgrade: 2L
+xc7a200tsbv484-3:
+ device: xc7a200t
+ package: sbv484
+ speedgrade: '3'
+xc7a35tcpg236-1:
+ device: xc7a35t
+ package: cpg236
+ speedgrade: '1'
+xc7a35tcpg236-2:
+ device: xc7a35t
+ package: cpg236
+ speedgrade: '2'
+xc7a35tcpg236-2L:
+ device: xc7a35t
+ package: cpg236
+ speedgrade: 2L
+xc7a35tcpg236-3:
+ device: xc7a35t
+ package: cpg236
+ speedgrade: '3'
+xc7a35tcsg324-1:
+ device: xc7a35t
+ package: csg324
+ speedgrade: '1'
+xc7a35tcsg324-2:
+ device: xc7a35t
+ package: csg324
+ speedgrade: '2'
+xc7a35tcsg324-2L:
+ device: xc7a35t
+ package: csg324
+ speedgrade: 2L
+xc7a35tcsg324-3:
+ device: xc7a35t
+ package: csg324
+ speedgrade: '3'
+xc7a35tcsg325-1:
+ device: xc7a35t
+ package: csg325
+ speedgrade: '1'
+xc7a35tcsg325-2:
+ device: xc7a35t
+ package: csg325
+ speedgrade: '2'
+xc7a35tcsg325-2L:
+ device: xc7a35t
+ package: csg325
+ speedgrade: 2L
+xc7a35tcsg325-3:
+ device: xc7a35t
+ package: csg325
+ speedgrade: '3'
+xc7a35tfgg484-1:
+ device: xc7a35t
+ package: fgg484
+ speedgrade: '1'
+xc7a35tfgg484-2:
+ device: xc7a35t
+ package: fgg484
+ speedgrade: '2'
+xc7a35tfgg484-2L:
+ device: xc7a35t
+ package: fgg484
+ speedgrade: 2L
+xc7a35tfgg484-3:
+ device: xc7a35t
+ package: fgg484
+ speedgrade: '3'
+xc7a35tftg256-1:
+ device: xc7a35t
+ package: ftg256
+ speedgrade: '1'
+xc7a35tftg256-2:
+ device: xc7a35t
+ package: ftg256
+ speedgrade: '2'
+xc7a35tftg256-2L:
+ device: xc7a35t
+ package: ftg256
+ speedgrade: 2L
+xc7a35tftg256-3:
+ device: xc7a35t
+ package: ftg256
+ speedgrade: '3'
+xc7a50tcpg236-1:
+ device: xc7a50t
+ package: cpg236
+ speedgrade: '1'
+xc7a50tcpg236-2:
+ device: xc7a50t
+ package: cpg236
+ speedgrade: '2'
+xc7a50tcpg236-2L:
+ device: xc7a50t
+ package: cpg236
+ speedgrade: 2L
+xc7a50tcpg236-3:
+ device: xc7a50t
+ package: cpg236
+ speedgrade: '3'
+xc7a50tcsg324-1:
+ device: xc7a50t
+ package: csg324
+ speedgrade: '1'
+xc7a50tcsg324-2:
+ device: xc7a50t
+ package: csg324
+ speedgrade: '2'
+xc7a50tcsg324-2L:
+ device: xc7a50t
+ package: csg324
+ speedgrade: 2L
+xc7a50tcsg324-3:
+ device: xc7a50t
+ package: csg324
+ speedgrade: '3'
+xc7a50tcsg325-1:
+ device: xc7a50t
+ package: csg325
+ speedgrade: '1'
+xc7a50tcsg325-2:
+ device: xc7a50t
+ package: csg325
+ speedgrade: '2'
+xc7a50tcsg325-2L:
+ device: xc7a50t
+ package: csg325
+ speedgrade: 2L
+xc7a50tcsg325-3:
+ device: xc7a50t
+ package: csg325
+ speedgrade: '3'
+xc7a50tfgg484-1:
+ device: xc7a50t
+ package: fgg484
+ speedgrade: '1'
+xc7a50tfgg484-2:
+ device: xc7a50t
+ package: fgg484
+ speedgrade: '2'
+xc7a50tfgg484-2L:
+ device: xc7a50t
+ package: fgg484
+ speedgrade: 2L
+xc7a50tfgg484-3:
+ device: xc7a50t
+ package: fgg484
+ speedgrade: '3'
+xc7a50tftg256-1:
+ device: xc7a50t
+ package: ftg256
+ speedgrade: '1'
+xc7a50tftg256-2:
+ device: xc7a50t
+ package: ftg256
+ speedgrade: '2'
+xc7a50tftg256-2L:
+ device: xc7a50t
+ package: ftg256
+ speedgrade: 2L
+xc7a50tftg256-3:
+ device: xc7a50t
+ package: ftg256
+ speedgrade: '3'
diff --git a/artix7/mask_bram_l.db b/artix7/mask_bram_l.db
index d7b7f10..ecb0a63 100644
--- a/artix7/mask_bram_l.db
+++ b/artix7/mask_bram_l.db
@@ -1,51 +1,24 @@
-bit 00_22
bit 00_25
bit 00_26
bit 00_27
-bit 00_29
bit 00_30
-bit 00_34
-bit 00_37
-bit 00_39
-bit 00_41
bit 00_42
-bit 00_86
bit 00_89
bit 00_90
bit 00_91
-bit 00_93
bit 00_94
-bit 00_97
-bit 00_98
-bit 00_101
-bit 00_102
-bit 00_103
-bit 00_105
bit 00_106
bit 00_139
bit 00_145
-bit 00_203
-bit 00_214
bit 00_217
bit 00_218
bit 00_219
bit 00_222
-bit 00_226
-bit 00_227
-bit 00_229
-bit 00_231
-bit 00_233
bit 00_234
-bit 00_267
-bit 00_278
bit 00_281
bit 00_282
bit 00_283
bit 00_286
-bit 00_289
-bit 00_290
-bit 00_291
-bit 00_295
bit 00_298
bit 01_20
bit 01_21
@@ -59,6 +32,9 @@
bit 01_37
bit 01_38
bit 01_41
+bit 01_73
+bit 01_74
+bit 01_78
bit 01_84
bit 01_85
bit 01_88
@@ -92,6 +68,7 @@
bit 01_233
bit 01_265
bit 01_266
+bit 01_269
bit 01_270
bit 01_277
bit 01_280
@@ -100,28 +77,30 @@
bit 01_285
bit 01_288
bit 01_290
+bit 01_292
bit 01_293
bit 01_294
bit 01_297
bit 02_06
-bit 02_102
-bit 02_103
+bit 02_142
+bit 02_206
bit 02_253
-bit 02_298
-bit 02_299
+bit 02_270
bit 03_06
bit 03_94
bit 03_198
bit 03_230
bit 03_252
+bit 04_12
+bit 04_15
bit 04_254
bit 05_94
bit 05_198
bit 05_230
bit 06_03
bit 06_05
+bit 06_15
bit 06_19
-bit 06_21
bit 06_27
bit 06_35
bit 06_37
@@ -129,33 +108,34 @@
bit 06_49
bit 06_51
bit 06_53
-bit 06_61
bit 06_65
bit 06_67
bit 06_69
-bit 06_71
bit 06_83
bit 06_85
+bit 06_93
bit 06_99
bit 06_101
bit 06_115
+bit 06_117
bit 06_125
bit 06_131
bit 06_133
bit 06_147
+bit 06_149
bit 06_157
bit 06_163
bit 06_165
+bit 06_171
bit 06_211
bit 06_213
bit 06_227
-bit 06_235
bit 06_243
bit 06_251
bit 06_259
-bit 06_271
bit 06_275
bit 06_291
+bit 06_293
bit 06_299
bit 06_307
bit 06_309
@@ -167,19 +147,18 @@
bit 07_12
bit 07_14
bit 07_16
-bit 07_18
bit 07_22
bit 07_28
bit 07_32
bit 07_38
bit 07_42
bit 07_48
+bit 07_52
bit 07_54
-bit 07_58
bit 07_64
bit 07_66
-bit 07_68
bit 07_70
+bit 07_72
bit 07_74
bit 07_76
bit 07_78
@@ -187,15 +166,17 @@
bit 07_86
bit 07_94
bit 07_96
-bit 07_98
bit 07_102
bit 07_112
bit 07_118
+bit 07_122
bit 07_126
bit 07_128
bit 07_134
bit 07_136
+bit 07_140
bit 07_142
+bit 07_143
bit 07_144
bit 07_150
bit 07_152
@@ -206,48 +187,51 @@
bit 07_174
bit 07_176
bit 07_182
+bit 07_184
bit 07_190
bit 07_192
-bit 07_202
bit 07_206
+bit 07_207
bit 07_208
-bit 07_214
bit 07_218
bit 07_222
+bit 07_228
bit 07_234
bit 07_238
bit 07_244
bit 07_246
+bit 07_248
bit 07_250
bit 07_254
bit 07_256
bit 07_262
bit 07_266
bit 07_270
+bit 07_271
bit 07_272
bit 07_278
+bit 07_284
bit 07_286
bit 07_288
bit 07_294
bit 07_310
-bit 07_314
bit 08_00
-bit 08_05
+bit 08_03
bit 08_06
bit 08_07
+bit 08_12
bit 08_16
bit 08_17
+bit 08_18
bit 08_19
+bit 08_21
bit 08_22
bit 08_23
-bit 08_26
bit 08_27
-bit 08_29
bit 08_32
bit 08_33
-bit 08_34
-bit 08_35
bit 08_36
+bit 08_37
bit 08_38
bit 08_39
bit 08_45
@@ -263,39 +247,37 @@
bit 08_62
bit 08_64
bit 08_65
+bit 08_67
bit 08_68
bit 08_70
bit 08_71
-bit 08_74
bit 08_78
+bit 08_79
bit 08_80
bit 08_81
-bit 08_84
bit 08_86
bit 08_87
-bit 08_93
-bit 08_94
bit 08_96
bit 08_97
bit 08_101
bit 08_102
bit 08_103
-bit 08_106
bit 08_109
-bit 08_110
bit 08_112
bit 08_113
+bit 08_114
+bit 08_117
bit 08_118
bit 08_119
+bit 08_121
bit 08_126
bit 08_127
bit 08_128
bit 08_129
-bit 08_131
bit 08_134
bit 08_135
bit 08_136
-bit 08_137
+bit 08_142
bit 08_143
bit 08_144
bit 08_145
@@ -304,14 +286,13 @@
bit 08_152
bit 08_160
bit 08_161
-bit 08_164
bit 08_165
bit 08_166
bit 08_167
bit 08_168
+bit 08_169
bit 08_176
bit 08_177
-bit 08_178
bit 08_182
bit 08_183
bit 08_184
@@ -319,8 +300,10 @@
bit 08_191
bit 08_192
bit 08_193
+bit 08_195
bit 08_200
bit 08_207
+bit 08_213
bit 08_216
bit 08_222
bit 08_223
@@ -331,32 +314,29 @@
bit 08_248
bit 08_254
bit 08_264
-bit 08_271
+bit 08_267
+bit 08_269
bit 08_280
-bit 08_284
-bit 08_285
bit 08_287
bit 08_288
bit 08_292
bit 08_293
bit 08_296
-bit 08_301
bit 08_304
-bit 08_306
-bit 08_307
bit 08_308
+bit 08_311
bit 08_312
bit 09_02
bit 09_03
bit 09_04
-bit 09_05
-bit 09_06
-bit 09_07
bit 09_08
-bit 09_13
+bit 09_14
bit 09_16
bit 09_18
bit 09_19
+bit 09_21
+bit 09_24
+bit 09_28
bit 09_32
bit 09_34
bit 09_35
@@ -365,49 +345,44 @@
bit 09_48
bit 09_50
bit 09_51
-bit 09_56
bit 09_59
bit 09_66
bit 09_67
-bit 09_69
bit 09_72
+bit 09_74
bit 09_76
+bit 09_80
bit 09_82
bit 09_83
-bit 09_93
+bit 09_88
bit 09_96
bit 09_98
bit 09_99
-bit 09_104
bit 09_112
bit 09_114
bit 09_115
bit 09_120
+bit 09_125
bit 09_130
+bit 09_140
bit 09_141
bit 09_144
bit 09_146
bit 09_149
-bit 09_157
bit 09_160
bit 09_162
bit 09_176
bit 09_184
+bit 09_186
bit 09_188
-bit 09_204
-bit 09_209
-bit 09_248
+bit 09_245
bit 09_250
bit 09_252
-bit 09_260
-bit 09_265
bit 09_269
bit 09_272
bit 09_274
+bit 09_289
bit 09_290
-bit 09_291
-bit 09_296
-bit 09_303
bit 09_306
bit 09_307
bit 09_309
@@ -417,38 +392,39 @@
bit 10_04
bit 10_05
bit 10_07
-bit 10_09
bit 10_11
+bit 10_12
bit 10_13
-bit 10_16
+bit 10_15
bit 10_17
bit 10_18
+bit 10_20
bit 10_23
bit 10_26
+bit 10_32
bit 10_33
bit 10_34
-bit 10_40
+bit 10_36
bit 10_48
bit 10_49
bit 10_50
bit 10_55
-bit 10_56
-bit 10_64
bit 10_65
bit 10_66
-bit 10_68
+bit 10_67
bit 10_69
-bit 10_76
+bit 10_73
+bit 10_75
bit 10_77
bit 10_79
bit 10_81
bit 10_82
-bit 10_84
-bit 10_96
bit 10_97
bit 10_98
bit 10_113
bit 10_114
+bit 10_117
+bit 10_124
bit 10_127
bit 10_129
bit 10_130
@@ -456,55 +432,56 @@
bit 10_145
bit 10_146
bit 10_148
+bit 10_149
bit 10_161
bit 10_163
+bit 10_165
bit 10_175
bit 10_177
bit 10_181
-bit 10_191
+bit 10_185
bit 10_193
bit 10_194
bit 10_210
bit 10_226
bit 10_242
-bit 10_245
-bit 10_251
-bit 10_255
bit 10_257
bit 10_258
bit 10_272
bit 10_274
-bit 10_288
bit 10_290
-bit 10_292
-bit 10_304
bit 10_305
bit 10_306
bit 11_01
-bit 11_03
bit 11_04
-bit 11_06
+bit 11_05
bit 11_07
+bit 11_08
bit 11_11
+bit 11_12
+bit 11_14
bit 11_15
bit 11_17
bit 11_21
bit 11_23
-bit 11_29
+bit 11_27
bit 11_32
bit 11_33
+bit 11_35
bit 11_37
bit 11_39
-bit 11_45
bit 11_48
bit 11_49
bit 11_50
bit 11_55
+bit 11_61
bit 11_64
bit 11_65
bit 11_71
bit 11_72
+bit 11_74
bit 11_76
+bit 11_78
bit 11_79
bit 11_80
bit 11_81
@@ -512,13 +489,11 @@
bit 11_84
bit 11_85
bit 11_87
-bit 11_95
-bit 11_96
bit 11_97
bit 11_98
bit 11_100
-bit 11_101
bit 11_103
+bit 11_111
bit 11_112
bit 11_113
bit 11_114
@@ -529,9 +504,7 @@
bit 11_135
bit 11_143
bit 11_145
-bit 11_148
bit 11_149
-bit 11_151
bit 11_159
bit 11_161
bit 11_162
@@ -541,73 +514,77 @@
bit 11_183
bit 11_185
bit 11_186
+bit 11_188
bit 11_191
bit 11_193
bit 11_207
bit 11_215
bit 11_223
-bit 11_229
bit 11_239
bit 11_248
bit 11_250
+bit 11_252
bit 11_255
bit 11_257
bit 11_271
-bit 11_275
bit 11_279
bit 11_285
bit 11_287
-bit 11_288
bit 11_295
+bit 11_301
bit 11_303
+bit 11_309
bit 11_311
bit 12_02
bit 12_04
-bit 12_06
+bit 12_12
+bit 12_14
bit 12_16
bit 12_18
bit 12_20
+bit 12_24
bit 12_26
+bit 12_28
bit 12_32
bit 12_34
bit 12_36
-bit 12_40
bit 12_42
bit 12_48
bit 12_50
bit 12_52
-bit 12_56
bit 12_64
bit 12_66
bit 12_68
-bit 12_76
+bit 12_75
bit 12_82
bit 12_84
+bit 12_88
+bit 12_92
bit 12_96
bit 12_98
bit 12_100
-bit 12_104
bit 12_112
bit 12_114
+bit 12_116
+bit 12_124
bit 12_130
bit 12_132
+bit 12_140
bit 12_144
bit 12_146
bit 12_148
bit 12_156
-bit 12_161
-bit 12_165
+bit 12_170
bit 12_176
+bit 12_186
bit 12_193
bit 12_194
-bit 12_204
-bit 12_208
bit 12_210
bit 12_212
bit 12_226
-bit 12_234
bit 12_239
bit 12_242
+bit 12_244
bit 12_250
bit 12_255
bit 12_258
@@ -619,18 +596,18 @@
bit 12_287
bit 12_288
bit 12_290
-bit 12_296
+bit 12_292
bit 12_297
bit 12_298
-bit 12_302
-bit 12_304
bit 12_306
bit 12_308
bit 12_313
bit 13_01
+bit 13_03
bit 13_05
bit 13_07
bit 13_11
+bit 13_13
bit 13_17
bit 13_19
bit 13_21
@@ -638,7 +615,6 @@
bit 13_27
bit 13_29
bit 13_33
-bit 13_35
bit 13_37
bit 13_39
bit 13_45
@@ -647,28 +623,32 @@
bit 13_53
bit 13_55
bit 13_59
+bit 13_61
bit 13_65
+bit 13_67
+bit 13_69
bit 13_71
-bit 13_75
+bit 13_77
bit 13_79
bit 13_81
bit 13_85
bit 13_87
-bit 13_93
-bit 13_95
bit 13_97
-bit 13_99
bit 13_101
bit 13_103
-bit 13_107
bit 13_109
bit 13_111
bit 13_113
+bit 13_115
+bit 13_117
bit 13_119
+bit 13_121
+bit 13_123
bit 13_127
bit 13_129
bit 13_135
bit 13_137
+bit 13_141
bit 13_143
bit 13_145
bit 13_149
@@ -680,13 +660,14 @@
bit 13_169
bit 13_175
bit 13_177
-bit 13_179
bit 13_183
bit 13_191
bit 13_193
+bit 13_195
bit 13_201
bit 13_207
bit 13_209
+bit 13_213
bit 13_215
bit 13_217
bit 13_223
@@ -699,14 +680,10 @@
bit 13_255
bit 13_257
bit 13_263
-bit 13_264
bit 13_265
-bit 13_267
bit 13_268
-bit 13_270
bit 13_271
bit 13_273
-bit 13_275
bit 13_279
bit 13_281
bit 13_285
@@ -718,7 +695,6 @@
bit 13_301
bit 13_303
bit 13_305
-bit 13_307
bit 13_309
bit 13_311
bit 13_313
@@ -726,31 +702,28 @@
bit 14_03
bit 14_04
bit 14_05
-bit 14_09
bit 14_11
-bit 14_12
bit 14_13
+bit 14_15
bit 14_18
+bit 14_20
bit 14_32
bit 14_34
bit 14_36
bit 14_48
bit 14_50
-bit 14_56
bit 14_58
-bit 14_60
bit 14_64
bit 14_66
bit 14_67
bit 14_69
-bit 14_70
+bit 14_73
+bit 14_75
bit 14_77
bit 14_79
bit 14_80
bit 14_82
bit 14_84
-bit 14_92
-bit 14_96
bit 14_98
bit 14_100
bit 14_112
@@ -762,35 +735,30 @@
bit 14_140
bit 14_146
bit 14_148
-bit 14_156
bit 14_160
bit 14_162
bit 14_164
-bit 14_176
bit 14_181
-bit 14_191
+bit 14_185
bit 14_245
-bit 14_251
-bit 14_255
+bit 14_249
bit 14_258
-bit 14_260
+bit 14_272
bit 14_274
-bit 14_288
bit 14_290
-bit 14_292
bit 14_306
bit 15_01
bit 15_03
bit 15_04
-bit 15_06
bit 15_07
bit 15_08
bit 15_11
+bit 15_12
+bit 15_14
bit 15_15
bit 15_17
bit 15_19
bit 15_23
-bit 15_29
bit 15_33
bit 15_35
bit 15_37
@@ -800,32 +768,32 @@
bit 15_51
bit 15_53
bit 15_55
-bit 15_59
bit 15_61
bit 15_63
bit 15_65
bit 15_69
bit 15_71
bit 15_72
+bit 15_74
bit 15_75
bit 15_76
+bit 15_78
bit 15_79
bit 15_81
-bit 15_85
bit 15_87
bit 15_95
bit 15_97
-bit 15_101
bit 15_103
bit 15_113
+bit 15_117
bit 15_119
bit 15_127
bit 15_129
-bit 15_131
bit 15_135
bit 15_137
bit 15_143
bit 15_145
+bit 15_149
bit 15_151
bit 15_153
bit 15_159
@@ -844,9 +812,7 @@
bit 15_191
bit 15_193
bit 15_201
-bit 15_203
bit 15_207
-bit 15_215
bit 15_217
bit 15_219
bit 15_223
@@ -864,16 +830,15 @@
bit 15_257
bit 15_263
bit 15_265
+bit 15_267
+bit 15_269
bit 15_271
-bit 15_285
bit 15_287
-bit 15_293
bit 15_295
bit 15_297
bit 15_305
bit 15_311
bit 15_313
-bit 15_315
bit 16_23
bit 16_40
bit 16_48
@@ -893,7 +858,6 @@
bit 16_83
bit 16_84
bit 16_85
-bit 16_87
bit 16_90
bit 16_91
bit 16_92
@@ -938,7 +902,6 @@
bit 16_147
bit 16_148
bit 16_149
-bit 16_150
bit 16_151
bit 16_152
bit 16_153
@@ -988,6 +951,7 @@
bit 16_211
bit 16_212
bit 16_213
+bit 16_215
bit 16_216
bit 16_218
bit 16_219
@@ -1003,7 +967,6 @@
bit 16_235
bit 16_236
bit 16_237
-bit 16_240
bit 16_242
bit 16_243
bit 16_244
@@ -1012,38 +975,43 @@
bit 16_296
bit 16_304
bit 17_23
-bit 17_40
bit 17_66
bit 17_67
bit 17_68
bit 17_82
-bit 17_83
+bit 17_84
bit 17_87
+bit 17_96
+bit 17_104
bit 17_119
bit 17_127
bit 17_135
bit 17_146
+bit 17_147
bit 17_148
bit 17_149
bit 17_150
bit 17_151
bit 17_153
bit 17_154
-bit 17_156
+bit 17_155
bit 17_157
bit 17_158
+bit 17_160
+bit 17_161
bit 17_168
bit 17_169
bit 17_170
bit 17_171
bit 17_173
bit 17_184
-bit 17_296
+bit 17_279
bit 17_304
bit 18_46
+bit 18_49
bit 18_54
bit 18_62
-bit 18_65
+bit 18_66
bit 18_67
bit 18_68
bit 18_69
@@ -1053,12 +1021,10 @@
bit 18_76
bit 18_77
bit 18_78
-bit 18_81
bit 18_82
bit 18_83
bit 18_84
bit 18_85
-bit 18_86
bit 18_90
bit 18_91
bit 18_92
@@ -1083,7 +1049,6 @@
bit 18_123
bit 18_124
bit 18_125
-bit 18_126
bit 18_130
bit 18_131
bit 18_132
@@ -1099,7 +1064,6 @@
bit 18_147
bit 18_148
bit 18_149
-bit 18_150
bit 18_151
bit 18_152
bit 18_154
@@ -1107,7 +1071,9 @@
bit 18_156
bit 18_157
bit 18_158
+bit 18_159
bit 18_160
+bit 18_161
bit 18_162
bit 18_163
bit 18_164
@@ -1129,7 +1095,6 @@
bit 18_181
bit 18_182
bit 18_183
-bit 18_185
bit 18_190
bit 18_194
bit 18_195
@@ -1167,12 +1132,11 @@
bit 18_244
bit 18_245
bit 18_294
-bit 19_41
bit 19_54
bit 19_62
bit 19_66
+bit 19_67
bit 19_68
-bit 19_69
bit 19_70
bit 19_74
bit 19_75
@@ -1188,6 +1152,7 @@
bit 19_92
bit 19_93
bit 19_94
+bit 19_97
bit 19_98
bit 19_99
bit 19_100
@@ -1221,6 +1186,7 @@
bit 19_142
bit 19_146
bit 19_147
+bit 19_148
bit 19_149
bit 19_150
bit 19_151
@@ -1229,7 +1195,6 @@
bit 19_155
bit 19_156
bit 19_157
-bit 19_158
bit 19_159
bit 19_160
bit 19_162
@@ -1286,7 +1251,6 @@
bit 19_235
bit 19_236
bit 19_237
-bit 19_241
bit 19_242
bit 19_243
bit 19_244
@@ -1448,6 +1412,7 @@
bit 22_92
bit 22_93
bit 22_95
+bit 22_96
bit 22_98
bit 22_99
bit 22_100
@@ -1492,6 +1457,7 @@
bit 22_157
bit 22_158
bit 22_159
+bit 22_160
bit 22_161
bit 22_162
bit 22_163
@@ -1529,6 +1495,7 @@
bit 22_211
bit 22_212
bit 22_213
+bit 22_215
bit 22_218
bit 22_219
bit 22_220
@@ -1543,38 +1510,40 @@
bit 22_235
bit 22_236
bit 22_237
+bit 22_240
bit 22_242
bit 22_243
bit 22_244
bit 22_245
bit 22_296
bit 23_23
+bit 23_40
+bit 23_48
bit 23_55
bit 23_66
bit 23_67
bit 23_68
bit 23_69
+bit 23_71
bit 23_80
bit 23_82
bit 23_83
bit 23_84
bit 23_85
-bit 23_87
bit 23_104
bit 23_127
-bit 23_135
bit 23_143
bit 23_146
+bit 23_147
bit 23_148
bit 23_149
bit 23_150
bit 23_153
bit 23_154
bit 23_155
-bit 23_156
bit 23_157
bit 23_158
-bit 23_159
+bit 23_160
bit 23_161
bit 23_168
bit 23_169
@@ -1586,7 +1555,6 @@
bit 23_175
bit 23_184
bit 23_192
-bit 23_240
bit 23_279
bit 23_295
bit 23_304
@@ -1596,7 +1564,6 @@
bit 24_48
bit 24_55
bit 24_63
-bit 24_64
bit 24_66
bit 24_67
bit 24_68
@@ -1612,7 +1579,6 @@
bit 24_83
bit 24_84
bit 24_85
-bit 24_87
bit 24_90
bit 24_91
bit 24_92
@@ -1710,6 +1676,7 @@
bit 24_211
bit 24_212
bit 24_213
+bit 24_215
bit 24_216
bit 24_218
bit 24_219
@@ -1739,6 +1706,7 @@
bit 24_304
bit 25_23
bit 25_40
+bit 25_48
bit 25_55
bit 25_66
bit 25_67
@@ -1753,6 +1721,7 @@
bit 25_85
bit 25_87
bit 25_95
+bit 25_96
bit 25_104
bit 25_119
bit 25_127
@@ -1775,6 +1744,7 @@
bit 25_157
bit 25_158
bit 25_159
+bit 25_160
bit 25_161
bit 25_168
bit 25_169
@@ -1791,6 +1761,7 @@
bit 25_184
bit 25_188
bit 25_192
+bit 25_215
bit 25_232
bit 25_240
bit 25_279
diff --git a/artix7/mask_bram_r.db b/artix7/mask_bram_r.db
index d7b7f10..ecb0a63 100644
--- a/artix7/mask_bram_r.db
+++ b/artix7/mask_bram_r.db
@@ -1,51 +1,24 @@
-bit 00_22
bit 00_25
bit 00_26
bit 00_27
-bit 00_29
bit 00_30
-bit 00_34
-bit 00_37
-bit 00_39
-bit 00_41
bit 00_42
-bit 00_86
bit 00_89
bit 00_90
bit 00_91
-bit 00_93
bit 00_94
-bit 00_97
-bit 00_98
-bit 00_101
-bit 00_102
-bit 00_103
-bit 00_105
bit 00_106
bit 00_139
bit 00_145
-bit 00_203
-bit 00_214
bit 00_217
bit 00_218
bit 00_219
bit 00_222
-bit 00_226
-bit 00_227
-bit 00_229
-bit 00_231
-bit 00_233
bit 00_234
-bit 00_267
-bit 00_278
bit 00_281
bit 00_282
bit 00_283
bit 00_286
-bit 00_289
-bit 00_290
-bit 00_291
-bit 00_295
bit 00_298
bit 01_20
bit 01_21
@@ -59,6 +32,9 @@
bit 01_37
bit 01_38
bit 01_41
+bit 01_73
+bit 01_74
+bit 01_78
bit 01_84
bit 01_85
bit 01_88
@@ -92,6 +68,7 @@
bit 01_233
bit 01_265
bit 01_266
+bit 01_269
bit 01_270
bit 01_277
bit 01_280
@@ -100,28 +77,30 @@
bit 01_285
bit 01_288
bit 01_290
+bit 01_292
bit 01_293
bit 01_294
bit 01_297
bit 02_06
-bit 02_102
-bit 02_103
+bit 02_142
+bit 02_206
bit 02_253
-bit 02_298
-bit 02_299
+bit 02_270
bit 03_06
bit 03_94
bit 03_198
bit 03_230
bit 03_252
+bit 04_12
+bit 04_15
bit 04_254
bit 05_94
bit 05_198
bit 05_230
bit 06_03
bit 06_05
+bit 06_15
bit 06_19
-bit 06_21
bit 06_27
bit 06_35
bit 06_37
@@ -129,33 +108,34 @@
bit 06_49
bit 06_51
bit 06_53
-bit 06_61
bit 06_65
bit 06_67
bit 06_69
-bit 06_71
bit 06_83
bit 06_85
+bit 06_93
bit 06_99
bit 06_101
bit 06_115
+bit 06_117
bit 06_125
bit 06_131
bit 06_133
bit 06_147
+bit 06_149
bit 06_157
bit 06_163
bit 06_165
+bit 06_171
bit 06_211
bit 06_213
bit 06_227
-bit 06_235
bit 06_243
bit 06_251
bit 06_259
-bit 06_271
bit 06_275
bit 06_291
+bit 06_293
bit 06_299
bit 06_307
bit 06_309
@@ -167,19 +147,18 @@
bit 07_12
bit 07_14
bit 07_16
-bit 07_18
bit 07_22
bit 07_28
bit 07_32
bit 07_38
bit 07_42
bit 07_48
+bit 07_52
bit 07_54
-bit 07_58
bit 07_64
bit 07_66
-bit 07_68
bit 07_70
+bit 07_72
bit 07_74
bit 07_76
bit 07_78
@@ -187,15 +166,17 @@
bit 07_86
bit 07_94
bit 07_96
-bit 07_98
bit 07_102
bit 07_112
bit 07_118
+bit 07_122
bit 07_126
bit 07_128
bit 07_134
bit 07_136
+bit 07_140
bit 07_142
+bit 07_143
bit 07_144
bit 07_150
bit 07_152
@@ -206,48 +187,51 @@
bit 07_174
bit 07_176
bit 07_182
+bit 07_184
bit 07_190
bit 07_192
-bit 07_202
bit 07_206
+bit 07_207
bit 07_208
-bit 07_214
bit 07_218
bit 07_222
+bit 07_228
bit 07_234
bit 07_238
bit 07_244
bit 07_246
+bit 07_248
bit 07_250
bit 07_254
bit 07_256
bit 07_262
bit 07_266
bit 07_270
+bit 07_271
bit 07_272
bit 07_278
+bit 07_284
bit 07_286
bit 07_288
bit 07_294
bit 07_310
-bit 07_314
bit 08_00
-bit 08_05
+bit 08_03
bit 08_06
bit 08_07
+bit 08_12
bit 08_16
bit 08_17
+bit 08_18
bit 08_19
+bit 08_21
bit 08_22
bit 08_23
-bit 08_26
bit 08_27
-bit 08_29
bit 08_32
bit 08_33
-bit 08_34
-bit 08_35
bit 08_36
+bit 08_37
bit 08_38
bit 08_39
bit 08_45
@@ -263,39 +247,37 @@
bit 08_62
bit 08_64
bit 08_65
+bit 08_67
bit 08_68
bit 08_70
bit 08_71
-bit 08_74
bit 08_78
+bit 08_79
bit 08_80
bit 08_81
-bit 08_84
bit 08_86
bit 08_87
-bit 08_93
-bit 08_94
bit 08_96
bit 08_97
bit 08_101
bit 08_102
bit 08_103
-bit 08_106
bit 08_109
-bit 08_110
bit 08_112
bit 08_113
+bit 08_114
+bit 08_117
bit 08_118
bit 08_119
+bit 08_121
bit 08_126
bit 08_127
bit 08_128
bit 08_129
-bit 08_131
bit 08_134
bit 08_135
bit 08_136
-bit 08_137
+bit 08_142
bit 08_143
bit 08_144
bit 08_145
@@ -304,14 +286,13 @@
bit 08_152
bit 08_160
bit 08_161
-bit 08_164
bit 08_165
bit 08_166
bit 08_167
bit 08_168
+bit 08_169
bit 08_176
bit 08_177
-bit 08_178
bit 08_182
bit 08_183
bit 08_184
@@ -319,8 +300,10 @@
bit 08_191
bit 08_192
bit 08_193
+bit 08_195
bit 08_200
bit 08_207
+bit 08_213
bit 08_216
bit 08_222
bit 08_223
@@ -331,32 +314,29 @@
bit 08_248
bit 08_254
bit 08_264
-bit 08_271
+bit 08_267
+bit 08_269
bit 08_280
-bit 08_284
-bit 08_285
bit 08_287
bit 08_288
bit 08_292
bit 08_293
bit 08_296
-bit 08_301
bit 08_304
-bit 08_306
-bit 08_307
bit 08_308
+bit 08_311
bit 08_312
bit 09_02
bit 09_03
bit 09_04
-bit 09_05
-bit 09_06
-bit 09_07
bit 09_08
-bit 09_13
+bit 09_14
bit 09_16
bit 09_18
bit 09_19
+bit 09_21
+bit 09_24
+bit 09_28
bit 09_32
bit 09_34
bit 09_35
@@ -365,49 +345,44 @@
bit 09_48
bit 09_50
bit 09_51
-bit 09_56
bit 09_59
bit 09_66
bit 09_67
-bit 09_69
bit 09_72
+bit 09_74
bit 09_76
+bit 09_80
bit 09_82
bit 09_83
-bit 09_93
+bit 09_88
bit 09_96
bit 09_98
bit 09_99
-bit 09_104
bit 09_112
bit 09_114
bit 09_115
bit 09_120
+bit 09_125
bit 09_130
+bit 09_140
bit 09_141
bit 09_144
bit 09_146
bit 09_149
-bit 09_157
bit 09_160
bit 09_162
bit 09_176
bit 09_184
+bit 09_186
bit 09_188
-bit 09_204
-bit 09_209
-bit 09_248
+bit 09_245
bit 09_250
bit 09_252
-bit 09_260
-bit 09_265
bit 09_269
bit 09_272
bit 09_274
+bit 09_289
bit 09_290
-bit 09_291
-bit 09_296
-bit 09_303
bit 09_306
bit 09_307
bit 09_309
@@ -417,38 +392,39 @@
bit 10_04
bit 10_05
bit 10_07
-bit 10_09
bit 10_11
+bit 10_12
bit 10_13
-bit 10_16
+bit 10_15
bit 10_17
bit 10_18
+bit 10_20
bit 10_23
bit 10_26
+bit 10_32
bit 10_33
bit 10_34
-bit 10_40
+bit 10_36
bit 10_48
bit 10_49
bit 10_50
bit 10_55
-bit 10_56
-bit 10_64
bit 10_65
bit 10_66
-bit 10_68
+bit 10_67
bit 10_69
-bit 10_76
+bit 10_73
+bit 10_75
bit 10_77
bit 10_79
bit 10_81
bit 10_82
-bit 10_84
-bit 10_96
bit 10_97
bit 10_98
bit 10_113
bit 10_114
+bit 10_117
+bit 10_124
bit 10_127
bit 10_129
bit 10_130
@@ -456,55 +432,56 @@
bit 10_145
bit 10_146
bit 10_148
+bit 10_149
bit 10_161
bit 10_163
+bit 10_165
bit 10_175
bit 10_177
bit 10_181
-bit 10_191
+bit 10_185
bit 10_193
bit 10_194
bit 10_210
bit 10_226
bit 10_242
-bit 10_245
-bit 10_251
-bit 10_255
bit 10_257
bit 10_258
bit 10_272
bit 10_274
-bit 10_288
bit 10_290
-bit 10_292
-bit 10_304
bit 10_305
bit 10_306
bit 11_01
-bit 11_03
bit 11_04
-bit 11_06
+bit 11_05
bit 11_07
+bit 11_08
bit 11_11
+bit 11_12
+bit 11_14
bit 11_15
bit 11_17
bit 11_21
bit 11_23
-bit 11_29
+bit 11_27
bit 11_32
bit 11_33
+bit 11_35
bit 11_37
bit 11_39
-bit 11_45
bit 11_48
bit 11_49
bit 11_50
bit 11_55
+bit 11_61
bit 11_64
bit 11_65
bit 11_71
bit 11_72
+bit 11_74
bit 11_76
+bit 11_78
bit 11_79
bit 11_80
bit 11_81
@@ -512,13 +489,11 @@
bit 11_84
bit 11_85
bit 11_87
-bit 11_95
-bit 11_96
bit 11_97
bit 11_98
bit 11_100
-bit 11_101
bit 11_103
+bit 11_111
bit 11_112
bit 11_113
bit 11_114
@@ -529,9 +504,7 @@
bit 11_135
bit 11_143
bit 11_145
-bit 11_148
bit 11_149
-bit 11_151
bit 11_159
bit 11_161
bit 11_162
@@ -541,73 +514,77 @@
bit 11_183
bit 11_185
bit 11_186
+bit 11_188
bit 11_191
bit 11_193
bit 11_207
bit 11_215
bit 11_223
-bit 11_229
bit 11_239
bit 11_248
bit 11_250
+bit 11_252
bit 11_255
bit 11_257
bit 11_271
-bit 11_275
bit 11_279
bit 11_285
bit 11_287
-bit 11_288
bit 11_295
+bit 11_301
bit 11_303
+bit 11_309
bit 11_311
bit 12_02
bit 12_04
-bit 12_06
+bit 12_12
+bit 12_14
bit 12_16
bit 12_18
bit 12_20
+bit 12_24
bit 12_26
+bit 12_28
bit 12_32
bit 12_34
bit 12_36
-bit 12_40
bit 12_42
bit 12_48
bit 12_50
bit 12_52
-bit 12_56
bit 12_64
bit 12_66
bit 12_68
-bit 12_76
+bit 12_75
bit 12_82
bit 12_84
+bit 12_88
+bit 12_92
bit 12_96
bit 12_98
bit 12_100
-bit 12_104
bit 12_112
bit 12_114
+bit 12_116
+bit 12_124
bit 12_130
bit 12_132
+bit 12_140
bit 12_144
bit 12_146
bit 12_148
bit 12_156
-bit 12_161
-bit 12_165
+bit 12_170
bit 12_176
+bit 12_186
bit 12_193
bit 12_194
-bit 12_204
-bit 12_208
bit 12_210
bit 12_212
bit 12_226
-bit 12_234
bit 12_239
bit 12_242
+bit 12_244
bit 12_250
bit 12_255
bit 12_258
@@ -619,18 +596,18 @@
bit 12_287
bit 12_288
bit 12_290
-bit 12_296
+bit 12_292
bit 12_297
bit 12_298
-bit 12_302
-bit 12_304
bit 12_306
bit 12_308
bit 12_313
bit 13_01
+bit 13_03
bit 13_05
bit 13_07
bit 13_11
+bit 13_13
bit 13_17
bit 13_19
bit 13_21
@@ -638,7 +615,6 @@
bit 13_27
bit 13_29
bit 13_33
-bit 13_35
bit 13_37
bit 13_39
bit 13_45
@@ -647,28 +623,32 @@
bit 13_53
bit 13_55
bit 13_59
+bit 13_61
bit 13_65
+bit 13_67
+bit 13_69
bit 13_71
-bit 13_75
+bit 13_77
bit 13_79
bit 13_81
bit 13_85
bit 13_87
-bit 13_93
-bit 13_95
bit 13_97
-bit 13_99
bit 13_101
bit 13_103
-bit 13_107
bit 13_109
bit 13_111
bit 13_113
+bit 13_115
+bit 13_117
bit 13_119
+bit 13_121
+bit 13_123
bit 13_127
bit 13_129
bit 13_135
bit 13_137
+bit 13_141
bit 13_143
bit 13_145
bit 13_149
@@ -680,13 +660,14 @@
bit 13_169
bit 13_175
bit 13_177
-bit 13_179
bit 13_183
bit 13_191
bit 13_193
+bit 13_195
bit 13_201
bit 13_207
bit 13_209
+bit 13_213
bit 13_215
bit 13_217
bit 13_223
@@ -699,14 +680,10 @@
bit 13_255
bit 13_257
bit 13_263
-bit 13_264
bit 13_265
-bit 13_267
bit 13_268
-bit 13_270
bit 13_271
bit 13_273
-bit 13_275
bit 13_279
bit 13_281
bit 13_285
@@ -718,7 +695,6 @@
bit 13_301
bit 13_303
bit 13_305
-bit 13_307
bit 13_309
bit 13_311
bit 13_313
@@ -726,31 +702,28 @@
bit 14_03
bit 14_04
bit 14_05
-bit 14_09
bit 14_11
-bit 14_12
bit 14_13
+bit 14_15
bit 14_18
+bit 14_20
bit 14_32
bit 14_34
bit 14_36
bit 14_48
bit 14_50
-bit 14_56
bit 14_58
-bit 14_60
bit 14_64
bit 14_66
bit 14_67
bit 14_69
-bit 14_70
+bit 14_73
+bit 14_75
bit 14_77
bit 14_79
bit 14_80
bit 14_82
bit 14_84
-bit 14_92
-bit 14_96
bit 14_98
bit 14_100
bit 14_112
@@ -762,35 +735,30 @@
bit 14_140
bit 14_146
bit 14_148
-bit 14_156
bit 14_160
bit 14_162
bit 14_164
-bit 14_176
bit 14_181
-bit 14_191
+bit 14_185
bit 14_245
-bit 14_251
-bit 14_255
+bit 14_249
bit 14_258
-bit 14_260
+bit 14_272
bit 14_274
-bit 14_288
bit 14_290
-bit 14_292
bit 14_306
bit 15_01
bit 15_03
bit 15_04
-bit 15_06
bit 15_07
bit 15_08
bit 15_11
+bit 15_12
+bit 15_14
bit 15_15
bit 15_17
bit 15_19
bit 15_23
-bit 15_29
bit 15_33
bit 15_35
bit 15_37
@@ -800,32 +768,32 @@
bit 15_51
bit 15_53
bit 15_55
-bit 15_59
bit 15_61
bit 15_63
bit 15_65
bit 15_69
bit 15_71
bit 15_72
+bit 15_74
bit 15_75
bit 15_76
+bit 15_78
bit 15_79
bit 15_81
-bit 15_85
bit 15_87
bit 15_95
bit 15_97
-bit 15_101
bit 15_103
bit 15_113
+bit 15_117
bit 15_119
bit 15_127
bit 15_129
-bit 15_131
bit 15_135
bit 15_137
bit 15_143
bit 15_145
+bit 15_149
bit 15_151
bit 15_153
bit 15_159
@@ -844,9 +812,7 @@
bit 15_191
bit 15_193
bit 15_201
-bit 15_203
bit 15_207
-bit 15_215
bit 15_217
bit 15_219
bit 15_223
@@ -864,16 +830,15 @@
bit 15_257
bit 15_263
bit 15_265
+bit 15_267
+bit 15_269
bit 15_271
-bit 15_285
bit 15_287
-bit 15_293
bit 15_295
bit 15_297
bit 15_305
bit 15_311
bit 15_313
-bit 15_315
bit 16_23
bit 16_40
bit 16_48
@@ -893,7 +858,6 @@
bit 16_83
bit 16_84
bit 16_85
-bit 16_87
bit 16_90
bit 16_91
bit 16_92
@@ -938,7 +902,6 @@
bit 16_147
bit 16_148
bit 16_149
-bit 16_150
bit 16_151
bit 16_152
bit 16_153
@@ -988,6 +951,7 @@
bit 16_211
bit 16_212
bit 16_213
+bit 16_215
bit 16_216
bit 16_218
bit 16_219
@@ -1003,7 +967,6 @@
bit 16_235
bit 16_236
bit 16_237
-bit 16_240
bit 16_242
bit 16_243
bit 16_244
@@ -1012,38 +975,43 @@
bit 16_296
bit 16_304
bit 17_23
-bit 17_40
bit 17_66
bit 17_67
bit 17_68
bit 17_82
-bit 17_83
+bit 17_84
bit 17_87
+bit 17_96
+bit 17_104
bit 17_119
bit 17_127
bit 17_135
bit 17_146
+bit 17_147
bit 17_148
bit 17_149
bit 17_150
bit 17_151
bit 17_153
bit 17_154
-bit 17_156
+bit 17_155
bit 17_157
bit 17_158
+bit 17_160
+bit 17_161
bit 17_168
bit 17_169
bit 17_170
bit 17_171
bit 17_173
bit 17_184
-bit 17_296
+bit 17_279
bit 17_304
bit 18_46
+bit 18_49
bit 18_54
bit 18_62
-bit 18_65
+bit 18_66
bit 18_67
bit 18_68
bit 18_69
@@ -1053,12 +1021,10 @@
bit 18_76
bit 18_77
bit 18_78
-bit 18_81
bit 18_82
bit 18_83
bit 18_84
bit 18_85
-bit 18_86
bit 18_90
bit 18_91
bit 18_92
@@ -1083,7 +1049,6 @@
bit 18_123
bit 18_124
bit 18_125
-bit 18_126
bit 18_130
bit 18_131
bit 18_132
@@ -1099,7 +1064,6 @@
bit 18_147
bit 18_148
bit 18_149
-bit 18_150
bit 18_151
bit 18_152
bit 18_154
@@ -1107,7 +1071,9 @@
bit 18_156
bit 18_157
bit 18_158
+bit 18_159
bit 18_160
+bit 18_161
bit 18_162
bit 18_163
bit 18_164
@@ -1129,7 +1095,6 @@
bit 18_181
bit 18_182
bit 18_183
-bit 18_185
bit 18_190
bit 18_194
bit 18_195
@@ -1167,12 +1132,11 @@
bit 18_244
bit 18_245
bit 18_294
-bit 19_41
bit 19_54
bit 19_62
bit 19_66
+bit 19_67
bit 19_68
-bit 19_69
bit 19_70
bit 19_74
bit 19_75
@@ -1188,6 +1152,7 @@
bit 19_92
bit 19_93
bit 19_94
+bit 19_97
bit 19_98
bit 19_99
bit 19_100
@@ -1221,6 +1186,7 @@
bit 19_142
bit 19_146
bit 19_147
+bit 19_148
bit 19_149
bit 19_150
bit 19_151
@@ -1229,7 +1195,6 @@
bit 19_155
bit 19_156
bit 19_157
-bit 19_158
bit 19_159
bit 19_160
bit 19_162
@@ -1286,7 +1251,6 @@
bit 19_235
bit 19_236
bit 19_237
-bit 19_241
bit 19_242
bit 19_243
bit 19_244
@@ -1448,6 +1412,7 @@
bit 22_92
bit 22_93
bit 22_95
+bit 22_96
bit 22_98
bit 22_99
bit 22_100
@@ -1492,6 +1457,7 @@
bit 22_157
bit 22_158
bit 22_159
+bit 22_160
bit 22_161
bit 22_162
bit 22_163
@@ -1529,6 +1495,7 @@
bit 22_211
bit 22_212
bit 22_213
+bit 22_215
bit 22_218
bit 22_219
bit 22_220
@@ -1543,38 +1510,40 @@
bit 22_235
bit 22_236
bit 22_237
+bit 22_240
bit 22_242
bit 22_243
bit 22_244
bit 22_245
bit 22_296
bit 23_23
+bit 23_40
+bit 23_48
bit 23_55
bit 23_66
bit 23_67
bit 23_68
bit 23_69
+bit 23_71
bit 23_80
bit 23_82
bit 23_83
bit 23_84
bit 23_85
-bit 23_87
bit 23_104
bit 23_127
-bit 23_135
bit 23_143
bit 23_146
+bit 23_147
bit 23_148
bit 23_149
bit 23_150
bit 23_153
bit 23_154
bit 23_155
-bit 23_156
bit 23_157
bit 23_158
-bit 23_159
+bit 23_160
bit 23_161
bit 23_168
bit 23_169
@@ -1586,7 +1555,6 @@
bit 23_175
bit 23_184
bit 23_192
-bit 23_240
bit 23_279
bit 23_295
bit 23_304
@@ -1596,7 +1564,6 @@
bit 24_48
bit 24_55
bit 24_63
-bit 24_64
bit 24_66
bit 24_67
bit 24_68
@@ -1612,7 +1579,6 @@
bit 24_83
bit 24_84
bit 24_85
-bit 24_87
bit 24_90
bit 24_91
bit 24_92
@@ -1710,6 +1676,7 @@
bit 24_211
bit 24_212
bit 24_213
+bit 24_215
bit 24_216
bit 24_218
bit 24_219
@@ -1739,6 +1706,7 @@
bit 24_304
bit 25_23
bit 25_40
+bit 25_48
bit 25_55
bit 25_66
bit 25_67
@@ -1753,6 +1721,7 @@
bit 25_85
bit 25_87
bit 25_95
+bit 25_96
bit 25_104
bit 25_119
bit 25_127
@@ -1775,6 +1744,7 @@
bit 25_157
bit 25_158
bit 25_159
+bit 25_160
bit 25_161
bit 25_168
bit 25_169
@@ -1791,6 +1761,7 @@
bit 25_184
bit 25_188
bit 25_192
+bit 25_215
bit 25_232
bit 25_240
bit 25_279
diff --git a/artix7/mask_dsp_l.db b/artix7/mask_dsp_l.db
index dc51987..2a016b6 100644
--- a/artix7/mask_dsp_l.db
+++ b/artix7/mask_dsp_l.db
@@ -1,9 +1,10 @@
bit 00_42
+bit 00_78
+bit 00_81
+bit 00_83
bit 00_86
bit 00_89
bit 00_106
-bit 00_135
-bit 00_137
bit 00_138
bit 00_139
bit 00_142
@@ -16,11 +17,14 @@
bit 00_214
bit 00_217
bit 00_234
+bit 00_266
+bit 00_267
bit 00_273
bit 00_295
bit 01_32
bit 01_37
bit 01_38
+bit 01_77
bit 01_85
bit 01_88
bit 01_96
@@ -40,13 +44,18 @@
bit 01_224
bit 01_229
bit 01_230
+bit 01_265
+bit 01_266
bit 01_269
+bit 01_270
bit 01_288
bit 01_293
bit 01_297
bit 02_03
bit 02_06
bit 02_07
+bit 02_14
+bit 02_15
bit 02_30
bit 02_31
bit 02_38
@@ -54,168 +63,196 @@
bit 02_46
bit 02_47
bit 02_54
+bit 02_55
bit 02_62
bit 02_63
bit 02_70
bit 02_71
-bit 02_86
+bit 02_78
+bit 02_94
bit 02_102
bit 02_103
bit 02_110
bit 02_111
bit 02_118
+bit 02_126
+bit 02_127
bit 02_134
bit 02_135
bit 02_142
bit 02_143
-bit 02_150
+bit 02_155
bit 02_158
bit 02_159
bit 02_166
bit 02_167
-bit 02_174
bit 02_182
bit 02_183
+bit 02_190
+bit 02_191
bit 02_198
bit 02_199
bit 02_206
-bit 02_214
-bit 02_215
+bit 02_207
bit 02_222
+bit 02_223
+bit 02_229
bit 02_230
bit 02_231
bit 02_238
bit 02_239
bit 02_246
+bit 02_247
+bit 02_253
bit 02_254
bit 02_255
bit 02_261
bit 02_262
+bit 02_263
+bit 02_269
+bit 02_270
+bit 02_271
+bit 02_277
bit 02_286
bit 02_294
bit 02_295
bit 02_302
-bit 02_303
bit 02_310
bit 02_311
bit 02_318
-bit 02_319
bit 03_06
-bit 03_34
-bit 03_38
+bit 03_14
bit 03_45
-bit 03_69
-bit 03_86
-bit 03_110
-bit 03_173
-bit 03_176
+bit 03_70
+bit 03_94
+bit 03_102
+bit 03_134
+bit 03_182
+bit 03_204
+bit 03_205
bit 03_206
-bit 03_238
-bit 03_246
+bit 03_222
bit 03_252
-bit 03_253
-bit 03_254
bit 03_260
-bit 03_261
-bit 03_262
+bit 03_268
+bit 03_269
bit 03_270
-bit 03_293
+bit 03_286
+bit 03_310
bit 04_04
-bit 04_55
-bit 04_71
+bit 04_12
+bit 04_79
bit 04_108
-bit 04_135
-bit 04_204
-bit 04_236
-bit 04_252
-bit 04_260
+bit 04_132
+bit 04_163
+bit 04_183
+bit 04_196
+bit 04_219
+bit 04_229
+bit 04_253
bit 04_261
bit 04_268
+bit 04_269
+bit 04_277
+bit 04_284
bit 05_02
-bit 05_34
-bit 05_38
-bit 05_53
-bit 05_70
-bit 05_131
-bit 05_179
-bit 05_182
-bit 05_246
+bit 05_06
+bit 05_154
+bit 05_162
+bit 05_218
+bit 05_230
+bit 05_242
+bit 05_255
+bit 05_263
bit 05_290
-bit 06_01
bit 06_03
-bit 06_05
-bit 06_35
+bit 06_07
+bit 06_11
+bit 06_41
bit 06_44
-bit 06_68
-bit 06_75
-bit 06_85
+bit 06_61
+bit 06_69
+bit 06_77
bit 06_101
-bit 06_128
-bit 06_129
+bit 06_125
bit 06_131
bit 06_133
+bit 06_141
bit 06_155
bit 06_171
-bit 06_172
bit 06_181
-bit 06_205
+bit 06_187
+bit 06_189
+bit 06_191
+bit 06_204
bit 06_221
-bit 06_251
-bit 06_257
+bit 06_225
+bit 06_229
+bit 06_235
bit 06_259
+bit 06_265
bit 06_267
-bit 06_269
-bit 06_273
-bit 06_275
+bit 06_268
+bit 06_283
bit 06_285
bit 06_291
-bit 06_292
+bit 06_293
bit 07_00
+bit 07_07
bit 07_08
+bit 07_15
bit 07_24
bit 07_39
bit 07_40
bit 07_47
bit 07_48
bit 07_55
+bit 07_56
+bit 07_63
bit 07_64
bit 07_70
bit 07_71
-bit 07_88
-bit 07_103
+bit 07_72
+bit 07_95
+bit 07_96
bit 07_104
bit 07_111
bit 07_112
+bit 07_116
bit 07_119
bit 07_120
+bit 07_127
bit 07_128
bit 07_135
bit 07_136
-bit 07_151
+bit 07_143
+bit 07_152
bit 07_154
bit 07_158
-bit 07_159
bit 07_160
bit 07_167
-bit 07_168
-bit 07_175
-bit 07_184
+bit 07_176
+bit 07_178
+bit 07_183
+bit 07_191
bit 07_192
+bit 07_198
bit 07_199
+bit 07_200
bit 07_207
bit 07_208
bit 07_216
-bit 07_223
bit 07_224
+bit 07_231
bit 07_232
bit 07_236
bit 07_239
-bit 07_247
+bit 07_240
+bit 07_243
bit 07_248
-bit 07_256
-bit 07_262
+bit 07_263
bit 07_264
-bit 07_272
+bit 07_280
bit 07_287
bit 07_291
bit 07_295
@@ -223,24 +260,32 @@
bit 07_303
bit 07_311
bit 07_312
+bit 07_318
+bit 07_319
bit 08_01
bit 08_08
bit 08_09
+bit 08_11
bit 08_14
-bit 08_25
+bit 08_15
+bit 08_29
bit 08_30
bit 08_38
bit 08_40
bit 08_41
+bit 08_46
bit 08_54
-bit 08_55
+bit 08_62
+bit 08_63
bit 08_70
bit 08_72
bit 08_73
-bit 08_81
bit 08_86
+bit 08_87
bit 08_94
+bit 08_95
bit 08_102
+bit 08_104
bit 08_105
bit 08_113
bit 08_118
@@ -248,44 +293,58 @@
bit 08_126
bit 08_129
bit 08_134
+bit 08_145
+bit 08_148
bit 08_150
-bit 08_161
bit 08_166
bit 08_167
bit 08_168
-bit 08_176
+bit 08_177
bit 08_182
+bit 08_183
+bit 08_190
+bit 08_191
bit 08_193
bit 08_198
+bit 08_199
+bit 08_205
bit 08_207
+bit 08_208
bit 08_209
-bit 08_214
bit 08_215
-bit 08_216
-bit 08_222
bit 08_223
bit 08_224
bit 08_225
-bit 08_230
+bit 08_231
bit 08_232
bit 08_238
+bit 08_241
bit 08_256
bit 08_262
bit 08_263
-bit 08_264
bit 08_265
+bit 08_270
bit 08_271
bit 08_273
+bit 08_280
+bit 08_286
+bit 08_287
+bit 08_291
+bit 08_294
bit 08_297
+bit 08_303
bit 08_310
+bit 08_312
+bit 08_313
bit 08_318
bit 09_02
bit 09_03
+bit 09_10
bit 09_11
-bit 09_24
+bit 09_18
bit 09_31
-bit 09_34
bit 09_35
+bit 09_36
bit 09_40
bit 09_42
bit 09_43
@@ -294,330 +353,377 @@
bit 09_58
bit 09_72
bit 09_73
-bit 09_74
-bit 09_82
-bit 09_84
+bit 09_96
bit 09_99
-bit 09_100
-bit 09_106
bit 09_107
+bit 09_111
bit 09_115
-bit 09_122
bit 09_128
bit 09_130
bit 09_131
bit 09_132
-bit 09_145
+bit 09_137
+bit 09_138
bit 09_147
bit 09_148
-bit 09_152
bit 09_154
+bit 09_155
+bit 09_159
bit 09_162
-bit 09_168
-bit 09_169
+bit 09_163
bit 09_170
bit 09_176
-bit 09_178
bit 09_179
bit 09_180
-bit 09_183
bit 09_186
bit 09_191
bit 09_195
bit 09_202
-bit 09_209
-bit 09_210
+bit 09_203
bit 09_211
-bit 09_216
-bit 09_224
-bit 09_226
+bit 09_218
bit 09_227
+bit 09_229
bit 09_232
bit 09_233
bit 09_234
+bit 09_235
+bit 09_239
bit 09_242
bit 09_243
+bit 09_248
bit 09_250
bit 09_258
bit 09_259
bit 09_266
-bit 09_272
-bit 09_274
+bit 09_269
bit 09_275
+bit 09_279
bit 09_282
bit 09_283
bit 09_285
bit 09_290
bit 09_291
+bit 09_297
bit 09_298
bit 09_306
-bit 09_319
-bit 10_10
-bit 10_23
+bit 09_314
+bit 09_317
+bit 10_06
+bit 10_09
+bit 10_11
+bit 10_14
+bit 10_41
+bit 10_73
+bit 10_87
bit 10_92
+bit 10_98
+bit 10_105
+bit 10_121
+bit 10_130
+bit 10_135
+bit 10_140
+bit 10_148
+bit 10_153
bit 10_154
-bit 10_167
+bit 10_159
bit 10_170
bit 10_174
-bit 10_180
-bit 10_199
-bit 10_231
-bit 10_234
-bit 10_249
-bit 10_254
-bit 10_257
-bit 10_268
-bit 10_274
-bit 10_280
-bit 10_284
-bit 10_291
-bit 11_01
+bit 10_179
+bit 10_186
+bit 10_193
+bit 10_200
+bit 10_204
+bit 10_217
+bit 10_218
+bit 10_223
+bit 10_226
+bit 10_232
+bit 10_238
+bit 10_242
+bit 10_263
+bit 10_264
+bit 10_265
+bit 10_270
+bit 10_276
+bit 10_282
+bit 10_292
bit 11_02
bit 11_09
+bit 11_10
bit 11_18
-bit 11_25
+bit 11_23
+bit 11_26
+bit 11_31
bit 11_34
-bit 11_39
bit 11_41
bit 11_42
+bit 11_47
bit 11_50
bit 11_58
bit 11_63
bit 11_66
-bit 11_71
bit 11_72
+bit 11_73
bit 11_74
-bit 11_81
-bit 11_82
-bit 11_87
+bit 11_76
+bit 11_90
bit 11_97
bit 11_98
bit 11_105
bit 11_106
bit 11_113
+bit 11_114
bit 11_119
-bit 11_128
-bit 11_129
+bit 11_122
bit 11_130
bit 11_135
+bit 11_137
bit 11_138
bit 11_145
bit 11_151
-bit 11_153
bit 11_154
bit 11_161
bit 11_162
bit 11_167
+bit 11_169
bit 11_170
bit 11_177
bit 11_178
+bit 11_180
bit 11_183
-bit 11_185
bit 11_186
+bit 11_192
bit 11_193
bit 11_194
bit 11_199
+bit 11_201
bit 11_209
+bit 11_215
+bit 11_217
+bit 11_218
bit 11_225
bit 11_226
-bit 11_231
bit 11_233
bit 11_234
-bit 11_241
-bit 11_248
+bit 11_239
+bit 11_249
bit 11_255
bit 11_257
bit 11_258
-bit 11_259
+bit 11_263
bit 11_264
-bit 11_265
bit 11_266
-bit 11_268
bit 11_273
bit 11_274
-bit 11_280
-bit 11_281
bit 11_282
bit 11_287
+bit 11_289
bit 11_290
-bit 11_295
bit 11_297
-bit 11_298
bit 11_303
-bit 11_305
bit 11_306
bit 11_314
bit 11_319
-bit 12_00
bit 12_01
bit 12_02
+bit 12_06
+bit 12_09
bit 12_10
+bit 12_15
+bit 12_18
bit 12_23
bit 12_25
+bit 12_31
bit 12_34
bit 12_39
bit 12_41
bit 12_42
+bit 12_47
bit 12_50
+bit 12_55
bit 12_58
bit 12_63
+bit 12_65
bit 12_71
bit 12_72
bit 12_73
-bit 12_74
-bit 12_84
bit 12_87
-bit 12_89
bit 12_92
bit 12_95
bit 12_98
-bit 12_100
bit 12_103
+bit 12_105
bit 12_106
bit 12_113
bit 12_114
bit 12_119
-bit 12_122
-bit 12_128
+bit 12_121
+bit 12_124
+bit 12_127
bit 12_129
bit 12_130
bit 12_132
bit 12_135
+bit 12_136
bit 12_137
+bit 12_138
+bit 12_140
bit 12_146
-bit 12_148
+bit 12_149
bit 12_151
+bit 12_154
bit 12_161
+bit 12_162
bit 12_167
-bit 12_168
-bit 12_169
bit 12_170
-bit 12_178
+bit 12_179
bit 12_180
bit 12_183
bit 12_186
+bit 12_188
+bit 12_190
bit 12_193
bit 12_194
bit 12_199
+bit 12_200
+bit 12_201
bit 12_202
-bit 12_208
-bit 12_209
+bit 12_204
+bit 12_205
bit 12_210
bit 12_215
bit 12_217
+bit 12_218
+bit 12_223
+bit 12_224
bit 12_225
bit 12_226
-bit 12_231
+bit 12_228
bit 12_232
bit 12_234
bit 12_239
+bit 12_241
bit 12_242
bit 12_249
bit 12_250
-bit 12_254
-bit 12_256
+bit 12_255
bit 12_258
bit 12_263
+bit 12_264
+bit 12_265
bit 12_266
-bit 12_272
-bit 12_273
+bit 12_271
bit 12_274
+bit 12_278
bit 12_282
-bit 12_284
bit 12_287
bit 12_290
-bit 12_291
-bit 12_295
+bit 12_292
+bit 12_296
bit 12_297
bit 12_298
bit 12_303
bit 12_306
bit 12_313
+bit 12_314
bit 12_319
bit 13_01
-bit 13_04
bit 13_09
+bit 13_11
+bit 13_14
bit 13_15
-bit 13_25
+bit 13_26
bit 13_30
bit 13_41
-bit 13_42
+bit 13_47
bit 13_50
-bit 13_55
+bit 13_58
+bit 13_60
+bit 13_63
bit 13_66
-bit 13_71
+bit 13_68
bit 13_72
bit 13_73
-bit 13_81
+bit 13_74
+bit 13_76
+bit 13_95
bit 13_97
bit 13_98
bit 13_105
+bit 13_110
bit 13_113
+bit 13_114
+bit 13_117
bit 13_119
+bit 13_122
bit 13_128
bit 13_129
bit 13_130
bit 13_132
bit 13_135
+bit 13_137
bit 13_138
+bit 13_140
bit 13_145
+bit 13_148
bit 13_151
+bit 13_154
bit 13_155
+bit 13_158
bit 13_159
bit 13_161
-bit 13_162
bit 13_167
-bit 13_170
+bit 13_169
bit 13_174
bit 13_176
bit 13_177
-bit 13_185
+bit 13_183
bit 13_186
-bit 13_190
+bit 13_191
+bit 13_192
bit 13_193
bit 13_194
bit 13_199
-bit 13_204
bit 13_207
bit 13_209
bit 13_215
-bit 13_216
bit 13_220
bit 13_223
-bit 13_224
bit 13_225
bit 13_226
+bit 13_228
bit 13_231
bit 13_232
bit 13_233
bit 13_234
bit 13_237
+bit 13_238
+bit 13_239
bit 13_241
bit 13_248
-bit 13_250
+bit 13_249
bit 13_257
-bit 13_259
+bit 13_258
bit 13_263
-bit 13_265
+bit 13_270
bit 13_271
-bit 13_272
bit 13_273
-bit 13_274
-bit 13_281
bit 13_282
bit 13_284
+bit 13_287
+bit 13_289
bit 13_290
bit 13_297
-bit 13_305
bit 13_306
+bit 13_313
bit 13_314
-bit 13_319
bit 14_02
-bit 14_04
bit 14_10
bit 14_18
-bit 14_24
+bit 14_26
bit 14_34
+bit 14_36
bit 14_40
bit 14_42
bit 14_50
@@ -625,27 +731,27 @@
bit 14_66
bit 14_72
bit 14_74
-bit 14_82
-bit 14_84
+bit 14_76
+bit 14_90
+bit 14_96
bit 14_98
bit 14_100
bit 14_106
+bit 14_114
+bit 14_122
bit 14_128
bit 14_130
bit 14_132
bit 14_138
-bit 14_144
bit 14_148
-bit 14_152
bit 14_154
bit 14_162
bit 14_170
bit 14_178
bit 14_180
-bit 14_182
bit 14_186
bit 14_194
-bit 14_210
+bit 14_218
bit 14_226
bit 14_232
bit 14_234
@@ -654,70 +760,75 @@
bit 14_266
bit 14_268
bit 14_274
-bit 14_280
+bit 14_276
+bit 14_282
bit 14_284
bit 14_290
-bit 14_298
+bit 14_292
bit 14_306
bit 14_314
-bit 14_318
-bit 15_01
+bit 14_316
bit 15_09
+bit 15_11
bit 15_15
bit 15_25
+bit 15_29
bit 15_31
bit 15_39
bit 15_41
bit 15_49
-bit 15_55
+bit 15_57
+bit 15_63
bit 15_65
bit 15_71
-bit 15_81
+bit 15_73
bit 15_87
+bit 15_97
+bit 15_103
bit 15_105
bit 15_113
bit 15_119
bit 15_121
-bit 15_127
bit 15_129
bit 15_135
bit 15_137
+bit 15_145
bit 15_151
bit 15_153
-bit 15_161
+bit 15_159
bit 15_167
-bit 15_169
bit 15_177
bit 15_183
-bit 15_185
bit 15_199
+bit 15_201
bit 15_209
bit 15_215
bit 15_217
bit 15_223
bit 15_225
-bit 15_231
bit 15_233
bit 15_249
bit 15_255
bit 15_257
bit 15_263
bit 15_265
+bit 15_271
+bit 15_281
+bit 15_291
+bit 15_295
bit 15_297
bit 15_303
bit 15_311
+bit 15_313
bit 15_319
bit 16_00
bit 16_07
-bit 16_95
-bit 16_96
bit 16_103
bit 16_135
bit 16_144
-bit 16_156
+bit 16_151
bit 16_157
bit 16_162
-bit 16_163
bit 16_176
bit 16_180
bit 16_181
@@ -727,92 +838,114 @@
bit 16_231
bit 16_234
bit 16_235
+bit 16_240
bit 16_247
+bit 16_248
bit 16_250
bit 16_256
bit 16_257
bit 16_258
bit 16_259
bit 16_262
+bit 16_263
+bit 16_264
bit 16_266
-bit 16_267
-bit 16_272
+bit 16_279
bit 16_280
bit 16_288
bit 17_00
bit 17_07
-bit 17_135
+bit 17_96
+bit 17_103
+bit 17_104
bit 17_151
bit 17_156
-bit 17_157
bit 17_160
bit 17_162
+bit 17_163
bit 17_176
bit 17_180
bit 17_181
bit 17_183
bit 17_199
+bit 17_208
+bit 17_223
bit 17_228
bit 17_229
-bit 17_235
+bit 17_231
+bit 17_234
+bit 17_240
+bit 17_248
bit 17_250
bit 17_251
bit 17_256
bit 17_257
bit 17_258
bit 17_259
+bit 17_262
bit 17_263
bit 17_266
bit 17_267
+bit 17_279
+bit 17_296
bit 18_01
bit 18_06
bit 18_97
bit 18_102
bit 18_105
+bit 18_145
+bit 18_150
bit 18_156
bit 18_157
-bit 18_161
bit 18_162
+bit 18_163
bit 18_169
+bit 18_177
bit 18_180
bit 18_181
bit 18_182
bit 18_193
bit 18_198
bit 18_206
+bit 18_222
bit 18_228
bit 18_229
+bit 18_230
bit 18_234
bit 18_235
bit 18_241
+bit 18_246
bit 18_250
-bit 18_254
bit 18_256
bit 18_257
bit 18_258
bit 18_259
bit 18_262
bit 18_263
+bit 18_265
bit 18_266
+bit 18_267
+bit 18_270
bit 18_273
bit 18_278
bit 18_289
+bit 18_294
bit 19_01
bit 19_06
bit 19_09
bit 19_17
+bit 19_94
bit 19_97
bit 19_102
-bit 19_134
bit 19_145
bit 19_150
bit 19_156
bit 19_157
-bit 19_161
bit 19_162
+bit 19_177
bit 19_180
bit 19_181
-bit 19_182
+bit 19_206
bit 19_222
bit 19_228
bit 19_229
@@ -820,6 +953,7 @@
bit 19_234
bit 19_235
bit 19_241
+bit 19_246
bit 19_249
bit 19_250
bit 19_251
@@ -835,42 +969,51 @@
bit 19_273
bit 19_278
bit 19_281
+bit 19_289
+bit 19_297
bit 20_00
bit 20_96
+bit 20_103
bit 20_156
-bit 20_162
-bit 20_163
+bit 20_180
bit 20_228
bit 20_234
bit 20_256
+bit 20_257
+bit 20_259
bit 20_262
-bit 20_266
bit 20_293
bit 21_07
+bit 21_96
bit 21_103
bit 21_157
bit 21_160
bit 21_163
bit 21_181
+bit 21_223
bit 21_229
+bit 21_231
bit 21_235
bit 21_242
bit 21_244
bit 21_247
+bit 21_256
bit 21_257
+bit 21_266
+bit 21_267
bit 21_292
bit 22_00
bit 22_07
bit 22_08
bit 22_16
bit 22_96
-bit 22_103
+bit 22_104
bit 22_144
bit 22_151
bit 22_156
bit 22_157
-bit 22_160
bit 22_162
+bit 22_163
bit 22_176
bit 22_180
bit 22_181
@@ -879,7 +1022,6 @@
bit 22_199
bit 22_228
bit 22_229
-bit 22_231
bit 22_234
bit 22_235
bit 22_240
@@ -899,12 +1041,10 @@
bit 22_279
bit 22_280
bit 22_288
+bit 22_296
bit 23_00
bit 23_07
-bit 23_95
-bit 23_96
bit 23_103
-bit 23_135
bit 23_144
bit 23_151
bit 23_156
@@ -936,9 +1076,11 @@
bit 23_263
bit 23_266
bit 23_267
+bit 23_271
bit 23_272
bit 23_279
bit 23_288
+bit 23_295
bit 24_00
bit 24_07
bit 24_08
@@ -946,12 +1088,12 @@
bit 24_95
bit 24_96
bit 24_103
+bit 24_104
bit 24_135
bit 24_144
bit 24_151
bit 24_156
bit 24_157
-bit 24_160
bit 24_162
bit 24_163
bit 24_168
@@ -982,11 +1124,14 @@
bit 24_264
bit 24_266
bit 24_267
+bit 24_271
bit 24_272
bit 24_279
bit 24_280
bit 24_288
bit 24_293
+bit 24_295
+bit 24_296
bit 25_00
bit 25_07
bit 25_08
@@ -995,7 +1140,6 @@
bit 25_96
bit 25_103
bit 25_104
-bit 25_135
bit 25_144
bit 25_151
bit 25_156
@@ -1011,6 +1155,7 @@
bit 25_192
bit 25_199
bit 25_207
+bit 25_208
bit 25_223
bit 25_228
bit 25_229
@@ -1024,7 +1169,6 @@
bit 25_248
bit 25_250
bit 25_251
-bit 25_255
bit 25_256
bit 25_257
bit 25_258
@@ -1034,11 +1178,14 @@
bit 25_264
bit 25_266
bit 25_267
+bit 25_271
bit 25_272
bit 25_279
bit 25_280
bit 25_288
bit 25_292
+bit 25_295
+bit 25_296
bit 26_01
bit 26_02
bit 26_03
diff --git a/artix7/mask_dsp_r.db b/artix7/mask_dsp_r.db
index 343a232..4365fee 100644
--- a/artix7/mask_dsp_r.db
+++ b/artix7/mask_dsp_r.db
@@ -1,5 +1,7 @@
-bit 00_11
bit 00_42
+bit 00_78
+bit 00_81
+bit 00_83
bit 00_86
bit 00_89
bit 00_106
@@ -11,8 +13,6 @@
bit 00_163
bit 00_167
bit 00_170
-bit 00_190
-bit 00_191
bit 00_209
bit 00_214
bit 00_217
@@ -21,12 +21,10 @@
bit 00_267
bit 00_273
bit 00_295
-bit 01_09
-bit 01_10
-bit 01_14
bit 01_32
bit 01_37
bit 01_38
+bit 01_77
bit 01_85
bit 01_88
bit 01_96
@@ -57,278 +55,396 @@
bit 02_03
bit 02_06
bit 02_07
+bit 02_09
+bit 02_14
+bit 02_15
+bit 02_22
+bit 02_23
bit 02_30
bit 02_31
bit 02_38
bit 02_39
-bit 02_41
+bit 02_46
+bit 02_47
bit 02_54
+bit 02_55
bit 02_62
bit 02_63
bit 02_70
bit 02_71
+bit 02_78
+bit 02_79
bit 02_86
bit 02_87
+bit 02_94
+bit 02_95
bit 02_102
bit 02_103
+bit 02_110
+bit 02_111
bit 02_118
bit 02_119
+bit 02_126
+bit 02_127
bit 02_134
bit 02_135
bit 02_142
bit 02_143
bit 02_150
-bit 02_154
+bit 02_158
bit 02_159
bit 02_166
bit 02_167
+bit 02_174
+bit 02_175
bit 02_182
bit 02_183
-bit 02_187
+bit 02_190
+bit 02_191
bit 02_198
bit 02_199
+bit 02_206
+bit 02_207
+bit 02_211
bit 02_214
bit 02_215
+bit 02_222
bit 02_229
bit 02_230
bit 02_231
+bit 02_238
+bit 02_239
bit 02_246
bit 02_247
+bit 02_251
+bit 02_253
+bit 02_254
+bit 02_255
+bit 02_258
+bit 02_259
bit 02_261
bit 02_262
bit 02_263
+bit 02_265
+bit 02_266
bit 02_269
bit 02_270
bit 02_271
-bit 02_277
bit 02_286
+bit 02_287
bit 02_294
bit 02_295
+bit 02_302
+bit 02_303
+bit 02_307
bit 02_310
bit 02_311
bit 02_318
bit 02_319
bit 03_02
bit 03_06
-bit 03_41
-bit 03_56
+bit 03_09
+bit 03_14
+bit 03_20
+bit 03_21
+bit 03_24
+bit 03_30
+bit 03_40
+bit 03_69
bit 03_70
+bit 03_78
+bit 03_86
+bit 03_88
+bit 03_94
+bit 03_102
bit 03_104
-bit 03_121
-bit 03_134
+bit 03_132
+bit 03_133
bit 03_136
-bit 03_152
-bit 03_154
+bit 03_140
+bit 03_141
+bit 03_142
+bit 03_150
+bit 03_158
bit 03_166
-bit 03_168
-bit 03_182
+bit 03_190
bit 03_198
-bit 03_212
-bit 03_213
-bit 03_214
+bit 03_204
+bit 03_205
+bit 03_206
+bit 03_228
bit 03_229
bit 03_230
+bit 03_238
+bit 03_245
+bit 03_246
bit 03_252
bit 03_253
+bit 03_254
+bit 03_258
bit 03_260
bit 03_261
bit 03_262
+bit 03_264
+bit 03_265
bit 03_266
+bit 03_268
bit 03_269
bit 03_270
-bit 03_272
-bit 03_277
-bit 03_290
-bit 03_292
+bit 03_276
+bit 03_284
+bit 03_285
+bit 03_286
bit 03_293
bit 03_294
+bit 03_296
+bit 03_318
bit 04_04
bit 04_12
-bit 04_57
-bit 04_84
-bit 04_87
bit 04_100
bit 04_105
-bit 04_119
bit 04_132
bit 04_137
bit 04_148
-bit 04_153
+bit 04_151
bit 04_156
-bit 04_164
-bit 04_167
-bit 04_169
-bit 04_199
-bit 04_213
-bit 04_228
+bit 04_223
bit 04_229
+bit 04_236
+bit 04_244
+bit 04_252
bit 04_260
bit 04_261
bit 04_268
-bit 04_271
+bit 04_269
bit 04_277
-bit 04_292
-bit 04_313
+bit 04_284
+bit 04_297
bit 05_02
+bit 05_06
+bit 05_27
+bit 05_43
bit 05_70
bit 05_91
-bit 05_118
-bit 05_120
-bit 05_126
bit 05_139
-bit 05_166
-bit 05_182
-bit 05_186
-bit 05_266
-bit 05_270
-bit 05_275
-bit 05_282
+bit 05_150
+bit 05_162
+bit 05_187
+bit 05_194
+bit 05_202
+bit 05_210
+bit 05_219
+bit 05_226
+bit 05_246
+bit 05_250
+bit 05_254
+bit 05_258
+bit 05_267
+bit 05_271
bit 05_290
-bit 06_05
-bit 06_35
-bit 06_53
+bit 05_306
+bit 05_318
+bit 06_03
+bit 06_11
+bit 06_37
+bit 06_39
+bit 06_61
+bit 06_68
bit 06_69
bit 06_75
-bit 06_83
+bit 06_77
bit 06_85
bit 06_88
+bit 06_91
bit 06_99
bit 06_101
-bit 06_115
+bit 06_107
+bit 06_125
bit 06_131
bit 06_133
-bit 06_147
+bit 06_141
bit 06_149
-bit 06_152
-bit 06_155
bit 06_163
-bit 06_169
-bit 06_179
+bit 06_165
+bit 06_171
bit 06_181
-bit 06_197
+bit 06_184
+bit 06_189
+bit 06_204
bit 06_205
-bit 06_212
-bit 06_228
-bit 06_252
+bit 06_216
+bit 06_227
+bit 06_229
+bit 06_244
+bit 06_253
+bit 06_257
bit 06_259
-bit 06_260
-bit 06_267
+bit 06_265
+bit 06_268
bit 06_269
-bit 06_271
-bit 06_275
-bit 06_276
bit 06_277
-bit 06_285
-bit 06_289
+bit 06_281
+bit 06_283
bit 06_291
+bit 06_292
bit 06_293
-bit 06_312
bit 06_315
bit 07_00
-bit 07_03
-bit 07_06
bit 07_07
bit 07_08
bit 07_15
-bit 07_22
bit 07_24
bit 07_32
bit 07_39
+bit 07_40
+bit 07_47
bit 07_48
bit 07_55
+bit 07_56
+bit 07_63
bit 07_64
-bit 07_70
bit 07_71
+bit 07_72
+bit 07_79
bit 07_80
+bit 07_88
+bit 07_95
+bit 07_102
bit 07_103
-bit 07_104
-bit 07_110
+bit 07_111
bit 07_112
bit 07_118
+bit 07_119
+bit 07_120
+bit 07_126
bit 07_127
bit 07_128
bit 07_135
bit 07_136
+bit 07_143
bit 07_144
bit 07_150
bit 07_151
+bit 07_152
+bit 07_154
+bit 07_156
+bit 07_158
+bit 07_159
bit 07_160
-bit 07_167
+bit 07_163
+bit 07_166
+bit 07_168
bit 07_172
bit 07_176
bit 07_182
+bit 07_184
+bit 07_191
bit 07_192
+bit 07_195
bit 07_198
bit 07_199
+bit 07_200
+bit 07_203
+bit 07_206
+bit 07_207
bit 07_208
+bit 07_211
+bit 07_214
bit 07_215
bit 07_216
bit 07_222
+bit 07_223
bit 07_224
+bit 07_227
bit 07_231
bit 07_232
bit 07_236
-bit 07_240
+bit 07_238
+bit 07_239
bit 07_248
+bit 07_251
+bit 07_254
+bit 07_255
bit 07_256
-bit 07_258
bit 07_262
-bit 07_263
bit 07_264
bit 07_271
bit 07_272
bit 07_274
-bit 07_283
-bit 07_287
+bit 07_278
+bit 07_280
bit 07_291
bit 07_295
bit 07_296
+bit 07_303
+bit 07_307
+bit 07_312
bit 07_318
bit 07_319
bit 08_01
bit 08_06
-bit 08_07
bit 08_08
bit 08_09
bit 08_14
+bit 08_15
+bit 08_19
+bit 08_22
+bit 08_23
bit 08_24
+bit 08_25
bit 08_30
-bit 08_37
+bit 08_31
bit 08_38
+bit 08_39
+bit 08_40
bit 08_46
+bit 08_48
bit 08_54
bit 08_55
bit 08_62
-bit 08_65
+bit 08_63
bit 08_70
bit 08_71
bit 08_72
bit 08_73
-bit 08_81
+bit 08_78
+bit 08_80
bit 08_86
bit 08_87
+bit 08_94
+bit 08_95
+bit 08_96
bit 08_102
+bit 08_105
bit 08_112
+bit 08_113
bit 08_118
bit 08_119
+bit 08_120
+bit 08_125
+bit 08_126
+bit 08_127
+bit 08_129
bit 08_134
-bit 08_135
bit 08_145
-bit 08_148
bit 08_150
+bit 08_153
+bit 08_160
bit 08_161
-bit 08_164
bit 08_166
bit 08_167
-bit 08_168
-bit 08_174
bit 08_175
+bit 08_176
bit 08_177
bit 08_182
+bit 08_186
bit 08_190
-bit 08_197
+bit 08_191
+bit 08_193
bit 08_198
bit 08_199
+bit 08_200
+bit 08_205
bit 08_206
bit 08_207
bit 08_208
@@ -338,300 +454,403 @@
bit 08_216
bit 08_217
bit 08_222
+bit 08_223
bit 08_224
bit 08_225
bit 08_230
bit 08_231
+bit 08_232
bit 08_233
-bit 08_236
+bit 08_238
bit 08_241
bit 08_248
+bit 08_253
+bit 08_254
bit 08_256
+bit 08_257
bit 08_262
bit 08_263
bit 08_264
bit 08_265
-bit 08_267
-bit 08_272
+bit 08_270
+bit 08_271
bit 08_273
-bit 08_278
+bit 08_279
+bit 08_280
+bit 08_281
bit 08_286
-bit 08_293
+bit 08_287
bit 08_294
bit 08_296
bit 08_297
bit 08_302
-bit 08_310
bit 08_311
-bit 08_313
bit 08_318
-bit 09_00
+bit 08_319
bit 09_02
+bit 09_03
bit 09_04
+bit 09_08
+bit 09_09
+bit 09_10
+bit 09_11
+bit 09_18
+bit 09_19
bit 09_24
+bit 09_26
bit 09_31
+bit 09_34
bit 09_35
-bit 09_36
+bit 09_40
bit 09_42
+bit 09_43
bit 09_50
bit 09_51
-bit 09_52
-bit 09_59
+bit 09_57
+bit 09_58
bit 09_64
-bit 09_66
bit 09_67
bit 09_73
bit 09_74
-bit 09_77
+bit 09_75
bit 09_82
-bit 09_83
+bit 09_88
+bit 09_90
+bit 09_95
bit 09_99
-bit 09_100
-bit 09_114
-bit 09_115
+bit 09_111
+bit 09_112
+bit 09_122
bit 09_123
-bit 09_125
+bit 09_124
bit 09_128
-bit 09_129
bit 09_130
bit 09_131
bit 09_132
+bit 09_136
+bit 09_137
+bit 09_138
+bit 09_139
+bit 09_146
bit 09_147
bit 09_148
+bit 09_152
+bit 09_153
bit 09_154
-bit 09_155
+bit 09_159
+bit 09_160
bit 09_162
bit 09_163
+bit 09_169
+bit 09_170
+bit 09_171
bit 09_175
bit 09_176
bit 09_177
bit 09_178
bit 09_179
bit 09_180
-bit 09_183
+bit 09_181
bit 09_186
-bit 09_192
+bit 09_187
bit 09_194
bit 09_195
bit 09_202
+bit 09_204
+bit 09_208
+bit 09_210
bit 09_211
-bit 09_216
-bit 09_217
-bit 09_223
+bit 09_218
+bit 09_219
bit 09_224
-bit 09_225
bit 09_227
bit 09_228
+bit 09_232
bit 09_233
-bit 09_235
+bit 09_236
+bit 09_241
bit 09_242
bit 09_243
+bit 09_248
+bit 09_250
+bit 09_251
bit 09_258
bit 09_259
-bit 09_260
-bit 09_263
+bit 09_264
+bit 09_265
bit 09_266
bit 09_267
bit 09_269
-bit 09_270
-bit 09_272
+bit 09_271
bit 09_274
bit 09_275
+bit 09_276
+bit 09_280
+bit 09_281
bit 09_282
bit 09_283
bit 09_285
-bit 09_289
+bit 09_286
bit 09_291
bit 09_292
+bit 09_297
+bit 09_298
bit 09_306
+bit 09_312
+bit 09_314
bit 09_317
-bit 09_318
-bit 09_319
-bit 10_07
+bit 10_02
+bit 10_08
bit 10_09
-bit 10_10
-bit 10_71
-bit 10_75
-bit 10_79
-bit 10_81
-bit 10_82
+bit 10_11
+bit 10_14
+bit 10_34
+bit 10_57
+bit 10_73
+bit 10_76
+bit 10_87
bit 10_98
-bit 10_128
+bit 10_122
bit 10_129
+bit 10_130
bit 10_132
-bit 10_138
-bit 10_148
-bit 10_151
+bit 10_140
+bit 10_145
bit 10_154
-bit 10_161
-bit 10_170
+bit 10_160
+bit 10_174
+bit 10_179
bit 10_180
bit 10_186
-bit 10_204
+bit 10_188
+bit 10_193
+bit 10_208
bit 10_209
-bit 10_210
+bit 10_217
bit 10_223
bit 10_225
bit 10_226
+bit 10_228
bit 10_232
-bit 10_233
-bit 10_234
bit 10_249
+bit 10_250
+bit 10_252
bit 10_255
-bit 10_257
+bit 10_256
+bit 10_258
+bit 10_263
bit 10_265
+bit 10_266
+bit 10_268
bit 10_270
bit 10_274
-bit 10_275
bit 10_276
-bit 10_282
bit 10_292
-bit 10_308
+bit 10_296
bit 11_01
bit 11_02
+bit 11_05
bit 11_09
bit 11_10
bit 11_18
+bit 11_23
+bit 11_25
+bit 11_26
bit 11_31
-bit 11_33
bit 11_34
+bit 11_41
bit 11_42
-bit 11_47
bit 11_50
+bit 11_57
bit 11_58
bit 11_63
bit 11_66
bit 11_71
+bit 11_72
+bit 11_73
bit 11_74
-bit 11_81
+bit 11_76
bit 11_82
bit 11_87
+bit 11_89
bit 11_90
+bit 11_95
+bit 11_96
bit 11_97
bit 11_98
+bit 11_101
bit 11_103
+bit 11_105
bit 11_113
bit 11_114
bit 11_119
+bit 11_121
bit 11_122
-bit 11_128
+bit 11_127
bit 11_129
bit 11_130
-bit 11_132
bit 11_135
+bit 11_137
bit 11_138
bit 11_145
bit 11_146
+bit 11_151
+bit 11_153
bit 11_154
+bit 11_159
bit 11_161
bit 11_162
-bit 11_164
-bit 11_175
+bit 11_167
+bit 11_169
+bit 11_170
+bit 11_171
bit 11_177
bit 11_178
+bit 11_183
+bit 11_185
bit 11_186
+bit 11_191
+bit 11_192
bit 11_193
bit 11_194
bit 11_199
+bit 11_201
bit 11_202
+bit 11_203
bit 11_207
-bit 11_208
bit 11_209
bit 11_215
bit 11_217
-bit 11_222
+bit 11_218
bit 11_223
bit 11_225
bit 11_226
bit 11_231
-bit 11_237
+bit 11_232
+bit 11_233
+bit 11_234
bit 11_239
bit 11_242
+bit 11_249
bit 11_250
bit 11_255
bit 11_257
bit 11_258
+bit 11_259
bit 11_263
+bit 11_264
bit 11_265
bit 11_266
bit 11_270
bit 11_271
bit 11_273
bit 11_274
+bit 11_279
bit 11_282
bit 11_287
+bit 11_289
bit 11_290
+bit 11_298
bit 11_303
+bit 11_305
bit 11_306
bit 11_311
+bit 11_313
bit 11_314
bit 11_319
bit 12_01
bit 12_02
bit 12_04
+bit 12_05
+bit 12_08
+bit 12_09
+bit 12_10
+bit 12_14
+bit 12_15
+bit 12_18
+bit 12_19
+bit 12_23
+bit 12_26
bit 12_31
bit 12_33
bit 12_34
-bit 12_36
-bit 12_37
bit 12_39
bit 12_42
bit 12_50
-bit 12_52
+bit 12_55
+bit 12_56
+bit 12_57
bit 12_58
bit 12_63
+bit 12_64
bit 12_65
bit 12_66
bit 12_71
bit 12_72
+bit 12_73
bit 12_74
-bit 12_75
-bit 12_79
-bit 12_81
+bit 12_76
bit 12_82
bit 12_87
+bit 12_88
+bit 12_89
+bit 12_90
+bit 12_94
+bit 12_95
bit 12_98
-bit 12_100
bit 12_103
-bit 12_113
-bit 12_114
+bit 12_106
bit 12_119
+bit 12_121
bit 12_122
-bit 12_128
+bit 12_124
+bit 12_125
+bit 12_127
bit 12_129
bit 12_130
bit 12_132
bit 12_135
+bit 12_136
+bit 12_137
bit 12_138
+bit 12_140
bit 12_145
bit 12_146
bit 12_148
-bit 12_149
+bit 12_151
+bit 12_153
bit 12_154
+bit 12_159
bit 12_161
bit 12_162
+bit 12_164
bit 12_167
bit 12_168
-bit 12_174
-bit 12_175
+bit 12_170
bit 12_176
bit 12_178
+bit 12_179
bit 12_180
bit 12_183
+bit 12_185
bit 12_186
-bit 12_192
+bit 12_188
+bit 12_191
bit 12_193
bit 12_194
-bit 12_197
bit 12_199
+bit 12_201
bit 12_202
+bit 12_203
bit 12_204
+bit 12_205
bit 12_207
+bit 12_208
bit 12_209
bit 12_210
bit 12_215
bit 12_217
-bit 12_222
+bit 12_218
bit 12_223
bit 12_224
bit 12_225
@@ -640,197 +859,258 @@
bit 12_231
bit 12_232
bit 12_233
-bit 12_234
+bit 12_236
bit 12_239
-bit 12_241
+bit 12_240
bit 12_242
bit 12_249
+bit 12_250
+bit 12_252
+bit 12_253
bit 12_255
+bit 12_256
bit 12_258
-bit 12_260
-bit 12_262
bit 12_263
-bit 12_265
+bit 12_264
bit 12_266
-bit 12_270
+bit 12_268
bit 12_271
+bit 12_273
bit 12_274
-bit 12_275
bit 12_276
+bit 12_279
+bit 12_280
bit 12_282
+bit 12_286
bit 12_287
-bit 12_288
bit 12_290
bit 12_292
-bit 12_293
bit 12_295
+bit 12_296
+bit 12_297
+bit 12_298
bit 12_303
bit 12_306
-bit 12_308
bit 12_311
+bit 12_313
bit 12_314
-bit 13_00
+bit 12_319
bit 13_01
bit 13_02
bit 13_07
bit 13_09
-bit 13_23
+bit 13_10
+bit 13_14
+bit 13_15
+bit 13_24
bit 13_25
+bit 13_26
bit 13_30
bit 13_31
bit 13_34
+bit 13_38
bit 13_39
+bit 13_41
+bit 13_42
+bit 13_47
+bit 13_49
bit 13_50
-bit 13_52
bit 13_55
+bit 13_57
bit 13_58
-bit 13_64
+bit 13_63
bit 13_65
-bit 13_66
+bit 13_68
bit 13_71
bit 13_73
bit 13_74
bit 13_76
-bit 13_81
-bit 13_82
+bit 13_79
bit 13_87
+bit 13_88
+bit 13_89
bit 13_90
+bit 13_95
bit 13_97
bit 13_98
+bit 13_101
bit 13_103
-bit 13_111
+bit 13_105
+bit 13_112
bit 13_113
bit 13_114
bit 13_119
+bit 13_121
+bit 13_122
bit 13_124
+bit 13_127
bit 13_128
bit 13_129
bit 13_130
bit 13_132
bit 13_135
+bit 13_136
+bit 13_137
+bit 13_138
+bit 13_140
bit 13_145
bit 13_146
bit 13_148
bit 13_151
+bit 13_153
+bit 13_155
+bit 13_157
+bit 13_158
+bit 13_159
+bit 13_160
bit 13_161
bit 13_162
-bit 13_164
bit 13_167
+bit 13_169
+bit 13_171
bit 13_173
+bit 13_174
bit 13_175
bit 13_177
bit 13_178
-bit 13_180
bit 13_183
+bit 13_185
+bit 13_186
+bit 13_187
+bit 13_188
bit 13_191
+bit 13_192
bit 13_193
bit 13_194
-bit 13_196
bit 13_199
bit 13_202
-bit 13_204
bit 13_207
bit 13_208
bit 13_209
+bit 13_210
bit 13_215
-bit 13_216
bit 13_217
bit 13_223
bit 13_225
-bit 13_226
bit 13_231
+bit 13_232
bit 13_233
bit 13_237
+bit 13_239
bit 13_241
bit 13_242
+bit 13_248
bit 13_249
+bit 13_250
+bit 13_255
bit 13_257
bit 13_258
-bit 13_259
bit 13_263
+bit 13_264
bit 13_265
bit 13_270
bit 13_271
-bit 13_272
bit 13_273
-bit 13_274
bit 13_275
bit 13_276
+bit 13_279
+bit 13_280
+bit 13_281
bit 13_282
-bit 13_284
bit 13_287
+bit 13_289
bit 13_290
bit 13_292
-bit 13_295
bit 13_297
+bit 13_298
bit 13_303
+bit 13_305
bit 13_306
bit 13_311
bit 13_313
bit 13_314
-bit 13_318
bit 13_319
bit 14_02
-bit 14_04
+bit 14_08
bit 14_10
bit 14_18
bit 14_24
bit 14_34
+bit 14_36
+bit 14_40
bit 14_42
bit 14_50
bit 14_58
+bit 14_60
bit 14_66
-bit 14_68
+bit 14_72
bit 14_74
+bit 14_76
bit 14_82
bit 14_84
+bit 14_90
+bit 14_96
bit 14_98
bit 14_100
+bit 14_110
bit 14_114
bit 14_122
+bit 14_128
bit 14_130
bit 14_132
bit 14_138
+bit 14_152
bit 14_154
+bit 14_160
bit 14_162
bit 14_170
+bit 14_174
bit 14_176
bit 14_178
bit 14_180
-bit 14_182
bit 14_186
+bit 14_188
bit 14_194
+bit 14_202
+bit 14_204
bit 14_210
-bit 14_222
+bit 14_218
bit 14_226
+bit 14_228
bit 14_232
+bit 14_234
bit 14_242
bit 14_250
+bit 14_252
bit 14_258
+bit 14_264
bit 14_266
bit 14_268
bit 14_270
bit 14_274
bit 14_276
+bit 14_280
bit 14_282
bit 14_284
bit 14_290
bit 14_292
+bit 14_296
bit 14_306
+bit 14_312
bit 14_314
bit 14_316
-bit 14_318
-bit 15_01
bit 15_07
bit 15_09
+bit 15_11
bit 15_15
+bit 15_23
bit 15_25
bit 15_31
-bit 15_33
bit 15_39
-bit 15_47
+bit 15_41
bit 15_49
bit 15_55
+bit 15_57
bit 15_63
bit 15_65
bit 15_71
@@ -838,21 +1118,26 @@
bit 15_81
bit 15_87
bit 15_103
-bit 15_105
bit 15_113
bit 15_119
+bit 15_121
+bit 15_127
bit 15_129
-bit 15_135
bit 15_137
+bit 15_145
bit 15_151
+bit 15_153
bit 15_161
-bit 15_165
bit 15_167
bit 15_169
bit 15_177
+bit 15_179
bit 15_183
+bit 15_185
+bit 15_191
bit 15_193
bit 15_199
+bit 15_201
bit 15_207
bit 15_209
bit 15_215
@@ -861,26 +1146,30 @@
bit 15_225
bit 15_231
bit 15_233
+bit 15_239
bit 15_249
bit 15_255
bit 15_257
+bit 15_259
bit 15_263
bit 15_265
-bit 15_267
+bit 15_271
bit 15_273
-bit 15_275
bit 15_279
+bit 15_281
bit 15_287
bit 15_295
bit 15_297
bit 15_303
-bit 15_311
+bit 15_313
bit 15_319
bit 16_00
bit 16_07
+bit 16_95
bit 16_96
bit 16_103
bit 16_135
+bit 16_144
bit 16_151
bit 16_156
bit 16_157
@@ -899,7 +1188,10 @@
bit 16_231
bit 16_234
bit 16_235
+bit 16_239
+bit 16_240
bit 16_247
+bit 16_248
bit 16_250
bit 16_251
bit 16_256
@@ -916,63 +1208,77 @@
bit 16_288
bit 17_00
bit 17_07
+bit 17_24
bit 17_96
bit 17_103
bit 17_104
bit 17_144
+bit 17_151
bit 17_156
bit 17_157
+bit 17_159
bit 17_160
bit 17_162
bit 17_163
+bit 17_168
bit 17_176
bit 17_180
bit 17_181
bit 17_183
+bit 17_208
bit 17_228
+bit 17_229
bit 17_231
bit 17_234
bit 17_235
+bit 17_240
+bit 17_247
bit 17_248
bit 17_250
+bit 17_251
bit 17_256
bit 17_257
bit 17_258
bit 17_259
bit 17_262
bit 17_263
+bit 17_264
bit 17_266
bit 17_267
bit 17_272
bit 17_279
bit 17_280
+bit 17_288
bit 17_296
bit 18_01
bit 18_06
-bit 18_17
+bit 18_25
bit 18_97
bit 18_102
-bit 18_105
-bit 18_134
+bit 18_145
bit 18_150
bit 18_156
+bit 18_157
bit 18_161
bit 18_162
-bit 18_163
bit 18_169
-bit 18_177
bit 18_180
bit 18_181
bit 18_182
+bit 18_185
bit 18_193
+bit 18_198
bit 18_206
-bit 18_209
+bit 18_222
bit 18_228
bit 18_229
+bit 18_230
bit 18_234
bit 18_235
+bit 18_238
bit 18_241
bit 18_246
+bit 18_249
bit 18_250
bit 18_251
bit 18_256
@@ -981,33 +1287,43 @@
bit 18_259
bit 18_262
bit 18_263
+bit 18_265
bit 18_266
bit 18_267
bit 18_270
bit 18_273
bit 18_278
+bit 18_281
bit 18_289
+bit 18_297
+bit 18_310
bit 19_01
bit 19_06
bit 19_09
bit 19_17
-bit 19_25
bit 19_94
bit 19_97
bit 19_102
+bit 19_105
+bit 19_113
+bit 19_134
bit 19_145
bit 19_150
bit 19_156
bit 19_157
+bit 19_158
bit 19_161
bit 19_162
bit 19_163
+bit 19_166
bit 19_169
+bit 19_174
bit 19_177
bit 19_180
bit 19_181
bit 19_182
bit 19_185
+bit 19_193
bit 19_206
bit 19_222
bit 19_228
@@ -1016,8 +1332,10 @@
bit 19_234
bit 19_235
bit 19_241
+bit 19_246
bit 19_249
bit 19_250
+bit 19_251
bit 19_256
bit 19_257
bit 19_258
@@ -1034,39 +1352,43 @@
bit 19_289
bit 20_00
bit 20_96
+bit 20_103
bit 20_144
bit 20_156
bit 20_160
+bit 20_162
bit 20_163
+bit 20_176
+bit 20_180
bit 20_183
bit 20_228
bit 20_234
-bit 20_248
+bit 20_240
bit 20_256
bit 20_257
bit 20_259
bit 20_262
bit 20_266
+bit 20_267
bit 20_272
bit 20_293
-bit 21_00
bit 21_07
+bit 21_96
bit 21_103
bit 21_157
bit 21_160
bit 21_163
-bit 21_181
+bit 21_180
bit 21_183
-bit 21_199
-bit 21_231
+bit 21_229
bit 21_235
-bit 21_239
bit 21_242
bit 21_244
bit 21_247
+bit 21_256
bit 21_257
bit 21_258
-bit 21_264
+bit 21_262
bit 21_266
bit 21_267
bit 21_279
@@ -1075,24 +1397,29 @@
bit 22_07
bit 22_08
bit 22_16
-bit 22_24
bit 22_96
bit 22_103
bit 22_104
+bit 22_112
bit 22_144
bit 22_151
bit 22_156
bit 22_157
+bit 22_159
bit 22_160
bit 22_162
bit 22_163
bit 22_168
+bit 22_175
bit 22_176
bit 22_180
bit 22_181
bit 22_183
+bit 22_184
+bit 22_192
bit 22_207
bit 22_228
+bit 22_229
bit 22_231
bit 22_234
bit 22_235
@@ -1114,10 +1441,14 @@
bit 22_279
bit 22_280
bit 22_288
+bit 22_296
bit 23_00
bit 23_07
+bit 23_24
+bit 23_95
bit 23_96
bit 23_103
+bit 23_104
bit 23_135
bit 23_144
bit 23_151
@@ -1126,18 +1457,22 @@
bit 23_160
bit 23_162
bit 23_163
+bit 23_168
+bit 23_176
bit 23_180
bit 23_181
bit 23_183
bit 23_184
bit 23_199
bit 23_207
+bit 23_208
bit 23_223
bit 23_228
bit 23_229
bit 23_231
bit 23_234
bit 23_235
+bit 23_239
bit 23_240
bit 23_247
bit 23_248
@@ -1149,34 +1484,43 @@
bit 23_259
bit 23_262
bit 23_263
+bit 23_264
bit 23_266
bit 23_267
bit 23_271
bit 23_272
bit 23_279
+bit 23_280
bit 23_288
+bit 23_311
bit 24_00
bit 24_07
bit 24_08
bit 24_16
bit 24_24
+bit 24_95
bit 24_96
bit 24_103
bit 24_104
+bit 24_112
bit 24_135
bit 24_144
bit 24_151
bit 24_156
bit 24_157
+bit 24_159
bit 24_160
bit 24_162
bit 24_163
+bit 24_167
bit 24_168
+bit 24_175
bit 24_176
bit 24_180
bit 24_181
bit 24_183
bit 24_184
+bit 24_192
bit 24_199
bit 24_207
bit 24_208
@@ -1186,6 +1530,7 @@
bit 24_231
bit 24_234
bit 24_235
+bit 24_239
bit 24_240
bit 24_247
bit 24_248
@@ -1206,6 +1551,8 @@
bit 24_280
bit 24_288
bit 24_293
+bit 24_296
+bit 24_311
bit 25_00
bit 25_07
bit 25_08
@@ -1215,6 +1562,7 @@
bit 25_96
bit 25_103
bit 25_104
+bit 25_112
bit 25_135
bit 25_144
bit 25_151
@@ -1225,6 +1573,7 @@
bit 25_162
bit 25_163
bit 25_168
+bit 25_175
bit 25_176
bit 25_180
bit 25_181
@@ -1264,6 +1613,7 @@
bit 25_288
bit 25_292
bit 25_296
+bit 25_311
bit 26_01
bit 26_02
bit 26_03
diff --git a/artix7/segbits_int_l.origin_info.db b/artix7/segbits_int_l.origin_info.db
index 79c24d8..aaee8ae 100644
--- a/artix7/segbits_int_l.origin_info.db
+++ b/artix7/segbits_int_l.origin_info.db
@@ -301,7 +301,7 @@
INT_L.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
-INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
+INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
INT_L.FAN_ALT0.SR1END_N3_3 origin:050-pip-seed !23_00 19_01 22_00 24_00 25_00
INT_L.FAN_ALT0.SS2END_N0_3 origin:050-pip-seed !22_00 !23_00 !24_00 17_00 25_00
INT_L.FAN_ALT0.SW2END_N0_3 origin:050-pip-seed !22_00 !23_00 !25_00 17_00 24_00
@@ -1877,7 +1877,7 @@
INT_L.EE4BEG0.SS2END0 origin:050-pip-seed 03_08 05_11
INT_L.EE4BEG0.SS6END0 origin:050-pip-seed 05_11 06_08
INT_L.EE4BEG0.SW2END0 origin:050-pip-seed 02_09 05_11
-INT_L.EE4BEG0.SW6END0 origin:056-pip-rem 05_08 05_11
+INT_L.EE4BEG0.SW6END0 origin:050-pip-seed 05_08 05_11
INT_L.EE4BEG1.LOGIC_OUTS_L1 origin:050-pip-seed 02_25 07_25
INT_L.EE4BEG1.LOGIC_OUTS_L5 origin:050-pip-seed 02_25 04_26
INT_L.EE4BEG1.LOGIC_OUTS_L9 origin:050-pip-seed 03_24 04_26
@@ -2253,7 +2253,7 @@
INT_L.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39
INT_L.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36
INT_L.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37
-INT_L.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36
+INT_L.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36
INT_L.NE6BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_53 04_54
INT_L.NE6BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_53 07_53
INT_L.NE6BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_52 07_53
@@ -2471,7 +2471,7 @@
INT_L.NN6BEG2.NW2END2 origin:050-pip-seed 03_38 04_36
INT_L.NN6BEG2.NW6END2 origin:050-pip-seed 04_36 07_39
INT_L.NN6BEG2.SE2END2 origin:050-pip-seed 03_38 05_38
-INT_L.NN6BEG2.SE6END2 origin:050-pip-seed 05_38 07_39
+INT_L.NN6BEG2.SE6END2 origin:056-pip-rem 05_38 07_39
INT_L.NN6BEG2.WW2END1 origin:050-pip-seed 02_39 04_36
INT_L.NN6BEG2.WW4END2 origin:050-pip-seed 04_36 04_39
INT_L.NN6BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 03_54 06_54
@@ -2887,7 +2887,7 @@
INT_L.SE6BEG3.NE2END3 origin:050-pip-seed 03_58 04_56
INT_L.SE6BEG3.NE6END3 origin:050-pip-seed 04_56 04_59
INT_L.SE6BEG3.NN2END3 origin:050-pip-seed 02_59 04_56
-INT_L.SE6BEG3.NN6END3 origin:056-pip-rem 04_56 07_59
+INT_L.SE6BEG3.NN6END3 origin:050-pip-seed 04_56 07_59
INT_L.SE6BEG3.SE2END3 origin:050-pip-seed 02_58 03_58
INT_L.SE6BEG3.SE6END3 origin:050-pip-seed 02_58 07_59
INT_L.SE6BEG3.SS2END3 origin:050-pip-seed 02_59 05_58
@@ -3323,7 +3323,7 @@
INT_L.SW6BEG2.LVB_L0 origin:056-pip-rem 04_46 05_44
INT_L.SW6BEG2.LVB_L12 origin:056-pip-rem 05_44 07_45
INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
+INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_L.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
INT_L.SW6BEG2.NW6END3 origin:050-pip-seed 05_47 06_44
INT_L.SW6BEG2.SE2END2 origin:050-pip-seed 02_45 04_45
@@ -3568,7 +3568,7 @@
INT_L.WW4BEG0.WW2END_N0_3 origin:050-pip-seed 03_00 03_01
INT_L.WW4BEG0.LH12 origin:056-pip-rem 05_00 07_01
INT_L.WW4BEG0.NE2END0 origin:050-pip-seed 02_01 05_03
-INT_L.WW4BEG0.NE6END0 origin:056-pip-rem 05_00 05_03
+INT_L.WW4BEG0.NE6END0 origin:050-pip-seed 05_00 05_03
INT_L.WW4BEG0.NN2END0 origin:050-pip-seed 03_00 05_03
INT_L.WW4BEG0.NN6END0 origin:050-pip-seed 05_03 06_00
INT_L.WW4BEG0.NW2END0 origin:050-pip-seed 02_01 03_01
diff --git a/artix7/segbits_int_r.origin_info.db b/artix7/segbits_int_r.origin_info.db
index a41b859..d97972d 100644
--- a/artix7/segbits_int_r.origin_info.db
+++ b/artix7/segbits_int_r.origin_info.db
@@ -332,7 +332,7 @@
INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
-INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
+INT_R.FAN_ALT4.LOGIC_OUTS18 origin:056-pip-rem !22_08 !23_08 !25_08 21_08 24_08
INT_R.FAN_ALT4.SR1BEG_S0 origin:050-pip-seed !23_08 19_09 22_08 24_08 25_08
INT_R.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
INT_R.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
@@ -665,7 +665,7 @@
INT_R.EE4BEG0.SS2END0 origin:050-pip-seed 03_08 05_11
INT_R.EE4BEG0.SS6END0 origin:050-pip-seed 05_11 06_08
INT_R.EE4BEG0.SW2END0 origin:050-pip-seed 02_09 05_11
-INT_R.EE4BEG0.SW6END0 origin:056-pip-rem 05_08 05_11
+INT_R.EE4BEG0.SW6END0 origin:050-pip-seed 05_08 05_11
INT_R.EE4BEG1.LOGIC_OUTS1 origin:050-pip-seed 02_25 07_25
INT_R.EE4BEG1.LOGIC_OUTS5 origin:050-pip-seed 02_25 04_26
INT_R.EE4BEG1.LOGIC_OUTS9 origin:050-pip-seed 03_24 04_26
@@ -725,7 +725,7 @@
INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
+INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
INT_R.EL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_20 14_21
INT_R.EL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_21 14_21
INT_R.EL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_21 13_21
@@ -2253,7 +2253,7 @@
INT_R.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39
INT_R.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36
INT_R.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37
-INT_R.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36
+INT_R.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36
INT_R.NE6BEG3.LOGIC_OUTS3 origin:050-pip-seed 02_53 04_54
INT_R.NE6BEG3.LOGIC_OUTS7 origin:050-pip-seed 02_53 07_53
INT_R.NE6BEG3.LOGIC_OUTS11 origin:050-pip-seed 03_52 07_53
@@ -3301,7 +3301,7 @@
INT_R.SW6BEG1.LOGIC_OUTS19 origin:050-pip-seed 06_28 07_29
INT_R.SW6BEG1.LOGIC_OUTS23 origin:050-pip-seed 04_30 06_28
INT_R.SW6BEG1.EE2END1 origin:050-pip-seed 03_28 04_29
-INT_R.SW6BEG1.EE4END1 origin:050-pip-seed 04_29 05_28
+INT_R.SW6BEG1.EE4END1 origin:056-pip-rem 04_29 05_28
INT_R.SW6BEG1.LH6 origin:056-pip-rem 05_28 07_29
INT_R.SW6BEG1.LV9 origin:056-pip-rem 04_30 05_28
INT_R.SW6BEG1.NW2END2 origin:050-pip-seed 02_29 05_31
@@ -3321,7 +3321,7 @@
INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
@@ -3348,7 +3348,7 @@
INT_R.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
INT_R.SW6BEG3.LV18 origin:056-pip-rem 05_60 07_61
INT_R.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61
-INT_R.SW6BEG3.SE6END3 origin:050-pip-seed 04_61 06_60
+INT_R.SW6BEG3.SE6END3 origin:056-pip-rem 04_61 06_60
INT_R.SW6BEG3.SS2END3 origin:050-pip-seed 03_60 03_61
INT_R.SW6BEG3.SS6END3 origin:050-pip-seed 03_61 06_60
INT_R.SW6BEG3.SW2END3 origin:050-pip-seed 02_61 03_61
@@ -3568,7 +3568,7 @@
INT_R.WW4BEG0.LH12 origin:056-pip-rem 05_00 07_01
INT_R.WW4BEG0.LV0 origin:056-pip-rem 04_02 05_00
INT_R.WW4BEG0.NE2END0 origin:050-pip-seed 02_01 05_03
-INT_R.WW4BEG0.NE6END0 origin:056-pip-rem 05_00 05_03
+INT_R.WW4BEG0.NE6END0 origin:050-pip-seed 05_00 05_03
INT_R.WW4BEG0.NN2END0 origin:050-pip-seed 03_00 05_03
INT_R.WW4BEG0.NN6END0 origin:050-pip-seed 05_03 06_00
INT_R.WW4BEG0.NW2END0 origin:050-pip-seed 02_01 03_01
@@ -3623,7 +3623,7 @@
INT_R.WW4BEG3.LH0 origin:056-pip-rem 04_50 05_48
INT_R.WW4BEG3.LV18 origin:056-pip-rem 05_48 07_49
INT_R.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51
-INT_R.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51
+INT_R.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51
INT_R.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51
INT_R.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48
INT_R.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49
diff --git a/artix7/segbits_pcie_int_interface_r.db b/artix7/segbits_pcie_int_interface_r.db
index 9be753d..ba1f243 100644
--- a/artix7/segbits_pcie_int_interface_r.db
+++ b/artix7/segbits_pcie_int_interface_r.db
@@ -20,8 +20,6 @@
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT19.PCIE_INT_INTERFACE_IMUX_DELAY19 26_27
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT20.PCIE_INT_INTERFACE_IMUX_DELAY20 26_35
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT21.PCIE_INT_INTERFACE_IMUX_DELAY21 26_43
-PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT22.PCIE_INT_INTERFACE_IMUX_DELAY22 26_51
-PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT23.PCIE_INT_INTERFACE_IMUX_DELAY23 26_59
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT24.PCIE_INT_INTERFACE_IMUX_DELAY24 27_04
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT25.PCIE_INT_INTERFACE_IMUX_DELAY25 27_12
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT32.PCIE_INT_INTERFACE_IMUX_DELAY32 27_05
diff --git a/artix7/segbits_pcie_int_interface_r.origin_info.db b/artix7/segbits_pcie_int_interface_r.origin_info.db
index 958252d..9aa3a12 100644
--- a/artix7/segbits_pcie_int_interface_r.origin_info.db
+++ b/artix7/segbits_pcie_int_interface_r.origin_info.db
@@ -20,8 +20,6 @@
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT19.PCIE_INT_INTERFACE_IMUX_DELAY19 origin:062-pcie-int-pips 26_27
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT20.PCIE_INT_INTERFACE_IMUX_DELAY20 origin:062-pcie-int-pips 26_35
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT21.PCIE_INT_INTERFACE_IMUX_DELAY21 origin:062-pcie-int-pips 26_43
-PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT22.PCIE_INT_INTERFACE_IMUX_DELAY22 origin:062-pcie-int-pips 26_51
-PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT23.PCIE_INT_INTERFACE_IMUX_DELAY23 origin:062-pcie-int-pips 26_59
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT24.PCIE_INT_INTERFACE_IMUX_DELAY24 origin:062-pcie-int-pips 27_04
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT25.PCIE_INT_INTERFACE_IMUX_DELAY25 origin:062-pcie-int-pips 27_12
PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_OUT32.PCIE_INT_INTERFACE_IMUX_DELAY32 origin:062-pcie-int-pips 27_05
diff --git a/artix7/xc7a100tcsg324-2/package_pins.csv b/artix7/xc7a100tcsg324-2/package_pins.csv
new file mode 100644
index 0000000..2057141
--- /dev/null
+++ b/artix7/xc7a100tcsg324-2/package_pins.csv
@@ -0,0 +1,213 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y131,RIOB33_X57Y131,IO_L9N_T1_DQS_AD7N_35
+A3,35,IOB_X1Y133,RIOB33_X57Y133,IO_L8N_T1_AD14N_35
+A4,35,IOB_X1Y134,RIOB33_X57Y133,IO_L8P_T1_AD14P_35
+A5,35,IOB_X1Y143,RIOB33_X57Y143,IO_L3N_T0_DQS_AD5N_35
+A6,35,IOB_X1Y144,RIOB33_X57Y143,IO_L3P_T0_DQS_AD5P_35
+A8,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
+A9,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16
+A10,16,IOB_X0Y172,LIOB33_X0Y171,IO_L14P_T2_SRCC_16
+A11,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_15
+A13,15,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_AD3P_15
+A14,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD3N_15
+A15,15,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_AD10P_15
+A16,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD10N_15
+A18,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD11N_15
+B1,35,IOB_X1Y132,RIOB33_X57Y131,IO_L9P_T1_DQS_AD7P_35
+B2,35,IOB_X1Y129,RIOB33_X57Y129,IO_L10N_T1_AD15N_35
+B3,35,IOB_X1Y130,RIOB33_X57Y129,IO_L10P_T1_AD15P_35
+B4,35,IOB_X1Y135,RIOB33_X57Y135,IO_L7N_T1_AD6N_35
+B6,35,IOB_X1Y145,RIOB33_X57Y145,IO_L2N_T0_AD12N_35
+B7,35,IOB_X1Y146,RIOB33_X57Y145,IO_L2P_T0_AD12P_35
+B8,16,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_16
+B9,16,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_16
+B11,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_15
+B12,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+B13,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+B14,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+B16,15,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_AD2P_15
+B17,15,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_AD2N_15
+B18,15,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_AD11P_15
+C1,35,IOB_X1Y117,RIOB33_X57Y117,IO_L16N_T2_35
+C2,35,IOB_X1Y118,RIOB33_X57Y117,IO_L16P_T2_35
+C4,35,IOB_X1Y136,RIOB33_X57Y135,IO_L7P_T1_AD6P_35
+C5,35,IOB_X1Y147,RIOB33_X57Y147,IO_L1N_T0_AD4N_35
+C6,35,IOB_X1Y148,RIOB33_X57Y147,IO_L1P_T0_AD4P_35
+C7,35,IOB_X1Y141,RIOB33_X57Y141,IO_L4N_T0_35
+C9,16,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_16
+C10,16,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_16
+C11,16,IOB_X0Y174,LIOB33_X0Y173,IO_L13P_T2_MRCC_16
+C12,15,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_AD1P_15
+C14,15,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_AD0N_15
+C15,15,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_15
+C16,15,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A20_15
+C17,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
+D2,35,IOB_X1Y121,RIOB33_X57Y121,IO_L14N_T2_SRCC_35
+D3,35,IOB_X1Y125,RIOB33_X57Y125,IO_L12N_T1_MRCC_35
+D4,35,IOB_X1Y127,RIOB33_X57Y127,IO_L11N_T1_SRCC_35
+D5,35,IOB_X1Y128,RIOB33_X57Y127,IO_L11P_T1_SRCC_35
+D7,35,IOB_X1Y137,RIOB33_X57Y137,IO_L6N_T0_VREF_35
+D8,35,IOB_X1Y142,RIOB33_X57Y141,IO_L4P_T0_35
+D9,16,IOB_X0Y187,LIOB33_X0Y187,IO_L6N_T0_VREF_16
+D10,16,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_VREF_16
+D12,15,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_15
+D13,15,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_15
+D14,15,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_AD0P_15
+D15,15,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_15
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diff --git a/artix7/xc7a100tcsg324-2/part.json b/artix7/xc7a100tcsg324-2/part.json
new file mode 100644
index 0000000..9affccb
--- /dev/null
+++ b/artix7/xc7a100tcsg324-2/part.json
@@ -0,0 +1,771 @@
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+ },
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+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "56": {
+ "frame_count": 30
+ },
+ "57": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
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+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "12": {
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+ },
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+ },
+ "14": {
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+ },
+ "15": {
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+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "29": {
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+ },
+ "30": {
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+ },
+ "31": {
+ "frame_count": 30
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 28
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 28
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 36
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 28
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 36
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 28
+ },
+ "49": {
+ "frame_count": 36
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56823955,
+ "iobanks": {
+ "0": "X1Y130",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182",
+ "34": "X146Y78",
+ "35": "X146Y130"
+ }
+}
diff --git a/artix7/xc7a100tcsg324-2/part.yaml b/artix7/xc7a100tcsg324-2/part.yaml
new file mode 100644
index 0000000..44833bb
--- /dev/null
+++ b/artix7/xc7a100tcsg324-2/part.yaml
@@ -0,0 +1,499 @@
+!<xilinx/xc7series/part>
+idcode: 0x3631093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
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+ 17: !<xilinx/xc7series/configuration_column>
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+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
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+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
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+ 24: !<xilinx/xc7series/configuration_column>
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+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
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+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 32: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
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+ 37: !<xilinx/xc7series/configuration_column>
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+ 38: !<xilinx/xc7series/configuration_column>
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+ 39: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
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+ 41: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
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+ 44: !<xilinx/xc7series/configuration_column>
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+ 45: !<xilinx/xc7series/configuration_column>
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+ 46: !<xilinx/xc7series/configuration_column>
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+ 47: !<xilinx/xc7series/configuration_column>
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+ 48: !<xilinx/xc7series/configuration_column>
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+ 49: !<xilinx/xc7series/configuration_column>
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+ 50: !<xilinx/xc7series/configuration_column>
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+ 51: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a100tcsg324-2L/package_pins.csv b/artix7/xc7a100tcsg324-2L/package_pins.csv
new file mode 100644
index 0000000..2057141
--- /dev/null
+++ b/artix7/xc7a100tcsg324-2L/package_pins.csv
@@ -0,0 +1,213 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y131,RIOB33_X57Y131,IO_L9N_T1_DQS_AD7N_35
+A3,35,IOB_X1Y133,RIOB33_X57Y133,IO_L8N_T1_AD14N_35
+A4,35,IOB_X1Y134,RIOB33_X57Y133,IO_L8P_T1_AD14P_35
+A5,35,IOB_X1Y143,RIOB33_X57Y143,IO_L3N_T0_DQS_AD5N_35
+A6,35,IOB_X1Y144,RIOB33_X57Y143,IO_L3P_T0_DQS_AD5P_35
+A8,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
+A9,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16
+A10,16,IOB_X0Y172,LIOB33_X0Y171,IO_L14P_T2_SRCC_16
+A11,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_15
+A13,15,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_AD3P_15
+A14,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD3N_15
+A15,15,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_AD10P_15
+A16,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD10N_15
+A18,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD11N_15
+B1,35,IOB_X1Y132,RIOB33_X57Y131,IO_L9P_T1_DQS_AD7P_35
+B2,35,IOB_X1Y129,RIOB33_X57Y129,IO_L10N_T1_AD15N_35
+B3,35,IOB_X1Y130,RIOB33_X57Y129,IO_L10P_T1_AD15P_35
+B4,35,IOB_X1Y135,RIOB33_X57Y135,IO_L7N_T1_AD6N_35
+B6,35,IOB_X1Y145,RIOB33_X57Y145,IO_L2N_T0_AD12N_35
+B7,35,IOB_X1Y146,RIOB33_X57Y145,IO_L2P_T0_AD12P_35
+B8,16,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_16
+B9,16,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_16
+B11,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_15
+B12,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+B13,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+B14,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+B16,15,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_AD2P_15
+B17,15,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_AD2N_15
+B18,15,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_AD11P_15
+C1,35,IOB_X1Y117,RIOB33_X57Y117,IO_L16N_T2_35
+C2,35,IOB_X1Y118,RIOB33_X57Y117,IO_L16P_T2_35
+C4,35,IOB_X1Y136,RIOB33_X57Y135,IO_L7P_T1_AD6P_35
+C5,35,IOB_X1Y147,RIOB33_X57Y147,IO_L1N_T0_AD4N_35
+C6,35,IOB_X1Y148,RIOB33_X57Y147,IO_L1P_T0_AD4P_35
+C7,35,IOB_X1Y141,RIOB33_X57Y141,IO_L4N_T0_35
+C9,16,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_16
+C10,16,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_16
+C11,16,IOB_X0Y174,LIOB33_X0Y173,IO_L13P_T2_MRCC_16
+C12,15,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_AD1P_15
+C14,15,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_AD0N_15
+C15,15,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_15
+C16,15,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A20_15
+C17,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
+D2,35,IOB_X1Y121,RIOB33_X57Y121,IO_L14N_T2_SRCC_35
+D3,35,IOB_X1Y125,RIOB33_X57Y125,IO_L12N_T1_MRCC_35
+D4,35,IOB_X1Y127,RIOB33_X57Y127,IO_L11N_T1_SRCC_35
+D5,35,IOB_X1Y128,RIOB33_X57Y127,IO_L11P_T1_SRCC_35
+D7,35,IOB_X1Y137,RIOB33_X57Y137,IO_L6N_T0_VREF_35
+D8,35,IOB_X1Y142,RIOB33_X57Y141,IO_L4P_T0_35
+D9,16,IOB_X0Y187,LIOB33_X0Y187,IO_L6N_T0_VREF_16
+D10,16,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_VREF_16
+D12,15,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_15
+D13,15,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_15
+D14,15,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_AD0P_15
+D15,15,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_15
+D17,15,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A27_15
+D18,15,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_A18_15
+E1,35,IOB_X1Y113,RIOB33_X57Y113,IO_L18N_T2_35
+E2,35,IOB_X1Y122,RIOB33_X57Y121,IO_L14P_T2_SRCC_35
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+E5,35,IOB_X1Y139,RIOB33_X57Y139,IO_L5N_T0_AD13N_35
+E6,35,IOB_X1Y140,RIOB33_X57Y139,IO_L5P_T0_AD13P_35
+E7,35,IOB_X1Y138,RIOB33_X57Y137,IO_L6P_T0_35
+E15,15,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_15
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+E18,15,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_15
+F1,35,IOB_X1Y114,RIOB33_X57Y113,IO_L18P_T2_35
+F3,35,IOB_X1Y123,RIOB33_X57Y123,IO_L13N_T2_MRCC_35
+F4,35,IOB_X1Y124,RIOB33_X57Y123,IO_L13P_T2_MRCC_35
+F5,35,IOB_X1Y149,RIOB33_SING_X57Y149,IO_0_35
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+F14,15,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_AD9N_15
+F15,15,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_15
+F16,15,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_15
+F18,15,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A16_15
+G1,35,IOB_X1Y115,RIOB33_X57Y115,IO_L17N_T2_35
+G2,35,IOB_X1Y119,RIOB33_X57Y119,IO_L15N_T2_DQS_35
+G3,35,IOB_X1Y109,RIOB33_X57Y109,IO_L20N_T3_35
+G4,35,IOB_X1Y110,RIOB33_X57Y109,IO_L20P_T3_35
+G6,35,IOB_X1Y112,RIOB33_X57Y111,IO_L19P_T3_35
+G13,15,IOB_X0Y149,LIOB33_SING_X0Y149,IO_0_15
+G14,15,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_ADV_B_15
+G16,15,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_15
+G17,15,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_A23_15
+G18,15,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A17_15
+H1,35,IOB_X1Y116,RIOB33_X57Y115,IO_L17P_T2_35
+H2,35,IOB_X1Y120,RIOB33_X57Y119,IO_L15P_T2_DQS_35
+H4,35,IOB_X1Y107,RIOB33_X57Y107,IO_L21N_T3_DQS_35
+H5,35,IOB_X1Y101,RIOB33_X57Y101,IO_L24N_T3_35
+H6,35,IOB_X1Y102,RIOB33_X57Y101,IO_L24P_T3_35
+H14,15,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_15
+H15,15,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_A21_VREF_15
+H16,15,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_15
+H17,15,IOB_X0Y114,LIOB33_X0Y113,IO_L18P_T2_A24_15
+J2,35,IOB_X1Y105,RIOB33_X57Y105,IO_L22N_T3_35
+J3,35,IOB_X1Y106,RIOB33_X57Y105,IO_L22P_T3_35
+J4,35,IOB_X1Y108,RIOB33_X57Y107,IO_L21P_T3_DQS_35
+J5,35,IOB_X1Y100,RIOB33_SING_X57Y100,IO_25_35
+J10,0,IPAD_X0Y30,MONITOR_BOT_X46Y131,VP_0
+J13,15,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A25_15
+J14,15,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_A22_15
+J15,15,IOB_X0Y101,LIOB33_X0Y101,IO_L24N_T3_RS0_15
+J17,15,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_FOE_B_15
+J18,15,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_FWE_B_15
+K1,35,IOB_X1Y103,RIOB33_X57Y103,IO_L23N_T3_35
+K2,35,IOB_X1Y104,RIOB33_X57Y103,IO_L23P_T3_35
+K3,34,IOB_X1Y96,RIOB33_X57Y95,IO_L2P_T0_34
+K5,34,IOB_X1Y90,RIOB33_X57Y89,IO_L5P_T0_34
+K6,34,IOB_X1Y99,RIOB33_SING_X57Y99,IO_0_34
+K9,0,IPAD_X0Y31,MONITOR_BOT_X46Y131,VN_0
+K13,15,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A26_15
+K15,15,IOB_X0Y102,LIOB33_X0Y101,IO_L24P_T3_RS1_15
+K16,15,IOB_X0Y100,LIOB33_SING_X0Y100,IO_25_15
+K17,14,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_D00_MOSI_14
+K18,14,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_D01_DIN_14
+L1,34,IOB_X1Y98,RIOB33_X57Y97,IO_L1P_T0_34
+L3,34,IOB_X1Y95,RIOB33_X57Y95,IO_L2N_T0_34
+L4,34,IOB_X1Y89,RIOB33_X57Y89,IO_L5N_T0_34
+L5,34,IOB_X1Y87,RIOB33_X57Y87,IO_L6N_T0_VREF_34
+L6,34,IOB_X1Y88,RIOB33_X57Y87,IO_L6P_T0_34
+L13,14,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_FCS_B_14
+L14,14,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_D02_14
+L15,14,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_PUDC_B_14
+L16,14,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_EMCCLK_14
+L18,14,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_D04_14
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+N6,34,IOB_X1Y63,RIOB33_X57Y63,IO_L18N_T2_34
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+N17,14,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_14
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+P18,14,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_D13_14
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+R3,34,IOB_X1Y78,RIOB33_X57Y77,IO_L11P_T1_SRCC_34
+R5,34,IOB_X1Y61,RIOB33_X57Y61,IO_L19N_T3_VREF_34
+R6,34,IOB_X1Y62,RIOB33_X57Y61,IO_L19P_T3_34
+R7,34,IOB_X1Y54,RIOB33_X57Y53,IO_L23P_T3_34
+R8,34,IOB_X1Y52,RIOB33_X57Y51,IO_L24P_T3_34
+R10,14,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_14
+R11,14,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_14
+R12,14,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_D06_14
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diff --git a/artix7/xc7a100tcsg324-2L/part.json b/artix7/xc7a100tcsg324-2L/part.json
new file mode 100644
index 0000000..9affccb
--- /dev/null
+++ b/artix7/xc7a100tcsg324-2L/part.json
@@ -0,0 +1,771 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
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+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
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+ },
+ "2": {
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+ }
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+ },
+ "CLB_IO_CLK": {
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+ }
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "49": {
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+ },
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+ },
+ "51": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56823955,
+ "iobanks": {
+ "0": "X1Y130",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182",
+ "34": "X146Y78",
+ "35": "X146Y130"
+ }
+}
diff --git a/artix7/xc7a100tcsg324-2L/part.yaml b/artix7/xc7a100tcsg324-2L/part.yaml
new file mode 100644
index 0000000..44833bb
--- /dev/null
+++ b/artix7/xc7a100tcsg324-2L/part.yaml
@@ -0,0 +1,499 @@
+!<xilinx/xc7series/part>
+idcode: 0x3631093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
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+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
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+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
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diff --git a/artix7/xc7a100tcsg324-3/package_pins.csv b/artix7/xc7a100tcsg324-3/package_pins.csv
new file mode 100644
index 0000000..2057141
--- /dev/null
+++ b/artix7/xc7a100tcsg324-3/package_pins.csv
@@ -0,0 +1,213 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y131,RIOB33_X57Y131,IO_L9N_T1_DQS_AD7N_35
+A3,35,IOB_X1Y133,RIOB33_X57Y133,IO_L8N_T1_AD14N_35
+A4,35,IOB_X1Y134,RIOB33_X57Y133,IO_L8P_T1_AD14P_35
+A5,35,IOB_X1Y143,RIOB33_X57Y143,IO_L3N_T0_DQS_AD5N_35
+A6,35,IOB_X1Y144,RIOB33_X57Y143,IO_L3P_T0_DQS_AD5P_35
+A8,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
+A9,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16
+A10,16,IOB_X0Y172,LIOB33_X0Y171,IO_L14P_T2_SRCC_16
+A11,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_15
+A13,15,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_AD3P_15
+A14,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD3N_15
+A15,15,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_AD10P_15
+A16,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD10N_15
+A18,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD11N_15
+B1,35,IOB_X1Y132,RIOB33_X57Y131,IO_L9P_T1_DQS_AD7P_35
+B2,35,IOB_X1Y129,RIOB33_X57Y129,IO_L10N_T1_AD15N_35
+B3,35,IOB_X1Y130,RIOB33_X57Y129,IO_L10P_T1_AD15P_35
+B4,35,IOB_X1Y135,RIOB33_X57Y135,IO_L7N_T1_AD6N_35
+B6,35,IOB_X1Y145,RIOB33_X57Y145,IO_L2N_T0_AD12N_35
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+B9,16,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_16
+B11,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_15
+B12,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+B13,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
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+B18,15,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_AD11P_15
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+C5,35,IOB_X1Y147,RIOB33_X57Y147,IO_L1N_T0_AD4N_35
+C6,35,IOB_X1Y148,RIOB33_X57Y147,IO_L1P_T0_AD4P_35
+C7,35,IOB_X1Y141,RIOB33_X57Y141,IO_L4N_T0_35
+C9,16,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_16
+C10,16,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_16
+C11,16,IOB_X0Y174,LIOB33_X0Y173,IO_L13P_T2_MRCC_16
+C12,15,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_AD1P_15
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+C16,15,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A20_15
+C17,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
+D2,35,IOB_X1Y121,RIOB33_X57Y121,IO_L14N_T2_SRCC_35
+D3,35,IOB_X1Y125,RIOB33_X57Y125,IO_L12N_T1_MRCC_35
+D4,35,IOB_X1Y127,RIOB33_X57Y127,IO_L11N_T1_SRCC_35
+D5,35,IOB_X1Y128,RIOB33_X57Y127,IO_L11P_T1_SRCC_35
+D7,35,IOB_X1Y137,RIOB33_X57Y137,IO_L6N_T0_VREF_35
+D8,35,IOB_X1Y142,RIOB33_X57Y141,IO_L4P_T0_35
+D9,16,IOB_X0Y187,LIOB33_X0Y187,IO_L6N_T0_VREF_16
+D10,16,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_VREF_16
+D12,15,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_15
+D13,15,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_15
+D14,15,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_AD0P_15
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diff --git a/artix7/xc7a100tcsg324-3/part.json b/artix7/xc7a100tcsg324-3/part.json
new file mode 100644
index 0000000..9affccb
--- /dev/null
+++ b/artix7/xc7a100tcsg324-3/part.json
@@ -0,0 +1,771 @@
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+ },
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+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ "frame_count": 30
+ },
+ "57": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
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+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "12": {
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+ },
+ "13": {
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+ },
+ "14": {
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+ },
+ "15": {
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+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "29": {
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+ },
+ "30": {
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+ },
+ "31": {
+ "frame_count": 30
+ },
+ "32": {
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+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 28
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 28
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 36
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 28
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 36
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 28
+ },
+ "49": {
+ "frame_count": 36
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56823955,
+ "iobanks": {
+ "0": "X1Y130",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182",
+ "34": "X146Y78",
+ "35": "X146Y130"
+ }
+}
diff --git a/artix7/xc7a100tcsg324-3/part.yaml b/artix7/xc7a100tcsg324-3/part.yaml
new file mode 100644
index 0000000..44833bb
--- /dev/null
+++ b/artix7/xc7a100tcsg324-3/part.yaml
@@ -0,0 +1,499 @@
+!<xilinx/xc7series/part>
+idcode: 0x3631093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
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+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
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+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 32: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
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+ 37: !<xilinx/xc7series/configuration_column>
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+ 38: !<xilinx/xc7series/configuration_column>
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+ 39: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
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+ 45: !<xilinx/xc7series/configuration_column>
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+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
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+ 48: !<xilinx/xc7series/configuration_column>
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+ 49: !<xilinx/xc7series/configuration_column>
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+ 50: !<xilinx/xc7series/configuration_column>
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+ 51: !<xilinx/xc7series/configuration_column>
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+ 52: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a100tfgg484-1/package_pins.csv b/artix7/xc7a100tfgg484-1/package_pins.csv
new file mode 100644
index 0000000..1b027c4
--- /dev/null
+++ b/artix7/xc7a100tfgg484-1/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y147,RIOB33_X57Y147,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y8,GTP_CHANNEL_0_X130Y162,MGTPTXN0_216
+A6,216,OPAD_X0Y12,GTP_CHANNEL_2_X130Y191,MGTPTXN2_216
+A8,216,IPAD_X1Y36,GTP_CHANNEL_0_X130Y162,MGTPRXN0_216
+A10,216,IPAD_X1Y54,GTP_CHANNEL_2_X130Y191,MGTPRXN2_216
+A13,16,IOB_X0Y180,LIOB33_X0Y179,IO_L10P_T1_16
+A14,16,IOB_X0Y179,LIOB33_X0Y179,IO_L10N_T1_16
+A15,16,IOB_X0Y182,LIOB33_X0Y181,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y181,LIOB33_X0Y181,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y166,LIOB33_X0Y165,IO_L17P_T2_16
+A19,16,IOB_X0Y165,LIOB33_X0Y165,IO_L17N_T2_16
+A20,16,IOB_X0Y167,LIOB33_X0Y167,IO_L16N_T2_16
+A21,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y86,RIOB33_X57Y85,IO_L7P_T1_34
+AA3,34,IOB_X1Y81,RIOB33_X57Y81,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y77,RIOB33_X57Y77,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y80,RIOB33_X57Y79,IO_L10P_T1_34
+AA6,34,IOB_X1Y63,RIOB33_X57Y63,IO_L18N_T2_34
+AA8,34,IOB_X1Y56,RIOB33_X57Y55,IO_L22P_T3_34
+AA9,13,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_13
+AA10,13,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_13
+AA11,13,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_13
+AA13,13,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_13
+AA14,13,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_13
+AA15,13,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_13
+AA16,13,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_13
+AA18,14,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y85,RIOB33_X57Y85,IO_L7N_T1_34
+AB2,34,IOB_X1Y83,RIOB33_X57Y83,IO_L8N_T1_34
+AB3,34,IOB_X1Y84,RIOB33_X57Y83,IO_L8P_T1_34
+AB5,34,IOB_X1Y79,RIOB33_X57Y79,IO_L10N_T1_34
+AB6,34,IOB_X1Y59,RIOB33_X57Y59,IO_L20N_T3_34
+AB7,34,IOB_X1Y60,RIOB33_X57Y59,IO_L20P_T3_34
+AB8,34,IOB_X1Y55,RIOB33_X57Y55,IO_L22N_T3_34
+AB10,13,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_13
+AB11,13,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_13
+AB12,13,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_13
+AB13,13,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_13
+AB15,13,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_13
+AB16,13,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_13
+AB17,13,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_13
+AB18,14,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_D14_14
+AB22,14,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_D15_14
+B1,35,IOB_X1Y148,RIOB33_X57Y147,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y145,RIOB33_X57Y145,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y9,GTP_CHANNEL_0_X130Y162,MGTPTXP0_216
+B6,216,OPAD_X0Y13,GTP_CHANNEL_2_X130Y191,MGTPTXP2_216
+B8,216,IPAD_X1Y37,GTP_CHANNEL_0_X130Y162,MGTPRXP0_216
+B10,216,IPAD_X1Y55,GTP_CHANNEL_2_X130Y191,MGTPRXP2_216
+B13,16,IOB_X0Y183,LIOB33_X0Y183,IO_L8N_T1_16
+B15,16,IOB_X0Y186,LIOB33_X0Y185,IO_L7P_T1_16
+B16,16,IOB_X0Y185,LIOB33_X0Y185,IO_L7N_T1_16
+B17,16,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_16
+B18,16,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_16
+B20,16,IOB_X0Y168,LIOB33_X0Y167,IO_L16P_T2_16
+B21,16,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_16
+B22,16,IOB_X0Y159,LIOB33_X0Y159,IO_L20N_T3_16
+C2,35,IOB_X1Y146,RIOB33_X57Y145,IO_L2P_T0_AD12P_35
+C5,216,OPAD_X0Y10,GTP_CHANNEL_1_X130Y173,MGTPTXN1_216
+C7,216,OPAD_X0Y14,GTP_CHANNEL_3_X130Y202,MGTPTXN3_216
+C9,216,IPAD_X1Y60,GTP_CHANNEL_3_X130Y202,MGTPRXN3_216
+C11,216,IPAD_X1Y42,GTP_CHANNEL_1_X130Y173,MGTPRXN1_216
+C13,16,IOB_X0Y184,LIOB33_X0Y183,IO_L8P_T1_16
+C14,16,IOB_X0Y194,LIOB33_X0Y193,IO_L3P_T0_DQS_16
+C15,16,IOB_X0Y193,LIOB33_X0Y193,IO_L3N_T0_DQS_16
+C17,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
+C18,16,IOB_X0Y174,LIOB33_X0Y173,IO_L13P_T2_MRCC_16
+C19,16,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_16
+C20,16,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_VREF_16
+C22,16,IOB_X0Y160,LIOB33_X0Y159,IO_L20P_T3_16
+D1,35,IOB_X1Y143,RIOB33_X57Y143,IO_L3N_T0_DQS_AD5N_35
+D2,35,IOB_X1Y141,RIOB33_X57Y141,IO_L4N_T0_35
+D5,216,OPAD_X0Y11,GTP_CHANNEL_1_X130Y173,MGTPTXP1_216
+D7,216,OPAD_X0Y15,GTP_CHANNEL_3_X130Y202,MGTPTXP3_216
+D9,216,IPAD_X1Y61,GTP_CHANNEL_3_X130Y202,MGTPRXP3_216
+D11,216,IPAD_X1Y43,GTP_CHANNEL_1_X130Y173,MGTPRXP1_216
+D14,16,IOB_X0Y188,LIOB33_X0Y187,IO_L6P_T0_16
+D15,16,IOB_X0Y187,LIOB33_X0Y187,IO_L6N_T0_VREF_16
+D16,16,IOB_X0Y189,LIOB33_X0Y189,IO_L5N_T0_16
+D17,16,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_16
+D19,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16
+D20,16,IOB_X0Y162,LIOB33_X0Y161,IO_L19P_T3_16
+D21,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+D22,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
+E1,35,IOB_X1Y144,RIOB33_X57Y143,IO_L3P_T0_DQS_AD5P_35
+E2,35,IOB_X1Y142,RIOB33_X57Y141,IO_L4P_T0_35
+E3,35,IOB_X1Y137,RIOB33_X57Y137,IO_L6N_T0_VREF_35
+E6,216,IPAD_X1Y45,GTP_COMMON_X130Y179,MGTREFCLK0N_216
+E10,216,IPAD_X1Y47,GTP_COMMON_X130Y179,MGTREFCLK1N_216
+E13,16,IOB_X0Y192,LIOB33_X0Y191,IO_L4P_T0_16
+E14,16,IOB_X0Y191,LIOB33_X0Y191,IO_L4N_T0_16
+E16,16,IOB_X0Y190,LIOB33_X0Y189,IO_L5P_T0_16
+E17,16,IOB_X0Y195,LIOB33_X0Y195,IO_L2N_T0_16
+E18,16,IOB_X0Y169,LIOB33_X0Y169,IO_L15N_T2_DQS_16
+E19,16,IOB_X0Y172,LIOB33_X0Y171,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_16
+E22,16,IOB_X0Y156,LIOB33_X0Y155,IO_L22P_T3_16
+F1,35,IOB_X1Y139,RIOB33_X57Y139,IO_L5N_T0_AD13N_35
+F3,35,IOB_X1Y138,RIOB33_X57Y137,IO_L6P_T0_35
+F4,35,IOB_X1Y149,RIOB33_SING_X57Y149,IO_0_35
+F6,216,IPAD_X1Y44,GTP_COMMON_X130Y179,MGTREFCLK0P_216
+F10,216,IPAD_X1Y46,GTP_COMMON_X130Y179,MGTREFCLK1P_216
+F13,16,IOB_X0Y198,LIOB33_X0Y197,IO_L1P_T0_16
+F14,16,IOB_X0Y197,LIOB33_X0Y197,IO_L1N_T0_16
+F15,16,IOB_X0Y199,LIOB33_SING_X0Y199,IO_0_16
+F16,16,IOB_X0Y196,LIOB33_X0Y195,IO_L2P_T0_16
+F18,16,IOB_X0Y170,LIOB33_X0Y169,IO_L15P_T2_DQS_16
+F19,16,IOB_X0Y164,LIOB33_X0Y163,IO_L18P_T2_16
+F20,16,IOB_X0Y163,LIOB33_X0Y163,IO_L18N_T2_16
+F21,16,IOB_X0Y150,LIOB33_SING_X0Y150,IO_25_16
+G1,35,IOB_X1Y140,RIOB33_X57Y139,IO_L5P_T0_AD13P_35
+G2,35,IOB_X1Y133,RIOB33_X57Y133,IO_L8N_T1_AD14N_35
+G3,35,IOB_X1Y127,RIOB33_X57Y127,IO_L11N_T1_SRCC_35
+G4,35,IOB_X1Y125,RIOB33_X57Y125,IO_L12N_T1_MRCC_35
+G13,15,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_AD0N_15
+G15,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+G16,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+G17,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_15
+G18,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_15
+G20,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD10N_15
+G21,16,IOB_X0Y152,LIOB33_X0Y151,IO_L24P_T3_16
+G22,16,IOB_X0Y151,LIOB33_X0Y151,IO_L24N_T3_16
+H2,35,IOB_X1Y134,RIOB33_X57Y133,IO_L8P_T1_AD14P_35
+H3,35,IOB_X1Y128,RIOB33_X57Y127,IO_L11P_T1_SRCC_35
+H4,35,IOB_X1Y126,RIOB33_X57Y125,IO_L12P_T1_MRCC_35
+H5,35,IOB_X1Y129,RIOB33_X57Y129,IO_L10N_T1_AD15N_35
+H13,15,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_AD0P_15
+H14,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+H15,15,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_AD9N_15
+H17,15,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_15
+H18,15,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_15
+H19,15,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_15
+H20,15,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_AD10P_15
+H22,15,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_AD2N_15
+J1,35,IOB_X1Y135,RIOB33_X57Y135,IO_L7N_T1_AD6N_35
+J2,35,IOB_X1Y131,RIOB33_X57Y131,IO_L9N_T1_DQS_AD7N_35
+J4,35,IOB_X1Y123,RIOB33_X57Y123,IO_L13N_T2_MRCC_35
+J5,35,IOB_X1Y130,RIOB33_X57Y129,IO_L10P_T1_AD15P_35
+J6,35,IOB_X1Y115,RIOB33_X57Y115,IO_L17N_T2_35
+J14,15,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_AD1P_15
+J15,15,IOB_X0Y140,LIOB33_X0Y139,IO_L5P_T0_AD9P_15
+J16,15,IOB_X0Y149,LIOB33_SING_X0Y149,IO_0_15
+J17,15,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_A18_15
+J19,15,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_15
+J20,15,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_15
+J21,15,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_15
+J22,15,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_AD2P_15
+K1,35,IOB_X1Y136,RIOB33_X57Y135,IO_L7P_T1_AD6P_35
+K2,35,IOB_X1Y132,RIOB33_X57Y131,IO_L9P_T1_DQS_AD7P_35
+K3,35,IOB_X1Y121,RIOB33_X57Y121,IO_L14N_T2_SRCC_35
+K4,35,IOB_X1Y124,RIOB33_X57Y123,IO_L13P_T2_MRCC_35
+K6,35,IOB_X1Y116,RIOB33_X57Y115,IO_L17P_T2_35
+K13,15,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_A22_15
+K14,15,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_A21_VREF_15
+K16,15,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_FWE_B_15
+K17,15,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_15
+K18,15,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_15
+K19,15,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_15
+K21,15,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_AD3P_15
+K22,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD3N_15
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diff --git a/artix7/xc7a100tfgg484-1/part.json b/artix7/xc7a100tfgg484-1/part.json
new file mode 100644
index 0000000..3a9350c
--- /dev/null
+++ b/artix7/xc7a100tfgg484-1/part.json
@@ -0,0 +1,772 @@
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+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "11": {
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+ },
+ "12": {
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+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 30
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 28
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 28
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 36
+ },
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+ },
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+ },
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+ },
+ "46": {
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+ },
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+ "frame_count": 36
+ },
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+ },
+ "49": {
+ "frame_count": 36
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 28
+ },
+ "52": {
+ "frame_count": 36
+ },
+ "53": {
+ "frame_count": 36
+ },
+ "54": {
+ "frame_count": 36
+ },
+ "55": {
+ "frame_count": 36
+ },
+ "56": {
+ "frame_count": 30
+ },
+ "57": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
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+ },
+ "5": {
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+ },
+ "6": {
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+ },
+ "7": {
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+ },
+ "8": {
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+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
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+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
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+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 30
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 28
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 28
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 36
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 28
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 36
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 28
+ },
+ "49": {
+ "frame_count": 36
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56823955,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182",
+ "34": "X146Y78",
+ "35": "X146Y130"
+ }
+}
diff --git a/artix7/xc7a100tfgg484-1/part.yaml b/artix7/xc7a100tfgg484-1/part.yaml
new file mode 100644
index 0000000..44833bb
--- /dev/null
+++ b/artix7/xc7a100tfgg484-1/part.yaml
@@ -0,0 +1,499 @@
+!<xilinx/xc7series/part>
+idcode: 0x3631093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a100tfgg484-2L/package_pins.csv b/artix7/xc7a100tfgg484-2L/package_pins.csv
new file mode 100644
index 0000000..1b027c4
--- /dev/null
+++ b/artix7/xc7a100tfgg484-2L/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y147,RIOB33_X57Y147,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y8,GTP_CHANNEL_0_X130Y162,MGTPTXN0_216
+A6,216,OPAD_X0Y12,GTP_CHANNEL_2_X130Y191,MGTPTXN2_216
+A8,216,IPAD_X1Y36,GTP_CHANNEL_0_X130Y162,MGTPRXN0_216
+A10,216,IPAD_X1Y54,GTP_CHANNEL_2_X130Y191,MGTPRXN2_216
+A13,16,IOB_X0Y180,LIOB33_X0Y179,IO_L10P_T1_16
+A14,16,IOB_X0Y179,LIOB33_X0Y179,IO_L10N_T1_16
+A15,16,IOB_X0Y182,LIOB33_X0Y181,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y181,LIOB33_X0Y181,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y166,LIOB33_X0Y165,IO_L17P_T2_16
+A19,16,IOB_X0Y165,LIOB33_X0Y165,IO_L17N_T2_16
+A20,16,IOB_X0Y167,LIOB33_X0Y167,IO_L16N_T2_16
+A21,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y86,RIOB33_X57Y85,IO_L7P_T1_34
+AA3,34,IOB_X1Y81,RIOB33_X57Y81,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y77,RIOB33_X57Y77,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y80,RIOB33_X57Y79,IO_L10P_T1_34
+AA6,34,IOB_X1Y63,RIOB33_X57Y63,IO_L18N_T2_34
+AA8,34,IOB_X1Y56,RIOB33_X57Y55,IO_L22P_T3_34
+AA9,13,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_13
+AA10,13,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_13
+AA11,13,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_13
+AA13,13,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_13
+AA14,13,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_13
+AA15,13,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_13
+AA16,13,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_13
+AA18,14,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y85,RIOB33_X57Y85,IO_L7N_T1_34
+AB2,34,IOB_X1Y83,RIOB33_X57Y83,IO_L8N_T1_34
+AB3,34,IOB_X1Y84,RIOB33_X57Y83,IO_L8P_T1_34
+AB5,34,IOB_X1Y79,RIOB33_X57Y79,IO_L10N_T1_34
+AB6,34,IOB_X1Y59,RIOB33_X57Y59,IO_L20N_T3_34
+AB7,34,IOB_X1Y60,RIOB33_X57Y59,IO_L20P_T3_34
+AB8,34,IOB_X1Y55,RIOB33_X57Y55,IO_L22N_T3_34
+AB10,13,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_13
+AB11,13,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_13
+AB12,13,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_13
+AB13,13,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_13
+AB15,13,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_13
+AB16,13,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_13
+AB17,13,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_13
+AB18,14,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_D14_14
+AB22,14,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_D15_14
+B1,35,IOB_X1Y148,RIOB33_X57Y147,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y145,RIOB33_X57Y145,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y9,GTP_CHANNEL_0_X130Y162,MGTPTXP0_216
+B6,216,OPAD_X0Y13,GTP_CHANNEL_2_X130Y191,MGTPTXP2_216
+B8,216,IPAD_X1Y37,GTP_CHANNEL_0_X130Y162,MGTPRXP0_216
+B10,216,IPAD_X1Y55,GTP_CHANNEL_2_X130Y191,MGTPRXP2_216
+B13,16,IOB_X0Y183,LIOB33_X0Y183,IO_L8N_T1_16
+B15,16,IOB_X0Y186,LIOB33_X0Y185,IO_L7P_T1_16
+B16,16,IOB_X0Y185,LIOB33_X0Y185,IO_L7N_T1_16
+B17,16,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_16
+B18,16,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_16
+B20,16,IOB_X0Y168,LIOB33_X0Y167,IO_L16P_T2_16
+B21,16,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_16
+B22,16,IOB_X0Y159,LIOB33_X0Y159,IO_L20N_T3_16
+C2,35,IOB_X1Y146,RIOB33_X57Y145,IO_L2P_T0_AD12P_35
+C5,216,OPAD_X0Y10,GTP_CHANNEL_1_X130Y173,MGTPTXN1_216
+C7,216,OPAD_X0Y14,GTP_CHANNEL_3_X130Y202,MGTPTXN3_216
+C9,216,IPAD_X1Y60,GTP_CHANNEL_3_X130Y202,MGTPRXN3_216
+C11,216,IPAD_X1Y42,GTP_CHANNEL_1_X130Y173,MGTPRXN1_216
+C13,16,IOB_X0Y184,LIOB33_X0Y183,IO_L8P_T1_16
+C14,16,IOB_X0Y194,LIOB33_X0Y193,IO_L3P_T0_DQS_16
+C15,16,IOB_X0Y193,LIOB33_X0Y193,IO_L3N_T0_DQS_16
+C17,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
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+C19,16,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_16
+C20,16,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_VREF_16
+C22,16,IOB_X0Y160,LIOB33_X0Y159,IO_L20P_T3_16
+D1,35,IOB_X1Y143,RIOB33_X57Y143,IO_L3N_T0_DQS_AD5N_35
+D2,35,IOB_X1Y141,RIOB33_X57Y141,IO_L4N_T0_35
+D5,216,OPAD_X0Y11,GTP_CHANNEL_1_X130Y173,MGTPTXP1_216
+D7,216,OPAD_X0Y15,GTP_CHANNEL_3_X130Y202,MGTPTXP3_216
+D9,216,IPAD_X1Y61,GTP_CHANNEL_3_X130Y202,MGTPRXP3_216
+D11,216,IPAD_X1Y43,GTP_CHANNEL_1_X130Y173,MGTPRXP1_216
+D14,16,IOB_X0Y188,LIOB33_X0Y187,IO_L6P_T0_16
+D15,16,IOB_X0Y187,LIOB33_X0Y187,IO_L6N_T0_VREF_16
+D16,16,IOB_X0Y189,LIOB33_X0Y189,IO_L5N_T0_16
+D17,16,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_16
+D19,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16
+D20,16,IOB_X0Y162,LIOB33_X0Y161,IO_L19P_T3_16
+D21,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+D22,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
+E1,35,IOB_X1Y144,RIOB33_X57Y143,IO_L3P_T0_DQS_AD5P_35
+E2,35,IOB_X1Y142,RIOB33_X57Y141,IO_L4P_T0_35
+E3,35,IOB_X1Y137,RIOB33_X57Y137,IO_L6N_T0_VREF_35
+E6,216,IPAD_X1Y45,GTP_COMMON_X130Y179,MGTREFCLK0N_216
+E10,216,IPAD_X1Y47,GTP_COMMON_X130Y179,MGTREFCLK1N_216
+E13,16,IOB_X0Y192,LIOB33_X0Y191,IO_L4P_T0_16
+E14,16,IOB_X0Y191,LIOB33_X0Y191,IO_L4N_T0_16
+E16,16,IOB_X0Y190,LIOB33_X0Y189,IO_L5P_T0_16
+E17,16,IOB_X0Y195,LIOB33_X0Y195,IO_L2N_T0_16
+E18,16,IOB_X0Y169,LIOB33_X0Y169,IO_L15N_T2_DQS_16
+E19,16,IOB_X0Y172,LIOB33_X0Y171,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_16
+E22,16,IOB_X0Y156,LIOB33_X0Y155,IO_L22P_T3_16
+F1,35,IOB_X1Y139,RIOB33_X57Y139,IO_L5N_T0_AD13N_35
+F3,35,IOB_X1Y138,RIOB33_X57Y137,IO_L6P_T0_35
+F4,35,IOB_X1Y149,RIOB33_SING_X57Y149,IO_0_35
+F6,216,IPAD_X1Y44,GTP_COMMON_X130Y179,MGTREFCLK0P_216
+F10,216,IPAD_X1Y46,GTP_COMMON_X130Y179,MGTREFCLK1P_216
+F13,16,IOB_X0Y198,LIOB33_X0Y197,IO_L1P_T0_16
+F14,16,IOB_X0Y197,LIOB33_X0Y197,IO_L1N_T0_16
+F15,16,IOB_X0Y199,LIOB33_SING_X0Y199,IO_0_16
+F16,16,IOB_X0Y196,LIOB33_X0Y195,IO_L2P_T0_16
+F18,16,IOB_X0Y170,LIOB33_X0Y169,IO_L15P_T2_DQS_16
+F19,16,IOB_X0Y164,LIOB33_X0Y163,IO_L18P_T2_16
+F20,16,IOB_X0Y163,LIOB33_X0Y163,IO_L18N_T2_16
+F21,16,IOB_X0Y150,LIOB33_SING_X0Y150,IO_25_16
+G1,35,IOB_X1Y140,RIOB33_X57Y139,IO_L5P_T0_AD13P_35
+G2,35,IOB_X1Y133,RIOB33_X57Y133,IO_L8N_T1_AD14N_35
+G3,35,IOB_X1Y127,RIOB33_X57Y127,IO_L11N_T1_SRCC_35
+G4,35,IOB_X1Y125,RIOB33_X57Y125,IO_L12N_T1_MRCC_35
+G13,15,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_AD0N_15
+G15,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+G16,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+G17,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_15
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+G21,16,IOB_X0Y152,LIOB33_X0Y151,IO_L24P_T3_16
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+H2,35,IOB_X1Y134,RIOB33_X57Y133,IO_L8P_T1_AD14P_35
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+H13,15,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_AD0P_15
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+J5,35,IOB_X1Y130,RIOB33_X57Y129,IO_L10P_T1_AD15P_35
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+K17,15,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_15
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+L6,35,IOB_X1Y100,RIOB33_SING_X57Y100,IO_25_35
+L10,0,IPAD_X0Y30,MONITOR_BOT_X46Y131,VP_0
+L13,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
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+L15,15,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A16_15
+L16,15,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_FOE_B_15
+L18,15,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A27_15
+L19,15,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_15
+L20,15,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_15
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diff --git a/artix7/xc7a100tfgg484-2L/part.json b/artix7/xc7a100tfgg484-2L/part.json
new file mode 100644
index 0000000..3a9350c
--- /dev/null
+++ b/artix7/xc7a100tfgg484-2L/part.json
@@ -0,0 +1,772 @@
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+ "30": {
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+ },
+ "31": {
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+ },
+ "32": {
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+ },
+ "33": {
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+ },
+ "34": {
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+ },
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+ },
+ "36": {
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+ },
+ "37": {
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+ },
+ "38": {
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+ },
+ "39": {
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+ },
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+ },
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+ },
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+ },
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+ },
+ "55": {
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+ },
+ "56": {
+ "frame_count": 30
+ },
+ "57": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "14": {
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+ },
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+ },
+ "16": {
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+ },
+ "17": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "31": {
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+ },
+ "32": {
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+ },
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+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
+ "35": {
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+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
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+ },
+ "39": {
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+ },
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+ },
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+ },
+ "42": {
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+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
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+ },
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+ },
+ "46": {
+ "frame_count": 36
+ },
+ "47": {
+ "frame_count": 36
+ },
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+ "frame_count": 28
+ },
+ "49": {
+ "frame_count": 36
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56823955,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182",
+ "34": "X146Y78",
+ "35": "X146Y130"
+ }
+}
diff --git a/artix7/xc7a100tfgg484-2L/part.yaml b/artix7/xc7a100tfgg484-2L/part.yaml
new file mode 100644
index 0000000..44833bb
--- /dev/null
+++ b/artix7/xc7a100tfgg484-2L/part.yaml
@@ -0,0 +1,499 @@
+!<xilinx/xc7series/part>
+idcode: 0x3631093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
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+ 14: !<xilinx/xc7series/configuration_column>
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+ 15: !<xilinx/xc7series/configuration_column>
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+ 16: !<xilinx/xc7series/configuration_column>
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+ 18: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
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+ 43: !<xilinx/xc7series/configuration_column>
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+ 45: !<xilinx/xc7series/configuration_column>
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+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
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+ 48: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
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+ 2: !<xilinx/xc7series/configuration_column>
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+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a100tfgg484-3/package_pins.csv b/artix7/xc7a100tfgg484-3/package_pins.csv
new file mode 100644
index 0000000..1b027c4
--- /dev/null
+++ b/artix7/xc7a100tfgg484-3/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y147,RIOB33_X57Y147,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y8,GTP_CHANNEL_0_X130Y162,MGTPTXN0_216
+A6,216,OPAD_X0Y12,GTP_CHANNEL_2_X130Y191,MGTPTXN2_216
+A8,216,IPAD_X1Y36,GTP_CHANNEL_0_X130Y162,MGTPRXN0_216
+A10,216,IPAD_X1Y54,GTP_CHANNEL_2_X130Y191,MGTPRXN2_216
+A13,16,IOB_X0Y180,LIOB33_X0Y179,IO_L10P_T1_16
+A14,16,IOB_X0Y179,LIOB33_X0Y179,IO_L10N_T1_16
+A15,16,IOB_X0Y182,LIOB33_X0Y181,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y181,LIOB33_X0Y181,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y166,LIOB33_X0Y165,IO_L17P_T2_16
+A19,16,IOB_X0Y165,LIOB33_X0Y165,IO_L17N_T2_16
+A20,16,IOB_X0Y167,LIOB33_X0Y167,IO_L16N_T2_16
+A21,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y86,RIOB33_X57Y85,IO_L7P_T1_34
+AA3,34,IOB_X1Y81,RIOB33_X57Y81,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y77,RIOB33_X57Y77,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y80,RIOB33_X57Y79,IO_L10P_T1_34
+AA6,34,IOB_X1Y63,RIOB33_X57Y63,IO_L18N_T2_34
+AA8,34,IOB_X1Y56,RIOB33_X57Y55,IO_L22P_T3_34
+AA9,13,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_13
+AA10,13,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_13
+AA11,13,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_13
+AA13,13,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_13
+AA14,13,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_13
+AA15,13,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_13
+AA16,13,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_13
+AA18,14,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y85,RIOB33_X57Y85,IO_L7N_T1_34
+AB2,34,IOB_X1Y83,RIOB33_X57Y83,IO_L8N_T1_34
+AB3,34,IOB_X1Y84,RIOB33_X57Y83,IO_L8P_T1_34
+AB5,34,IOB_X1Y79,RIOB33_X57Y79,IO_L10N_T1_34
+AB6,34,IOB_X1Y59,RIOB33_X57Y59,IO_L20N_T3_34
+AB7,34,IOB_X1Y60,RIOB33_X57Y59,IO_L20P_T3_34
+AB8,34,IOB_X1Y55,RIOB33_X57Y55,IO_L22N_T3_34
+AB10,13,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_13
+AB11,13,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_13
+AB12,13,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_13
+AB13,13,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_13
+AB15,13,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_13
+AB16,13,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_13
+AB17,13,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_13
+AB18,14,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_D14_14
+AB22,14,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_D15_14
+B1,35,IOB_X1Y148,RIOB33_X57Y147,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y145,RIOB33_X57Y145,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y9,GTP_CHANNEL_0_X130Y162,MGTPTXP0_216
+B6,216,OPAD_X0Y13,GTP_CHANNEL_2_X130Y191,MGTPTXP2_216
+B8,216,IPAD_X1Y37,GTP_CHANNEL_0_X130Y162,MGTPRXP0_216
+B10,216,IPAD_X1Y55,GTP_CHANNEL_2_X130Y191,MGTPRXP2_216
+B13,16,IOB_X0Y183,LIOB33_X0Y183,IO_L8N_T1_16
+B15,16,IOB_X0Y186,LIOB33_X0Y185,IO_L7P_T1_16
+B16,16,IOB_X0Y185,LIOB33_X0Y185,IO_L7N_T1_16
+B17,16,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_16
+B18,16,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_16
+B20,16,IOB_X0Y168,LIOB33_X0Y167,IO_L16P_T2_16
+B21,16,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_16
+B22,16,IOB_X0Y159,LIOB33_X0Y159,IO_L20N_T3_16
+C2,35,IOB_X1Y146,RIOB33_X57Y145,IO_L2P_T0_AD12P_35
+C5,216,OPAD_X0Y10,GTP_CHANNEL_1_X130Y173,MGTPTXN1_216
+C7,216,OPAD_X0Y14,GTP_CHANNEL_3_X130Y202,MGTPTXN3_216
+C9,216,IPAD_X1Y60,GTP_CHANNEL_3_X130Y202,MGTPRXN3_216
+C11,216,IPAD_X1Y42,GTP_CHANNEL_1_X130Y173,MGTPRXN1_216
+C13,16,IOB_X0Y184,LIOB33_X0Y183,IO_L8P_T1_16
+C14,16,IOB_X0Y194,LIOB33_X0Y193,IO_L3P_T0_DQS_16
+C15,16,IOB_X0Y193,LIOB33_X0Y193,IO_L3N_T0_DQS_16
+C17,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
+C18,16,IOB_X0Y174,LIOB33_X0Y173,IO_L13P_T2_MRCC_16
+C19,16,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_16
+C20,16,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_VREF_16
+C22,16,IOB_X0Y160,LIOB33_X0Y159,IO_L20P_T3_16
+D1,35,IOB_X1Y143,RIOB33_X57Y143,IO_L3N_T0_DQS_AD5N_35
+D2,35,IOB_X1Y141,RIOB33_X57Y141,IO_L4N_T0_35
+D5,216,OPAD_X0Y11,GTP_CHANNEL_1_X130Y173,MGTPTXP1_216
+D7,216,OPAD_X0Y15,GTP_CHANNEL_3_X130Y202,MGTPTXP3_216
+D9,216,IPAD_X1Y61,GTP_CHANNEL_3_X130Y202,MGTPRXP3_216
+D11,216,IPAD_X1Y43,GTP_CHANNEL_1_X130Y173,MGTPRXP1_216
+D14,16,IOB_X0Y188,LIOB33_X0Y187,IO_L6P_T0_16
+D15,16,IOB_X0Y187,LIOB33_X0Y187,IO_L6N_T0_VREF_16
+D16,16,IOB_X0Y189,LIOB33_X0Y189,IO_L5N_T0_16
+D17,16,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_16
+D19,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16
+D20,16,IOB_X0Y162,LIOB33_X0Y161,IO_L19P_T3_16
+D21,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+D22,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
+E1,35,IOB_X1Y144,RIOB33_X57Y143,IO_L3P_T0_DQS_AD5P_35
+E2,35,IOB_X1Y142,RIOB33_X57Y141,IO_L4P_T0_35
+E3,35,IOB_X1Y137,RIOB33_X57Y137,IO_L6N_T0_VREF_35
+E6,216,IPAD_X1Y45,GTP_COMMON_X130Y179,MGTREFCLK0N_216
+E10,216,IPAD_X1Y47,GTP_COMMON_X130Y179,MGTREFCLK1N_216
+E13,16,IOB_X0Y192,LIOB33_X0Y191,IO_L4P_T0_16
+E14,16,IOB_X0Y191,LIOB33_X0Y191,IO_L4N_T0_16
+E16,16,IOB_X0Y190,LIOB33_X0Y189,IO_L5P_T0_16
+E17,16,IOB_X0Y195,LIOB33_X0Y195,IO_L2N_T0_16
+E18,16,IOB_X0Y169,LIOB33_X0Y169,IO_L15N_T2_DQS_16
+E19,16,IOB_X0Y172,LIOB33_X0Y171,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_16
+E22,16,IOB_X0Y156,LIOB33_X0Y155,IO_L22P_T3_16
+F1,35,IOB_X1Y139,RIOB33_X57Y139,IO_L5N_T0_AD13N_35
+F3,35,IOB_X1Y138,RIOB33_X57Y137,IO_L6P_T0_35
+F4,35,IOB_X1Y149,RIOB33_SING_X57Y149,IO_0_35
+F6,216,IPAD_X1Y44,GTP_COMMON_X130Y179,MGTREFCLK0P_216
+F10,216,IPAD_X1Y46,GTP_COMMON_X130Y179,MGTREFCLK1P_216
+F13,16,IOB_X0Y198,LIOB33_X0Y197,IO_L1P_T0_16
+F14,16,IOB_X0Y197,LIOB33_X0Y197,IO_L1N_T0_16
+F15,16,IOB_X0Y199,LIOB33_SING_X0Y199,IO_0_16
+F16,16,IOB_X0Y196,LIOB33_X0Y195,IO_L2P_T0_16
+F18,16,IOB_X0Y170,LIOB33_X0Y169,IO_L15P_T2_DQS_16
+F19,16,IOB_X0Y164,LIOB33_X0Y163,IO_L18P_T2_16
+F20,16,IOB_X0Y163,LIOB33_X0Y163,IO_L18N_T2_16
+F21,16,IOB_X0Y150,LIOB33_SING_X0Y150,IO_25_16
+G1,35,IOB_X1Y140,RIOB33_X57Y139,IO_L5P_T0_AD13P_35
+G2,35,IOB_X1Y133,RIOB33_X57Y133,IO_L8N_T1_AD14N_35
+G3,35,IOB_X1Y127,RIOB33_X57Y127,IO_L11N_T1_SRCC_35
+G4,35,IOB_X1Y125,RIOB33_X57Y125,IO_L12N_T1_MRCC_35
+G13,15,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_AD0N_15
+G15,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+G16,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+G17,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_15
+G18,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_15
+G20,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD10N_15
+G21,16,IOB_X0Y152,LIOB33_X0Y151,IO_L24P_T3_16
+G22,16,IOB_X0Y151,LIOB33_X0Y151,IO_L24N_T3_16
+H2,35,IOB_X1Y134,RIOB33_X57Y133,IO_L8P_T1_AD14P_35
+H3,35,IOB_X1Y128,RIOB33_X57Y127,IO_L11P_T1_SRCC_35
+H4,35,IOB_X1Y126,RIOB33_X57Y125,IO_L12P_T1_MRCC_35
+H5,35,IOB_X1Y129,RIOB33_X57Y129,IO_L10N_T1_AD15N_35
+H13,15,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_AD0P_15
+H14,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+H15,15,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_AD9N_15
+H17,15,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_15
+H18,15,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_15
+H19,15,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_15
+H20,15,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_AD10P_15
+H22,15,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_AD2N_15
+J1,35,IOB_X1Y135,RIOB33_X57Y135,IO_L7N_T1_AD6N_35
+J2,35,IOB_X1Y131,RIOB33_X57Y131,IO_L9N_T1_DQS_AD7N_35
+J4,35,IOB_X1Y123,RIOB33_X57Y123,IO_L13N_T2_MRCC_35
+J5,35,IOB_X1Y130,RIOB33_X57Y129,IO_L10P_T1_AD15P_35
+J6,35,IOB_X1Y115,RIOB33_X57Y115,IO_L17N_T2_35
+J14,15,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_AD1P_15
+J15,15,IOB_X0Y140,LIOB33_X0Y139,IO_L5P_T0_AD9P_15
+J16,15,IOB_X0Y149,LIOB33_SING_X0Y149,IO_0_15
+J17,15,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_A18_15
+J19,15,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_15
+J20,15,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_15
+J21,15,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_15
+J22,15,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_AD2P_15
+K1,35,IOB_X1Y136,RIOB33_X57Y135,IO_L7P_T1_AD6P_35
+K2,35,IOB_X1Y132,RIOB33_X57Y131,IO_L9P_T1_DQS_AD7P_35
+K3,35,IOB_X1Y121,RIOB33_X57Y121,IO_L14N_T2_SRCC_35
+K4,35,IOB_X1Y124,RIOB33_X57Y123,IO_L13P_T2_MRCC_35
+K6,35,IOB_X1Y116,RIOB33_X57Y115,IO_L17P_T2_35
+K13,15,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_A22_15
+K14,15,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_A21_VREF_15
+K16,15,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_FWE_B_15
+K17,15,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_15
+K18,15,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_15
+K19,15,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_15
+K21,15,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_AD3P_15
+K22,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD3N_15
+L1,35,IOB_X1Y119,RIOB33_X57Y119,IO_L15N_T2_DQS_35
+L3,35,IOB_X1Y122,RIOB33_X57Y121,IO_L14P_T2_SRCC_35
+L4,35,IOB_X1Y113,RIOB33_X57Y113,IO_L18N_T2_35
+L5,35,IOB_X1Y114,RIOB33_X57Y113,IO_L18P_T2_35
+L6,35,IOB_X1Y100,RIOB33_SING_X57Y100,IO_25_35
+L10,0,IPAD_X0Y30,MONITOR_BOT_X46Y131,VP_0
+L13,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
+L14,15,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A17_15
+L15,15,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A16_15
+L16,15,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_FOE_B_15
+L18,15,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A27_15
+L19,15,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_15
+L20,15,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_15
+L21,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD11N_15
+M1,35,IOB_X1Y120,RIOB33_X57Y119,IO_L15P_T2_DQS_35
+M2,35,IOB_X1Y117,RIOB33_X57Y117,IO_L16N_T2_35
+M3,35,IOB_X1Y118,RIOB33_X57Y117,IO_L16P_T2_35
+M5,35,IOB_X1Y103,RIOB33_X57Y103,IO_L23N_T3_35
+M6,35,IOB_X1Y104,RIOB33_X57Y103,IO_L23P_T3_35
+M9,0,IPAD_X0Y31,MONITOR_BOT_X46Y131,VN_0
+M13,15,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A20_15
+M15,15,IOB_X0Y102,LIOB33_X0Y101,IO_L24P_T3_RS1_15
+M16,15,IOB_X0Y101,LIOB33_X0Y101,IO_L24N_T3_RS0_15
+M17,15,IOB_X0Y100,LIOB33_SING_X0Y100,IO_25_15
+M18,15,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_A28_15
+M20,15,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_A23_15
+M21,15,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_AD11P_15
+M22,15,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_ADV_B_15
+N2,35,IOB_X1Y105,RIOB33_X57Y105,IO_L22N_T3_35
+N3,35,IOB_X1Y111,RIOB33_X57Y111,IO_L19N_T3_VREF_35
+N4,35,IOB_X1Y112,RIOB33_X57Y111,IO_L19P_T3_35
+N5,35,IOB_X1Y101,RIOB33_X57Y101,IO_L24N_T3_35
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diff --git a/artix7/xc7a100tfgg484-3/part.json b/artix7/xc7a100tfgg484-3/part.json
new file mode 100644
index 0000000..3a9350c
--- /dev/null
+++ b/artix7/xc7a100tfgg484-3/part.json
@@ -0,0 +1,772 @@
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+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
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+ },
+ "7": {
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+ },
+ "8": {
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+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
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+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
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+ },
+ "22": {
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+ },
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+ },
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+ },
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+ },
+ "26": {
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+ },
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+ },
+ "28": {
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+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 30
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 28
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 28
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 36
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 28
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 36
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 28
+ },
+ "49": {
+ "frame_count": 36
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56823955,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182",
+ "34": "X146Y78",
+ "35": "X146Y130"
+ }
+}
diff --git a/artix7/xc7a100tfgg484-3/part.yaml b/artix7/xc7a100tfgg484-3/part.yaml
new file mode 100644
index 0000000..44833bb
--- /dev/null
+++ b/artix7/xc7a100tfgg484-3/part.yaml
@@ -0,0 +1,499 @@
+!<xilinx/xc7series/part>
+idcode: 0x3631093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
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+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
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+ 21: !<xilinx/xc7series/configuration_column>
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+ 22: !<xilinx/xc7series/configuration_column>
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+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ frame_count: 36
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+ frame_count: 36
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+ frame_count: 36
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+ frame_count: 36
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+ frame_count: 30
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+ frame_count: 36
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+ frame_count: 36
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+ frame_count: 36
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+ 39: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
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+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
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+ 50: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
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+ frame_count: 36
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+ frame_count: 36
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+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
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+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a100tfgg676-2/package_pins.csv b/artix7/xc7a100tfgg676-2/package_pins.csv
new file mode 100644
index 0000000..ee263e4
--- /dev/null
+++ b/artix7/xc7a100tfgg676-2/package_pins.csv
@@ -0,0 +1,343 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y109,RIOB33_X57Y109,IO_L20N_T3_35
+A3,35,IOB_X1Y110,RIOB33_X57Y109,IO_L20P_T3_35
+A4,35,IOB_X1Y117,RIOB33_X57Y117,IO_L16N_T2_35
+A5,35,IOB_X1Y119,RIOB33_X57Y119,IO_L15N_T2_DQS_35
+A7,216,OPAD_X0Y8,GTP_CHANNEL_0_X130Y162,MGTPTXN0_216
+A9,216,OPAD_X0Y12,GTP_CHANNEL_2_X130Y191,MGTPTXN2_216
+A11,216,IPAD_X1Y36,GTP_CHANNEL_0_X130Y162,MGTPRXN0_216
+A13,216,IPAD_X1Y54,GTP_CHANNEL_2_X130Y191,MGTPRXN2_216
+A17,16,IOB_X0Y182,LIOB33_X0Y181,IO_L9P_T1_DQS_16
+A18,16,IOB_X0Y181,LIOB33_X0Y181,IO_L9N_T1_DQS_16
+A19,16,IOB_X0Y179,LIOB33_X0Y179,IO_L10N_T1_16
+A20,16,IOB_X0Y169,LIOB33_X0Y169,IO_L15N_T2_DQS_16
+A22,16,IOB_X0Y165,LIOB33_X0Y165,IO_L17N_T2_16
+A23,16,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_16
+A24,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A25,16,IOB_X0Y159,LIOB33_X0Y159,IO_L20N_T3_16
+AA11,213,IPAD_X1Y10,GTP_COMMON_X130Y23,MGTREFCLK1P_213
+AA13,213,IPAD_X1Y8,GTP_COMMON_X130Y23,MGTREFCLK0P_213
+AA22,13,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_13
+AA23,13,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_13
+AA24,13,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_13
+AA25,13,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_13
+AB11,213,IPAD_X1Y11,GTP_COMMON_X130Y23,MGTREFCLK1N_213
+AB13,213,IPAD_X1Y9,GTP_COMMON_X130Y23,MGTREFCLK0N_213
+AB24,13,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_13
+AB25,13,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_13
+AB26,13,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_13
+AC8,213,OPAD_X0Y5,GTP_CHANNEL_2_X130Y35,MGTPTXP2_213
+AC10,213,OPAD_X0Y1,GTP_CHANNEL_0_X130Y6,MGTPTXP0_213
+AC12,213,IPAD_X1Y1,GTP_CHANNEL_0_X130Y6,MGTPRXP0_213
+AC14,213,IPAD_X1Y19,GTP_CHANNEL_2_X130Y35,MGTPRXP2_213
+AC24,13,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_13
+AC26,13,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_13
+AD8,213,OPAD_X0Y4,GTP_CHANNEL_2_X130Y35,MGTPTXN2_213
+AD10,213,OPAD_X0Y0,GTP_CHANNEL_0_X130Y6,MGTPTXN0_213
+AD12,213,IPAD_X1Y0,GTP_CHANNEL_0_X130Y6,MGTPRXN0_213
+AD14,213,IPAD_X1Y18,GTP_CHANNEL_2_X130Y35,MGTPRXN2_213
+AE7,213,OPAD_X0Y7,GTP_CHANNEL_3_X130Y46,MGTPTXP3_213
+AE9,213,OPAD_X0Y3,GTP_CHANNEL_1_X130Y17,MGTPTXP1_213
+AE11,213,IPAD_X1Y25,GTP_CHANNEL_3_X130Y46,MGTPRXP3_213
+AE13,213,IPAD_X1Y7,GTP_CHANNEL_1_X130Y17,MGTPRXP1_213
+AF7,213,OPAD_X0Y6,GTP_CHANNEL_3_X130Y46,MGTPTXN3_213
+AF9,213,OPAD_X0Y2,GTP_CHANNEL_1_X130Y17,MGTPTXN1_213
+AF11,213,IPAD_X1Y24,GTP_CHANNEL_3_X130Y46,MGTPRXN3_213
+AF13,213,IPAD_X1Y6,GTP_CHANNEL_1_X130Y17,MGTPRXN1_213
+B1,35,IOB_X1Y107,RIOB33_X57Y107,IO_L21N_T3_DQS_35
+B2,35,IOB_X1Y111,RIOB33_X57Y111,IO_L19N_T3_VREF_35
+B4,35,IOB_X1Y118,RIOB33_X57Y117,IO_L16P_T2_35
+B5,35,IOB_X1Y120,RIOB33_X57Y119,IO_L15P_T2_DQS_35
+B7,216,OPAD_X0Y9,GTP_CHANNEL_0_X130Y162,MGTPTXP0_216
+B9,216,OPAD_X0Y13,GTP_CHANNEL_2_X130Y191,MGTPTXP2_216
+B11,216,IPAD_X1Y37,GTP_CHANNEL_0_X130Y162,MGTPRXP0_216
+B13,216,IPAD_X1Y55,GTP_CHANNEL_2_X130Y191,MGTPRXP2_216
+B17,16,IOB_X0Y185,LIOB33_X0Y185,IO_L7N_T1_16
+B19,16,IOB_X0Y180,LIOB33_X0Y179,IO_L10P_T1_16
+B20,16,IOB_X0Y170,LIOB33_X0Y169,IO_L15P_T2_DQS_16
+B21,16,IOB_X0Y167,LIOB33_X0Y167,IO_L16N_T2_16
+B22,16,IOB_X0Y166,LIOB33_X0Y165,IO_L17P_T2_16
+B24,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+B25,16,IOB_X0Y160,LIOB33_X0Y159,IO_L20P_T3_16
+B26,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
+C1,35,IOB_X1Y108,RIOB33_X57Y107,IO_L21P_T3_DQS_35
+C2,35,IOB_X1Y112,RIOB33_X57Y111,IO_L19P_T3_35
+C3,35,IOB_X1Y115,RIOB33_X57Y115,IO_L17N_T2_35
+C4,35,IOB_X1Y121,RIOB33_X57Y121,IO_L14N_T2_SRCC_35
+C8,216,OPAD_X0Y10,GTP_CHANNEL_1_X130Y173,MGTPTXN1_216
+C10,216,OPAD_X0Y14,GTP_CHANNEL_3_X130Y202,MGTPTXN3_216
+C12,216,IPAD_X1Y60,GTP_CHANNEL_3_X130Y202,MGTPRXN3_216
+C14,216,IPAD_X1Y42,GTP_CHANNEL_1_X130Y173,MGTPRXN1_216
+C17,16,IOB_X0Y186,LIOB33_X0Y185,IO_L7P_T1_16
+C18,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
+C19,16,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_16
+C21,16,IOB_X0Y168,LIOB33_X0Y167,IO_L16P_T2_16
+C22,16,IOB_X0Y162,LIOB33_X0Y161,IO_L19P_T3_16
+C23,16,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_VREF_16
+C24,16,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_16
+C26,16,IOB_X0Y156,LIOB33_X0Y155,IO_L22P_T3_16
+D1,35,IOB_X1Y103,RIOB33_X57Y103,IO_L23N_T3_35
+D3,35,IOB_X1Y116,RIOB33_X57Y115,IO_L17P_T2_35
+D4,35,IOB_X1Y122,RIOB33_X57Y121,IO_L14P_T2_SRCC_35
+D5,35,IOB_X1Y123,RIOB33_X57Y123,IO_L13N_T2_MRCC_35
+D6,35,IOB_X1Y147,RIOB33_X57Y147,IO_L1N_T0_AD4N_35
+D8,216,OPAD_X0Y11,GTP_CHANNEL_1_X130Y173,MGTPTXP1_216
+D10,216,OPAD_X0Y15,GTP_CHANNEL_3_X130Y202,MGTPTXP3_216
+D12,216,IPAD_X1Y61,GTP_CHANNEL_3_X130Y202,MGTPRXP3_216
+D14,216,IPAD_X1Y43,GTP_CHANNEL_1_X130Y173,MGTPRXP1_216
+D16,16,IOB_X0Y183,LIOB33_X0Y183,IO_L8N_T1_16
+D18,16,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_16
+D19,16,IOB_X0Y174,LIOB33_X0Y173,IO_L13P_T2_MRCC_16
+D20,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16
+D21,16,IOB_X0Y163,LIOB33_X0Y163,IO_L18N_T2_16
+D23,16,IOB_X0Y152,LIOB33_X0Y151,IO_L24P_T3_16
+D24,16,IOB_X0Y151,LIOB33_X0Y151,IO_L24N_T3_16
+D25,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
+D26,15,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_A18_15
+E1,35,IOB_X1Y104,RIOB33_X57Y103,IO_L23P_T3_35
+E2,35,IOB_X1Y105,RIOB33_X57Y105,IO_L22N_T3_35
+E3,35,IOB_X1Y113,RIOB33_X57Y113,IO_L18N_T2_35
+E5,35,IOB_X1Y124,RIOB33_X57Y123,IO_L13P_T2_MRCC_35
+E6,35,IOB_X1Y148,RIOB33_X57Y147,IO_L1P_T0_AD4P_35
+E11,216,IPAD_X1Y45,GTP_COMMON_X130Y179,MGTREFCLK0N_216
+E13,216,IPAD_X1Y47,GTP_COMMON_X130Y179,MGTREFCLK1N_216
+E16,16,IOB_X0Y184,LIOB33_X0Y183,IO_L8P_T1_16
+E17,16,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_16
+E18,16,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_16
+E20,16,IOB_X0Y172,LIOB33_X0Y171,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y164,LIOB33_X0Y163,IO_L18P_T2_16
+E22,16,IOB_X0Y150,LIOB33_SING_X0Y150,IO_25_16
+E23,15,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A25_15
+E25,15,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A20_15
+E26,15,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_15
+F2,35,IOB_X1Y106,RIOB33_X57Y105,IO_L22P_T3_35
+F3,35,IOB_X1Y114,RIOB33_X57Y113,IO_L18P_T2_35
+F4,35,IOB_X1Y127,RIOB33_X57Y127,IO_L11N_T1_SRCC_35
+F5,35,IOB_X1Y125,RIOB33_X57Y125,IO_L12N_T1_MRCC_35
+F7,35,IOB_X1Y141,RIOB33_X57Y141,IO_L4N_T0_35
+F8,35,IOB_X1Y142,RIOB33_X57Y141,IO_L4P_T0_35
+F11,216,IPAD_X1Y44,GTP_COMMON_X130Y179,MGTREFCLK0P_216
+F13,216,IPAD_X1Y46,GTP_COMMON_X130Y179,MGTREFCLK1P_216
+F15,16,IOB_X0Y191,LIOB33_X0Y191,IO_L4N_T0_16
+F17,16,IOB_X0Y195,LIOB33_X0Y195,IO_L2N_T0_16
+F18,16,IOB_X0Y194,LIOB33_X0Y193,IO_L3P_T0_DQS_16
+F19,16,IOB_X0Y193,LIOB33_X0Y193,IO_L3N_T0_DQS_16
+F20,16,IOB_X0Y189,LIOB33_X0Y189,IO_L5N_T0_16
+F22,15,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_ADV_B_15
+F23,15,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A26_15
+F24,15,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_A21_VREF_15
+F25,15,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_FWE_B_15
+G1,35,IOB_X1Y101,RIOB33_X57Y101,IO_L24N_T3_35
+G2,35,IOB_X1Y102,RIOB33_X57Y101,IO_L24P_T3_35
+G4,35,IOB_X1Y128,RIOB33_X57Y127,IO_L11P_T1_SRCC_35
+G5,35,IOB_X1Y126,RIOB33_X57Y125,IO_L12P_T1_MRCC_35
+G6,35,IOB_X1Y139,RIOB33_X57Y139,IO_L5N_T0_AD13N_35
+G7,35,IOB_X1Y143,RIOB33_X57Y143,IO_L3N_T0_DQS_AD5N_35
+G8,35,IOB_X1Y145,RIOB33_X57Y145,IO_L2N_T0_AD12N_35
+G9,35,IOB_X1Y137,RIOB33_X57Y137,IO_L6N_T0_VREF_35
+G15,16,IOB_X0Y192,LIOB33_X0Y191,IO_L4P_T0_16
+G16,16,IOB_X0Y187,LIOB33_X0Y187,IO_L6N_T0_VREF_16
+G17,16,IOB_X0Y196,LIOB33_X0Y195,IO_L2P_T0_16
+G19,16,IOB_X0Y190,LIOB33_X0Y189,IO_L5P_T0_16
+G20,15,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_15
+G21,15,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_15
+G22,15,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_15
+G24,15,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_A22_15
+G25,15,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_FOE_B_15
+G26,15,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A16_15
+H1,34,IOB_X1Y79,RIOB33_X57Y79,IO_L10N_T1_34
+H2,34,IOB_X1Y80,RIOB33_X57Y79,IO_L10P_T1_34
+H3,35,IOB_X1Y100,RIOB33_SING_X57Y100,IO_25_35
+H4,35,IOB_X1Y131,RIOB33_X57Y131,IO_L9N_T1_DQS_AD7N_35
+H6,35,IOB_X1Y140,RIOB33_X57Y139,IO_L5P_T0_AD13P_35
+H7,35,IOB_X1Y144,RIOB33_X57Y143,IO_L3P_T0_DQS_AD5P_35
+H8,35,IOB_X1Y146,RIOB33_X57Y145,IO_L2P_T0_AD12P_35
+H9,35,IOB_X1Y138,RIOB33_X57Y137,IO_L6P_T0_35
+H14,16,IOB_X0Y198,LIOB33_X0Y197,IO_L1P_T0_16
+H15,16,IOB_X0Y197,LIOB33_X0Y197,IO_L1N_T0_16
+H16,16,IOB_X0Y188,LIOB33_X0Y187,IO_L6P_T0_16
+H17,16,IOB_X0Y199,LIOB33_SING_X0Y199,IO_0_16
+H18,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD11N_15
+H19,15,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_AD2N_15
+H21,15,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_15
+H22,15,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_15
+H23,15,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_15
+H24,15,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A27_15
+H26,15,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A17_15
+J1,34,IOB_X1Y85,RIOB33_X57Y85,IO_L7N_T1_34
+J3,34,IOB_X1Y97,RIOB33_X57Y97,IO_L1N_T0_34
+J4,35,IOB_X1Y132,RIOB33_X57Y131,IO_L9P_T1_DQS_AD7P_35
+J5,35,IOB_X1Y135,RIOB33_X57Y135,IO_L7N_T1_AD6N_35
+J6,35,IOB_X1Y136,RIOB33_X57Y135,IO_L7P_T1_AD6P_35
+J8,35,IOB_X1Y149,RIOB33_SING_X57Y149,IO_0_35
+J14,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+J15,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+J16,15,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_AD0N_15
+J18,15,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_AD11P_15
+J19,15,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_AD2P_15
+J20,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD3N_15
+J21,15,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_15
+J23,15,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_15
+J24,15,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_A28_15
+J25,15,IOB_X0Y102,LIOB33_X0Y101,IO_L24P_T3_RS1_15
+J26,15,IOB_X0Y101,LIOB33_X0Y101,IO_L24N_T3_RS0_15
+K1,34,IOB_X1Y86,RIOB33_X57Y85,IO_L7P_T1_34
+K2,34,IOB_X1Y83,RIOB33_X57Y83,IO_L8N_T1_34
+K3,34,IOB_X1Y98,RIOB33_X57Y97,IO_L1P_T0_34
+K5,34,IOB_X1Y91,RIOB33_X57Y91,IO_L4N_T0_34
+K6,35,IOB_X1Y129,RIOB33_X57Y129,IO_L10N_T1_AD15N_35
+K7,35,IOB_X1Y130,RIOB33_X57Y129,IO_L10P_T1_AD15P_35
+K8,35,IOB_X1Y133,RIOB33_X57Y133,IO_L8N_T1_AD14N_35
+K15,15,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_AD0P_15
+K16,15,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_AD1P_15
+K17,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+K18,15,IOB_X0Y149,LIOB33_SING_X0Y149,IO_0_15
+K20,15,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_AD3P_15
+K21,15,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_15
+K22,15,IOB_X0Y114,LIOB33_X0Y113,IO_L18P_T2_A24_15
+K23,15,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_A23_15
+K25,14,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_D09_14
+K26,14,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_D10_14
+L2,34,IOB_X1Y77,RIOB33_X57Y77,IO_L11N_T1_SRCC_34
+L3,34,IOB_X1Y84,RIOB33_X57Y83,IO_L8P_T1_34
+L4,34,IOB_X1Y93,RIOB33_X57Y93,IO_L3N_T0_DQS_34
+L5,34,IOB_X1Y92,RIOB33_X57Y91,IO_L4P_T0_34
+L7,34,IOB_X1Y95,RIOB33_X57Y95,IO_L2N_T0_34
+L8,35,IOB_X1Y134,RIOB33_X57Y133,IO_L8P_T1_AD14P_35
+L14,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_15
+L15,15,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_AD9N_15
+L17,15,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_AD10P_15
+L18,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD10N_15
+L19,15,IOB_X0Y100,LIOB33_SING_X0Y100,IO_25_15
+L20,14,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_D12_14
+L22,14,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_14
+L23,14,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_14
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diff --git a/artix7/xc7a100tfgg676-2/part.json b/artix7/xc7a100tfgg676-2/part.json
new file mode 100644
index 0000000..3a9350c
--- /dev/null
+++ b/artix7/xc7a100tfgg676-2/part.json
@@ -0,0 +1,772 @@
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+ },
+ "25": {
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+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
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+ },
+ "29": {
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+ },
+ "30": {
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+ },
+ "31": {
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+ },
+ "32": {
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+ },
+ "33": {
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+ },
+ "34": {
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+ },
+ "35": {
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+ },
+ "36": {
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+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 28
+ },
+ "39": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "53": {
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+ },
+ "54": {
+ "frame_count": 36
+ },
+ "55": {
+ "frame_count": 36
+ },
+ "56": {
+ "frame_count": 30
+ },
+ "57": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
+ "4": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "11": {
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+ },
+ "12": {
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+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
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+ },
+ "15": {
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+ },
+ "16": {
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+ },
+ "17": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "30": {
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+ },
+ "31": {
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+ },
+ "32": {
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+ },
+ "33": {
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+ },
+ "34": {
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+ },
+ "35": {
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+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 28
+ },
+ "39": {
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+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
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+ },
+ "42": {
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+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 28
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 36
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 28
+ },
+ "49": {
+ "frame_count": 36
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56823955,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182",
+ "34": "X146Y78",
+ "35": "X146Y130"
+ }
+}
diff --git a/artix7/xc7a100tfgg676-2/part.yaml b/artix7/xc7a100tfgg676-2/part.yaml
new file mode 100644
index 0000000..44833bb
--- /dev/null
+++ b/artix7/xc7a100tfgg676-2/part.yaml
@@ -0,0 +1,499 @@
+!<xilinx/xc7series/part>
+idcode: 0x3631093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
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+ 16: !<xilinx/xc7series/configuration_column>
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+ 17: !<xilinx/xc7series/configuration_column>
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+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
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+ 20: !<xilinx/xc7series/configuration_column>
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+ 21: !<xilinx/xc7series/configuration_column>
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+ 22: !<xilinx/xc7series/configuration_column>
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+ frame_count: 36
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+ frame_count: 36
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+ frame_count: 36
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+ frame_count: 36
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+ frame_count: 30
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+ frame_count: 36
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+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
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+ 49: !<xilinx/xc7series/configuration_column>
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+ 50: !<xilinx/xc7series/configuration_column>
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+ 51: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
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+ 2: !<xilinx/xc7series/configuration_column>
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+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a100tfgg676-2L/package_pins.csv b/artix7/xc7a100tfgg676-2L/package_pins.csv
new file mode 100644
index 0000000..ee263e4
--- /dev/null
+++ b/artix7/xc7a100tfgg676-2L/package_pins.csv
@@ -0,0 +1,343 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y109,RIOB33_X57Y109,IO_L20N_T3_35
+A3,35,IOB_X1Y110,RIOB33_X57Y109,IO_L20P_T3_35
+A4,35,IOB_X1Y117,RIOB33_X57Y117,IO_L16N_T2_35
+A5,35,IOB_X1Y119,RIOB33_X57Y119,IO_L15N_T2_DQS_35
+A7,216,OPAD_X0Y8,GTP_CHANNEL_0_X130Y162,MGTPTXN0_216
+A9,216,OPAD_X0Y12,GTP_CHANNEL_2_X130Y191,MGTPTXN2_216
+A11,216,IPAD_X1Y36,GTP_CHANNEL_0_X130Y162,MGTPRXN0_216
+A13,216,IPAD_X1Y54,GTP_CHANNEL_2_X130Y191,MGTPRXN2_216
+A17,16,IOB_X0Y182,LIOB33_X0Y181,IO_L9P_T1_DQS_16
+A18,16,IOB_X0Y181,LIOB33_X0Y181,IO_L9N_T1_DQS_16
+A19,16,IOB_X0Y179,LIOB33_X0Y179,IO_L10N_T1_16
+A20,16,IOB_X0Y169,LIOB33_X0Y169,IO_L15N_T2_DQS_16
+A22,16,IOB_X0Y165,LIOB33_X0Y165,IO_L17N_T2_16
+A23,16,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_16
+A24,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A25,16,IOB_X0Y159,LIOB33_X0Y159,IO_L20N_T3_16
+AA11,213,IPAD_X1Y10,GTP_COMMON_X130Y23,MGTREFCLK1P_213
+AA13,213,IPAD_X1Y8,GTP_COMMON_X130Y23,MGTREFCLK0P_213
+AA22,13,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_13
+AA23,13,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_13
+AA24,13,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_13
+AA25,13,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_13
+AB11,213,IPAD_X1Y11,GTP_COMMON_X130Y23,MGTREFCLK1N_213
+AB13,213,IPAD_X1Y9,GTP_COMMON_X130Y23,MGTREFCLK0N_213
+AB24,13,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_13
+AB25,13,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_13
+AB26,13,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_13
+AC8,213,OPAD_X0Y5,GTP_CHANNEL_2_X130Y35,MGTPTXP2_213
+AC10,213,OPAD_X0Y1,GTP_CHANNEL_0_X130Y6,MGTPTXP0_213
+AC12,213,IPAD_X1Y1,GTP_CHANNEL_0_X130Y6,MGTPRXP0_213
+AC14,213,IPAD_X1Y19,GTP_CHANNEL_2_X130Y35,MGTPRXP2_213
+AC24,13,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_13
+AC26,13,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_13
+AD8,213,OPAD_X0Y4,GTP_CHANNEL_2_X130Y35,MGTPTXN2_213
+AD10,213,OPAD_X0Y0,GTP_CHANNEL_0_X130Y6,MGTPTXN0_213
+AD12,213,IPAD_X1Y0,GTP_CHANNEL_0_X130Y6,MGTPRXN0_213
+AD14,213,IPAD_X1Y18,GTP_CHANNEL_2_X130Y35,MGTPRXN2_213
+AE7,213,OPAD_X0Y7,GTP_CHANNEL_3_X130Y46,MGTPTXP3_213
+AE9,213,OPAD_X0Y3,GTP_CHANNEL_1_X130Y17,MGTPTXP1_213
+AE11,213,IPAD_X1Y25,GTP_CHANNEL_3_X130Y46,MGTPRXP3_213
+AE13,213,IPAD_X1Y7,GTP_CHANNEL_1_X130Y17,MGTPRXP1_213
+AF7,213,OPAD_X0Y6,GTP_CHANNEL_3_X130Y46,MGTPTXN3_213
+AF9,213,OPAD_X0Y2,GTP_CHANNEL_1_X130Y17,MGTPTXN1_213
+AF11,213,IPAD_X1Y24,GTP_CHANNEL_3_X130Y46,MGTPRXN3_213
+AF13,213,IPAD_X1Y6,GTP_CHANNEL_1_X130Y17,MGTPRXN1_213
+B1,35,IOB_X1Y107,RIOB33_X57Y107,IO_L21N_T3_DQS_35
+B2,35,IOB_X1Y111,RIOB33_X57Y111,IO_L19N_T3_VREF_35
+B4,35,IOB_X1Y118,RIOB33_X57Y117,IO_L16P_T2_35
+B5,35,IOB_X1Y120,RIOB33_X57Y119,IO_L15P_T2_DQS_35
+B7,216,OPAD_X0Y9,GTP_CHANNEL_0_X130Y162,MGTPTXP0_216
+B9,216,OPAD_X0Y13,GTP_CHANNEL_2_X130Y191,MGTPTXP2_216
+B11,216,IPAD_X1Y37,GTP_CHANNEL_0_X130Y162,MGTPRXP0_216
+B13,216,IPAD_X1Y55,GTP_CHANNEL_2_X130Y191,MGTPRXP2_216
+B17,16,IOB_X0Y185,LIOB33_X0Y185,IO_L7N_T1_16
+B19,16,IOB_X0Y180,LIOB33_X0Y179,IO_L10P_T1_16
+B20,16,IOB_X0Y170,LIOB33_X0Y169,IO_L15P_T2_DQS_16
+B21,16,IOB_X0Y167,LIOB33_X0Y167,IO_L16N_T2_16
+B22,16,IOB_X0Y166,LIOB33_X0Y165,IO_L17P_T2_16
+B24,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+B25,16,IOB_X0Y160,LIOB33_X0Y159,IO_L20P_T3_16
+B26,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
+C1,35,IOB_X1Y108,RIOB33_X57Y107,IO_L21P_T3_DQS_35
+C2,35,IOB_X1Y112,RIOB33_X57Y111,IO_L19P_T3_35
+C3,35,IOB_X1Y115,RIOB33_X57Y115,IO_L17N_T2_35
+C4,35,IOB_X1Y121,RIOB33_X57Y121,IO_L14N_T2_SRCC_35
+C8,216,OPAD_X0Y10,GTP_CHANNEL_1_X130Y173,MGTPTXN1_216
+C10,216,OPAD_X0Y14,GTP_CHANNEL_3_X130Y202,MGTPTXN3_216
+C12,216,IPAD_X1Y60,GTP_CHANNEL_3_X130Y202,MGTPRXN3_216
+C14,216,IPAD_X1Y42,GTP_CHANNEL_1_X130Y173,MGTPRXN1_216
+C17,16,IOB_X0Y186,LIOB33_X0Y185,IO_L7P_T1_16
+C18,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
+C19,16,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_16
+C21,16,IOB_X0Y168,LIOB33_X0Y167,IO_L16P_T2_16
+C22,16,IOB_X0Y162,LIOB33_X0Y161,IO_L19P_T3_16
+C23,16,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_VREF_16
+C24,16,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_16
+C26,16,IOB_X0Y156,LIOB33_X0Y155,IO_L22P_T3_16
+D1,35,IOB_X1Y103,RIOB33_X57Y103,IO_L23N_T3_35
+D3,35,IOB_X1Y116,RIOB33_X57Y115,IO_L17P_T2_35
+D4,35,IOB_X1Y122,RIOB33_X57Y121,IO_L14P_T2_SRCC_35
+D5,35,IOB_X1Y123,RIOB33_X57Y123,IO_L13N_T2_MRCC_35
+D6,35,IOB_X1Y147,RIOB33_X57Y147,IO_L1N_T0_AD4N_35
+D8,216,OPAD_X0Y11,GTP_CHANNEL_1_X130Y173,MGTPTXP1_216
+D10,216,OPAD_X0Y15,GTP_CHANNEL_3_X130Y202,MGTPTXP3_216
+D12,216,IPAD_X1Y61,GTP_CHANNEL_3_X130Y202,MGTPRXP3_216
+D14,216,IPAD_X1Y43,GTP_CHANNEL_1_X130Y173,MGTPRXP1_216
+D16,16,IOB_X0Y183,LIOB33_X0Y183,IO_L8N_T1_16
+D18,16,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_16
+D19,16,IOB_X0Y174,LIOB33_X0Y173,IO_L13P_T2_MRCC_16
+D20,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16
+D21,16,IOB_X0Y163,LIOB33_X0Y163,IO_L18N_T2_16
+D23,16,IOB_X0Y152,LIOB33_X0Y151,IO_L24P_T3_16
+D24,16,IOB_X0Y151,LIOB33_X0Y151,IO_L24N_T3_16
+D25,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
+D26,15,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_A18_15
+E1,35,IOB_X1Y104,RIOB33_X57Y103,IO_L23P_T3_35
+E2,35,IOB_X1Y105,RIOB33_X57Y105,IO_L22N_T3_35
+E3,35,IOB_X1Y113,RIOB33_X57Y113,IO_L18N_T2_35
+E5,35,IOB_X1Y124,RIOB33_X57Y123,IO_L13P_T2_MRCC_35
+E6,35,IOB_X1Y148,RIOB33_X57Y147,IO_L1P_T0_AD4P_35
+E11,216,IPAD_X1Y45,GTP_COMMON_X130Y179,MGTREFCLK0N_216
+E13,216,IPAD_X1Y47,GTP_COMMON_X130Y179,MGTREFCLK1N_216
+E16,16,IOB_X0Y184,LIOB33_X0Y183,IO_L8P_T1_16
+E17,16,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_16
+E18,16,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_16
+E20,16,IOB_X0Y172,LIOB33_X0Y171,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y164,LIOB33_X0Y163,IO_L18P_T2_16
+E22,16,IOB_X0Y150,LIOB33_SING_X0Y150,IO_25_16
+E23,15,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A25_15
+E25,15,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A20_15
+E26,15,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_15
+F2,35,IOB_X1Y106,RIOB33_X57Y105,IO_L22P_T3_35
+F3,35,IOB_X1Y114,RIOB33_X57Y113,IO_L18P_T2_35
+F4,35,IOB_X1Y127,RIOB33_X57Y127,IO_L11N_T1_SRCC_35
+F5,35,IOB_X1Y125,RIOB33_X57Y125,IO_L12N_T1_MRCC_35
+F7,35,IOB_X1Y141,RIOB33_X57Y141,IO_L4N_T0_35
+F8,35,IOB_X1Y142,RIOB33_X57Y141,IO_L4P_T0_35
+F11,216,IPAD_X1Y44,GTP_COMMON_X130Y179,MGTREFCLK0P_216
+F13,216,IPAD_X1Y46,GTP_COMMON_X130Y179,MGTREFCLK1P_216
+F15,16,IOB_X0Y191,LIOB33_X0Y191,IO_L4N_T0_16
+F17,16,IOB_X0Y195,LIOB33_X0Y195,IO_L2N_T0_16
+F18,16,IOB_X0Y194,LIOB33_X0Y193,IO_L3P_T0_DQS_16
+F19,16,IOB_X0Y193,LIOB33_X0Y193,IO_L3N_T0_DQS_16
+F20,16,IOB_X0Y189,LIOB33_X0Y189,IO_L5N_T0_16
+F22,15,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_ADV_B_15
+F23,15,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A26_15
+F24,15,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_A21_VREF_15
+F25,15,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_FWE_B_15
+G1,35,IOB_X1Y101,RIOB33_X57Y101,IO_L24N_T3_35
+G2,35,IOB_X1Y102,RIOB33_X57Y101,IO_L24P_T3_35
+G4,35,IOB_X1Y128,RIOB33_X57Y127,IO_L11P_T1_SRCC_35
+G5,35,IOB_X1Y126,RIOB33_X57Y125,IO_L12P_T1_MRCC_35
+G6,35,IOB_X1Y139,RIOB33_X57Y139,IO_L5N_T0_AD13N_35
+G7,35,IOB_X1Y143,RIOB33_X57Y143,IO_L3N_T0_DQS_AD5N_35
+G8,35,IOB_X1Y145,RIOB33_X57Y145,IO_L2N_T0_AD12N_35
+G9,35,IOB_X1Y137,RIOB33_X57Y137,IO_L6N_T0_VREF_35
+G15,16,IOB_X0Y192,LIOB33_X0Y191,IO_L4P_T0_16
+G16,16,IOB_X0Y187,LIOB33_X0Y187,IO_L6N_T0_VREF_16
+G17,16,IOB_X0Y196,LIOB33_X0Y195,IO_L2P_T0_16
+G19,16,IOB_X0Y190,LIOB33_X0Y189,IO_L5P_T0_16
+G20,15,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_15
+G21,15,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_15
+G22,15,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_15
+G24,15,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_A22_15
+G25,15,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_FOE_B_15
+G26,15,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A16_15
+H1,34,IOB_X1Y79,RIOB33_X57Y79,IO_L10N_T1_34
+H2,34,IOB_X1Y80,RIOB33_X57Y79,IO_L10P_T1_34
+H3,35,IOB_X1Y100,RIOB33_SING_X57Y100,IO_25_35
+H4,35,IOB_X1Y131,RIOB33_X57Y131,IO_L9N_T1_DQS_AD7N_35
+H6,35,IOB_X1Y140,RIOB33_X57Y139,IO_L5P_T0_AD13P_35
+H7,35,IOB_X1Y144,RIOB33_X57Y143,IO_L3P_T0_DQS_AD5P_35
+H8,35,IOB_X1Y146,RIOB33_X57Y145,IO_L2P_T0_AD12P_35
+H9,35,IOB_X1Y138,RIOB33_X57Y137,IO_L6P_T0_35
+H14,16,IOB_X0Y198,LIOB33_X0Y197,IO_L1P_T0_16
+H15,16,IOB_X0Y197,LIOB33_X0Y197,IO_L1N_T0_16
+H16,16,IOB_X0Y188,LIOB33_X0Y187,IO_L6P_T0_16
+H17,16,IOB_X0Y199,LIOB33_SING_X0Y199,IO_0_16
+H18,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD11N_15
+H19,15,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_AD2N_15
+H21,15,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_15
+H22,15,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_15
+H23,15,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_15
+H24,15,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A27_15
+H26,15,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A17_15
+J1,34,IOB_X1Y85,RIOB33_X57Y85,IO_L7N_T1_34
+J3,34,IOB_X1Y97,RIOB33_X57Y97,IO_L1N_T0_34
+J4,35,IOB_X1Y132,RIOB33_X57Y131,IO_L9P_T1_DQS_AD7P_35
+J5,35,IOB_X1Y135,RIOB33_X57Y135,IO_L7N_T1_AD6N_35
+J6,35,IOB_X1Y136,RIOB33_X57Y135,IO_L7P_T1_AD6P_35
+J8,35,IOB_X1Y149,RIOB33_SING_X57Y149,IO_0_35
+J14,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+J15,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+J16,15,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_AD0N_15
+J18,15,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_AD11P_15
+J19,15,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_AD2P_15
+J20,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD3N_15
+J21,15,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_15
+J23,15,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_15
+J24,15,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_A28_15
+J25,15,IOB_X0Y102,LIOB33_X0Y101,IO_L24P_T3_RS1_15
+J26,15,IOB_X0Y101,LIOB33_X0Y101,IO_L24N_T3_RS0_15
+K1,34,IOB_X1Y86,RIOB33_X57Y85,IO_L7P_T1_34
+K2,34,IOB_X1Y83,RIOB33_X57Y83,IO_L8N_T1_34
+K3,34,IOB_X1Y98,RIOB33_X57Y97,IO_L1P_T0_34
+K5,34,IOB_X1Y91,RIOB33_X57Y91,IO_L4N_T0_34
+K6,35,IOB_X1Y129,RIOB33_X57Y129,IO_L10N_T1_AD15N_35
+K7,35,IOB_X1Y130,RIOB33_X57Y129,IO_L10P_T1_AD15P_35
+K8,35,IOB_X1Y133,RIOB33_X57Y133,IO_L8N_T1_AD14N_35
+K15,15,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_AD0P_15
+K16,15,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_AD1P_15
+K17,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+K18,15,IOB_X0Y149,LIOB33_SING_X0Y149,IO_0_15
+K20,15,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_AD3P_15
+K21,15,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_15
+K22,15,IOB_X0Y114,LIOB33_X0Y113,IO_L18P_T2_A24_15
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diff --git a/artix7/xc7a100tfgg676-2L/part.json b/artix7/xc7a100tfgg676-2L/part.json
new file mode 100644
index 0000000..3a9350c
--- /dev/null
+++ b/artix7/xc7a100tfgg676-2L/part.json
@@ -0,0 +1,772 @@
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+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 30
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 28
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 28
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
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+ },
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+ },
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+ },
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+ },
+ "46": {
+ "frame_count": 36
+ },
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+ },
+ "48": {
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+ },
+ "49": {
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+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 28
+ },
+ "52": {
+ "frame_count": 36
+ },
+ "53": {
+ "frame_count": 36
+ },
+ "54": {
+ "frame_count": 36
+ },
+ "55": {
+ "frame_count": 36
+ },
+ "56": {
+ "frame_count": 30
+ },
+ "57": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
+ "4": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "11": {
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+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
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+ },
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+ },
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+ },
+ "23": {
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+ },
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+ },
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+ },
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+ },
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+ },
+ "28": {
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+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 30
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 28
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 28
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 36
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 28
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 36
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 28
+ },
+ "49": {
+ "frame_count": 36
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56823955,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182",
+ "34": "X146Y78",
+ "35": "X146Y130"
+ }
+}
diff --git a/artix7/xc7a100tfgg676-2L/part.yaml b/artix7/xc7a100tfgg676-2L/part.yaml
new file mode 100644
index 0000000..44833bb
--- /dev/null
+++ b/artix7/xc7a100tfgg676-2L/part.yaml
@@ -0,0 +1,499 @@
+!<xilinx/xc7series/part>
+idcode: 0x3631093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
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+ 15: !<xilinx/xc7series/configuration_column>
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+ 17: !<xilinx/xc7series/configuration_column>
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+ 18: !<xilinx/xc7series/configuration_column>
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+ 19: !<xilinx/xc7series/configuration_column>
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+ 20: !<xilinx/xc7series/configuration_column>
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+ 21: !<xilinx/xc7series/configuration_column>
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+ 22: !<xilinx/xc7series/configuration_column>
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+ 23: !<xilinx/xc7series/configuration_column>
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+ 24: !<xilinx/xc7series/configuration_column>
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+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
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+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
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+ 37: !<xilinx/xc7series/configuration_column>
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+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
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+ 43: !<xilinx/xc7series/configuration_column>
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+ 44: !<xilinx/xc7series/configuration_column>
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+ 45: !<xilinx/xc7series/configuration_column>
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+ 46: !<xilinx/xc7series/configuration_column>
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+ 47: !<xilinx/xc7series/configuration_column>
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+ 48: !<xilinx/xc7series/configuration_column>
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+ 49: !<xilinx/xc7series/configuration_column>
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+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a100tfgg676-3/package_pins.csv b/artix7/xc7a100tfgg676-3/package_pins.csv
new file mode 100644
index 0000000..ee263e4
--- /dev/null
+++ b/artix7/xc7a100tfgg676-3/package_pins.csv
@@ -0,0 +1,343 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y109,RIOB33_X57Y109,IO_L20N_T3_35
+A3,35,IOB_X1Y110,RIOB33_X57Y109,IO_L20P_T3_35
+A4,35,IOB_X1Y117,RIOB33_X57Y117,IO_L16N_T2_35
+A5,35,IOB_X1Y119,RIOB33_X57Y119,IO_L15N_T2_DQS_35
+A7,216,OPAD_X0Y8,GTP_CHANNEL_0_X130Y162,MGTPTXN0_216
+A9,216,OPAD_X0Y12,GTP_CHANNEL_2_X130Y191,MGTPTXN2_216
+A11,216,IPAD_X1Y36,GTP_CHANNEL_0_X130Y162,MGTPRXN0_216
+A13,216,IPAD_X1Y54,GTP_CHANNEL_2_X130Y191,MGTPRXN2_216
+A17,16,IOB_X0Y182,LIOB33_X0Y181,IO_L9P_T1_DQS_16
+A18,16,IOB_X0Y181,LIOB33_X0Y181,IO_L9N_T1_DQS_16
+A19,16,IOB_X0Y179,LIOB33_X0Y179,IO_L10N_T1_16
+A20,16,IOB_X0Y169,LIOB33_X0Y169,IO_L15N_T2_DQS_16
+A22,16,IOB_X0Y165,LIOB33_X0Y165,IO_L17N_T2_16
+A23,16,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_16
+A24,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A25,16,IOB_X0Y159,LIOB33_X0Y159,IO_L20N_T3_16
+AA11,213,IPAD_X1Y10,GTP_COMMON_X130Y23,MGTREFCLK1P_213
+AA13,213,IPAD_X1Y8,GTP_COMMON_X130Y23,MGTREFCLK0P_213
+AA22,13,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_13
+AA23,13,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_13
+AA24,13,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_13
+AA25,13,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_13
+AB11,213,IPAD_X1Y11,GTP_COMMON_X130Y23,MGTREFCLK1N_213
+AB13,213,IPAD_X1Y9,GTP_COMMON_X130Y23,MGTREFCLK0N_213
+AB24,13,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_13
+AB25,13,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_13
+AB26,13,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_13
+AC8,213,OPAD_X0Y5,GTP_CHANNEL_2_X130Y35,MGTPTXP2_213
+AC10,213,OPAD_X0Y1,GTP_CHANNEL_0_X130Y6,MGTPTXP0_213
+AC12,213,IPAD_X1Y1,GTP_CHANNEL_0_X130Y6,MGTPRXP0_213
+AC14,213,IPAD_X1Y19,GTP_CHANNEL_2_X130Y35,MGTPRXP2_213
+AC24,13,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_13
+AC26,13,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_13
+AD8,213,OPAD_X0Y4,GTP_CHANNEL_2_X130Y35,MGTPTXN2_213
+AD10,213,OPAD_X0Y0,GTP_CHANNEL_0_X130Y6,MGTPTXN0_213
+AD12,213,IPAD_X1Y0,GTP_CHANNEL_0_X130Y6,MGTPRXN0_213
+AD14,213,IPAD_X1Y18,GTP_CHANNEL_2_X130Y35,MGTPRXN2_213
+AE7,213,OPAD_X0Y7,GTP_CHANNEL_3_X130Y46,MGTPTXP3_213
+AE9,213,OPAD_X0Y3,GTP_CHANNEL_1_X130Y17,MGTPTXP1_213
+AE11,213,IPAD_X1Y25,GTP_CHANNEL_3_X130Y46,MGTPRXP3_213
+AE13,213,IPAD_X1Y7,GTP_CHANNEL_1_X130Y17,MGTPRXP1_213
+AF7,213,OPAD_X0Y6,GTP_CHANNEL_3_X130Y46,MGTPTXN3_213
+AF9,213,OPAD_X0Y2,GTP_CHANNEL_1_X130Y17,MGTPTXN1_213
+AF11,213,IPAD_X1Y24,GTP_CHANNEL_3_X130Y46,MGTPRXN3_213
+AF13,213,IPAD_X1Y6,GTP_CHANNEL_1_X130Y17,MGTPRXN1_213
+B1,35,IOB_X1Y107,RIOB33_X57Y107,IO_L21N_T3_DQS_35
+B2,35,IOB_X1Y111,RIOB33_X57Y111,IO_L19N_T3_VREF_35
+B4,35,IOB_X1Y118,RIOB33_X57Y117,IO_L16P_T2_35
+B5,35,IOB_X1Y120,RIOB33_X57Y119,IO_L15P_T2_DQS_35
+B7,216,OPAD_X0Y9,GTP_CHANNEL_0_X130Y162,MGTPTXP0_216
+B9,216,OPAD_X0Y13,GTP_CHANNEL_2_X130Y191,MGTPTXP2_216
+B11,216,IPAD_X1Y37,GTP_CHANNEL_0_X130Y162,MGTPRXP0_216
+B13,216,IPAD_X1Y55,GTP_CHANNEL_2_X130Y191,MGTPRXP2_216
+B17,16,IOB_X0Y185,LIOB33_X0Y185,IO_L7N_T1_16
+B19,16,IOB_X0Y180,LIOB33_X0Y179,IO_L10P_T1_16
+B20,16,IOB_X0Y170,LIOB33_X0Y169,IO_L15P_T2_DQS_16
+B21,16,IOB_X0Y167,LIOB33_X0Y167,IO_L16N_T2_16
+B22,16,IOB_X0Y166,LIOB33_X0Y165,IO_L17P_T2_16
+B24,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+B25,16,IOB_X0Y160,LIOB33_X0Y159,IO_L20P_T3_16
+B26,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
+C1,35,IOB_X1Y108,RIOB33_X57Y107,IO_L21P_T3_DQS_35
+C2,35,IOB_X1Y112,RIOB33_X57Y111,IO_L19P_T3_35
+C3,35,IOB_X1Y115,RIOB33_X57Y115,IO_L17N_T2_35
+C4,35,IOB_X1Y121,RIOB33_X57Y121,IO_L14N_T2_SRCC_35
+C8,216,OPAD_X0Y10,GTP_CHANNEL_1_X130Y173,MGTPTXN1_216
+C10,216,OPAD_X0Y14,GTP_CHANNEL_3_X130Y202,MGTPTXN3_216
+C12,216,IPAD_X1Y60,GTP_CHANNEL_3_X130Y202,MGTPRXN3_216
+C14,216,IPAD_X1Y42,GTP_CHANNEL_1_X130Y173,MGTPRXN1_216
+C17,16,IOB_X0Y186,LIOB33_X0Y185,IO_L7P_T1_16
+C18,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
+C19,16,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_16
+C21,16,IOB_X0Y168,LIOB33_X0Y167,IO_L16P_T2_16
+C22,16,IOB_X0Y162,LIOB33_X0Y161,IO_L19P_T3_16
+C23,16,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_VREF_16
+C24,16,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_16
+C26,16,IOB_X0Y156,LIOB33_X0Y155,IO_L22P_T3_16
+D1,35,IOB_X1Y103,RIOB33_X57Y103,IO_L23N_T3_35
+D3,35,IOB_X1Y116,RIOB33_X57Y115,IO_L17P_T2_35
+D4,35,IOB_X1Y122,RIOB33_X57Y121,IO_L14P_T2_SRCC_35
+D5,35,IOB_X1Y123,RIOB33_X57Y123,IO_L13N_T2_MRCC_35
+D6,35,IOB_X1Y147,RIOB33_X57Y147,IO_L1N_T0_AD4N_35
+D8,216,OPAD_X0Y11,GTP_CHANNEL_1_X130Y173,MGTPTXP1_216
+D10,216,OPAD_X0Y15,GTP_CHANNEL_3_X130Y202,MGTPTXP3_216
+D12,216,IPAD_X1Y61,GTP_CHANNEL_3_X130Y202,MGTPRXP3_216
+D14,216,IPAD_X1Y43,GTP_CHANNEL_1_X130Y173,MGTPRXP1_216
+D16,16,IOB_X0Y183,LIOB33_X0Y183,IO_L8N_T1_16
+D18,16,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_16
+D19,16,IOB_X0Y174,LIOB33_X0Y173,IO_L13P_T2_MRCC_16
+D20,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16
+D21,16,IOB_X0Y163,LIOB33_X0Y163,IO_L18N_T2_16
+D23,16,IOB_X0Y152,LIOB33_X0Y151,IO_L24P_T3_16
+D24,16,IOB_X0Y151,LIOB33_X0Y151,IO_L24N_T3_16
+D25,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
+D26,15,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_A18_15
+E1,35,IOB_X1Y104,RIOB33_X57Y103,IO_L23P_T3_35
+E2,35,IOB_X1Y105,RIOB33_X57Y105,IO_L22N_T3_35
+E3,35,IOB_X1Y113,RIOB33_X57Y113,IO_L18N_T2_35
+E5,35,IOB_X1Y124,RIOB33_X57Y123,IO_L13P_T2_MRCC_35
+E6,35,IOB_X1Y148,RIOB33_X57Y147,IO_L1P_T0_AD4P_35
+E11,216,IPAD_X1Y45,GTP_COMMON_X130Y179,MGTREFCLK0N_216
+E13,216,IPAD_X1Y47,GTP_COMMON_X130Y179,MGTREFCLK1N_216
+E16,16,IOB_X0Y184,LIOB33_X0Y183,IO_L8P_T1_16
+E17,16,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_16
+E18,16,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_16
+E20,16,IOB_X0Y172,LIOB33_X0Y171,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y164,LIOB33_X0Y163,IO_L18P_T2_16
+E22,16,IOB_X0Y150,LIOB33_SING_X0Y150,IO_25_16
+E23,15,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A25_15
+E25,15,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A20_15
+E26,15,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_15
+F2,35,IOB_X1Y106,RIOB33_X57Y105,IO_L22P_T3_35
+F3,35,IOB_X1Y114,RIOB33_X57Y113,IO_L18P_T2_35
+F4,35,IOB_X1Y127,RIOB33_X57Y127,IO_L11N_T1_SRCC_35
+F5,35,IOB_X1Y125,RIOB33_X57Y125,IO_L12N_T1_MRCC_35
+F7,35,IOB_X1Y141,RIOB33_X57Y141,IO_L4N_T0_35
+F8,35,IOB_X1Y142,RIOB33_X57Y141,IO_L4P_T0_35
+F11,216,IPAD_X1Y44,GTP_COMMON_X130Y179,MGTREFCLK0P_216
+F13,216,IPAD_X1Y46,GTP_COMMON_X130Y179,MGTREFCLK1P_216
+F15,16,IOB_X0Y191,LIOB33_X0Y191,IO_L4N_T0_16
+F17,16,IOB_X0Y195,LIOB33_X0Y195,IO_L2N_T0_16
+F18,16,IOB_X0Y194,LIOB33_X0Y193,IO_L3P_T0_DQS_16
+F19,16,IOB_X0Y193,LIOB33_X0Y193,IO_L3N_T0_DQS_16
+F20,16,IOB_X0Y189,LIOB33_X0Y189,IO_L5N_T0_16
+F22,15,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_ADV_B_15
+F23,15,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A26_15
+F24,15,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_A21_VREF_15
+F25,15,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_FWE_B_15
+G1,35,IOB_X1Y101,RIOB33_X57Y101,IO_L24N_T3_35
+G2,35,IOB_X1Y102,RIOB33_X57Y101,IO_L24P_T3_35
+G4,35,IOB_X1Y128,RIOB33_X57Y127,IO_L11P_T1_SRCC_35
+G5,35,IOB_X1Y126,RIOB33_X57Y125,IO_L12P_T1_MRCC_35
+G6,35,IOB_X1Y139,RIOB33_X57Y139,IO_L5N_T0_AD13N_35
+G7,35,IOB_X1Y143,RIOB33_X57Y143,IO_L3N_T0_DQS_AD5N_35
+G8,35,IOB_X1Y145,RIOB33_X57Y145,IO_L2N_T0_AD12N_35
+G9,35,IOB_X1Y137,RIOB33_X57Y137,IO_L6N_T0_VREF_35
+G15,16,IOB_X0Y192,LIOB33_X0Y191,IO_L4P_T0_16
+G16,16,IOB_X0Y187,LIOB33_X0Y187,IO_L6N_T0_VREF_16
+G17,16,IOB_X0Y196,LIOB33_X0Y195,IO_L2P_T0_16
+G19,16,IOB_X0Y190,LIOB33_X0Y189,IO_L5P_T0_16
+G20,15,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_15
+G21,15,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_15
+G22,15,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_15
+G24,15,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_A22_15
+G25,15,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_FOE_B_15
+G26,15,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A16_15
+H1,34,IOB_X1Y79,RIOB33_X57Y79,IO_L10N_T1_34
+H2,34,IOB_X1Y80,RIOB33_X57Y79,IO_L10P_T1_34
+H3,35,IOB_X1Y100,RIOB33_SING_X57Y100,IO_25_35
+H4,35,IOB_X1Y131,RIOB33_X57Y131,IO_L9N_T1_DQS_AD7N_35
+H6,35,IOB_X1Y140,RIOB33_X57Y139,IO_L5P_T0_AD13P_35
+H7,35,IOB_X1Y144,RIOB33_X57Y143,IO_L3P_T0_DQS_AD5P_35
+H8,35,IOB_X1Y146,RIOB33_X57Y145,IO_L2P_T0_AD12P_35
+H9,35,IOB_X1Y138,RIOB33_X57Y137,IO_L6P_T0_35
+H14,16,IOB_X0Y198,LIOB33_X0Y197,IO_L1P_T0_16
+H15,16,IOB_X0Y197,LIOB33_X0Y197,IO_L1N_T0_16
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+H17,16,IOB_X0Y199,LIOB33_SING_X0Y199,IO_0_16
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+H19,15,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_AD2N_15
+H21,15,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_15
+H22,15,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_15
+H23,15,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_15
+H24,15,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A27_15
+H26,15,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A17_15
+J1,34,IOB_X1Y85,RIOB33_X57Y85,IO_L7N_T1_34
+J3,34,IOB_X1Y97,RIOB33_X57Y97,IO_L1N_T0_34
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+J5,35,IOB_X1Y135,RIOB33_X57Y135,IO_L7N_T1_AD6N_35
+J6,35,IOB_X1Y136,RIOB33_X57Y135,IO_L7P_T1_AD6P_35
+J8,35,IOB_X1Y149,RIOB33_SING_X57Y149,IO_0_35
+J14,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+J15,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+J16,15,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_AD0N_15
+J18,15,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_AD11P_15
+J19,15,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_AD2P_15
+J20,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD3N_15
+J21,15,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_15
+J23,15,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_15
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diff --git a/artix7/xc7a100tfgg676-3/part.json b/artix7/xc7a100tfgg676-3/part.json
new file mode 100644
index 0000000..3a9350c
--- /dev/null
+++ b/artix7/xc7a100tfgg676-3/part.json
@@ -0,0 +1,772 @@
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+ },
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+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "56": {
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+ },
+ "57": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "12": {
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+ },
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+ },
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+ },
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+ },
+ "16": {
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+ },
+ "17": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "32": {
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+ },
+ "33": {
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+ },
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+ },
+ "35": {
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+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
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+ },
+ "39": {
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+ },
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+ },
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+ },
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+ },
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+ },
+ "44": {
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+ },
+ "45": {
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+ },
+ "46": {
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+ },
+ "47": {
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+ },
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+ },
+ "49": {
+ "frame_count": 36
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56823955,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182",
+ "34": "X146Y78",
+ "35": "X146Y130"
+ }
+}
diff --git a/artix7/xc7a100tfgg676-3/part.yaml b/artix7/xc7a100tfgg676-3/part.yaml
new file mode 100644
index 0000000..44833bb
--- /dev/null
+++ b/artix7/xc7a100tfgg676-3/part.yaml
@@ -0,0 +1,499 @@
+!<xilinx/xc7series/part>
+idcode: 0x3631093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a100tftg256-1/package_pins.csv b/artix7/xc7a100tftg256-1/package_pins.csv
new file mode 100644
index 0000000..99daf1b
--- /dev/null
+++ b/artix7/xc7a100tftg256-1/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y133,RIOB33_X57Y133,IO_L8N_T1_AD14N_35
+A3,35,IOB_X1Y141,RIOB33_X57Y141,IO_L4N_T0_35
+A4,35,IOB_X1Y143,RIOB33_X57Y143,IO_L3N_T0_DQS_AD5N_35
+A5,35,IOB_X1Y144,RIOB33_X57Y143,IO_L3P_T0_DQS_AD5P_35
+A7,35,IOB_X1Y147,RIOB33_X57Y147,IO_L1N_T0_AD4N_35
+A8,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+A9,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+A10,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+A12,15,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_AD9N_15
+A13,15,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_AD2P_15
+A14,15,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_AD2N_15
+A15,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD3N_15
+B1,35,IOB_X1Y131,RIOB33_X57Y131,IO_L9N_T1_DQS_AD7N_35
+B2,35,IOB_X1Y134,RIOB33_X57Y133,IO_L8P_T1_AD14P_35
+B4,35,IOB_X1Y142,RIOB33_X57Y141,IO_L4P_T0_35
+B5,35,IOB_X1Y145,RIOB33_X57Y145,IO_L2N_T0_AD12N_35
+B6,35,IOB_X1Y146,RIOB33_X57Y145,IO_L2P_T0_AD12P_35
+B7,35,IOB_X1Y148,RIOB33_X57Y147,IO_L1P_T0_AD4P_35
+B9,15,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_AD1P_15
+B10,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_15
+B11,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_15
+B12,15,IOB_X0Y140,LIOB33_X0Y139,IO_L5P_T0_AD9P_15
+B14,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD10N_15
+B15,15,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_AD3P_15
+B16,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD11N_15
+C1,35,IOB_X1Y132,RIOB33_X57Y131,IO_L9P_T1_DQS_AD7P_35
+C2,35,IOB_X1Y135,RIOB33_X57Y135,IO_L7N_T1_AD6N_35
+C3,35,IOB_X1Y136,RIOB33_X57Y135,IO_L7P_T1_AD6P_35
+C4,35,IOB_X1Y125,RIOB33_X57Y125,IO_L12N_T1_MRCC_35
+C6,35,IOB_X1Y139,RIOB33_X57Y139,IO_L5N_T0_AD13N_35
+C7,35,IOB_X1Y140,RIOB33_X57Y139,IO_L5P_T0_AD13P_35
+C8,15,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_AD0P_15
+C9,15,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_AD0N_15
+C11,15,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_15
+C12,15,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_15
+C13,15,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_15
+C14,15,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_AD10P_15
+C16,15,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_AD11P_15
+D1,35,IOB_X1Y129,RIOB33_X57Y129,IO_L10N_T1_AD15N_35
+D3,35,IOB_X1Y127,RIOB33_X57Y127,IO_L11N_T1_SRCC_35
+D4,35,IOB_X1Y126,RIOB33_X57Y125,IO_L12P_T1_MRCC_35
+D5,35,IOB_X1Y137,RIOB33_X57Y137,IO_L6N_T0_VREF_35
+D6,35,IOB_X1Y138,RIOB33_X57Y137,IO_L6P_T0_35
+D8,15,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_15
+D9,15,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_15
+D10,15,IOB_X0Y149,LIOB33_SING_X0Y149,IO_0_15
+D11,15,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_15
+D13,15,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_15
+D14,15,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_15
+D15,15,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_ADV_B_15
+D16,15,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A25_15
+E1,35,IOB_X1Y119,RIOB33_X57Y119,IO_L15N_T2_DQS_35
+E2,35,IOB_X1Y130,RIOB33_X57Y129,IO_L10P_T1_AD15P_35
+E3,35,IOB_X1Y128,RIOB33_X57Y127,IO_L11P_T1_SRCC_35
+E5,35,IOB_X1Y123,RIOB33_X57Y123,IO_L13N_T2_MRCC_35
+E6,35,IOB_X1Y149,RIOB33_SING_X57Y149,IO_0_35
+E11,15,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_15
+E12,15,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_15
+E13,15,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_15
+E15,15,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_A23_15
+E16,15,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A26_15
+F2,35,IOB_X1Y120,RIOB33_X57Y119,IO_L15P_T2_DQS_35
+F3,35,IOB_X1Y121,RIOB33_X57Y121,IO_L14N_T2_SRCC_35
+F4,35,IOB_X1Y122,RIOB33_X57Y121,IO_L14P_T2_SRCC_35
+F5,35,IOB_X1Y124,RIOB33_X57Y123,IO_L13P_T2_MRCC_35
+F12,15,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_A28_15
+F13,15,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A27_15
+F14,15,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_A18_15
+F15,15,IOB_X0Y114,LIOB33_X0Y113,IO_L18P_T2_A24_15
+G1,35,IOB_X1Y115,RIOB33_X57Y115,IO_L17N_T2_35
+G2,35,IOB_X1Y116,RIOB33_X57Y115,IO_L17P_T2_35
+G4,35,IOB_X1Y117,RIOB33_X57Y117,IO_L16N_T2_35
+G5,35,IOB_X1Y118,RIOB33_X57Y117,IO_L16P_T2_35
+G11,15,IOB_X0Y100,LIOB33_SING_X0Y100,IO_25_15
+G12,15,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_A21_VREF_15
+G14,15,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_15
+G15,15,IOB_X0Y101,LIOB33_X0Y101,IO_L24N_T3_RS0_15
+G16,15,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A16_15
+H1,35,IOB_X1Y109,RIOB33_X57Y109,IO_L20N_T3_35
+H2,35,IOB_X1Y110,RIOB33_X57Y109,IO_L20P_T3_35
+H3,35,IOB_X1Y107,RIOB33_X57Y107,IO_L21N_T3_DQS_35
+H4,35,IOB_X1Y113,RIOB33_X57Y113,IO_L18N_T2_35
+H5,35,IOB_X1Y114,RIOB33_X57Y113,IO_L18P_T2_35
+H8,0,IPAD_X0Y30,MONITOR_BOT_X46Y131,VP_0
+H11,15,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_A22_15
+H12,15,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A20_15
+H13,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
+H14,15,IOB_X0Y102,LIOB33_X0Y101,IO_L24P_T3_RS1_15
+H16,15,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A17_15
+J1,35,IOB_X1Y105,RIOB33_X57Y105,IO_L22N_T3_35
+J3,35,IOB_X1Y108,RIOB33_X57Y107,IO_L21P_T3_DQS_35
+J4,35,IOB_X1Y111,RIOB33_X57Y111,IO_L19N_T3_VREF_35
+J5,35,IOB_X1Y112,RIOB33_X57Y111,IO_L19P_T3_35
+J7,0,IPAD_X0Y31,MONITOR_BOT_X46Y131,VN_0
+J13,14,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_D00_MOSI_14
+J14,14,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_D01_DIN_14
+J15,15,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_FOE_B_15
+J16,15,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_FWE_B_15
+K1,35,IOB_X1Y106,RIOB33_X57Y105,IO_L22P_T3_35
+K2,35,IOB_X1Y101,RIOB33_X57Y101,IO_L24N_T3_35
+K3,35,IOB_X1Y102,RIOB33_X57Y101,IO_L24P_T3_35
+K5,35,IOB_X1Y100,RIOB33_SING_X57Y100,IO_25_35
+K12,14,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_14
+K13,14,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_D06_14
+K15,14,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_D02_14
+K16,14,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_D03_14
+L2,35,IOB_X1Y103,RIOB33_X57Y103,IO_L23N_T3_35
+L3,35,IOB_X1Y104,RIOB33_X57Y103,IO_L23P_T3_35
+L4,34,IOB_X1Y98,RIOB33_X57Y97,IO_L1P_T0_34
+L5,34,IOB_X1Y99,RIOB33_SING_X57Y99,IO_0_34
+L12,14,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_FCS_B_14
+L13,14,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_D07_14
+L14,14,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_D04_14
+L15,14,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_PUDC_B_14
+M1,34,IOB_X1Y95,RIOB33_X57Y95,IO_L2N_T0_34
+M2,34,IOB_X1Y96,RIOB33_X57Y95,IO_L2P_T0_34
+M4,34,IOB_X1Y97,RIOB33_X57Y97,IO_L1N_T0_34
+M5,34,IOB_X1Y88,RIOB33_X57Y87,IO_L6P_T0_34
+M6,14,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_A10_D26_14
+M12,14,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_D08_VREF_14
+M14,14,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_D05_14
+M15,14,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_EMCCLK_14
+M16,14,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_D09_14
+N1,34,IOB_X1Y92,RIOB33_X57Y91,IO_L4P_T0_34
+N2,34,IOB_X1Y93,RIOB33_X57Y93,IO_L3N_T0_DQS_34
+N3,34,IOB_X1Y94,RIOB33_X57Y93,IO_L3P_T0_DQS_34
+N4,34,IOB_X1Y87,RIOB33_X57Y87,IO_L6N_T0_VREF_34
+N6,14,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_A09_D25_VREF_14
+N9,14,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_A12_D28_14
+N11,14,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_14
+N12,14,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_14
+N13,14,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_14
+N14,14,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_14
+N16,14,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_D10_14
+P1,34,IOB_X1Y91,RIOB33_X57Y91,IO_L4N_T0_34
+P3,34,IOB_X1Y89,RIOB33_X57Y89,IO_L5N_T0_34
+P4,34,IOB_X1Y90,RIOB33_X57Y89,IO_L5P_T0_34
+P5,34,IOB_X1Y80,RIOB33_X57Y79,IO_L10P_T1_34
+P6,14,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_14
+P8,14,IOB_X0Y60,LIOB33_X0Y59,IO_L20P_T3_A08_D24_14
+P9,14,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_A11_D27_14
+P10,14,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_14
+P11,14,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_14
+P13,14,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_14
+P14,14,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_14
+P15,14,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_D11_14
+P16,14,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_D12_14
+R1,34,IOB_X1Y85,RIOB33_X57Y85,IO_L7N_T1_34
+R2,34,IOB_X1Y86,RIOB33_X57Y85,IO_L7P_T1_34
+R3,34,IOB_X1Y84,RIOB33_X57Y83,IO_L8P_T1_34
+R5,14,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_A03_D19_14
+R6,14,IOB_X0Y52,LIOB33_X0Y51,IO_L24P_T3_A01_D17_14
+R7,14,IOB_X0Y51,LIOB33_X0Y51,IO_L24N_T3_A00_D16_14
+R8,14,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_A07_D23_14
+R10,14,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A14_D30_14
+R11,14,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A13_D29_14
+R12,14,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_RDWR_B_14
+R13,14,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_CSI_B_14
+R15,14,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_14
+R16,14,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_D13_14
+T2,34,IOB_X1Y83,RIOB33_X57Y83,IO_L8N_T1_34
+T3,34,IOB_X1Y81,RIOB33_X57Y81,IO_L9N_T1_DQS_34
+T4,34,IOB_X1Y82,RIOB33_X57Y81,IO_L9P_T1_DQS_34
+T5,14,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_A02_D18_14
+T7,14,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_14
+T8,14,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_A06_D22_14
+T9,14,IOB_X0Y56,LIOB33_X0Y55,IO_L22P_T3_A05_D21_14
+T10,14,IOB_X0Y55,LIOB33_X0Y55,IO_L22N_T3_A04_D20_14
+T12,14,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_DOUT_CSO_B_14
+T13,14,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A15_D31_14
+T14,14,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_D14_14
+T15,14,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_D15_14
diff --git a/artix7/xc7a100tftg256-1/part.json b/artix7/xc7a100tftg256-1/part.json
new file mode 100644
index 0000000..1cefd49
--- /dev/null
+++ b/artix7/xc7a100tftg256-1/part.json
@@ -0,0 +1,770 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
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+ },
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+ },
+ "20": {
+ "frame_count": 36
+ },
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+ },
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+ },
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+ },
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+ },
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+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
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+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
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+ },
+ "31": {
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+ },
+ "32": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ "frame_count": 30
+ },
+ "57": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
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+ },
+ "13": {
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+ },
+ "14": {
+ "frame_count": 36
+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "20": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ "frame_count": 28
+ },
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+ },
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+ },
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+ },
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+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
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+ "frame_count": 28
+ },
+ "45": {
+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 28
+ },
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+ "frame_count": 36
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
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+ "frame_count": 28
+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "56": {
+ "frame_count": 30
+ },
+ "57": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
+ "4": {
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+ },
+ "5": {
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+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
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+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 30
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 28
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 28
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 36
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 28
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 36
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 28
+ },
+ "49": {
+ "frame_count": 36
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56823955,
+ "iobanks": {
+ "0": "X1Y130",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "34": "X146Y78",
+ "35": "X146Y130"
+ }
+}
diff --git a/artix7/xc7a100tftg256-1/part.yaml b/artix7/xc7a100tftg256-1/part.yaml
new file mode 100644
index 0000000..44833bb
--- /dev/null
+++ b/artix7/xc7a100tftg256-1/part.yaml
@@ -0,0 +1,499 @@
+!<xilinx/xc7series/part>
+idcode: 0x3631093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ rows:
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
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+ configuration_buses:
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
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diff --git a/artix7/xc7a100tftg256-2/package_pins.csv b/artix7/xc7a100tftg256-2/package_pins.csv
new file mode 100644
index 0000000..99daf1b
--- /dev/null
+++ b/artix7/xc7a100tftg256-2/package_pins.csv
@@ -0,0 +1,173 @@
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diff --git a/artix7/xc7a100tftg256-2/part.json b/artix7/xc7a100tftg256-2/part.json
new file mode 100644
index 0000000..1cefd49
--- /dev/null
+++ b/artix7/xc7a100tftg256-2/part.json
@@ -0,0 +1,770 @@
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+ "42": {
+ "frame_count": 36
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 28
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 36
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 28
+ },
+ "49": {
+ "frame_count": 36
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56823955,
+ "iobanks": {
+ "0": "X1Y130",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "34": "X146Y78",
+ "35": "X146Y130"
+ }
+}
diff --git a/artix7/xc7a100tftg256-2/part.yaml b/artix7/xc7a100tftg256-2/part.yaml
new file mode 100644
index 0000000..44833bb
--- /dev/null
+++ b/artix7/xc7a100tftg256-2/part.yaml
@@ -0,0 +1,499 @@
+!<xilinx/xc7series/part>
+idcode: 0x3631093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
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+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
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+ 12: !<xilinx/xc7series/configuration_column>
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+ 13: !<xilinx/xc7series/configuration_column>
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+ 14: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 44: !<xilinx/xc7series/configuration_column>
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+ 46: !<xilinx/xc7series/configuration_column>
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+ 47: !<xilinx/xc7series/configuration_column>
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+ 48: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
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+ 2: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
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+ 25: !<xilinx/xc7series/configuration_column>
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+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a100tftg256-2L/package_pins.csv b/artix7/xc7a100tftg256-2L/package_pins.csv
new file mode 100644
index 0000000..99daf1b
--- /dev/null
+++ b/artix7/xc7a100tftg256-2L/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y133,RIOB33_X57Y133,IO_L8N_T1_AD14N_35
+A3,35,IOB_X1Y141,RIOB33_X57Y141,IO_L4N_T0_35
+A4,35,IOB_X1Y143,RIOB33_X57Y143,IO_L3N_T0_DQS_AD5N_35
+A5,35,IOB_X1Y144,RIOB33_X57Y143,IO_L3P_T0_DQS_AD5P_35
+A7,35,IOB_X1Y147,RIOB33_X57Y147,IO_L1N_T0_AD4N_35
+A8,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+A9,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+A10,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+A12,15,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_AD9N_15
+A13,15,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_AD2P_15
+A14,15,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_AD2N_15
+A15,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD3N_15
+B1,35,IOB_X1Y131,RIOB33_X57Y131,IO_L9N_T1_DQS_AD7N_35
+B2,35,IOB_X1Y134,RIOB33_X57Y133,IO_L8P_T1_AD14P_35
+B4,35,IOB_X1Y142,RIOB33_X57Y141,IO_L4P_T0_35
+B5,35,IOB_X1Y145,RIOB33_X57Y145,IO_L2N_T0_AD12N_35
+B6,35,IOB_X1Y146,RIOB33_X57Y145,IO_L2P_T0_AD12P_35
+B7,35,IOB_X1Y148,RIOB33_X57Y147,IO_L1P_T0_AD4P_35
+B9,15,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_AD1P_15
+B10,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_15
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diff --git a/artix7/xc7a100tftg256-2L/part.json b/artix7/xc7a100tftg256-2L/part.json
new file mode 100644
index 0000000..1cefd49
--- /dev/null
+++ b/artix7/xc7a100tftg256-2L/part.json
@@ -0,0 +1,770 @@
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+ "50": {
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+ },
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+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "56": {
+ "frame_count": 30
+ },
+ "57": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "15": {
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+ },
+ "16": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "30": {
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+ },
+ "31": {
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+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 28
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
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+ },
+ "39": {
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+ },
+ "40": {
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+ },
+ "41": {
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+ },
+ "42": {
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+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
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+ },
+ "45": {
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+ },
+ "46": {
+ "frame_count": 36
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 28
+ },
+ "49": {
+ "frame_count": 36
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56823955,
+ "iobanks": {
+ "0": "X1Y130",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "34": "X146Y78",
+ "35": "X146Y130"
+ }
+}
diff --git a/artix7/xc7a100tftg256-2L/part.yaml b/artix7/xc7a100tftg256-2L/part.yaml
new file mode 100644
index 0000000..44833bb
--- /dev/null
+++ b/artix7/xc7a100tftg256-2L/part.yaml
@@ -0,0 +1,499 @@
+!<xilinx/xc7series/part>
+idcode: 0x3631093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
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+ 16: !<xilinx/xc7series/configuration_column>
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+ 17: !<xilinx/xc7series/configuration_column>
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+ 18: !<xilinx/xc7series/configuration_column>
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+ 19: !<xilinx/xc7series/configuration_column>
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+ 20: !<xilinx/xc7series/configuration_column>
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+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
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+ 23: !<xilinx/xc7series/configuration_column>
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+ 24: !<xilinx/xc7series/configuration_column>
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+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
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+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
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+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
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+ 39: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
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+ 49: !<xilinx/xc7series/configuration_column>
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+ 50: !<xilinx/xc7series/configuration_column>
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+ 51: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a100tftg256-3/package_pins.csv b/artix7/xc7a100tftg256-3/package_pins.csv
new file mode 100644
index 0000000..99daf1b
--- /dev/null
+++ b/artix7/xc7a100tftg256-3/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y133,RIOB33_X57Y133,IO_L8N_T1_AD14N_35
+A3,35,IOB_X1Y141,RIOB33_X57Y141,IO_L4N_T0_35
+A4,35,IOB_X1Y143,RIOB33_X57Y143,IO_L3N_T0_DQS_AD5N_35
+A5,35,IOB_X1Y144,RIOB33_X57Y143,IO_L3P_T0_DQS_AD5P_35
+A7,35,IOB_X1Y147,RIOB33_X57Y147,IO_L1N_T0_AD4N_35
+A8,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+A9,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+A10,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+A12,15,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_AD9N_15
+A13,15,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_AD2P_15
+A14,15,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_AD2N_15
+A15,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD3N_15
+B1,35,IOB_X1Y131,RIOB33_X57Y131,IO_L9N_T1_DQS_AD7N_35
+B2,35,IOB_X1Y134,RIOB33_X57Y133,IO_L8P_T1_AD14P_35
+B4,35,IOB_X1Y142,RIOB33_X57Y141,IO_L4P_T0_35
+B5,35,IOB_X1Y145,RIOB33_X57Y145,IO_L2N_T0_AD12N_35
+B6,35,IOB_X1Y146,RIOB33_X57Y145,IO_L2P_T0_AD12P_35
+B7,35,IOB_X1Y148,RIOB33_X57Y147,IO_L1P_T0_AD4P_35
+B9,15,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_AD1P_15
+B10,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_15
+B11,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_15
+B12,15,IOB_X0Y140,LIOB33_X0Y139,IO_L5P_T0_AD9P_15
+B14,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD10N_15
+B15,15,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_AD3P_15
+B16,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD11N_15
+C1,35,IOB_X1Y132,RIOB33_X57Y131,IO_L9P_T1_DQS_AD7P_35
+C2,35,IOB_X1Y135,RIOB33_X57Y135,IO_L7N_T1_AD6N_35
+C3,35,IOB_X1Y136,RIOB33_X57Y135,IO_L7P_T1_AD6P_35
+C4,35,IOB_X1Y125,RIOB33_X57Y125,IO_L12N_T1_MRCC_35
+C6,35,IOB_X1Y139,RIOB33_X57Y139,IO_L5N_T0_AD13N_35
+C7,35,IOB_X1Y140,RIOB33_X57Y139,IO_L5P_T0_AD13P_35
+C8,15,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_AD0P_15
+C9,15,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_AD0N_15
+C11,15,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_15
+C12,15,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_15
+C13,15,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_15
+C14,15,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_AD10P_15
+C16,15,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_AD11P_15
+D1,35,IOB_X1Y129,RIOB33_X57Y129,IO_L10N_T1_AD15N_35
+D3,35,IOB_X1Y127,RIOB33_X57Y127,IO_L11N_T1_SRCC_35
+D4,35,IOB_X1Y126,RIOB33_X57Y125,IO_L12P_T1_MRCC_35
+D5,35,IOB_X1Y137,RIOB33_X57Y137,IO_L6N_T0_VREF_35
+D6,35,IOB_X1Y138,RIOB33_X57Y137,IO_L6P_T0_35
+D8,15,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_15
+D9,15,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_15
+D10,15,IOB_X0Y149,LIOB33_SING_X0Y149,IO_0_15
+D11,15,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_15
+D13,15,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_15
+D14,15,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_15
+D15,15,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_ADV_B_15
+D16,15,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A25_15
+E1,35,IOB_X1Y119,RIOB33_X57Y119,IO_L15N_T2_DQS_35
+E2,35,IOB_X1Y130,RIOB33_X57Y129,IO_L10P_T1_AD15P_35
+E3,35,IOB_X1Y128,RIOB33_X57Y127,IO_L11P_T1_SRCC_35
+E5,35,IOB_X1Y123,RIOB33_X57Y123,IO_L13N_T2_MRCC_35
+E6,35,IOB_X1Y149,RIOB33_SING_X57Y149,IO_0_35
+E11,15,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_15
+E12,15,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_15
+E13,15,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_15
+E15,15,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_A23_15
+E16,15,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A26_15
+F2,35,IOB_X1Y120,RIOB33_X57Y119,IO_L15P_T2_DQS_35
+F3,35,IOB_X1Y121,RIOB33_X57Y121,IO_L14N_T2_SRCC_35
+F4,35,IOB_X1Y122,RIOB33_X57Y121,IO_L14P_T2_SRCC_35
+F5,35,IOB_X1Y124,RIOB33_X57Y123,IO_L13P_T2_MRCC_35
+F12,15,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_A28_15
+F13,15,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A27_15
+F14,15,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_A18_15
+F15,15,IOB_X0Y114,LIOB33_X0Y113,IO_L18P_T2_A24_15
+G1,35,IOB_X1Y115,RIOB33_X57Y115,IO_L17N_T2_35
+G2,35,IOB_X1Y116,RIOB33_X57Y115,IO_L17P_T2_35
+G4,35,IOB_X1Y117,RIOB33_X57Y117,IO_L16N_T2_35
+G5,35,IOB_X1Y118,RIOB33_X57Y117,IO_L16P_T2_35
+G11,15,IOB_X0Y100,LIOB33_SING_X0Y100,IO_25_15
+G12,15,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_A21_VREF_15
+G14,15,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_15
+G15,15,IOB_X0Y101,LIOB33_X0Y101,IO_L24N_T3_RS0_15
+G16,15,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A16_15
+H1,35,IOB_X1Y109,RIOB33_X57Y109,IO_L20N_T3_35
+H2,35,IOB_X1Y110,RIOB33_X57Y109,IO_L20P_T3_35
+H3,35,IOB_X1Y107,RIOB33_X57Y107,IO_L21N_T3_DQS_35
+H4,35,IOB_X1Y113,RIOB33_X57Y113,IO_L18N_T2_35
+H5,35,IOB_X1Y114,RIOB33_X57Y113,IO_L18P_T2_35
+H8,0,IPAD_X0Y30,MONITOR_BOT_X46Y131,VP_0
+H11,15,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_A22_15
+H12,15,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A20_15
+H13,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
+H14,15,IOB_X0Y102,LIOB33_X0Y101,IO_L24P_T3_RS1_15
+H16,15,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A17_15
+J1,35,IOB_X1Y105,RIOB33_X57Y105,IO_L22N_T3_35
+J3,35,IOB_X1Y108,RIOB33_X57Y107,IO_L21P_T3_DQS_35
+J4,35,IOB_X1Y111,RIOB33_X57Y111,IO_L19N_T3_VREF_35
+J5,35,IOB_X1Y112,RIOB33_X57Y111,IO_L19P_T3_35
+J7,0,IPAD_X0Y31,MONITOR_BOT_X46Y131,VN_0
+J13,14,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_D00_MOSI_14
+J14,14,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_D01_DIN_14
+J15,15,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_FOE_B_15
+J16,15,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_FWE_B_15
+K1,35,IOB_X1Y106,RIOB33_X57Y105,IO_L22P_T3_35
+K2,35,IOB_X1Y101,RIOB33_X57Y101,IO_L24N_T3_35
+K3,35,IOB_X1Y102,RIOB33_X57Y101,IO_L24P_T3_35
+K5,35,IOB_X1Y100,RIOB33_SING_X57Y100,IO_25_35
+K12,14,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_14
+K13,14,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_D06_14
+K15,14,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_D02_14
+K16,14,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_D03_14
+L2,35,IOB_X1Y103,RIOB33_X57Y103,IO_L23N_T3_35
+L3,35,IOB_X1Y104,RIOB33_X57Y103,IO_L23P_T3_35
+L4,34,IOB_X1Y98,RIOB33_X57Y97,IO_L1P_T0_34
+L5,34,IOB_X1Y99,RIOB33_SING_X57Y99,IO_0_34
+L12,14,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_FCS_B_14
+L13,14,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_D07_14
+L14,14,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_D04_14
+L15,14,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_PUDC_B_14
+M1,34,IOB_X1Y95,RIOB33_X57Y95,IO_L2N_T0_34
+M2,34,IOB_X1Y96,RIOB33_X57Y95,IO_L2P_T0_34
+M4,34,IOB_X1Y97,RIOB33_X57Y97,IO_L1N_T0_34
+M5,34,IOB_X1Y88,RIOB33_X57Y87,IO_L6P_T0_34
+M6,14,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_A10_D26_14
+M12,14,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_D08_VREF_14
+M14,14,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_D05_14
+M15,14,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_EMCCLK_14
+M16,14,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_D09_14
+N1,34,IOB_X1Y92,RIOB33_X57Y91,IO_L4P_T0_34
+N2,34,IOB_X1Y93,RIOB33_X57Y93,IO_L3N_T0_DQS_34
+N3,34,IOB_X1Y94,RIOB33_X57Y93,IO_L3P_T0_DQS_34
+N4,34,IOB_X1Y87,RIOB33_X57Y87,IO_L6N_T0_VREF_34
+N6,14,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_A09_D25_VREF_14
+N9,14,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_A12_D28_14
+N11,14,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_14
+N12,14,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_14
+N13,14,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_14
+N14,14,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_14
+N16,14,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_D10_14
+P1,34,IOB_X1Y91,RIOB33_X57Y91,IO_L4N_T0_34
+P3,34,IOB_X1Y89,RIOB33_X57Y89,IO_L5N_T0_34
+P4,34,IOB_X1Y90,RIOB33_X57Y89,IO_L5P_T0_34
+P5,34,IOB_X1Y80,RIOB33_X57Y79,IO_L10P_T1_34
+P6,14,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_14
+P8,14,IOB_X0Y60,LIOB33_X0Y59,IO_L20P_T3_A08_D24_14
+P9,14,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_A11_D27_14
+P10,14,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_14
+P11,14,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_14
+P13,14,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_14
+P14,14,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_14
+P15,14,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_D11_14
+P16,14,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_D12_14
+R1,34,IOB_X1Y85,RIOB33_X57Y85,IO_L7N_T1_34
+R2,34,IOB_X1Y86,RIOB33_X57Y85,IO_L7P_T1_34
+R3,34,IOB_X1Y84,RIOB33_X57Y83,IO_L8P_T1_34
+R5,14,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_A03_D19_14
+R6,14,IOB_X0Y52,LIOB33_X0Y51,IO_L24P_T3_A01_D17_14
+R7,14,IOB_X0Y51,LIOB33_X0Y51,IO_L24N_T3_A00_D16_14
+R8,14,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_A07_D23_14
+R10,14,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A14_D30_14
+R11,14,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A13_D29_14
+R12,14,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_RDWR_B_14
+R13,14,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_CSI_B_14
+R15,14,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_14
+R16,14,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_D13_14
+T2,34,IOB_X1Y83,RIOB33_X57Y83,IO_L8N_T1_34
+T3,34,IOB_X1Y81,RIOB33_X57Y81,IO_L9N_T1_DQS_34
+T4,34,IOB_X1Y82,RIOB33_X57Y81,IO_L9P_T1_DQS_34
+T5,14,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_A02_D18_14
+T7,14,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_14
+T8,14,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_A06_D22_14
+T9,14,IOB_X0Y56,LIOB33_X0Y55,IO_L22P_T3_A05_D21_14
+T10,14,IOB_X0Y55,LIOB33_X0Y55,IO_L22N_T3_A04_D20_14
+T12,14,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_DOUT_CSO_B_14
+T13,14,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A15_D31_14
+T14,14,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_D14_14
+T15,14,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_D15_14
diff --git a/artix7/xc7a100tftg256-3/part.json b/artix7/xc7a100tftg256-3/part.json
new file mode 100644
index 0000000..1cefd49
--- /dev/null
+++ b/artix7/xc7a100tftg256-3/part.json
@@ -0,0 +1,770 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
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+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
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+ },
+ "27": {
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+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
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+ },
+ "31": {
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+ },
+ "32": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ "frame_count": 30
+ },
+ "57": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
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+ },
+ "13": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "31": {
+ "frame_count": 30
+ },
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+ "frame_count": 36
+ },
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+ },
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+ "frame_count": 36
+ },
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+ },
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+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 28
+ },
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+ },
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+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 28
+ },
+ "45": {
+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 28
+ },
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+ "frame_count": 36
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
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+ "frame_count": 28
+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
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+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 30
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
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+ },
+ "36": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ "frame_count": 36
+ },
+ "56": {
+ "frame_count": 30
+ },
+ "57": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
+ "4": {
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+ },
+ "5": {
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+ },
+ "6": {
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+ },
+ "7": {
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+ },
+ "8": {
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+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 30
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 28
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 28
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 36
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 28
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 36
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 28
+ },
+ "49": {
+ "frame_count": 36
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56823955,
+ "iobanks": {
+ "0": "X1Y130",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "34": "X146Y78",
+ "35": "X146Y130"
+ }
+}
diff --git a/artix7/xc7a100tftg256-3/part.yaml b/artix7/xc7a100tftg256-3/part.yaml
new file mode 100644
index 0000000..44833bb
--- /dev/null
+++ b/artix7/xc7a100tftg256-3/part.yaml
@@ -0,0 +1,499 @@
+!<xilinx/xc7series/part>
+idcode: 0x3631093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
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+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
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+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
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+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
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+ 2: !<xilinx/xc7series/configuration_column>
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diff --git a/artix7/xc7a200tfbg484-1/package_pins.csv b/artix7/xc7a200tfbg484-1/package_pins.csv
new file mode 100644
index 0000000..4bd6953
--- /dev/null
+++ b/artix7/xc7a200tfbg484-1/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y197,RIOB33_X105Y197,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
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+A8,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A10,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A13,16,IOB_X0Y230,LIOB33_X0Y229,IO_L10P_T1_16
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+A16,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
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+AA1,34,IOB_X1Y136,RIOB33_X105Y135,IO_L7P_T1_34
+AA3,34,IOB_X1Y131,RIOB33_X105Y131,IO_L9N_T1_DQS_34
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+AA5,34,IOB_X1Y130,RIOB33_X105Y129,IO_L10P_T1_34
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+AA18,14,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_D11_14
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+AB7,34,IOB_X1Y110,RIOB33_X105Y109,IO_L20P_T3_34
+AB8,34,IOB_X1Y105,RIOB33_X105Y105,IO_L22N_T3_34
+AB10,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AB11,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AB12,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
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+B1,35,IOB_X1Y198,RIOB33_X105Y197,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y195,RIOB33_X105Y195,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y9,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXP0_216
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+B8,216,IPAD_X1Y37,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXP0_216
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+D11,216,IPAD_X1Y43,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXP1_216
+D14,16,IOB_X0Y238,LIOB33_X0Y237,IO_L6P_T0_16
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+E3,35,IOB_X1Y187,RIOB33_X105Y187,IO_L6N_T0_VREF_35
+E6,216,IPAD_X1Y45,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0N_216
+E10,216,IPAD_X1Y47,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1N_216
+E13,16,IOB_X0Y242,LIOB33_X0Y241,IO_L4P_T0_16
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+E17,16,IOB_X0Y245,LIOB33_X0Y245,IO_L2N_T0_16
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diff --git a/artix7/xc7a200tfbg484-1/part.json b/artix7/xc7a200tfbg484-1/part.json
new file mode 100644
index 0000000..44ab6a4
--- /dev/null
+++ b/artix7/xc7a200tfbg484-1/part.json
@@ -0,0 +1,1808 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
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+ "iobanks": {
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+ "13": "X1Y78",
+ "14": "X1Y130",
+ "15": "X1Y182",
+ "16": "X1Y234",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tfbg484-1/part.yaml b/artix7/xc7a200tfbg484-1/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbg484-1/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
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+ 22: !<xilinx/xc7series/configuration_column>
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+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
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+ 45: !<xilinx/xc7series/configuration_column>
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+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
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+ 50: !<xilinx/xc7series/configuration_column>
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+ 51: !<xilinx/xc7series/configuration_column>
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+ 52: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
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+ 58: !<xilinx/xc7series/configuration_column>
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+ 60: !<xilinx/xc7series/configuration_column>
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+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ 69: !<xilinx/xc7series/configuration_column>
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+ 79: !<xilinx/xc7series/configuration_column>
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+ 82: !<xilinx/xc7series/configuration_column>
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+ 83: !<xilinx/xc7series/configuration_column>
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+ 84: !<xilinx/xc7series/configuration_column>
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+ 85: !<xilinx/xc7series/configuration_column>
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+ 86: !<xilinx/xc7series/configuration_column>
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+ 87: !<xilinx/xc7series/configuration_column>
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+ 88: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 89: !<xilinx/xc7series/configuration_column>
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+ 90: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
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+ 93: !<xilinx/xc7series/configuration_column>
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+ 94: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 95: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 96: !<xilinx/xc7series/configuration_column>
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+ 97: !<xilinx/xc7series/configuration_column>
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+ 98: !<xilinx/xc7series/configuration_column>
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+ 99: !<xilinx/xc7series/configuration_column>
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+ 100: !<xilinx/xc7series/configuration_column>
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+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
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+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
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+ 3: !<xilinx/xc7series/configuration_column>
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+ 6: !<xilinx/xc7series/configuration_column>
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+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
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+ frame_count: 128
+ 2: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
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+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
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+ 4: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
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+ 6: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a200tfbg484-2/package_pins.csv b/artix7/xc7a200tfbg484-2/package_pins.csv
new file mode 100644
index 0000000..4bd6953
--- /dev/null
+++ b/artix7/xc7a200tfbg484-2/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y197,RIOB33_X105Y197,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+A6,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A8,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A10,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A13,16,IOB_X0Y230,LIOB33_X0Y229,IO_L10P_T1_16
+A14,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16
+A15,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y216,LIOB33_X0Y215,IO_L17P_T2_16
+A19,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+A20,16,IOB_X0Y217,LIOB33_X0Y217,IO_L16N_T2_16
+A21,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y136,RIOB33_X105Y135,IO_L7P_T1_34
+AA3,34,IOB_X1Y131,RIOB33_X105Y131,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y127,RIOB33_X105Y127,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y130,RIOB33_X105Y129,IO_L10P_T1_34
+AA6,34,IOB_X1Y113,RIOB33_X105Y113,IO_L18N_T2_34
+AA8,34,IOB_X1Y106,RIOB33_X105Y105,IO_L22P_T3_34
+AA9,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
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+AA11,13,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_13
+AA13,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AA14,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
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+AA16,13,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_13
+AA18,14,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y135,RIOB33_X105Y135,IO_L7N_T1_34
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+AB5,34,IOB_X1Y129,RIOB33_X105Y129,IO_L10N_T1_34
+AB6,34,IOB_X1Y109,RIOB33_X105Y109,IO_L20N_T3_34
+AB7,34,IOB_X1Y110,RIOB33_X105Y109,IO_L20P_T3_34
+AB8,34,IOB_X1Y105,RIOB33_X105Y105,IO_L22N_T3_34
+AB10,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AB11,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AB12,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
+AB13,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
+AB15,13,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_13
+AB16,13,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_13
+AB17,13,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_13
+AB18,14,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_D14_14
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+B1,35,IOB_X1Y198,RIOB33_X105Y197,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y195,RIOB33_X105Y195,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y9,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXP0_216
+B6,216,OPAD_X0Y13,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXP2_216
+B8,216,IPAD_X1Y37,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXP0_216
+B10,216,IPAD_X1Y55,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXP2_216
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+D11,216,IPAD_X1Y43,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXP1_216
+D14,16,IOB_X0Y238,LIOB33_X0Y237,IO_L6P_T0_16
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+D17,16,IOB_X0Y226,LIOB33_X0Y225,IO_L12P_T1_MRCC_16
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+E3,35,IOB_X1Y187,RIOB33_X105Y187,IO_L6N_T0_VREF_35
+E6,216,IPAD_X1Y45,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0N_216
+E10,216,IPAD_X1Y47,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1N_216
+E13,16,IOB_X0Y242,LIOB33_X0Y241,IO_L4P_T0_16
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+E17,16,IOB_X0Y245,LIOB33_X0Y245,IO_L2N_T0_16
+E18,16,IOB_X0Y219,LIOB33_X0Y219,IO_L15N_T2_DQS_16
+E19,16,IOB_X0Y222,LIOB33_X0Y221,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y204,LIOB33_X0Y203,IO_L23P_T3_16
+E22,16,IOB_X0Y206,LIOB33_X0Y205,IO_L22P_T3_16
+F1,35,IOB_X1Y189,RIOB33_X105Y189,IO_L5N_T0_AD13N_35
+F3,35,IOB_X1Y188,RIOB33_X105Y187,IO_L6P_T0_35
+F4,35,IOB_X1Y199,RIOB33_SING_X105Y199,IO_0_35
+F6,216,IPAD_X1Y44,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0P_216
+F10,216,IPAD_X1Y46,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1P_216
+F13,16,IOB_X0Y248,LIOB33_X0Y247,IO_L1P_T0_16
+F14,16,IOB_X0Y247,LIOB33_X0Y247,IO_L1N_T0_16
+F15,16,IOB_X0Y249,LIOB33_SING_X0Y249,IO_0_16
+F16,16,IOB_X0Y246,LIOB33_X0Y245,IO_L2P_T0_16
+F18,16,IOB_X0Y220,LIOB33_X0Y219,IO_L15P_T2_DQS_16
+F19,16,IOB_X0Y214,LIOB33_X0Y213,IO_L18P_T2_16
+F20,16,IOB_X0Y213,LIOB33_X0Y213,IO_L18N_T2_16
+F21,16,IOB_X0Y200,LIOB33_SING_X0Y200,IO_25_16
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diff --git a/artix7/xc7a200tfbg484-2/part.json b/artix7/xc7a200tfbg484-2/part.json
new file mode 100644
index 0000000..44ab6a4
--- /dev/null
+++ b/artix7/xc7a200tfbg484-2/part.json
@@ -0,0 +1,1808 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
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+ },
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+ },
+ "7": {
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+ },
+ "8": {
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+ }
+ }
+ },
+ "CLB_IO_CLK": {
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+ },
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+ },
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+ },
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+ }
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+ }
+ }
+ }
+ }
+ },
+ "idcode": 56844435,
+ "iobanks": {
+ "0": "X1Y182",
+ "13": "X1Y78",
+ "14": "X1Y130",
+ "15": "X1Y182",
+ "16": "X1Y234",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tfbg484-2/part.yaml b/artix7/xc7a200tfbg484-2/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbg484-2/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
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+ 52: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
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+ 58: !<xilinx/xc7series/configuration_column>
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+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ frame_count: 36
+ 69: !<xilinx/xc7series/configuration_column>
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+ 83: !<xilinx/xc7series/configuration_column>
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+ 84: !<xilinx/xc7series/configuration_column>
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+ 85: !<xilinx/xc7series/configuration_column>
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+ 86: !<xilinx/xc7series/configuration_column>
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+ 87: !<xilinx/xc7series/configuration_column>
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+ 88: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 89: !<xilinx/xc7series/configuration_column>
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+ 90: !<xilinx/xc7series/configuration_column>
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+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 93: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 94: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 95: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 96: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 97: !<xilinx/xc7series/configuration_column>
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+ 98: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 99: !<xilinx/xc7series/configuration_column>
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+ 100: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
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+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
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+ 3: !<xilinx/xc7series/configuration_column>
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diff --git a/artix7/xc7a200tfbg484-2L/package_pins.csv b/artix7/xc7a200tfbg484-2L/package_pins.csv
new file mode 100644
index 0000000..4bd6953
--- /dev/null
+++ b/artix7/xc7a200tfbg484-2L/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
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diff --git a/artix7/xc7a200tfbg484-2L/part.json b/artix7/xc7a200tfbg484-2L/part.json
new file mode 100644
index 0000000..44ab6a4
--- /dev/null
+++ b/artix7/xc7a200tfbg484-2L/part.json
@@ -0,0 +1,1808 @@
+{
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+ }
+ }
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+ }
+ }
+ }
+ }
+ },
+ "idcode": 56844435,
+ "iobanks": {
+ "0": "X1Y182",
+ "13": "X1Y78",
+ "14": "X1Y130",
+ "15": "X1Y182",
+ "16": "X1Y234",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tfbg484-2L/part.yaml b/artix7/xc7a200tfbg484-2L/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbg484-2L/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
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+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
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+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
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+ 39: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
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+ 41: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
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+ 45: !<xilinx/xc7series/configuration_column>
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+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
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+ 51: !<xilinx/xc7series/configuration_column>
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+ 52: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 82: !<xilinx/xc7series/configuration_column>
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+ 83: !<xilinx/xc7series/configuration_column>
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+ 85: !<xilinx/xc7series/configuration_column>
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+ 86: !<xilinx/xc7series/configuration_column>
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+ 88: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 89: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 90: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 93: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ 95: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 96: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 97: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 98: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 99: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 100: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
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+ 3: !<xilinx/xc7series/configuration_column>
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+ 4: !<xilinx/xc7series/configuration_column>
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+ 6: !<xilinx/xc7series/configuration_column>
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+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
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+ 2: !<xilinx/xc7series/configuration_column>
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diff --git a/artix7/xc7a200tfbg484-3/package_pins.csv b/artix7/xc7a200tfbg484-3/package_pins.csv
new file mode 100644
index 0000000..4bd6953
--- /dev/null
+++ b/artix7/xc7a200tfbg484-3/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y197,RIOB33_X105Y197,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+A6,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A8,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A10,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A13,16,IOB_X0Y230,LIOB33_X0Y229,IO_L10P_T1_16
+A14,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16
+A15,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y216,LIOB33_X0Y215,IO_L17P_T2_16
+A19,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+A20,16,IOB_X0Y217,LIOB33_X0Y217,IO_L16N_T2_16
+A21,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y136,RIOB33_X105Y135,IO_L7P_T1_34
+AA3,34,IOB_X1Y131,RIOB33_X105Y131,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y127,RIOB33_X105Y127,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y130,RIOB33_X105Y129,IO_L10P_T1_34
+AA6,34,IOB_X1Y113,RIOB33_X105Y113,IO_L18N_T2_34
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+AA9,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
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+AA18,14,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_D12_14
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+AB7,34,IOB_X1Y110,RIOB33_X105Y109,IO_L20P_T3_34
+AB8,34,IOB_X1Y105,RIOB33_X105Y105,IO_L22N_T3_34
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+AB11,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AB12,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
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+AB16,13,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_13
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+AB18,14,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_DOUT_CSO_B_14
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+B2,35,IOB_X1Y195,RIOB33_X105Y195,IO_L2N_T0_AD12N_35
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+D14,16,IOB_X0Y238,LIOB33_X0Y237,IO_L6P_T0_16
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+F4,35,IOB_X1Y199,RIOB33_SING_X105Y199,IO_0_35
+F6,216,IPAD_X1Y44,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0P_216
+F10,216,IPAD_X1Y46,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1P_216
+F13,16,IOB_X0Y248,LIOB33_X0Y247,IO_L1P_T0_16
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+F19,16,IOB_X0Y214,LIOB33_X0Y213,IO_L18P_T2_16
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+G4,35,IOB_X1Y175,RIOB33_X105Y175,IO_L12N_T1_MRCC_35
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diff --git a/artix7/xc7a200tfbg484-3/part.json b/artix7/xc7a200tfbg484-3/part.json
new file mode 100644
index 0000000..44ab6a4
--- /dev/null
+++ b/artix7/xc7a200tfbg484-3/part.json
@@ -0,0 +1,1808 @@
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+}
diff --git a/artix7/xc7a200tfbg484-3/part.yaml b/artix7/xc7a200tfbg484-3/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbg484-3/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
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+ frame_count: 42
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+ 2: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
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+ 105: !<xilinx/xc7series/configuration_column>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
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+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
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diff --git a/artix7/xc7a200tfbg676-1/package_pins.csv b/artix7/xc7a200tfbg676-1/package_pins.csv
new file mode 100644
index 0000000..d434221
--- /dev/null
+++ b/artix7/xc7a200tfbg676-1/package_pins.csv
@@ -0,0 +1,443 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y159,RIOB33_X105Y159,IO_L20N_T3_35
+A3,35,IOB_X1Y160,RIOB33_X105Y159,IO_L20P_T3_35
+A4,35,IOB_X1Y167,RIOB33_X105Y167,IO_L16N_T2_35
+A5,35,IOB_X1Y169,RIOB33_X105Y169,IO_L15N_T2_DQS_35
+A7,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+A9,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A11,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A13,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A17,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16
+A18,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
+A19,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16
+A20,16,IOB_X0Y219,LIOB33_X0Y219,IO_L15N_T2_DQS_16
+A22,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+A23,16,IOB_X0Y208,LIOB33_X0Y207,IO_L21P_T3_DQS_16
+A24,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+A25,16,IOB_X0Y209,LIOB33_X0Y209,IO_L20N_T3_16
+AA2,33,IOB_X1Y75,RIOB33_X105Y75,IO_L12N_T1_MRCC_33
+AA3,33,IOB_X1Y76,RIOB33_X105Y75,IO_L12P_T1_MRCC_33
+AA4,33,IOB_X1Y74,RIOB33_X105Y73,IO_L13P_T2_MRCC_33
+AA5,33,IOB_X1Y56,RIOB33_X105Y55,IO_L22P_T3_33
+AA7,33,IOB_X1Y61,RIOB33_X105Y61,IO_L19N_T3_VREF_33
+AA8,33,IOB_X1Y53,RIOB33_X105Y53,IO_L23N_T3_33
+AA11,213,IPAD_X1Y10,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1P_213
+AA13,213,IPAD_X1Y8,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0P_213
+AA15,12,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_12
+AA17,12,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_12
+AA18,12,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_12
+AA19,12,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_12
+AA20,12,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_12
+AA22,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
+AA23,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AA24,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AA25,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
+AB1,33,IOB_X1Y86,RIOB33_X105Y85,IO_L7P_T1_33
+AB2,33,IOB_X1Y78,RIOB33_X105Y77,IO_L11P_T1_SRCC_33
+AB4,33,IOB_X1Y73,RIOB33_X105Y73,IO_L13N_T2_MRCC_33
+AB5,33,IOB_X1Y55,RIOB33_X105Y55,IO_L22N_T3_33
+AB6,33,IOB_X1Y52,RIOB33_X105Y51,IO_L24P_T3_33
+AB11,213,IPAD_X1Y11,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1N_213
+AB13,213,IPAD_X1Y9,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0N_213
+AB16,12,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_12
+AB17,12,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_12
+AB19,12,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_12
+AB20,12,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_12
+AB21,12,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_12
+AB22,12,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_12
+AB24,13,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_13
+AB25,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
+AB26,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AC1,33,IOB_X1Y85,RIOB33_X105Y85,IO_L7N_T1_33
+AC2,33,IOB_X1Y77,RIOB33_X105Y77,IO_L11N_T1_SRCC_33
+AC3,33,IOB_X1Y72,RIOB33_X105Y71,IO_L14P_T2_SRCC_33
+AC4,33,IOB_X1Y64,RIOB33_X105Y63,IO_L18P_T2_33
+AC6,33,IOB_X1Y51,RIOB33_X105Y51,IO_L24N_T3_33
+AC8,213,OPAD_X0Y5,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXP2_213
+AC10,213,OPAD_X0Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPTXP0_213
+AC12,213,IPAD_X1Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXP0_213
+AC14,213,IPAD_X1Y19,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXP2_213
+AC16,12,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_12
+AC17,12,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_12
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+AD17,12,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_12
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+AD19,12,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_12
+AD20,12,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_12
+AD21,12,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_12
+AD23,12,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_12
+AD24,12,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_VREF_12
+AD25,12,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_12
+AD26,12,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_12
+AE1,33,IOB_X1Y81,RIOB33_X105Y81,IO_L9N_T1_DQS_33
+AE2,33,IOB_X1Y80,RIOB33_X105Y79,IO_L10P_T1_33
+AE3,33,IOB_X1Y68,RIOB33_X105Y67,IO_L16P_T2_33
+AE5,33,IOB_X1Y69,RIOB33_X105Y69,IO_L15N_T2_DQS_33
+AE7,213,OPAD_X0Y7,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXP3_213
+AE9,213,OPAD_X0Y3,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXP1_213
+AE11,213,IPAD_X1Y25,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXP3_213
+AE13,213,IPAD_X1Y7,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXP1_213
+AE17,12,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_12
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+AE21,12,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_12
+AE22,12,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_12
+AE23,12,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_12
+AE25,12,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_12
+AE26,12,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_12
+AF2,33,IOB_X1Y79,RIOB33_X105Y79,IO_L10N_T1_33
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+AF4,33,IOB_X1Y65,RIOB33_X105Y65,IO_L17N_T2_33
+AF5,33,IOB_X1Y66,RIOB33_X105Y65,IO_L17P_T2_33
+AF7,213,OPAD_X0Y6,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXN3_213
+AF9,213,OPAD_X0Y2,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXN1_213
+AF11,213,IPAD_X1Y24,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXN3_213
+AF13,213,IPAD_X1Y6,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXN1_213
+AF17,12,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_12
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+AF19,12,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_12
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+B1,35,IOB_X1Y157,RIOB33_X105Y157,IO_L21N_T3_DQS_35
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+B5,35,IOB_X1Y170,RIOB33_X105Y169,IO_L15P_T2_DQS_35
+B7,216,OPAD_X0Y9,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXP0_216
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+B11,216,IPAD_X1Y37,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXP0_216
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diff --git a/artix7/xc7a200tfbg676-1/part.json b/artix7/xc7a200tfbg676-1/part.json
new file mode 100644
index 0000000..6b0ff28
--- /dev/null
+++ b/artix7/xc7a200tfbg676-1/part.json
@@ -0,0 +1,1811 @@
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+}
diff --git a/artix7/xc7a200tfbg676-1/part.yaml b/artix7/xc7a200tfbg676-1/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbg676-1/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
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diff --git a/artix7/xc7a200tfbg676-2/package_pins.csv b/artix7/xc7a200tfbg676-2/package_pins.csv
new file mode 100644
index 0000000..d434221
--- /dev/null
+++ b/artix7/xc7a200tfbg676-2/package_pins.csv
@@ -0,0 +1,443 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y159,RIOB33_X105Y159,IO_L20N_T3_35
+A3,35,IOB_X1Y160,RIOB33_X105Y159,IO_L20P_T3_35
+A4,35,IOB_X1Y167,RIOB33_X105Y167,IO_L16N_T2_35
+A5,35,IOB_X1Y169,RIOB33_X105Y169,IO_L15N_T2_DQS_35
+A7,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+A9,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A11,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A13,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A17,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16
+A18,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
+A19,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16
+A20,16,IOB_X0Y219,LIOB33_X0Y219,IO_L15N_T2_DQS_16
+A22,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+A23,16,IOB_X0Y208,LIOB33_X0Y207,IO_L21P_T3_DQS_16
+A24,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+A25,16,IOB_X0Y209,LIOB33_X0Y209,IO_L20N_T3_16
+AA2,33,IOB_X1Y75,RIOB33_X105Y75,IO_L12N_T1_MRCC_33
+AA3,33,IOB_X1Y76,RIOB33_X105Y75,IO_L12P_T1_MRCC_33
+AA4,33,IOB_X1Y74,RIOB33_X105Y73,IO_L13P_T2_MRCC_33
+AA5,33,IOB_X1Y56,RIOB33_X105Y55,IO_L22P_T3_33
+AA7,33,IOB_X1Y61,RIOB33_X105Y61,IO_L19N_T3_VREF_33
+AA8,33,IOB_X1Y53,RIOB33_X105Y53,IO_L23N_T3_33
+AA11,213,IPAD_X1Y10,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1P_213
+AA13,213,IPAD_X1Y8,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0P_213
+AA15,12,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_12
+AA17,12,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_12
+AA18,12,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_12
+AA19,12,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_12
+AA20,12,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_12
+AA22,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
+AA23,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AA24,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AA25,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
+AB1,33,IOB_X1Y86,RIOB33_X105Y85,IO_L7P_T1_33
+AB2,33,IOB_X1Y78,RIOB33_X105Y77,IO_L11P_T1_SRCC_33
+AB4,33,IOB_X1Y73,RIOB33_X105Y73,IO_L13N_T2_MRCC_33
+AB5,33,IOB_X1Y55,RIOB33_X105Y55,IO_L22N_T3_33
+AB6,33,IOB_X1Y52,RIOB33_X105Y51,IO_L24P_T3_33
+AB11,213,IPAD_X1Y11,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1N_213
+AB13,213,IPAD_X1Y9,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0N_213
+AB16,12,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_12
+AB17,12,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_12
+AB19,12,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_12
+AB20,12,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_12
+AB21,12,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_12
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diff --git a/artix7/xc7a200tfbg676-2/part.json b/artix7/xc7a200tfbg676-2/part.json
new file mode 100644
index 0000000..6b0ff28
--- /dev/null
+++ b/artix7/xc7a200tfbg676-2/part.json
@@ -0,0 +1,1811 @@
+{
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+ }
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+ "CLB_IO_CLK": {
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+ },
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+ },
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+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56844435,
+ "iobanks": {
+ "0": "X1Y182",
+ "12": "X1Y26",
+ "13": "X1Y78",
+ "14": "X1Y130",
+ "15": "X1Y182",
+ "16": "X1Y234",
+ "33": "X263Y78",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "213": "X1Y26",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tfbg676-2/part.yaml b/artix7/xc7a200tfbg676-2/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbg676-2/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 32: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
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+ 58: !<xilinx/xc7series/configuration_column>
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+ 60: !<xilinx/xc7series/configuration_column>
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+ frame_count: 28
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+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ frame_count: 28
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+ frame_count: 36
+ 69: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
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+ frame_count: 36
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+ frame_count: 36
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+ 79: !<xilinx/xc7series/configuration_column>
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+ 80: !<xilinx/xc7series/configuration_column>
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+ 81: !<xilinx/xc7series/configuration_column>
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+ 82: !<xilinx/xc7series/configuration_column>
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+ 83: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 84: !<xilinx/xc7series/configuration_column>
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+ 85: !<xilinx/xc7series/configuration_column>
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+ 86: !<xilinx/xc7series/configuration_column>
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+ 87: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 88: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 89: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 90: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 93: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 94: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 95: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 96: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 97: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 98: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 99: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 100: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
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+ 3: !<xilinx/xc7series/configuration_column>
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diff --git a/artix7/xc7a200tfbg676-2L/package_pins.csv b/artix7/xc7a200tfbg676-2L/package_pins.csv
new file mode 100644
index 0000000..d434221
--- /dev/null
+++ b/artix7/xc7a200tfbg676-2L/package_pins.csv
@@ -0,0 +1,443 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y159,RIOB33_X105Y159,IO_L20N_T3_35
+A3,35,IOB_X1Y160,RIOB33_X105Y159,IO_L20P_T3_35
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+A7,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+A9,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A11,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A13,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A17,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16
+A18,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
+A19,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16
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+A22,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+A23,16,IOB_X0Y208,LIOB33_X0Y207,IO_L21P_T3_DQS_16
+A24,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+A25,16,IOB_X0Y209,LIOB33_X0Y209,IO_L20N_T3_16
+AA2,33,IOB_X1Y75,RIOB33_X105Y75,IO_L12N_T1_MRCC_33
+AA3,33,IOB_X1Y76,RIOB33_X105Y75,IO_L12P_T1_MRCC_33
+AA4,33,IOB_X1Y74,RIOB33_X105Y73,IO_L13P_T2_MRCC_33
+AA5,33,IOB_X1Y56,RIOB33_X105Y55,IO_L22P_T3_33
+AA7,33,IOB_X1Y61,RIOB33_X105Y61,IO_L19N_T3_VREF_33
+AA8,33,IOB_X1Y53,RIOB33_X105Y53,IO_L23N_T3_33
+AA11,213,IPAD_X1Y10,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1P_213
+AA13,213,IPAD_X1Y8,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0P_213
+AA15,12,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_12
+AA17,12,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_12
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+AA20,12,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_12
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+AB4,33,IOB_X1Y73,RIOB33_X105Y73,IO_L13N_T2_MRCC_33
+AB5,33,IOB_X1Y55,RIOB33_X105Y55,IO_L22N_T3_33
+AB6,33,IOB_X1Y52,RIOB33_X105Y51,IO_L24P_T3_33
+AB11,213,IPAD_X1Y11,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1N_213
+AB13,213,IPAD_X1Y9,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0N_213
+AB16,12,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_12
+AB17,12,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_12
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diff --git a/artix7/xc7a200tfbg676-2L/part.json b/artix7/xc7a200tfbg676-2L/part.json
new file mode 100644
index 0000000..6b0ff28
--- /dev/null
+++ b/artix7/xc7a200tfbg676-2L/part.json
@@ -0,0 +1,1811 @@
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+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tfbg676-2L/part.yaml b/artix7/xc7a200tfbg676-2L/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbg676-2L/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
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diff --git a/artix7/xc7a200tfbg676-3/package_pins.csv b/artix7/xc7a200tfbg676-3/package_pins.csv
new file mode 100644
index 0000000..d434221
--- /dev/null
+++ b/artix7/xc7a200tfbg676-3/package_pins.csv
@@ -0,0 +1,443 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y159,RIOB33_X105Y159,IO_L20N_T3_35
+A3,35,IOB_X1Y160,RIOB33_X105Y159,IO_L20P_T3_35
+A4,35,IOB_X1Y167,RIOB33_X105Y167,IO_L16N_T2_35
+A5,35,IOB_X1Y169,RIOB33_X105Y169,IO_L15N_T2_DQS_35
+A7,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+A9,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A11,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A13,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A17,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16
+A18,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
+A19,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16
+A20,16,IOB_X0Y219,LIOB33_X0Y219,IO_L15N_T2_DQS_16
+A22,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+A23,16,IOB_X0Y208,LIOB33_X0Y207,IO_L21P_T3_DQS_16
+A24,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+A25,16,IOB_X0Y209,LIOB33_X0Y209,IO_L20N_T3_16
+AA2,33,IOB_X1Y75,RIOB33_X105Y75,IO_L12N_T1_MRCC_33
+AA3,33,IOB_X1Y76,RIOB33_X105Y75,IO_L12P_T1_MRCC_33
+AA4,33,IOB_X1Y74,RIOB33_X105Y73,IO_L13P_T2_MRCC_33
+AA5,33,IOB_X1Y56,RIOB33_X105Y55,IO_L22P_T3_33
+AA7,33,IOB_X1Y61,RIOB33_X105Y61,IO_L19N_T3_VREF_33
+AA8,33,IOB_X1Y53,RIOB33_X105Y53,IO_L23N_T3_33
+AA11,213,IPAD_X1Y10,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1P_213
+AA13,213,IPAD_X1Y8,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0P_213
+AA15,12,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_12
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+AA18,12,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_12
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+AA20,12,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_12
+AA22,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
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+AA24,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AA25,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
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+AB2,33,IOB_X1Y78,RIOB33_X105Y77,IO_L11P_T1_SRCC_33
+AB4,33,IOB_X1Y73,RIOB33_X105Y73,IO_L13N_T2_MRCC_33
+AB5,33,IOB_X1Y55,RIOB33_X105Y55,IO_L22N_T3_33
+AB6,33,IOB_X1Y52,RIOB33_X105Y51,IO_L24P_T3_33
+AB11,213,IPAD_X1Y11,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1N_213
+AB13,213,IPAD_X1Y9,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0N_213
+AB16,12,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_12
+AB17,12,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_12
+AB19,12,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_12
+AB20,12,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_12
+AB21,12,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_12
+AB22,12,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_12
+AB24,13,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_13
+AB25,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
+AB26,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AC1,33,IOB_X1Y85,RIOB33_X105Y85,IO_L7N_T1_33
+AC2,33,IOB_X1Y77,RIOB33_X105Y77,IO_L11N_T1_SRCC_33
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+AC4,33,IOB_X1Y64,RIOB33_X105Y63,IO_L18P_T2_33
+AC6,33,IOB_X1Y51,RIOB33_X105Y51,IO_L24N_T3_33
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+AC10,213,OPAD_X0Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPTXP0_213
+AC12,213,IPAD_X1Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXP0_213
+AC14,213,IPAD_X1Y19,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXP2_213
+AC16,12,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_12
+AC17,12,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_12
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+AC19,12,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_12
+AC21,12,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_12
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+AC23,12,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_12
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+AC26,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
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+AD5,33,IOB_X1Y70,RIOB33_X105Y69,IO_L15P_T2_DQS_33
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+AD12,213,IPAD_X1Y0,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXN0_213
+AD14,213,IPAD_X1Y18,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXN2_213
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+AD25,12,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_12
+AD26,12,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_12
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+AE9,213,OPAD_X0Y3,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXP1_213
+AE11,213,IPAD_X1Y25,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXP3_213
+AE13,213,IPAD_X1Y7,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXP1_213
+AE17,12,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_12
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+AF4,33,IOB_X1Y65,RIOB33_X105Y65,IO_L17N_T2_33
+AF5,33,IOB_X1Y66,RIOB33_X105Y65,IO_L17P_T2_33
+AF7,213,OPAD_X0Y6,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXN3_213
+AF9,213,OPAD_X0Y2,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXN1_213
+AF11,213,IPAD_X1Y24,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXN3_213
+AF13,213,IPAD_X1Y6,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXN1_213
+AF17,12,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_12
+AF18,12,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_12
+AF19,12,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_12
+AF20,12,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_12
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+AF23,12,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_12
+AF24,12,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_12
+AF25,12,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_12
+B1,35,IOB_X1Y157,RIOB33_X105Y157,IO_L21N_T3_DQS_35
+B2,35,IOB_X1Y161,RIOB33_X105Y161,IO_L19N_T3_VREF_35
+B4,35,IOB_X1Y168,RIOB33_X105Y167,IO_L16P_T2_35
+B5,35,IOB_X1Y170,RIOB33_X105Y169,IO_L15P_T2_DQS_35
+B7,216,OPAD_X0Y9,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXP0_216
+B9,216,OPAD_X0Y13,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXP2_216
+B11,216,IPAD_X1Y37,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXP0_216
+B13,216,IPAD_X1Y55,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXP2_216
+B17,16,IOB_X0Y235,LIOB33_X0Y235,IO_L7N_T1_16
+B19,16,IOB_X0Y230,LIOB33_X0Y229,IO_L10P_T1_16
+B20,16,IOB_X0Y220,LIOB33_X0Y219,IO_L15P_T2_DQS_16
+B21,16,IOB_X0Y217,LIOB33_X0Y217,IO_L16N_T2_16
+B22,16,IOB_X0Y216,LIOB33_X0Y215,IO_L17P_T2_16
+B24,16,IOB_X0Y203,LIOB33_X0Y203,IO_L23N_T3_16
+B25,16,IOB_X0Y210,LIOB33_X0Y209,IO_L20P_T3_16
+B26,16,IOB_X0Y205,LIOB33_X0Y205,IO_L22N_T3_16
+C1,35,IOB_X1Y158,RIOB33_X105Y157,IO_L21P_T3_DQS_35
+C2,35,IOB_X1Y162,RIOB33_X105Y161,IO_L19P_T3_35
+C3,35,IOB_X1Y165,RIOB33_X105Y165,IO_L17N_T2_35
+C4,35,IOB_X1Y171,RIOB33_X105Y171,IO_L14N_T2_SRCC_35
+C8,216,OPAD_X0Y10,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPTXN1_216
+C10,216,OPAD_X0Y14,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXN3_216
+C12,216,IPAD_X1Y60,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXN3_216
+C14,216,IPAD_X1Y42,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXN1_216
+C17,16,IOB_X0Y236,LIOB33_X0Y235,IO_L7P_T1_16
+C18,16,IOB_X0Y225,LIOB33_X0Y225,IO_L12N_T1_MRCC_16
+C19,16,IOB_X0Y223,LIOB33_X0Y223,IO_L13N_T2_MRCC_16
+C21,16,IOB_X0Y218,LIOB33_X0Y217,IO_L16P_T2_16
+C22,16,IOB_X0Y212,LIOB33_X0Y211,IO_L19P_T3_16
+C23,16,IOB_X0Y211,LIOB33_X0Y211,IO_L19N_T3_VREF_16
+C24,16,IOB_X0Y204,LIOB33_X0Y203,IO_L23P_T3_16
+C26,16,IOB_X0Y206,LIOB33_X0Y205,IO_L22P_T3_16
+D1,35,IOB_X1Y153,RIOB33_X105Y153,IO_L23N_T3_35
+D3,35,IOB_X1Y166,RIOB33_X105Y165,IO_L17P_T2_35
+D4,35,IOB_X1Y172,RIOB33_X105Y171,IO_L14P_T2_SRCC_35
+D5,35,IOB_X1Y173,RIOB33_X105Y173,IO_L13N_T2_MRCC_35
+D6,35,IOB_X1Y197,RIOB33_X105Y197,IO_L1N_T0_AD4N_35
+D8,216,OPAD_X0Y11,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPTXP1_216
+D10,216,OPAD_X0Y15,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXP3_216
+D12,216,IPAD_X1Y61,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXP3_216
+D14,216,IPAD_X1Y43,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXP1_216
+D16,16,IOB_X0Y233,LIOB33_X0Y233,IO_L8N_T1_16
+D18,16,IOB_X0Y226,LIOB33_X0Y225,IO_L12P_T1_MRCC_16
+D19,16,IOB_X0Y224,LIOB33_X0Y223,IO_L13P_T2_MRCC_16
+D20,16,IOB_X0Y221,LIOB33_X0Y221,IO_L14N_T2_SRCC_16
+D21,16,IOB_X0Y213,LIOB33_X0Y213,IO_L18N_T2_16
+D23,16,IOB_X0Y202,LIOB33_X0Y201,IO_L24P_T3_16
+D24,16,IOB_X0Y201,LIOB33_X0Y201,IO_L24N_T3_16
+D25,15,IOB_X0Y159,LIOB33_X0Y159,IO_L20N_T3_A19_15
+D26,15,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_A18_15
+E1,35,IOB_X1Y154,RIOB33_X105Y153,IO_L23P_T3_35
+E2,35,IOB_X1Y155,RIOB33_X105Y155,IO_L22N_T3_35
+E3,35,IOB_X1Y163,RIOB33_X105Y163,IO_L18N_T2_35
+E5,35,IOB_X1Y174,RIOB33_X105Y173,IO_L13P_T2_MRCC_35
+E6,35,IOB_X1Y198,RIOB33_X105Y197,IO_L1P_T0_AD4P_35
+E11,216,IPAD_X1Y45,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0N_216
+E13,216,IPAD_X1Y47,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1N_216
+E16,16,IOB_X0Y234,LIOB33_X0Y233,IO_L8P_T1_16
+E17,16,IOB_X0Y228,LIOB33_X0Y227,IO_L11P_T1_SRCC_16
+E18,16,IOB_X0Y227,LIOB33_X0Y227,IO_L11N_T1_SRCC_16
+E20,16,IOB_X0Y222,LIOB33_X0Y221,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y214,LIOB33_X0Y213,IO_L18P_T2_16
+E22,16,IOB_X0Y200,LIOB33_SING_X0Y200,IO_25_16
+E23,15,IOB_X0Y165,LIOB33_X0Y165,IO_L17N_T2_A25_15
+E25,15,IOB_X0Y160,LIOB33_X0Y159,IO_L20P_T3_A20_15
+E26,15,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_15
+F2,35,IOB_X1Y156,RIOB33_X105Y155,IO_L22P_T3_35
+F3,35,IOB_X1Y164,RIOB33_X105Y163,IO_L18P_T2_35
+F4,35,IOB_X1Y177,RIOB33_X105Y177,IO_L11N_T1_SRCC_35
+F5,35,IOB_X1Y175,RIOB33_X105Y175,IO_L12N_T1_MRCC_35
+F7,35,IOB_X1Y191,RIOB33_X105Y191,IO_L4N_T0_35
+F8,35,IOB_X1Y192,RIOB33_X105Y191,IO_L4P_T0_35
+F11,216,IPAD_X1Y44,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0P_216
+F13,216,IPAD_X1Y46,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1P_216
+F15,16,IOB_X0Y241,LIOB33_X0Y241,IO_L4N_T0_16
+F17,16,IOB_X0Y245,LIOB33_X0Y245,IO_L2N_T0_16
+F18,16,IOB_X0Y244,LIOB33_X0Y243,IO_L3P_T0_DQS_16
+F19,16,IOB_X0Y243,LIOB33_X0Y243,IO_L3N_T0_DQS_16
+F20,16,IOB_X0Y239,LIOB33_X0Y239,IO_L5N_T0_16
+F22,15,IOB_X0Y169,LIOB33_X0Y169,IO_L15N_T2_DQS_ADV_B_15
+F23,15,IOB_X0Y166,LIOB33_X0Y165,IO_L17P_T2_A26_15
+F24,15,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_A21_VREF_15
+F25,15,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_FWE_B_15
+G1,35,IOB_X1Y151,RIOB33_X105Y151,IO_L24N_T3_35
+G2,35,IOB_X1Y152,RIOB33_X105Y151,IO_L24P_T3_35
+G4,35,IOB_X1Y178,RIOB33_X105Y177,IO_L11P_T1_SRCC_35
+G5,35,IOB_X1Y176,RIOB33_X105Y175,IO_L12P_T1_MRCC_35
+G6,35,IOB_X1Y189,RIOB33_X105Y189,IO_L5N_T0_AD13N_35
+G7,35,IOB_X1Y193,RIOB33_X105Y193,IO_L3N_T0_DQS_AD5N_35
+G8,35,IOB_X1Y195,RIOB33_X105Y195,IO_L2N_T0_AD12N_35
+G9,35,IOB_X1Y187,RIOB33_X105Y187,IO_L6N_T0_VREF_35
+G15,16,IOB_X0Y242,LIOB33_X0Y241,IO_L4P_T0_16
+G16,16,IOB_X0Y237,LIOB33_X0Y237,IO_L6N_T0_VREF_16
+G17,16,IOB_X0Y246,LIOB33_X0Y245,IO_L2P_T0_16
+G19,16,IOB_X0Y240,LIOB33_X0Y239,IO_L5P_T0_16
+G20,15,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_15
+G21,15,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_15
+G22,15,IOB_X0Y170,LIOB33_X0Y169,IO_L15P_T2_DQS_15
+G24,15,IOB_X0Y162,LIOB33_X0Y161,IO_L19P_T3_A22_15
+G25,15,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_FOE_B_15
+G26,15,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_A16_15
+H1,34,IOB_X1Y129,RIOB33_X105Y129,IO_L10N_T1_34
+H2,34,IOB_X1Y130,RIOB33_X105Y129,IO_L10P_T1_34
+H3,35,IOB_X1Y150,RIOB33_SING_X105Y150,IO_25_35
+H4,35,IOB_X1Y181,RIOB33_X105Y181,IO_L9N_T1_DQS_AD7N_35
+H6,35,IOB_X1Y190,RIOB33_X105Y189,IO_L5P_T0_AD13P_35
+H7,35,IOB_X1Y194,RIOB33_X105Y193,IO_L3P_T0_DQS_AD5P_35
+H8,35,IOB_X1Y196,RIOB33_X105Y195,IO_L2P_T0_AD12P_35
+H9,35,IOB_X1Y188,RIOB33_X105Y187,IO_L6P_T0_35
+H14,16,IOB_X0Y248,LIOB33_X0Y247,IO_L1P_T0_16
+H15,16,IOB_X0Y247,LIOB33_X0Y247,IO_L1N_T0_16
+H16,16,IOB_X0Y238,LIOB33_X0Y237,IO_L6P_T0_16
+H17,16,IOB_X0Y249,LIOB33_SING_X0Y249,IO_0_16
+H18,15,IOB_X0Y179,LIOB33_X0Y179,IO_L10N_T1_AD11N_15
+H19,15,IOB_X0Y185,LIOB33_X0Y185,IO_L7N_T1_AD2N_15
+H21,15,IOB_X0Y174,LIOB33_X0Y173,IO_L13P_T2_MRCC_15
+H22,15,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_15
+H23,15,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_15
+H24,15,IOB_X0Y167,LIOB33_X0Y167,IO_L16N_T2_A27_15
+H26,15,IOB_X0Y156,LIOB33_X0Y155,IO_L22P_T3_A17_15
+J1,34,IOB_X1Y135,RIOB33_X105Y135,IO_L7N_T1_34
+J3,34,IOB_X1Y147,RIOB33_X105Y147,IO_L1N_T0_34
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diff --git a/artix7/xc7a200tfbg676-3/part.json b/artix7/xc7a200tfbg676-3/part.json
new file mode 100644
index 0000000..6b0ff28
--- /dev/null
+++ b/artix7/xc7a200tfbg676-3/part.json
@@ -0,0 +1,1811 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ },
+ "4": {
+ "frame_count": 128
+ },
+ "5": {
+ "frame_count": 128
+ },
+ "6": {
+ "frame_count": 128
+ },
+ "7": {
+ "frame_count": 128
+ },
+ "8": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
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+ }
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+ },
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+ "iobanks": {
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+ "12": "X1Y26",
+ "13": "X1Y78",
+ "14": "X1Y130",
+ "15": "X1Y182",
+ "16": "X1Y234",
+ "33": "X263Y78",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "213": "X1Y26",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tfbg676-3/part.yaml b/artix7/xc7a200tfbg676-3/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbg676-3/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
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+ 52: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
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+ 58: !<xilinx/xc7series/configuration_column>
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+ 59: !<xilinx/xc7series/configuration_column>
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+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
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+ frame_count: 36
+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 65: !<xilinx/xc7series/configuration_column>
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+ 66: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 67: !<xilinx/xc7series/configuration_column>
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+ 68: !<xilinx/xc7series/configuration_column>
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+ 69: !<xilinx/xc7series/configuration_column>
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+ 73: !<xilinx/xc7series/configuration_column>
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+ 78: !<xilinx/xc7series/configuration_column>
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+ 79: !<xilinx/xc7series/configuration_column>
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+ 80: !<xilinx/xc7series/configuration_column>
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+ 81: !<xilinx/xc7series/configuration_column>
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+ 82: !<xilinx/xc7series/configuration_column>
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+ 83: !<xilinx/xc7series/configuration_column>
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+ 84: !<xilinx/xc7series/configuration_column>
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+ 85: !<xilinx/xc7series/configuration_column>
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+ 86: !<xilinx/xc7series/configuration_column>
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+ 87: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 88: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 89: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 90: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 93: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 94: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 95: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 96: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 97: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 98: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 99: !<xilinx/xc7series/configuration_column>
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+ 100: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
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+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
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+ 3: !<xilinx/xc7series/configuration_column>
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+ 4: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
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+ 6: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 14: !<xilinx/xc7series/configuration_column>
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+ 16: !<xilinx/xc7series/configuration_column>
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+ 2: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
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+ frame_count: 42
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+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
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+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 6: !<xilinx/xc7series/configuration_column>
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+ 7: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a200tfbv484-1/package_pins.csv b/artix7/xc7a200tfbv484-1/package_pins.csv
new file mode 100644
index 0000000..4bd6953
--- /dev/null
+++ b/artix7/xc7a200tfbv484-1/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y197,RIOB33_X105Y197,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+A6,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A8,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A10,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A13,16,IOB_X0Y230,LIOB33_X0Y229,IO_L10P_T1_16
+A14,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16
+A15,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y216,LIOB33_X0Y215,IO_L17P_T2_16
+A19,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+A20,16,IOB_X0Y217,LIOB33_X0Y217,IO_L16N_T2_16
+A21,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y136,RIOB33_X105Y135,IO_L7P_T1_34
+AA3,34,IOB_X1Y131,RIOB33_X105Y131,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y127,RIOB33_X105Y127,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y130,RIOB33_X105Y129,IO_L10P_T1_34
+AA6,34,IOB_X1Y113,RIOB33_X105Y113,IO_L18N_T2_34
+AA8,34,IOB_X1Y106,RIOB33_X105Y105,IO_L22P_T3_34
+AA9,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
+AA10,13,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_13
+AA11,13,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_13
+AA13,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AA14,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
+AA15,13,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_13
+AA16,13,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_13
+AA18,14,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y135,RIOB33_X105Y135,IO_L7N_T1_34
+AB2,34,IOB_X1Y133,RIOB33_X105Y133,IO_L8N_T1_34
+AB3,34,IOB_X1Y134,RIOB33_X105Y133,IO_L8P_T1_34
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+AB6,34,IOB_X1Y109,RIOB33_X105Y109,IO_L20N_T3_34
+AB7,34,IOB_X1Y110,RIOB33_X105Y109,IO_L20P_T3_34
+AB8,34,IOB_X1Y105,RIOB33_X105Y105,IO_L22N_T3_34
+AB10,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AB11,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AB12,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
+AB13,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
+AB15,13,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_13
+AB16,13,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_13
+AB17,13,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_13
+AB18,14,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_D14_14
+AB22,14,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_D15_14
+B1,35,IOB_X1Y198,RIOB33_X105Y197,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y195,RIOB33_X105Y195,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y9,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXP0_216
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+B8,216,IPAD_X1Y37,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXP0_216
+B10,216,IPAD_X1Y55,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXP2_216
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+D14,16,IOB_X0Y238,LIOB33_X0Y237,IO_L6P_T0_16
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+E3,35,IOB_X1Y187,RIOB33_X105Y187,IO_L6N_T0_VREF_35
+E6,216,IPAD_X1Y45,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0N_216
+E10,216,IPAD_X1Y47,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1N_216
+E13,16,IOB_X0Y242,LIOB33_X0Y241,IO_L4P_T0_16
+E14,16,IOB_X0Y241,LIOB33_X0Y241,IO_L4N_T0_16
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+E17,16,IOB_X0Y245,LIOB33_X0Y245,IO_L2N_T0_16
+E18,16,IOB_X0Y219,LIOB33_X0Y219,IO_L15N_T2_DQS_16
+E19,16,IOB_X0Y222,LIOB33_X0Y221,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y204,LIOB33_X0Y203,IO_L23P_T3_16
+E22,16,IOB_X0Y206,LIOB33_X0Y205,IO_L22P_T3_16
+F1,35,IOB_X1Y189,RIOB33_X105Y189,IO_L5N_T0_AD13N_35
+F3,35,IOB_X1Y188,RIOB33_X105Y187,IO_L6P_T0_35
+F4,35,IOB_X1Y199,RIOB33_SING_X105Y199,IO_0_35
+F6,216,IPAD_X1Y44,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0P_216
+F10,216,IPAD_X1Y46,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1P_216
+F13,16,IOB_X0Y248,LIOB33_X0Y247,IO_L1P_T0_16
+F14,16,IOB_X0Y247,LIOB33_X0Y247,IO_L1N_T0_16
+F15,16,IOB_X0Y249,LIOB33_SING_X0Y249,IO_0_16
+F16,16,IOB_X0Y246,LIOB33_X0Y245,IO_L2P_T0_16
+F18,16,IOB_X0Y220,LIOB33_X0Y219,IO_L15P_T2_DQS_16
+F19,16,IOB_X0Y214,LIOB33_X0Y213,IO_L18P_T2_16
+F20,16,IOB_X0Y213,LIOB33_X0Y213,IO_L18N_T2_16
+F21,16,IOB_X0Y200,LIOB33_SING_X0Y200,IO_25_16
+G1,35,IOB_X1Y190,RIOB33_X105Y189,IO_L5P_T0_AD13P_35
+G2,35,IOB_X1Y183,RIOB33_X105Y183,IO_L8N_T1_AD14N_35
+G3,35,IOB_X1Y177,RIOB33_X105Y177,IO_L11N_T1_SRCC_35
+G4,35,IOB_X1Y175,RIOB33_X105Y175,IO_L12N_T1_MRCC_35
+G13,15,IOB_X0Y197,LIOB33_X0Y197,IO_L1N_T0_AD0N_15
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diff --git a/artix7/xc7a200tfbv484-1/part.json b/artix7/xc7a200tfbv484-1/part.json
new file mode 100644
index 0000000..44ab6a4
--- /dev/null
+++ b/artix7/xc7a200tfbv484-1/part.json
@@ -0,0 +1,1808 @@
+{
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+ "rows": {
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+ }
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+ }
+ },
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+ "iobanks": {
+ "0": "X1Y182",
+ "13": "X1Y78",
+ "14": "X1Y130",
+ "15": "X1Y182",
+ "16": "X1Y234",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tfbv484-1/part.yaml b/artix7/xc7a200tfbv484-1/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbv484-1/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
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+ 19: !<xilinx/xc7series/configuration_column>
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+ 20: !<xilinx/xc7series/configuration_column>
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+ 21: !<xilinx/xc7series/configuration_column>
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+ 22: !<xilinx/xc7series/configuration_column>
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+ 23: !<xilinx/xc7series/configuration_column>
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+ 24: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
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+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
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+ 39: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
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+ 41: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
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+ 43: !<xilinx/xc7series/configuration_column>
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+ 44: !<xilinx/xc7series/configuration_column>
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+ 45: !<xilinx/xc7series/configuration_column>
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+ 46: !<xilinx/xc7series/configuration_column>
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+ 47: !<xilinx/xc7series/configuration_column>
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+ 48: !<xilinx/xc7series/configuration_column>
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+ 49: !<xilinx/xc7series/configuration_column>
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+ 50: !<xilinx/xc7series/configuration_column>
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+ 51: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 90: !<xilinx/xc7series/configuration_column>
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+ 91: !<xilinx/xc7series/configuration_column>
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+ 93: !<xilinx/xc7series/configuration_column>
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+ 95: !<xilinx/xc7series/configuration_column>
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+ 96: !<xilinx/xc7series/configuration_column>
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+ 97: !<xilinx/xc7series/configuration_column>
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+ 98: !<xilinx/xc7series/configuration_column>
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+ 99: !<xilinx/xc7series/configuration_column>
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+ 100: !<xilinx/xc7series/configuration_column>
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+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
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+ 2: !<xilinx/xc7series/configuration_column>
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+ 3: !<xilinx/xc7series/configuration_column>
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+ 4: !<xilinx/xc7series/configuration_column>
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+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
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+ 2: !<xilinx/xc7series/configuration_column>
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diff --git a/artix7/xc7a200tfbv484-2/package_pins.csv b/artix7/xc7a200tfbv484-2/package_pins.csv
new file mode 100644
index 0000000..4bd6953
--- /dev/null
+++ b/artix7/xc7a200tfbv484-2/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
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+A4,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
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+AA1,34,IOB_X1Y136,RIOB33_X105Y135,IO_L7P_T1_34
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diff --git a/artix7/xc7a200tfbv484-2/part.json b/artix7/xc7a200tfbv484-2/part.json
new file mode 100644
index 0000000..44ab6a4
--- /dev/null
+++ b/artix7/xc7a200tfbv484-2/part.json
@@ -0,0 +1,1808 @@
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+ },
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+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56844435,
+ "iobanks": {
+ "0": "X1Y182",
+ "13": "X1Y78",
+ "14": "X1Y130",
+ "15": "X1Y182",
+ "16": "X1Y234",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tfbv484-2/part.yaml b/artix7/xc7a200tfbv484-2/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbv484-2/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
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+ 16: !<xilinx/xc7series/configuration_column>
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+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
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+ 19: !<xilinx/xc7series/configuration_column>
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+ 20: !<xilinx/xc7series/configuration_column>
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+ 21: !<xilinx/xc7series/configuration_column>
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+ 22: !<xilinx/xc7series/configuration_column>
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+ 23: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
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+ 38: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
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+ 43: !<xilinx/xc7series/configuration_column>
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+ 44: !<xilinx/xc7series/configuration_column>
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+ 47: !<xilinx/xc7series/configuration_column>
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+ 48: !<xilinx/xc7series/configuration_column>
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+ 49: !<xilinx/xc7series/configuration_column>
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+ 50: !<xilinx/xc7series/configuration_column>
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+ 51: !<xilinx/xc7series/configuration_column>
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+ 101: !<xilinx/xc7series/configuration_column>
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+ 102: !<xilinx/xc7series/configuration_column>
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+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
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+ 1: !<xilinx/xc7series/configuration_column>
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+ 2: !<xilinx/xc7series/configuration_column>
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+ 3: !<xilinx/xc7series/configuration_column>
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+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
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diff --git a/artix7/xc7a200tfbv484-2L/package_pins.csv b/artix7/xc7a200tfbv484-2L/package_pins.csv
new file mode 100644
index 0000000..4bd6953
--- /dev/null
+++ b/artix7/xc7a200tfbv484-2L/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y197,RIOB33_X105Y197,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+A6,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A8,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A10,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A13,16,IOB_X0Y230,LIOB33_X0Y229,IO_L10P_T1_16
+A14,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16
+A15,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y216,LIOB33_X0Y215,IO_L17P_T2_16
+A19,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+A20,16,IOB_X0Y217,LIOB33_X0Y217,IO_L16N_T2_16
+A21,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y136,RIOB33_X105Y135,IO_L7P_T1_34
+AA3,34,IOB_X1Y131,RIOB33_X105Y131,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y127,RIOB33_X105Y127,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y130,RIOB33_X105Y129,IO_L10P_T1_34
+AA6,34,IOB_X1Y113,RIOB33_X105Y113,IO_L18N_T2_34
+AA8,34,IOB_X1Y106,RIOB33_X105Y105,IO_L22P_T3_34
+AA9,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
+AA10,13,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_13
+AA11,13,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_13
+AA13,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
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+AA16,13,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_13
+AA18,14,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y135,RIOB33_X105Y135,IO_L7N_T1_34
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+AB3,34,IOB_X1Y134,RIOB33_X105Y133,IO_L8P_T1_34
+AB5,34,IOB_X1Y129,RIOB33_X105Y129,IO_L10N_T1_34
+AB6,34,IOB_X1Y109,RIOB33_X105Y109,IO_L20N_T3_34
+AB7,34,IOB_X1Y110,RIOB33_X105Y109,IO_L20P_T3_34
+AB8,34,IOB_X1Y105,RIOB33_X105Y105,IO_L22N_T3_34
+AB10,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AB11,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AB12,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
+AB13,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
+AB15,13,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_13
+AB16,13,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_13
+AB17,13,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_13
+AB18,14,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_D14_14
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+B1,35,IOB_X1Y198,RIOB33_X105Y197,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y195,RIOB33_X105Y195,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y9,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXP0_216
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+B8,216,IPAD_X1Y37,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXP0_216
+B10,216,IPAD_X1Y55,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXP2_216
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+D7,216,OPAD_X0Y15,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXP3_216
+D9,216,IPAD_X1Y61,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXP3_216
+D11,216,IPAD_X1Y43,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXP1_216
+D14,16,IOB_X0Y238,LIOB33_X0Y237,IO_L6P_T0_16
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+D16,16,IOB_X0Y239,LIOB33_X0Y239,IO_L5N_T0_16
+D17,16,IOB_X0Y226,LIOB33_X0Y225,IO_L12P_T1_MRCC_16
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+D20,16,IOB_X0Y212,LIOB33_X0Y211,IO_L19P_T3_16
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+E3,35,IOB_X1Y187,RIOB33_X105Y187,IO_L6N_T0_VREF_35
+E6,216,IPAD_X1Y45,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0N_216
+E10,216,IPAD_X1Y47,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1N_216
+E13,16,IOB_X0Y242,LIOB33_X0Y241,IO_L4P_T0_16
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+F4,35,IOB_X1Y199,RIOB33_SING_X105Y199,IO_0_35
+F6,216,IPAD_X1Y44,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0P_216
+F10,216,IPAD_X1Y46,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1P_216
+F13,16,IOB_X0Y248,LIOB33_X0Y247,IO_L1P_T0_16
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+F19,16,IOB_X0Y214,LIOB33_X0Y213,IO_L18P_T2_16
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+G1,35,IOB_X1Y190,RIOB33_X105Y189,IO_L5P_T0_AD13P_35
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diff --git a/artix7/xc7a200tfbv484-2L/part.json b/artix7/xc7a200tfbv484-2L/part.json
new file mode 100644
index 0000000..44ab6a4
--- /dev/null
+++ b/artix7/xc7a200tfbv484-2L/part.json
@@ -0,0 +1,1808 @@
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+ }
+}
diff --git a/artix7/xc7a200tfbv484-2L/part.yaml b/artix7/xc7a200tfbv484-2L/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbv484-2L/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
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+ frame_count: 42
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+ 2: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
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+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
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+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
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+ 105: !<xilinx/xc7series/configuration_column>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
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+ 2: !<xilinx/xc7series/configuration_column>
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+ 3: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
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diff --git a/artix7/xc7a200tfbv484-3/package_pins.csv b/artix7/xc7a200tfbv484-3/package_pins.csv
new file mode 100644
index 0000000..4bd6953
--- /dev/null
+++ b/artix7/xc7a200tfbv484-3/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y197,RIOB33_X105Y197,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+A6,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A8,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A10,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A13,16,IOB_X0Y230,LIOB33_X0Y229,IO_L10P_T1_16
+A14,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16
+A15,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y216,LIOB33_X0Y215,IO_L17P_T2_16
+A19,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+A20,16,IOB_X0Y217,LIOB33_X0Y217,IO_L16N_T2_16
+A21,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y136,RIOB33_X105Y135,IO_L7P_T1_34
+AA3,34,IOB_X1Y131,RIOB33_X105Y131,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y127,RIOB33_X105Y127,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y130,RIOB33_X105Y129,IO_L10P_T1_34
+AA6,34,IOB_X1Y113,RIOB33_X105Y113,IO_L18N_T2_34
+AA8,34,IOB_X1Y106,RIOB33_X105Y105,IO_L22P_T3_34
+AA9,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
+AA10,13,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_13
+AA11,13,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_13
+AA13,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AA14,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
+AA15,13,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_13
+AA16,13,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_13
+AA18,14,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y135,RIOB33_X105Y135,IO_L7N_T1_34
+AB2,34,IOB_X1Y133,RIOB33_X105Y133,IO_L8N_T1_34
+AB3,34,IOB_X1Y134,RIOB33_X105Y133,IO_L8P_T1_34
+AB5,34,IOB_X1Y129,RIOB33_X105Y129,IO_L10N_T1_34
+AB6,34,IOB_X1Y109,RIOB33_X105Y109,IO_L20N_T3_34
+AB7,34,IOB_X1Y110,RIOB33_X105Y109,IO_L20P_T3_34
+AB8,34,IOB_X1Y105,RIOB33_X105Y105,IO_L22N_T3_34
+AB10,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AB11,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AB12,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
+AB13,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
+AB15,13,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_13
+AB16,13,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_13
+AB17,13,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_13
+AB18,14,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_D14_14
+AB22,14,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_D15_14
+B1,35,IOB_X1Y198,RIOB33_X105Y197,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y195,RIOB33_X105Y195,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y9,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXP0_216
+B6,216,OPAD_X0Y13,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXP2_216
+B8,216,IPAD_X1Y37,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXP0_216
+B10,216,IPAD_X1Y55,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXP2_216
+B13,16,IOB_X0Y233,LIOB33_X0Y233,IO_L8N_T1_16
+B15,16,IOB_X0Y236,LIOB33_X0Y235,IO_L7P_T1_16
+B16,16,IOB_X0Y235,LIOB33_X0Y235,IO_L7N_T1_16
+B17,16,IOB_X0Y228,LIOB33_X0Y227,IO_L11P_T1_SRCC_16
+B18,16,IOB_X0Y227,LIOB33_X0Y227,IO_L11N_T1_SRCC_16
+B20,16,IOB_X0Y218,LIOB33_X0Y217,IO_L16P_T2_16
+B21,16,IOB_X0Y208,LIOB33_X0Y207,IO_L21P_T3_DQS_16
+B22,16,IOB_X0Y209,LIOB33_X0Y209,IO_L20N_T3_16
+C2,35,IOB_X1Y196,RIOB33_X105Y195,IO_L2P_T0_AD12P_35
+C5,216,OPAD_X0Y10,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPTXN1_216
+C7,216,OPAD_X0Y14,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXN3_216
+C9,216,IPAD_X1Y60,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXN3_216
+C11,216,IPAD_X1Y42,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXN1_216
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+C22,16,IOB_X0Y210,LIOB33_X0Y209,IO_L20P_T3_16
+D1,35,IOB_X1Y193,RIOB33_X105Y193,IO_L3N_T0_DQS_AD5N_35
+D2,35,IOB_X1Y191,RIOB33_X105Y191,IO_L4N_T0_35
+D5,216,OPAD_X0Y11,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPTXP1_216
+D7,216,OPAD_X0Y15,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXP3_216
+D9,216,IPAD_X1Y61,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXP3_216
+D11,216,IPAD_X1Y43,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXP1_216
+D14,16,IOB_X0Y238,LIOB33_X0Y237,IO_L6P_T0_16
+D15,16,IOB_X0Y237,LIOB33_X0Y237,IO_L6N_T0_VREF_16
+D16,16,IOB_X0Y239,LIOB33_X0Y239,IO_L5N_T0_16
+D17,16,IOB_X0Y226,LIOB33_X0Y225,IO_L12P_T1_MRCC_16
+D19,16,IOB_X0Y221,LIOB33_X0Y221,IO_L14N_T2_SRCC_16
+D20,16,IOB_X0Y212,LIOB33_X0Y211,IO_L19P_T3_16
+D21,16,IOB_X0Y203,LIOB33_X0Y203,IO_L23N_T3_16
+D22,16,IOB_X0Y205,LIOB33_X0Y205,IO_L22N_T3_16
+E1,35,IOB_X1Y194,RIOB33_X105Y193,IO_L3P_T0_DQS_AD5P_35
+E2,35,IOB_X1Y192,RIOB33_X105Y191,IO_L4P_T0_35
+E3,35,IOB_X1Y187,RIOB33_X105Y187,IO_L6N_T0_VREF_35
+E6,216,IPAD_X1Y45,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0N_216
+E10,216,IPAD_X1Y47,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1N_216
+E13,16,IOB_X0Y242,LIOB33_X0Y241,IO_L4P_T0_16
+E14,16,IOB_X0Y241,LIOB33_X0Y241,IO_L4N_T0_16
+E16,16,IOB_X0Y240,LIOB33_X0Y239,IO_L5P_T0_16
+E17,16,IOB_X0Y245,LIOB33_X0Y245,IO_L2N_T0_16
+E18,16,IOB_X0Y219,LIOB33_X0Y219,IO_L15N_T2_DQS_16
+E19,16,IOB_X0Y222,LIOB33_X0Y221,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y204,LIOB33_X0Y203,IO_L23P_T3_16
+E22,16,IOB_X0Y206,LIOB33_X0Y205,IO_L22P_T3_16
+F1,35,IOB_X1Y189,RIOB33_X105Y189,IO_L5N_T0_AD13N_35
+F3,35,IOB_X1Y188,RIOB33_X105Y187,IO_L6P_T0_35
+F4,35,IOB_X1Y199,RIOB33_SING_X105Y199,IO_0_35
+F6,216,IPAD_X1Y44,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0P_216
+F10,216,IPAD_X1Y46,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1P_216
+F13,16,IOB_X0Y248,LIOB33_X0Y247,IO_L1P_T0_16
+F14,16,IOB_X0Y247,LIOB33_X0Y247,IO_L1N_T0_16
+F15,16,IOB_X0Y249,LIOB33_SING_X0Y249,IO_0_16
+F16,16,IOB_X0Y246,LIOB33_X0Y245,IO_L2P_T0_16
+F18,16,IOB_X0Y220,LIOB33_X0Y219,IO_L15P_T2_DQS_16
+F19,16,IOB_X0Y214,LIOB33_X0Y213,IO_L18P_T2_16
+F20,16,IOB_X0Y213,LIOB33_X0Y213,IO_L18N_T2_16
+F21,16,IOB_X0Y200,LIOB33_SING_X0Y200,IO_25_16
+G1,35,IOB_X1Y190,RIOB33_X105Y189,IO_L5P_T0_AD13P_35
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+G3,35,IOB_X1Y177,RIOB33_X105Y177,IO_L11N_T1_SRCC_35
+G4,35,IOB_X1Y175,RIOB33_X105Y175,IO_L12N_T1_MRCC_35
+G13,15,IOB_X0Y197,LIOB33_X0Y197,IO_L1N_T0_AD0N_15
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+G21,16,IOB_X0Y202,LIOB33_X0Y201,IO_L24P_T3_16
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+L3,35,IOB_X1Y172,RIOB33_X105Y171,IO_L14P_T2_SRCC_35
+L4,35,IOB_X1Y163,RIOB33_X105Y163,IO_L18N_T2_35
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diff --git a/artix7/xc7a200tfbv484-3/part.json b/artix7/xc7a200tfbv484-3/part.json
new file mode 100644
index 0000000..44ab6a4
--- /dev/null
+++ b/artix7/xc7a200tfbv484-3/part.json
@@ -0,0 +1,1808 @@
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+ "16": "X1Y234",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tfbv484-3/part.yaml b/artix7/xc7a200tfbv484-3/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbv484-3/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
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+ 6: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
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+ 11: !<xilinx/xc7series/configuration_column>
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+ 12: !<xilinx/xc7series/configuration_column>
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+ 14: !<xilinx/xc7series/configuration_column>
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+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
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+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
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+ rows:
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+ 82: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 83: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 84: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 85: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 86: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 87: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 88: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 89: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 90: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 93: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 94: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 95: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 96: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 97: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 98: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 99: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 100: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a200tfbv676-1/package_pins.csv b/artix7/xc7a200tfbv676-1/package_pins.csv
new file mode 100644
index 0000000..d434221
--- /dev/null
+++ b/artix7/xc7a200tfbv676-1/package_pins.csv
@@ -0,0 +1,443 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y159,RIOB33_X105Y159,IO_L20N_T3_35
+A3,35,IOB_X1Y160,RIOB33_X105Y159,IO_L20P_T3_35
+A4,35,IOB_X1Y167,RIOB33_X105Y167,IO_L16N_T2_35
+A5,35,IOB_X1Y169,RIOB33_X105Y169,IO_L15N_T2_DQS_35
+A7,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+A9,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A11,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A13,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A17,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16
+A18,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
+A19,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16
+A20,16,IOB_X0Y219,LIOB33_X0Y219,IO_L15N_T2_DQS_16
+A22,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+A23,16,IOB_X0Y208,LIOB33_X0Y207,IO_L21P_T3_DQS_16
+A24,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+A25,16,IOB_X0Y209,LIOB33_X0Y209,IO_L20N_T3_16
+AA2,33,IOB_X1Y75,RIOB33_X105Y75,IO_L12N_T1_MRCC_33
+AA3,33,IOB_X1Y76,RIOB33_X105Y75,IO_L12P_T1_MRCC_33
+AA4,33,IOB_X1Y74,RIOB33_X105Y73,IO_L13P_T2_MRCC_33
+AA5,33,IOB_X1Y56,RIOB33_X105Y55,IO_L22P_T3_33
+AA7,33,IOB_X1Y61,RIOB33_X105Y61,IO_L19N_T3_VREF_33
+AA8,33,IOB_X1Y53,RIOB33_X105Y53,IO_L23N_T3_33
+AA11,213,IPAD_X1Y10,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1P_213
+AA13,213,IPAD_X1Y8,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0P_213
+AA15,12,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_12
+AA17,12,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_12
+AA18,12,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_12
+AA19,12,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_12
+AA20,12,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_12
+AA22,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
+AA23,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AA24,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AA25,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
+AB1,33,IOB_X1Y86,RIOB33_X105Y85,IO_L7P_T1_33
+AB2,33,IOB_X1Y78,RIOB33_X105Y77,IO_L11P_T1_SRCC_33
+AB4,33,IOB_X1Y73,RIOB33_X105Y73,IO_L13N_T2_MRCC_33
+AB5,33,IOB_X1Y55,RIOB33_X105Y55,IO_L22N_T3_33
+AB6,33,IOB_X1Y52,RIOB33_X105Y51,IO_L24P_T3_33
+AB11,213,IPAD_X1Y11,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1N_213
+AB13,213,IPAD_X1Y9,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0N_213
+AB16,12,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_12
+AB17,12,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_12
+AB19,12,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_12
+AB20,12,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_12
+AB21,12,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_12
+AB22,12,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_12
+AB24,13,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_13
+AB25,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
+AB26,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AC1,33,IOB_X1Y85,RIOB33_X105Y85,IO_L7N_T1_33
+AC2,33,IOB_X1Y77,RIOB33_X105Y77,IO_L11N_T1_SRCC_33
+AC3,33,IOB_X1Y72,RIOB33_X105Y71,IO_L14P_T2_SRCC_33
+AC4,33,IOB_X1Y64,RIOB33_X105Y63,IO_L18P_T2_33
+AC6,33,IOB_X1Y51,RIOB33_X105Y51,IO_L24N_T3_33
+AC8,213,OPAD_X0Y5,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXP2_213
+AC10,213,OPAD_X0Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPTXP0_213
+AC12,213,IPAD_X1Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXP0_213
+AC14,213,IPAD_X1Y19,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXP2_213
+AC16,12,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_12
+AC17,12,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_12
+AC18,12,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_12
+AC19,12,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_12
+AC21,12,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_12
+AC22,12,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_12
+AC23,12,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_12
+AC24,13,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_13
+AC26,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
+AD1,33,IOB_X1Y82,RIOB33_X105Y81,IO_L9P_T1_DQS_33
+AD3,33,IOB_X1Y71,RIOB33_X105Y71,IO_L14N_T2_SRCC_33
+AD4,33,IOB_X1Y63,RIOB33_X105Y63,IO_L18N_T2_33
+AD5,33,IOB_X1Y70,RIOB33_X105Y69,IO_L15P_T2_DQS_33
+AD8,213,OPAD_X0Y4,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXN2_213
+AD10,213,OPAD_X0Y0,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPTXN0_213
+AD12,213,IPAD_X1Y0,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXN0_213
+AD14,213,IPAD_X1Y18,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXN2_213
+AD17,12,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_12
+AD18,12,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_12
+AD19,12,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_12
+AD20,12,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_12
+AD21,12,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_12
+AD23,12,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_12
+AD24,12,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_VREF_12
+AD25,12,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_12
+AD26,12,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_12
+AE1,33,IOB_X1Y81,RIOB33_X105Y81,IO_L9N_T1_DQS_33
+AE2,33,IOB_X1Y80,RIOB33_X105Y79,IO_L10P_T1_33
+AE3,33,IOB_X1Y68,RIOB33_X105Y67,IO_L16P_T2_33
+AE5,33,IOB_X1Y69,RIOB33_X105Y69,IO_L15N_T2_DQS_33
+AE7,213,OPAD_X0Y7,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXP3_213
+AE9,213,OPAD_X0Y3,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXP1_213
+AE11,213,IPAD_X1Y25,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXP3_213
+AE13,213,IPAD_X1Y7,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXP1_213
+AE17,12,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_12
+AE18,12,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_12
+AE20,12,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_12
+AE21,12,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_12
+AE22,12,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_12
+AE23,12,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_12
+AE25,12,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_12
+AE26,12,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_12
+AF2,33,IOB_X1Y79,RIOB33_X105Y79,IO_L10N_T1_33
+AF3,33,IOB_X1Y67,RIOB33_X105Y67,IO_L16N_T2_33
+AF4,33,IOB_X1Y65,RIOB33_X105Y65,IO_L17N_T2_33
+AF5,33,IOB_X1Y66,RIOB33_X105Y65,IO_L17P_T2_33
+AF7,213,OPAD_X0Y6,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXN3_213
+AF9,213,OPAD_X0Y2,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXN1_213
+AF11,213,IPAD_X1Y24,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXN3_213
+AF13,213,IPAD_X1Y6,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXN1_213
+AF17,12,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_12
+AF18,12,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_12
+AF19,12,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_12
+AF20,12,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_12
+AF22,12,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_12
+AF23,12,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_12
+AF24,12,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_12
+AF25,12,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_12
+B1,35,IOB_X1Y157,RIOB33_X105Y157,IO_L21N_T3_DQS_35
+B2,35,IOB_X1Y161,RIOB33_X105Y161,IO_L19N_T3_VREF_35
+B4,35,IOB_X1Y168,RIOB33_X105Y167,IO_L16P_T2_35
+B5,35,IOB_X1Y170,RIOB33_X105Y169,IO_L15P_T2_DQS_35
+B7,216,OPAD_X0Y9,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXP0_216
+B9,216,OPAD_X0Y13,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXP2_216
+B11,216,IPAD_X1Y37,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXP0_216
+B13,216,IPAD_X1Y55,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXP2_216
+B17,16,IOB_X0Y235,LIOB33_X0Y235,IO_L7N_T1_16
+B19,16,IOB_X0Y230,LIOB33_X0Y229,IO_L10P_T1_16
+B20,16,IOB_X0Y220,LIOB33_X0Y219,IO_L15P_T2_DQS_16
+B21,16,IOB_X0Y217,LIOB33_X0Y217,IO_L16N_T2_16
+B22,16,IOB_X0Y216,LIOB33_X0Y215,IO_L17P_T2_16
+B24,16,IOB_X0Y203,LIOB33_X0Y203,IO_L23N_T3_16
+B25,16,IOB_X0Y210,LIOB33_X0Y209,IO_L20P_T3_16
+B26,16,IOB_X0Y205,LIOB33_X0Y205,IO_L22N_T3_16
+C1,35,IOB_X1Y158,RIOB33_X105Y157,IO_L21P_T3_DQS_35
+C2,35,IOB_X1Y162,RIOB33_X105Y161,IO_L19P_T3_35
+C3,35,IOB_X1Y165,RIOB33_X105Y165,IO_L17N_T2_35
+C4,35,IOB_X1Y171,RIOB33_X105Y171,IO_L14N_T2_SRCC_35
+C8,216,OPAD_X0Y10,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPTXN1_216
+C10,216,OPAD_X0Y14,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXN3_216
+C12,216,IPAD_X1Y60,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXN3_216
+C14,216,IPAD_X1Y42,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXN1_216
+C17,16,IOB_X0Y236,LIOB33_X0Y235,IO_L7P_T1_16
+C18,16,IOB_X0Y225,LIOB33_X0Y225,IO_L12N_T1_MRCC_16
+C19,16,IOB_X0Y223,LIOB33_X0Y223,IO_L13N_T2_MRCC_16
+C21,16,IOB_X0Y218,LIOB33_X0Y217,IO_L16P_T2_16
+C22,16,IOB_X0Y212,LIOB33_X0Y211,IO_L19P_T3_16
+C23,16,IOB_X0Y211,LIOB33_X0Y211,IO_L19N_T3_VREF_16
+C24,16,IOB_X0Y204,LIOB33_X0Y203,IO_L23P_T3_16
+C26,16,IOB_X0Y206,LIOB33_X0Y205,IO_L22P_T3_16
+D1,35,IOB_X1Y153,RIOB33_X105Y153,IO_L23N_T3_35
+D3,35,IOB_X1Y166,RIOB33_X105Y165,IO_L17P_T2_35
+D4,35,IOB_X1Y172,RIOB33_X105Y171,IO_L14P_T2_SRCC_35
+D5,35,IOB_X1Y173,RIOB33_X105Y173,IO_L13N_T2_MRCC_35
+D6,35,IOB_X1Y197,RIOB33_X105Y197,IO_L1N_T0_AD4N_35
+D8,216,OPAD_X0Y11,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPTXP1_216
+D10,216,OPAD_X0Y15,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXP3_216
+D12,216,IPAD_X1Y61,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXP3_216
+D14,216,IPAD_X1Y43,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXP1_216
+D16,16,IOB_X0Y233,LIOB33_X0Y233,IO_L8N_T1_16
+D18,16,IOB_X0Y226,LIOB33_X0Y225,IO_L12P_T1_MRCC_16
+D19,16,IOB_X0Y224,LIOB33_X0Y223,IO_L13P_T2_MRCC_16
+D20,16,IOB_X0Y221,LIOB33_X0Y221,IO_L14N_T2_SRCC_16
+D21,16,IOB_X0Y213,LIOB33_X0Y213,IO_L18N_T2_16
+D23,16,IOB_X0Y202,LIOB33_X0Y201,IO_L24P_T3_16
+D24,16,IOB_X0Y201,LIOB33_X0Y201,IO_L24N_T3_16
+D25,15,IOB_X0Y159,LIOB33_X0Y159,IO_L20N_T3_A19_15
+D26,15,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_A18_15
+E1,35,IOB_X1Y154,RIOB33_X105Y153,IO_L23P_T3_35
+E2,35,IOB_X1Y155,RIOB33_X105Y155,IO_L22N_T3_35
+E3,35,IOB_X1Y163,RIOB33_X105Y163,IO_L18N_T2_35
+E5,35,IOB_X1Y174,RIOB33_X105Y173,IO_L13P_T2_MRCC_35
+E6,35,IOB_X1Y198,RIOB33_X105Y197,IO_L1P_T0_AD4P_35
+E11,216,IPAD_X1Y45,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0N_216
+E13,216,IPAD_X1Y47,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1N_216
+E16,16,IOB_X0Y234,LIOB33_X0Y233,IO_L8P_T1_16
+E17,16,IOB_X0Y228,LIOB33_X0Y227,IO_L11P_T1_SRCC_16
+E18,16,IOB_X0Y227,LIOB33_X0Y227,IO_L11N_T1_SRCC_16
+E20,16,IOB_X0Y222,LIOB33_X0Y221,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y214,LIOB33_X0Y213,IO_L18P_T2_16
+E22,16,IOB_X0Y200,LIOB33_SING_X0Y200,IO_25_16
+E23,15,IOB_X0Y165,LIOB33_X0Y165,IO_L17N_T2_A25_15
+E25,15,IOB_X0Y160,LIOB33_X0Y159,IO_L20P_T3_A20_15
+E26,15,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_15
+F2,35,IOB_X1Y156,RIOB33_X105Y155,IO_L22P_T3_35
+F3,35,IOB_X1Y164,RIOB33_X105Y163,IO_L18P_T2_35
+F4,35,IOB_X1Y177,RIOB33_X105Y177,IO_L11N_T1_SRCC_35
+F5,35,IOB_X1Y175,RIOB33_X105Y175,IO_L12N_T1_MRCC_35
+F7,35,IOB_X1Y191,RIOB33_X105Y191,IO_L4N_T0_35
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diff --git a/artix7/xc7a200tfbv676-1/part.json b/artix7/xc7a200tfbv676-1/part.json
new file mode 100644
index 0000000..6b0ff28
--- /dev/null
+++ b/artix7/xc7a200tfbv676-1/part.json
@@ -0,0 +1,1811 @@
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+}
diff --git a/artix7/xc7a200tfbv676-1/part.yaml b/artix7/xc7a200tfbv676-1/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbv676-1/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
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+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
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+ 13: !<xilinx/xc7series/configuration_column>
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+ 14: !<xilinx/xc7series/configuration_column>
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+ 15: !<xilinx/xc7series/configuration_column>
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+ 16: !<xilinx/xc7series/configuration_column>
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+ 17: !<xilinx/xc7series/configuration_column>
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+ 18: !<xilinx/xc7series/configuration_column>
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+ 19: !<xilinx/xc7series/configuration_column>
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+ 20: !<xilinx/xc7series/configuration_column>
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+ 21: !<xilinx/xc7series/configuration_column>
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+ 22: !<xilinx/xc7series/configuration_column>
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+ 23: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
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+ 37: !<xilinx/xc7series/configuration_column>
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+ 38: !<xilinx/xc7series/configuration_column>
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+ 39: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
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+ 41: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
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+ 43: !<xilinx/xc7series/configuration_column>
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+ 44: !<xilinx/xc7series/configuration_column>
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+ 45: !<xilinx/xc7series/configuration_column>
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+ 46: !<xilinx/xc7series/configuration_column>
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+ 47: !<xilinx/xc7series/configuration_column>
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+ 48: !<xilinx/xc7series/configuration_column>
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+ 49: !<xilinx/xc7series/configuration_column>
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+ 50: !<xilinx/xc7series/configuration_column>
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+ 51: !<xilinx/xc7series/configuration_column>
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+ 52: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 54: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
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+ 58: !<xilinx/xc7series/configuration_column>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
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diff --git a/artix7/xc7a200tfbv676-2/package_pins.csv b/artix7/xc7a200tfbv676-2/package_pins.csv
new file mode 100644
index 0000000..d434221
--- /dev/null
+++ b/artix7/xc7a200tfbv676-2/package_pins.csv
@@ -0,0 +1,443 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y159,RIOB33_X105Y159,IO_L20N_T3_35
+A3,35,IOB_X1Y160,RIOB33_X105Y159,IO_L20P_T3_35
+A4,35,IOB_X1Y167,RIOB33_X105Y167,IO_L16N_T2_35
+A5,35,IOB_X1Y169,RIOB33_X105Y169,IO_L15N_T2_DQS_35
+A7,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+A9,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A11,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A13,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A17,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16
+A18,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
+A19,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16
+A20,16,IOB_X0Y219,LIOB33_X0Y219,IO_L15N_T2_DQS_16
+A22,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+A23,16,IOB_X0Y208,LIOB33_X0Y207,IO_L21P_T3_DQS_16
+A24,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+A25,16,IOB_X0Y209,LIOB33_X0Y209,IO_L20N_T3_16
+AA2,33,IOB_X1Y75,RIOB33_X105Y75,IO_L12N_T1_MRCC_33
+AA3,33,IOB_X1Y76,RIOB33_X105Y75,IO_L12P_T1_MRCC_33
+AA4,33,IOB_X1Y74,RIOB33_X105Y73,IO_L13P_T2_MRCC_33
+AA5,33,IOB_X1Y56,RIOB33_X105Y55,IO_L22P_T3_33
+AA7,33,IOB_X1Y61,RIOB33_X105Y61,IO_L19N_T3_VREF_33
+AA8,33,IOB_X1Y53,RIOB33_X105Y53,IO_L23N_T3_33
+AA11,213,IPAD_X1Y10,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1P_213
+AA13,213,IPAD_X1Y8,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0P_213
+AA15,12,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_12
+AA17,12,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_12
+AA18,12,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_12
+AA19,12,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_12
+AA20,12,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_12
+AA22,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
+AA23,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AA24,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AA25,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
+AB1,33,IOB_X1Y86,RIOB33_X105Y85,IO_L7P_T1_33
+AB2,33,IOB_X1Y78,RIOB33_X105Y77,IO_L11P_T1_SRCC_33
+AB4,33,IOB_X1Y73,RIOB33_X105Y73,IO_L13N_T2_MRCC_33
+AB5,33,IOB_X1Y55,RIOB33_X105Y55,IO_L22N_T3_33
+AB6,33,IOB_X1Y52,RIOB33_X105Y51,IO_L24P_T3_33
+AB11,213,IPAD_X1Y11,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1N_213
+AB13,213,IPAD_X1Y9,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0N_213
+AB16,12,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_12
+AB17,12,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_12
+AB19,12,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_12
+AB20,12,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_12
+AB21,12,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_12
+AB22,12,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_12
+AB24,13,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_13
+AB25,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
+AB26,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AC1,33,IOB_X1Y85,RIOB33_X105Y85,IO_L7N_T1_33
+AC2,33,IOB_X1Y77,RIOB33_X105Y77,IO_L11N_T1_SRCC_33
+AC3,33,IOB_X1Y72,RIOB33_X105Y71,IO_L14P_T2_SRCC_33
+AC4,33,IOB_X1Y64,RIOB33_X105Y63,IO_L18P_T2_33
+AC6,33,IOB_X1Y51,RIOB33_X105Y51,IO_L24N_T3_33
+AC8,213,OPAD_X0Y5,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXP2_213
+AC10,213,OPAD_X0Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPTXP0_213
+AC12,213,IPAD_X1Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXP0_213
+AC14,213,IPAD_X1Y19,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXP2_213
+AC16,12,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_12
+AC17,12,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_12
+AC18,12,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_12
+AC19,12,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_12
+AC21,12,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_12
+AC22,12,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_12
+AC23,12,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_12
+AC24,13,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_13
+AC26,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
+AD1,33,IOB_X1Y82,RIOB33_X105Y81,IO_L9P_T1_DQS_33
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diff --git a/artix7/xc7a200tfbv676-2/part.json b/artix7/xc7a200tfbv676-2/part.json
new file mode 100644
index 0000000..6b0ff28
--- /dev/null
+++ b/artix7/xc7a200tfbv676-2/part.json
@@ -0,0 +1,1811 @@
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+}
diff --git a/artix7/xc7a200tfbv676-2/part.yaml b/artix7/xc7a200tfbv676-2/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbv676-2/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
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+ frame_count: 42
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+ 2: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
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+ 10: !<xilinx/xc7series/configuration_column>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
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+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
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diff --git a/artix7/xc7a200tfbv676-2L/package_pins.csv b/artix7/xc7a200tfbv676-2L/package_pins.csv
new file mode 100644
index 0000000..d434221
--- /dev/null
+++ b/artix7/xc7a200tfbv676-2L/package_pins.csv
@@ -0,0 +1,443 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y159,RIOB33_X105Y159,IO_L20N_T3_35
+A3,35,IOB_X1Y160,RIOB33_X105Y159,IO_L20P_T3_35
+A4,35,IOB_X1Y167,RIOB33_X105Y167,IO_L16N_T2_35
+A5,35,IOB_X1Y169,RIOB33_X105Y169,IO_L15N_T2_DQS_35
+A7,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+A9,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A11,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A13,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A17,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16
+A18,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
+A19,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16
+A20,16,IOB_X0Y219,LIOB33_X0Y219,IO_L15N_T2_DQS_16
+A22,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+A23,16,IOB_X0Y208,LIOB33_X0Y207,IO_L21P_T3_DQS_16
+A24,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+A25,16,IOB_X0Y209,LIOB33_X0Y209,IO_L20N_T3_16
+AA2,33,IOB_X1Y75,RIOB33_X105Y75,IO_L12N_T1_MRCC_33
+AA3,33,IOB_X1Y76,RIOB33_X105Y75,IO_L12P_T1_MRCC_33
+AA4,33,IOB_X1Y74,RIOB33_X105Y73,IO_L13P_T2_MRCC_33
+AA5,33,IOB_X1Y56,RIOB33_X105Y55,IO_L22P_T3_33
+AA7,33,IOB_X1Y61,RIOB33_X105Y61,IO_L19N_T3_VREF_33
+AA8,33,IOB_X1Y53,RIOB33_X105Y53,IO_L23N_T3_33
+AA11,213,IPAD_X1Y10,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1P_213
+AA13,213,IPAD_X1Y8,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0P_213
+AA15,12,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_12
+AA17,12,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_12
+AA18,12,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_12
+AA19,12,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_12
+AA20,12,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_12
+AA22,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
+AA23,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AA24,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AA25,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
+AB1,33,IOB_X1Y86,RIOB33_X105Y85,IO_L7P_T1_33
+AB2,33,IOB_X1Y78,RIOB33_X105Y77,IO_L11P_T1_SRCC_33
+AB4,33,IOB_X1Y73,RIOB33_X105Y73,IO_L13N_T2_MRCC_33
+AB5,33,IOB_X1Y55,RIOB33_X105Y55,IO_L22N_T3_33
+AB6,33,IOB_X1Y52,RIOB33_X105Y51,IO_L24P_T3_33
+AB11,213,IPAD_X1Y11,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1N_213
+AB13,213,IPAD_X1Y9,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0N_213
+AB16,12,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_12
+AB17,12,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_12
+AB19,12,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_12
+AB20,12,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_12
+AB21,12,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_12
+AB22,12,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_12
+AB24,13,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_13
+AB25,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
+AB26,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AC1,33,IOB_X1Y85,RIOB33_X105Y85,IO_L7N_T1_33
+AC2,33,IOB_X1Y77,RIOB33_X105Y77,IO_L11N_T1_SRCC_33
+AC3,33,IOB_X1Y72,RIOB33_X105Y71,IO_L14P_T2_SRCC_33
+AC4,33,IOB_X1Y64,RIOB33_X105Y63,IO_L18P_T2_33
+AC6,33,IOB_X1Y51,RIOB33_X105Y51,IO_L24N_T3_33
+AC8,213,OPAD_X0Y5,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXP2_213
+AC10,213,OPAD_X0Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPTXP0_213
+AC12,213,IPAD_X1Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXP0_213
+AC14,213,IPAD_X1Y19,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXP2_213
+AC16,12,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_12
+AC17,12,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_12
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+AD20,12,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_12
+AD21,12,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_12
+AD23,12,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_12
+AD24,12,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_VREF_12
+AD25,12,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_12
+AD26,12,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_12
+AE1,33,IOB_X1Y81,RIOB33_X105Y81,IO_L9N_T1_DQS_33
+AE2,33,IOB_X1Y80,RIOB33_X105Y79,IO_L10P_T1_33
+AE3,33,IOB_X1Y68,RIOB33_X105Y67,IO_L16P_T2_33
+AE5,33,IOB_X1Y69,RIOB33_X105Y69,IO_L15N_T2_DQS_33
+AE7,213,OPAD_X0Y7,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXP3_213
+AE9,213,OPAD_X0Y3,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXP1_213
+AE11,213,IPAD_X1Y25,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXP3_213
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+AE17,12,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_12
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+AE22,12,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_12
+AE23,12,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_12
+AE25,12,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_12
+AE26,12,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_12
+AF2,33,IOB_X1Y79,RIOB33_X105Y79,IO_L10N_T1_33
+AF3,33,IOB_X1Y67,RIOB33_X105Y67,IO_L16N_T2_33
+AF4,33,IOB_X1Y65,RIOB33_X105Y65,IO_L17N_T2_33
+AF5,33,IOB_X1Y66,RIOB33_X105Y65,IO_L17P_T2_33
+AF7,213,OPAD_X0Y6,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXN3_213
+AF9,213,OPAD_X0Y2,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXN1_213
+AF11,213,IPAD_X1Y24,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXN3_213
+AF13,213,IPAD_X1Y6,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXN1_213
+AF17,12,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_12
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+AF19,12,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_12
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+B1,35,IOB_X1Y157,RIOB33_X105Y157,IO_L21N_T3_DQS_35
+B2,35,IOB_X1Y161,RIOB33_X105Y161,IO_L19N_T3_VREF_35
+B4,35,IOB_X1Y168,RIOB33_X105Y167,IO_L16P_T2_35
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+B7,216,OPAD_X0Y9,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXP0_216
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diff --git a/artix7/xc7a200tfbv676-2L/part.json b/artix7/xc7a200tfbv676-2L/part.json
new file mode 100644
index 0000000..6b0ff28
--- /dev/null
+++ b/artix7/xc7a200tfbv676-2L/part.json
@@ -0,0 +1,1811 @@
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+ }
+}
diff --git a/artix7/xc7a200tfbv676-2L/part.yaml b/artix7/xc7a200tfbv676-2L/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbv676-2L/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
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diff --git a/artix7/xc7a200tfbv676-3/package_pins.csv b/artix7/xc7a200tfbv676-3/package_pins.csv
new file mode 100644
index 0000000..d434221
--- /dev/null
+++ b/artix7/xc7a200tfbv676-3/package_pins.csv
@@ -0,0 +1,443 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y159,RIOB33_X105Y159,IO_L20N_T3_35
+A3,35,IOB_X1Y160,RIOB33_X105Y159,IO_L20P_T3_35
+A4,35,IOB_X1Y167,RIOB33_X105Y167,IO_L16N_T2_35
+A5,35,IOB_X1Y169,RIOB33_X105Y169,IO_L15N_T2_DQS_35
+A7,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+A9,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A11,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A13,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A17,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16
+A18,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
+A19,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16
+A20,16,IOB_X0Y219,LIOB33_X0Y219,IO_L15N_T2_DQS_16
+A22,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+A23,16,IOB_X0Y208,LIOB33_X0Y207,IO_L21P_T3_DQS_16
+A24,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+A25,16,IOB_X0Y209,LIOB33_X0Y209,IO_L20N_T3_16
+AA2,33,IOB_X1Y75,RIOB33_X105Y75,IO_L12N_T1_MRCC_33
+AA3,33,IOB_X1Y76,RIOB33_X105Y75,IO_L12P_T1_MRCC_33
+AA4,33,IOB_X1Y74,RIOB33_X105Y73,IO_L13P_T2_MRCC_33
+AA5,33,IOB_X1Y56,RIOB33_X105Y55,IO_L22P_T3_33
+AA7,33,IOB_X1Y61,RIOB33_X105Y61,IO_L19N_T3_VREF_33
+AA8,33,IOB_X1Y53,RIOB33_X105Y53,IO_L23N_T3_33
+AA11,213,IPAD_X1Y10,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1P_213
+AA13,213,IPAD_X1Y8,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0P_213
+AA15,12,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_12
+AA17,12,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_12
+AA18,12,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_12
+AA19,12,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_12
+AA20,12,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_12
+AA22,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
+AA23,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AA24,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AA25,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
+AB1,33,IOB_X1Y86,RIOB33_X105Y85,IO_L7P_T1_33
+AB2,33,IOB_X1Y78,RIOB33_X105Y77,IO_L11P_T1_SRCC_33
+AB4,33,IOB_X1Y73,RIOB33_X105Y73,IO_L13N_T2_MRCC_33
+AB5,33,IOB_X1Y55,RIOB33_X105Y55,IO_L22N_T3_33
+AB6,33,IOB_X1Y52,RIOB33_X105Y51,IO_L24P_T3_33
+AB11,213,IPAD_X1Y11,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1N_213
+AB13,213,IPAD_X1Y9,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0N_213
+AB16,12,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_12
+AB17,12,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_12
+AB19,12,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_12
+AB20,12,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_12
+AB21,12,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_12
+AB22,12,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_12
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diff --git a/artix7/xc7a200tfbv676-3/part.json b/artix7/xc7a200tfbv676-3/part.json
new file mode 100644
index 0000000..6b0ff28
--- /dev/null
+++ b/artix7/xc7a200tfbv676-3/part.json
@@ -0,0 +1,1811 @@
+{
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+ }
+ }
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+ }
+ }
+ }
+ }
+ },
+ "idcode": 56844435,
+ "iobanks": {
+ "0": "X1Y182",
+ "12": "X1Y26",
+ "13": "X1Y78",
+ "14": "X1Y130",
+ "15": "X1Y182",
+ "16": "X1Y234",
+ "33": "X263Y78",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "213": "X1Y26",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tfbv676-3/part.yaml b/artix7/xc7a200tfbv676-3/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tfbv676-3/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
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+ 24: !<xilinx/xc7series/configuration_column>
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+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
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+ 39: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
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+ 41: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
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+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
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+ 51: !<xilinx/xc7series/configuration_column>
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+ 52: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
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+ 83: !<xilinx/xc7series/configuration_column>
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+ 84: !<xilinx/xc7series/configuration_column>
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+ 85: !<xilinx/xc7series/configuration_column>
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+ 86: !<xilinx/xc7series/configuration_column>
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+ 87: !<xilinx/xc7series/configuration_column>
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+ 88: !<xilinx/xc7series/configuration_column>
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+ 89: !<xilinx/xc7series/configuration_column>
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+ 90: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
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+ 93: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 94: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 95: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 96: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 97: !<xilinx/xc7series/configuration_column>
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+ 98: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 99: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 100: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
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+ 4: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
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+ 6: !<xilinx/xc7series/configuration_column>
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+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
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+ 2: !<xilinx/xc7series/configuration_column>
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+ 105: !<xilinx/xc7series/configuration_column>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
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diff --git a/artix7/xc7a200tffg1156-2/package_pins.csv b/artix7/xc7a200tffg1156-2/package_pins.csv
new file mode 100644
index 0000000..f1d64d7
--- /dev/null
+++ b/artix7/xc7a200tffg1156-2/package_pins.csv
@@ -0,0 +1,583 @@
+pin,bank,site,tile,pin_function
+A13,116,OPAD_X1Y8,GTP_CHANNEL_0_MID_RIGHT_X167Y214,MGTPTXN0_116
+A15,116,OPAD_X1Y12,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPTXN2_116
+A17,116,OPAD_X1Y14,GTP_CHANNEL_3_MID_RIGHT_X167Y254,MGTPTXN3_116
+A19,216,OPAD_X0Y14,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXN3_216
+A21,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A23,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+AA2,34,IOB_X1Y117,RIOB33_X105Y117,IO_L16N_T2_34
+AA3,34,IOB_X1Y118,RIOB33_X105Y117,IO_L16P_T2_34
+AA4,34,IOB_X1Y123,RIOB33_X105Y123,IO_L13N_T2_MRCC_34
+AA5,34,IOB_X1Y124,RIOB33_X105Y123,IO_L13P_T2_MRCC_34
+AA7,34,IOB_X1Y111,RIOB33_X105Y111,IO_L19N_T3_VREF_34
+AA8,34,IOB_X1Y112,RIOB33_X105Y111,IO_L19P_T3_34
+AA9,34,IOB_X1Y103,RIOB33_X105Y103,IO_L23N_T3_34
+AA10,34,IOB_X1Y104,RIOB33_X105Y103,IO_L23P_T3_34
+AA24,14,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_A03_D19_14
+AA25,14,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_A02_D18_14
+AA27,14,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A08_D24_14
+AA28,14,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A07_D23_14
+AA29,14,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A05_D21_14
+AA30,14,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_14
+AA32,14,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_CSI_B_14
+AA33,14,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A15_D31_14
+AA34,14,IOB_X0Y114,LIOB33_X0Y113,IO_L18P_T2_A12_D28_14
+AB1,34,IOB_X1Y119,RIOB33_X105Y119,IO_L15N_T2_DQS_34
+AB2,34,IOB_X1Y120,RIOB33_X105Y119,IO_L15P_T2_DQS_34
+AB4,34,IOB_X1Y121,RIOB33_X105Y121,IO_L14N_T2_SRCC_34
+AB5,34,IOB_X1Y122,RIOB33_X105Y121,IO_L14P_T2_SRCC_34
+AB6,34,IOB_X1Y107,RIOB33_X105Y107,IO_L21N_T3_DQS_34
+AB7,34,IOB_X1Y108,RIOB33_X105Y107,IO_L21P_T3_DQS_34
+AB9,34,IOB_X1Y101,RIOB33_X105Y101,IO_L24N_T3_34
+AB10,34,IOB_X1Y102,RIOB33_X105Y101,IO_L24P_T3_34
+AB11,34,IOB_X1Y100,RIOB33_SING_X105Y100,IO_25_34
+AB24,14,IOB_X0Y102,LIOB33_X0Y101,IO_L24P_T3_A01_D17_14
+AB25,14,IOB_X0Y101,LIOB33_X0Y101,IO_L24N_T3_A00_D16_14
+AB26,14,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_14
+AB27,14,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_A06_D22_14
+AB29,14,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A04_D20_14
+AB30,14,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_14
+AB31,14,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_14
+AB32,14,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_14
+AB34,14,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_A11_D27_14
+AC1,34,IOB_X1Y115,RIOB33_X105Y115,IO_L17N_T2_34
+AC2,34,IOB_X1Y116,RIOB33_X105Y115,IO_L17P_T2_34
+AC3,34,IOB_X1Y113,RIOB33_X105Y113,IO_L18N_T2_34
+AC4,34,IOB_X1Y114,RIOB33_X105Y113,IO_L18P_T2_34
+AC6,34,IOB_X1Y109,RIOB33_X105Y109,IO_L20N_T3_34
+AC7,34,IOB_X1Y110,RIOB33_X105Y109,IO_L20P_T3_34
+AC8,34,IOB_X1Y105,RIOB33_X105Y105,IO_L22N_T3_34
+AC9,34,IOB_X1Y106,RIOB33_X105Y105,IO_L22P_T3_34
+AC11,33,IOB_X1Y99,RIOB33_SING_X105Y99,IO_0_33
+AC24,13,IOB_X0Y56,LIOB33_X0Y55,IO_L22P_T3_13
+AC26,13,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_13
+AC27,13,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_13
+AC28,14,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_A10_D26_14
+AC29,14,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_A09_D25_VREF_14
+AC31,14,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A14_D30_14
+AC32,14,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A13_D29_14
+AC33,14,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_RDWR_B_14
+AC34,14,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AD1,33,IOB_X1Y96,RIOB33_X105Y95,IO_L2P_T0_33
+AD3,33,IOB_X1Y80,RIOB33_X105Y79,IO_L10P_T1_33
+AD4,33,IOB_X1Y83,RIOB33_X105Y83,IO_L8N_T1_33
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+AD6,33,IOB_X1Y74,RIOB33_X105Y73,IO_L13P_T2_MRCC_33
+AD8,33,IOB_X1Y69,RIOB33_X105Y69,IO_L15N_T2_DQS_33
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+AD11,33,IOB_X1Y56,RIOB33_X105Y55,IO_L22P_T3_33
+AD23,13,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_13
+AD24,13,IOB_X0Y55,LIOB33_X0Y55,IO_L22N_T3_13
+AD25,13,IOB_X0Y52,LIOB33_X0Y51,IO_L24P_T3_13
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+AD29,13,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_13
+AD30,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
+AD31,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AD33,13,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_13
+AD34,13,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_13
+AE1,33,IOB_X1Y95,RIOB33_X105Y95,IO_L2N_T0_33
+AE2,33,IOB_X1Y92,RIOB33_X105Y91,IO_L4P_T0_33
+AE3,33,IOB_X1Y79,RIOB33_X105Y79,IO_L10N_T1_33
+AE5,33,IOB_X1Y76,RIOB33_X105Y75,IO_L12P_T1_MRCC_33
+AE6,33,IOB_X1Y73,RIOB33_X105Y73,IO_L13N_T2_MRCC_33
+AE7,33,IOB_X1Y67,RIOB33_X105Y67,IO_L16N_T2_33
+AE8,33,IOB_X1Y68,RIOB33_X105Y67,IO_L16P_T2_33
+AE10,33,IOB_X1Y51,RIOB33_X105Y51,IO_L24N_T3_33
+AE11,33,IOB_X1Y55,RIOB33_X105Y55,IO_L22N_T3_33
+AE23,13,IOB_X0Y60,LIOB33_X0Y59,IO_L20P_T3_13
+AE25,13,IOB_X0Y51,LIOB33_X0Y51,IO_L24N_T3_13
+AE26,13,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_13
+AE27,13,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_13
+AE28,13,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_13
+AE30,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AE31,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
+AE32,13,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_13
+AE33,13,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_13
+AF2,33,IOB_X1Y91,RIOB33_X105Y91,IO_L4N_T0_33
+AF3,33,IOB_X1Y90,RIOB33_X105Y89,IO_L5P_T0_33
+AF4,33,IOB_X1Y86,RIOB33_X105Y85,IO_L7P_T1_33
+AF5,33,IOB_X1Y75,RIOB33_X105Y75,IO_L12N_T1_MRCC_33
+AF7,33,IOB_X1Y72,RIOB33_X105Y71,IO_L14P_T2_SRCC_33
+AF8,33,IOB_X1Y63,RIOB33_X105Y63,IO_L18N_T2_33
+AF9,33,IOB_X1Y64,RIOB33_X105Y63,IO_L18P_T2_33
+AF10,33,IOB_X1Y50,RIOB33_SING_X105Y50,IO_25_33
+AF12,33,IOB_X1Y60,RIOB33_X105Y59,IO_L20P_T3_33
+AF23,13,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_13
+AF24,13,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_13
+AF25,13,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_13
+AF27,13,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_13
+AF28,13,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_13
+AF29,13,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_13
+AF30,13,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_13
+AF32,13,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_13
+AF33,13,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_13
+AF34,13,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_13
+AG1,33,IOB_X1Y98,RIOB33_X105Y97,IO_L1P_T0_33
+AG2,33,IOB_X1Y89,RIOB33_X105Y89,IO_L5N_T0_33
+AG4,33,IOB_X1Y85,RIOB33_X105Y85,IO_L7N_T1_33
+AG5,33,IOB_X1Y77,RIOB33_X105Y77,IO_L11N_T1_SRCC_33
+AG6,33,IOB_X1Y78,RIOB33_X105Y77,IO_L11P_T1_SRCC_33
+AG7,33,IOB_X1Y71,RIOB33_X105Y71,IO_L14N_T2_SRCC_33
+AG9,33,IOB_X1Y57,RIOB33_X105Y57,IO_L21N_T3_DQS_33
+AG10,33,IOB_X1Y58,RIOB33_X105Y57,IO_L21P_T3_DQS_33
+AG11,33,IOB_X1Y54,RIOB33_X105Y53,IO_L23P_T3_33
+AG12,33,IOB_X1Y59,RIOB33_X105Y59,IO_L20N_T3_33
+AG14,113,IPAD_X2Y8,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK0P_113
+AG16,113,IPAD_X2Y10,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK1P_113
+AG18,213,IPAD_X1Y10,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1P_213
+AG20,213,IPAD_X1Y8,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0P_213
+AG24,13,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_13
+AG25,13,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_13
+AG26,13,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_13
+AG27,13,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_13
+AG29,13,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_13
+AG30,13,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_13
+AG31,13,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_13
+AG32,13,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_13
+AG34,13,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_13
+AH1,33,IOB_X1Y97,RIOB33_X105Y97,IO_L1N_T0_33
+AH2,33,IOB_X1Y94,RIOB33_X105Y93,IO_L3P_T0_DQS_33
+AH3,33,IOB_X1Y88,RIOB33_X105Y87,IO_L6P_T0_33
+AH4,33,IOB_X1Y82,RIOB33_X105Y81,IO_L9P_T1_DQS_33
+AH6,33,IOB_X1Y65,RIOB33_X105Y65,IO_L17N_T2_33
+AH7,33,IOB_X1Y66,RIOB33_X105Y65,IO_L17P_T2_33
+AH8,33,IOB_X1Y61,RIOB33_X105Y61,IO_L19N_T3_VREF_33
+AH9,33,IOB_X1Y62,RIOB33_X105Y61,IO_L19P_T3_33
+AH11,33,IOB_X1Y53,RIOB33_X105Y53,IO_L23N_T3_33
+AH14,113,IPAD_X2Y9,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK0N_113
+AH16,113,IPAD_X2Y11,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK1N_113
+AH18,213,IPAD_X1Y11,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1N_213
+AH20,213,IPAD_X1Y9,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0N_213
+AH24,13,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_13
+AH26,13,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_VREF_13
+AH27,13,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_13
+AH28,13,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_13
+AH29,13,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_13
+AH31,13,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_13
+AH32,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
+AH33,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AH34,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
+AJ1,33,IOB_X1Y93,RIOB33_X105Y93,IO_L3N_T0_DQS_33
+AJ3,33,IOB_X1Y87,RIOB33_X105Y87,IO_L6N_T0_VREF_33
+AJ4,33,IOB_X1Y81,RIOB33_X105Y81,IO_L9N_T1_DQS_33
+AJ5,32,IOB_X1Y34,RIOB33_X105Y33,IO_L8P_T1_32
+AJ6,32,IOB_X1Y26,RIOB33_X105Y25,IO_L12P_T1_MRCC_32
+AJ8,32,IOB_X1Y20,RIOB33_X105Y19,IO_L15P_T2_DQS_32
+AJ9,32,IOB_X1Y49,RIOB33_SING_X105Y49,IO_0_32
+AJ10,32,IOB_X1Y12,RIOB33_X105Y11,IO_L19P_T3_32
+AJ11,32,IOB_X1Y4,RIOB33_X105Y3,IO_L23P_T3_32
+AJ13,113,IPAD_X2Y25,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPRXP3_113
+AJ15,113,IPAD_X2Y19,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPRXP2_113
+AJ17,113,IPAD_X2Y1,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPRXP0_113
+AJ19,213,IPAD_X1Y7,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXP1_213
+AJ21,213,IPAD_X1Y25,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXP3_213
+AJ24,12,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_12
+AJ25,12,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_12
+AJ26,12,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_12
+AJ28,12,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_12
+AJ29,12,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_12
+AJ30,12,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_12
+AJ31,12,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_12
+AJ33,12,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_12
+AJ34,12,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_12
+AK1,32,IOB_X1Y45,RIOB33_X105Y45,IO_L2N_T0_32
+AK2,32,IOB_X1Y46,RIOB33_X105Y45,IO_L2P_T0_32
+AK3,32,IOB_X1Y38,RIOB33_X105Y37,IO_L6P_T0_32
+AK5,32,IOB_X1Y33,RIOB33_X105Y33,IO_L8N_T1_32
+AK6,32,IOB_X1Y25,RIOB33_X105Y25,IO_L12N_T1_MRCC_32
+AK7,32,IOB_X1Y24,RIOB33_X105Y23,IO_L13P_T2_MRCC_32
+AK8,32,IOB_X1Y19,RIOB33_X105Y19,IO_L15N_T2_DQS_32
+AK10,32,IOB_X1Y11,RIOB33_X105Y11,IO_L19N_T3_VREF_32
+AK11,32,IOB_X1Y3,RIOB33_X105Y3,IO_L23N_T3_32
+AK13,113,IPAD_X2Y24,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPRXN3_113
+AK15,113,IPAD_X2Y18,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPRXN2_113
+AK17,113,IPAD_X2Y0,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPRXN0_113
+AK19,213,IPAD_X1Y6,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXN1_213
+AK21,213,IPAD_X1Y24,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXN3_213
+AK25,12,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_12
+AK26,12,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_12
+AK27,12,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_12
+AK28,12,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_12
+AK30,12,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_12
+AK31,12,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_12
+AK32,12,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_12
+AK33,12,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_12
+AL2,32,IOB_X1Y42,RIOB33_X105Y41,IO_L4P_T0_32
+AL3,32,IOB_X1Y37,RIOB33_X105Y37,IO_L6N_T0_VREF_32
+AL4,32,IOB_X1Y30,RIOB33_X105Y29,IO_L10P_T1_32
+AL5,32,IOB_X1Y28,RIOB33_X105Y27,IO_L11P_T1_SRCC_32
+AL7,32,IOB_X1Y23,RIOB33_X105Y23,IO_L13N_T2_MRCC_32
+AL8,32,IOB_X1Y0,RIOB33_SING_X105Y0,IO_25_32
+AL9,32,IOB_X1Y8,RIOB33_X105Y7,IO_L21P_T3_DQS_32
+AL10,32,IOB_X1Y2,RIOB33_X105Y1,IO_L24P_T3_32
+AL14,113,OPAD_X1Y5,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPTXP2_113
+AL16,113,IPAD_X2Y7,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPRXP1_113
+AL18,213,IPAD_X1Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXP0_213
+AL20,213,IPAD_X1Y19,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXP2_213
+AL22,213,OPAD_X0Y5,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXP2_213
+AL24,12,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_12
+AL25,12,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_12
+AL27,12,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_12
+AL28,12,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_12
+AL29,12,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_12
+AL30,12,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_12
+AL32,12,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_12
+AL33,12,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_12
+AL34,12,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_12
+AM1,32,IOB_X1Y41,RIOB33_X105Y41,IO_L4N_T0_32
+AM2,32,IOB_X1Y44,RIOB33_X105Y43,IO_L3P_T0_DQS_32
+AM4,32,IOB_X1Y29,RIOB33_X105Y29,IO_L10N_T1_32
+AM5,32,IOB_X1Y27,RIOB33_X105Y27,IO_L11N_T1_SRCC_32
+AM6,32,IOB_X1Y21,RIOB33_X105Y21,IO_L14N_T2_SRCC_32
+AM7,32,IOB_X1Y22,RIOB33_X105Y21,IO_L14P_T2_SRCC_32
+AM9,32,IOB_X1Y7,RIOB33_X105Y7,IO_L21N_T3_DQS_32
+AM10,32,IOB_X1Y1,RIOB33_X105Y1,IO_L24N_T3_32
+AM11,32,IOB_X1Y6,RIOB33_X105Y5,IO_L22P_T3_32
+AM14,113,OPAD_X1Y4,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPTXN2_113
+AM16,113,IPAD_X2Y6,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPRXN1_113
+AM18,213,IPAD_X1Y0,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXN0_213
+AM20,213,IPAD_X1Y18,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXN2_213
+AM22,213,OPAD_X0Y4,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXN2_213
+AM25,12,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_12
+AM26,12,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_12
+AM27,12,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_12
+AM29,12,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_12
+AM30,12,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_12
+AM31,12,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_12
+AM32,12,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_VREF_12
+AM34,12,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_12
+AN1,32,IOB_X1Y48,RIOB33_X105Y47,IO_L1P_T0_32
+AN2,32,IOB_X1Y43,RIOB33_X105Y43,IO_L3N_T0_DQS_32
+AN3,32,IOB_X1Y40,RIOB33_X105Y39,IO_L5P_T0_32
+AN4,32,IOB_X1Y36,RIOB33_X105Y35,IO_L7P_T1_32
+AN6,32,IOB_X1Y15,RIOB33_X105Y15,IO_L17N_T2_32
+AN7,32,IOB_X1Y16,RIOB33_X105Y15,IO_L17P_T2_32
+AN8,32,IOB_X1Y18,RIOB33_X105Y17,IO_L16P_T2_32
+AN9,32,IOB_X1Y14,RIOB33_X105Y13,IO_L18P_T2_32
+AN11,32,IOB_X1Y5,RIOB33_X105Y5,IO_L22N_T3_32
+AN13,113,OPAD_X1Y7,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPTXP3_113
+AN15,113,OPAD_X1Y3,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPTXP1_113
+AN17,113,OPAD_X1Y1,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPTXP0_113
+AN19,213,OPAD_X0Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPTXP0_213
+AN21,213,OPAD_X0Y3,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXP1_213
+AN23,213,OPAD_X0Y7,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXP3_213
+AN26,12,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_12
+AN27,12,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_12
+AN28,12,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_12
+AN29,12,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_12
+AN31,12,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_12
+AN32,12,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_12
+AN33,12,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_12
+AN34,12,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_12
+AP1,32,IOB_X1Y47,RIOB33_X105Y47,IO_L1N_T0_32
+AP3,32,IOB_X1Y39,RIOB33_X105Y39,IO_L5N_T0_32
+AP4,32,IOB_X1Y35,RIOB33_X105Y35,IO_L7N_T1_32
+AP5,32,IOB_X1Y31,RIOB33_X105Y31,IO_L9N_T1_DQS_32
+AP6,32,IOB_X1Y32,RIOB33_X105Y31,IO_L9P_T1_DQS_32
+AP8,32,IOB_X1Y17,RIOB33_X105Y17,IO_L16N_T2_32
+AP9,32,IOB_X1Y13,RIOB33_X105Y13,IO_L18N_T2_32
+AP10,32,IOB_X1Y9,RIOB33_X105Y9,IO_L20N_T3_32
+AP11,32,IOB_X1Y10,RIOB33_X105Y9,IO_L20P_T3_32
+AP13,113,OPAD_X1Y6,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPTXN3_113
+AP15,113,OPAD_X1Y2,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPTXN1_113
+AP17,113,OPAD_X1Y0,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPTXN0_113
+AP19,213,OPAD_X0Y0,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPTXN0_213
+AP21,213,OPAD_X0Y2,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXN1_213
+AP23,213,OPAD_X0Y6,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXN3_213
+AP25,12,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_12
+AP26,12,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_12
+AP28,12,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_12
+AP29,12,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_12
+AP30,12,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_12
+AP31,12,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_12
+AP33,12,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_12
+AP34,12,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_12
+B13,116,OPAD_X1Y9,GTP_CHANNEL_0_MID_RIGHT_X167Y214,MGTPTXP0_116
+B15,116,OPAD_X1Y13,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPTXP2_116
+B17,116,OPAD_X1Y15,GTP_CHANNEL_3_MID_RIGHT_X167Y254,MGTPTXP3_116
+B19,216,OPAD_X0Y15,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXP3_216
+B21,216,OPAD_X0Y13,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXP2_216
+B23,216,OPAD_X0Y9,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXP0_216
+C14,116,OPAD_X1Y10,GTP_CHANNEL_1_MID_RIGHT_X167Y225,MGTPTXN1_116
+C16,116,IPAD_X2Y54,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPRXN2_116
+C18,216,IPAD_X1Y60,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXN3_216
+C20,216,IPAD_X1Y42,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXN1_216
+C22,216,OPAD_X0Y10,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPTXN1_216
+D14,116,OPAD_X1Y11,GTP_CHANNEL_1_MID_RIGHT_X167Y225,MGTPTXP1_116
+D16,116,IPAD_X2Y55,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPRXP2_116
+D18,216,IPAD_X1Y61,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXP3_216
+D20,216,IPAD_X1Y43,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXP1_216
+D22,216,OPAD_X0Y11,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPTXP1_216
+E13,116,IPAD_X2Y36,GTP_CHANNEL_0_MID_RIGHT_X167Y214,MGTPRXN0_116
+E15,116,IPAD_X2Y42,GTP_CHANNEL_1_MID_RIGHT_X167Y225,MGTPRXN1_116
+E17,116,IPAD_X2Y60,GTP_CHANNEL_3_MID_RIGHT_X167Y254,MGTPRXN3_116
+E19,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+E21,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+F2,36,IOB_X1Y219,RIOB33_X105Y219,IO_L15N_T2_DQS_36
+F3,36,IOB_X1Y220,RIOB33_X105Y219,IO_L15P_T2_DQS_36
+F13,116,IPAD_X2Y37,GTP_CHANNEL_0_MID_RIGHT_X167Y214,MGTPRXP0_116
+F15,116,IPAD_X2Y43,GTP_CHANNEL_1_MID_RIGHT_X167Y225,MGTPRXP1_116
+F17,116,IPAD_X2Y61,GTP_CHANNEL_3_MID_RIGHT_X167Y254,MGTPRXP3_116
+F19,216,IPAD_X1Y55,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXP2_216
+F21,216,IPAD_X1Y37,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXP0_216
+G1,36,IOB_X1Y205,RIOB33_X105Y205,IO_L22N_T3_36
+G2,36,IOB_X1Y209,RIOB33_X105Y209,IO_L20N_T3_36
+G4,36,IOB_X1Y223,RIOB33_X105Y223,IO_L13N_T2_MRCC_36
+G5,36,IOB_X1Y224,RIOB33_X105Y223,IO_L13P_T2_MRCC_36
+G6,36,IOB_X1Y229,RIOB33_X105Y229,IO_L10N_T1_36
+G7,36,IOB_X1Y230,RIOB33_X105Y229,IO_L10P_T1_36
+G9,36,IOB_X1Y245,RIOB33_X105Y245,IO_L2N_T0_36
+G10,36,IOB_X1Y246,RIOB33_X105Y245,IO_L2P_T0_36
+G11,36,IOB_X1Y241,RIOB33_X105Y241,IO_L4N_T0_36
+G14,116,IPAD_X2Y47,GTP_COMMON_MID_RIGHT_X167Y231,MGTREFCLK1N_116
+G16,116,IPAD_X2Y45,GTP_COMMON_MID_RIGHT_X167Y231,MGTREFCLK0N_116
+G18,216,IPAD_X1Y45,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0N_216
+G20,216,IPAD_X1Y47,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1N_216
+G24,16,IOB_X0Y244,LIOB33_X0Y243,IO_L3P_T0_DQS_16
+G25,16,IOB_X0Y243,LIOB33_X0Y243,IO_L3N_T0_DQS_16
+G26,16,IOB_X0Y233,LIOB33_X0Y233,IO_L8N_T1_16
+G27,16,IOB_X0Y235,LIOB33_X0Y235,IO_L7N_T1_16
+G29,16,IOB_X0Y220,LIOB33_X0Y219,IO_L15P_T2_DQS_16
+G30,16,IOB_X0Y219,LIOB33_X0Y219,IO_L15N_T2_DQS_16
+G31,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+G32,16,IOB_X0Y211,LIOB33_X0Y211,IO_L19N_T3_VREF_16
+G34,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+H1,36,IOB_X1Y206,RIOB33_X105Y205,IO_L22P_T3_36
+H2,36,IOB_X1Y210,RIOB33_X105Y209,IO_L20P_T3_36
+H3,36,IOB_X1Y215,RIOB33_X105Y215,IO_L17N_T2_36
+H4,36,IOB_X1Y216,RIOB33_X105Y215,IO_L17P_T2_36
+H6,36,IOB_X1Y225,RIOB33_X105Y225,IO_L12N_T1_MRCC_36
+H7,36,IOB_X1Y226,RIOB33_X105Y225,IO_L12P_T1_MRCC_36
+H8,36,IOB_X1Y233,RIOB33_X105Y233,IO_L8N_T1_36
+H9,36,IOB_X1Y234,RIOB33_X105Y233,IO_L8P_T1_36
+H11,36,IOB_X1Y242,RIOB33_X105Y241,IO_L4P_T0_36
+H12,36,IOB_X1Y249,RIOB33_SING_X105Y249,IO_0_36
+H14,116,IPAD_X2Y46,GTP_COMMON_MID_RIGHT_X167Y231,MGTREFCLK1P_116
+H16,116,IPAD_X2Y44,GTP_COMMON_MID_RIGHT_X167Y231,MGTREFCLK0P_116
+H18,216,IPAD_X1Y44,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0P_216
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new file mode 100644
index 0000000..8f37c63
--- /dev/null
+++ b/artix7/xc7a200tffg1156-2/part.json
@@ -0,0 +1,1815 @@
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+ "iobanks": {
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+ "12": "X1Y26",
+ "13": "X1Y78",
+ "14": "X1Y130",
+ "15": "X1Y182",
+ "16": "X1Y234",
+ "32": "X263Y26",
+ "33": "X263Y78",
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+ "35": "X263Y182",
+ "36": "X263Y234",
+ "113": "X263Y26",
+ "116": "X263Y234",
+ "213": "X1Y26",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tffg1156-2/part.yaml b/artix7/xc7a200tffg1156-2/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tffg1156-2/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
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+ 32: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
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+ 58: !<xilinx/xc7series/configuration_column>
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+ 59: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 62: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 65: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 66: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 67: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 68: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 69: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 70: !<xilinx/xc7series/configuration_column>
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+ 71: !<xilinx/xc7series/configuration_column>
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+ 72: !<xilinx/xc7series/configuration_column>
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+ 73: !<xilinx/xc7series/configuration_column>
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+ 75: !<xilinx/xc7series/configuration_column>
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+ 76: !<xilinx/xc7series/configuration_column>
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+ 77: !<xilinx/xc7series/configuration_column>
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+ 78: !<xilinx/xc7series/configuration_column>
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+ 79: !<xilinx/xc7series/configuration_column>
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+ 80: !<xilinx/xc7series/configuration_column>
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+ 81: !<xilinx/xc7series/configuration_column>
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+ 82: !<xilinx/xc7series/configuration_column>
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+ 83: !<xilinx/xc7series/configuration_column>
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+ 84: !<xilinx/xc7series/configuration_column>
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+ 85: !<xilinx/xc7series/configuration_column>
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+ 86: !<xilinx/xc7series/configuration_column>
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+ 87: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 88: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 89: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 90: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 93: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 94: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 95: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 96: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 97: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 98: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 99: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 100: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
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+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
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+ 4: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
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+ 6: !<xilinx/xc7series/configuration_column>
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+ 7: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
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+ 10: !<xilinx/xc7series/configuration_column>
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+ 11: !<xilinx/xc7series/configuration_column>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
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diff --git a/artix7/xc7a200tffg1156-2L/package_pins.csv b/artix7/xc7a200tffg1156-2L/package_pins.csv
new file mode 100644
index 0000000..f1d64d7
--- /dev/null
+++ b/artix7/xc7a200tffg1156-2L/package_pins.csv
@@ -0,0 +1,583 @@
+pin,bank,site,tile,pin_function
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+AF4,33,IOB_X1Y86,RIOB33_X105Y85,IO_L7P_T1_33
+AF5,33,IOB_X1Y75,RIOB33_X105Y75,IO_L12N_T1_MRCC_33
+AF7,33,IOB_X1Y72,RIOB33_X105Y71,IO_L14P_T2_SRCC_33
+AF8,33,IOB_X1Y63,RIOB33_X105Y63,IO_L18N_T2_33
+AF9,33,IOB_X1Y64,RIOB33_X105Y63,IO_L18P_T2_33
+AF10,33,IOB_X1Y50,RIOB33_SING_X105Y50,IO_25_33
+AF12,33,IOB_X1Y60,RIOB33_X105Y59,IO_L20P_T3_33
+AF23,13,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_13
+AF24,13,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_13
+AF25,13,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_13
+AF27,13,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_13
+AF28,13,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_13
+AF29,13,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_13
+AF30,13,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_13
+AF32,13,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_13
+AF33,13,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_13
+AF34,13,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_13
+AG1,33,IOB_X1Y98,RIOB33_X105Y97,IO_L1P_T0_33
+AG2,33,IOB_X1Y89,RIOB33_X105Y89,IO_L5N_T0_33
+AG4,33,IOB_X1Y85,RIOB33_X105Y85,IO_L7N_T1_33
+AG5,33,IOB_X1Y77,RIOB33_X105Y77,IO_L11N_T1_SRCC_33
+AG6,33,IOB_X1Y78,RIOB33_X105Y77,IO_L11P_T1_SRCC_33
+AG7,33,IOB_X1Y71,RIOB33_X105Y71,IO_L14N_T2_SRCC_33
+AG9,33,IOB_X1Y57,RIOB33_X105Y57,IO_L21N_T3_DQS_33
+AG10,33,IOB_X1Y58,RIOB33_X105Y57,IO_L21P_T3_DQS_33
+AG11,33,IOB_X1Y54,RIOB33_X105Y53,IO_L23P_T3_33
+AG12,33,IOB_X1Y59,RIOB33_X105Y59,IO_L20N_T3_33
+AG14,113,IPAD_X2Y8,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK0P_113
+AG16,113,IPAD_X2Y10,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK1P_113
+AG18,213,IPAD_X1Y10,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1P_213
+AG20,213,IPAD_X1Y8,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0P_213
+AG24,13,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_13
+AG25,13,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_13
+AG26,13,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_13
+AG27,13,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_13
+AG29,13,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_13
+AG30,13,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_13
+AG31,13,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_13
+AG32,13,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_13
+AG34,13,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_13
+AH1,33,IOB_X1Y97,RIOB33_X105Y97,IO_L1N_T0_33
+AH2,33,IOB_X1Y94,RIOB33_X105Y93,IO_L3P_T0_DQS_33
+AH3,33,IOB_X1Y88,RIOB33_X105Y87,IO_L6P_T0_33
+AH4,33,IOB_X1Y82,RIOB33_X105Y81,IO_L9P_T1_DQS_33
+AH6,33,IOB_X1Y65,RIOB33_X105Y65,IO_L17N_T2_33
+AH7,33,IOB_X1Y66,RIOB33_X105Y65,IO_L17P_T2_33
+AH8,33,IOB_X1Y61,RIOB33_X105Y61,IO_L19N_T3_VREF_33
+AH9,33,IOB_X1Y62,RIOB33_X105Y61,IO_L19P_T3_33
+AH11,33,IOB_X1Y53,RIOB33_X105Y53,IO_L23N_T3_33
+AH14,113,IPAD_X2Y9,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK0N_113
+AH16,113,IPAD_X2Y11,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK1N_113
+AH18,213,IPAD_X1Y11,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1N_213
+AH20,213,IPAD_X1Y9,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0N_213
+AH24,13,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_13
+AH26,13,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_VREF_13
+AH27,13,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_13
+AH28,13,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_13
+AH29,13,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_13
+AH31,13,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_13
+AH32,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
+AH33,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AH34,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
+AJ1,33,IOB_X1Y93,RIOB33_X105Y93,IO_L3N_T0_DQS_33
+AJ3,33,IOB_X1Y87,RIOB33_X105Y87,IO_L6N_T0_VREF_33
+AJ4,33,IOB_X1Y81,RIOB33_X105Y81,IO_L9N_T1_DQS_33
+AJ5,32,IOB_X1Y34,RIOB33_X105Y33,IO_L8P_T1_32
+AJ6,32,IOB_X1Y26,RIOB33_X105Y25,IO_L12P_T1_MRCC_32
+AJ8,32,IOB_X1Y20,RIOB33_X105Y19,IO_L15P_T2_DQS_32
+AJ9,32,IOB_X1Y49,RIOB33_SING_X105Y49,IO_0_32
+AJ10,32,IOB_X1Y12,RIOB33_X105Y11,IO_L19P_T3_32
+AJ11,32,IOB_X1Y4,RIOB33_X105Y3,IO_L23P_T3_32
+AJ13,113,IPAD_X2Y25,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPRXP3_113
+AJ15,113,IPAD_X2Y19,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPRXP2_113
+AJ17,113,IPAD_X2Y1,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPRXP0_113
+AJ19,213,IPAD_X1Y7,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXP1_213
+AJ21,213,IPAD_X1Y25,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXP3_213
+AJ24,12,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_12
+AJ25,12,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_12
+AJ26,12,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_12
+AJ28,12,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_12
+AJ29,12,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_12
+AJ30,12,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_12
+AJ31,12,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_12
+AJ33,12,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_12
+AJ34,12,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_12
+AK1,32,IOB_X1Y45,RIOB33_X105Y45,IO_L2N_T0_32
+AK2,32,IOB_X1Y46,RIOB33_X105Y45,IO_L2P_T0_32
+AK3,32,IOB_X1Y38,RIOB33_X105Y37,IO_L6P_T0_32
+AK5,32,IOB_X1Y33,RIOB33_X105Y33,IO_L8N_T1_32
+AK6,32,IOB_X1Y25,RIOB33_X105Y25,IO_L12N_T1_MRCC_32
+AK7,32,IOB_X1Y24,RIOB33_X105Y23,IO_L13P_T2_MRCC_32
+AK8,32,IOB_X1Y19,RIOB33_X105Y19,IO_L15N_T2_DQS_32
+AK10,32,IOB_X1Y11,RIOB33_X105Y11,IO_L19N_T3_VREF_32
+AK11,32,IOB_X1Y3,RIOB33_X105Y3,IO_L23N_T3_32
+AK13,113,IPAD_X2Y24,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPRXN3_113
+AK15,113,IPAD_X2Y18,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPRXN2_113
+AK17,113,IPAD_X2Y0,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPRXN0_113
+AK19,213,IPAD_X1Y6,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXN1_213
+AK21,213,IPAD_X1Y24,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXN3_213
+AK25,12,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_12
+AK26,12,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_12
+AK27,12,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_12
+AK28,12,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_12
+AK30,12,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_12
+AK31,12,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_12
+AK32,12,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_12
+AK33,12,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_12
+AL2,32,IOB_X1Y42,RIOB33_X105Y41,IO_L4P_T0_32
+AL3,32,IOB_X1Y37,RIOB33_X105Y37,IO_L6N_T0_VREF_32
+AL4,32,IOB_X1Y30,RIOB33_X105Y29,IO_L10P_T1_32
+AL5,32,IOB_X1Y28,RIOB33_X105Y27,IO_L11P_T1_SRCC_32
+AL7,32,IOB_X1Y23,RIOB33_X105Y23,IO_L13N_T2_MRCC_32
+AL8,32,IOB_X1Y0,RIOB33_SING_X105Y0,IO_25_32
+AL9,32,IOB_X1Y8,RIOB33_X105Y7,IO_L21P_T3_DQS_32
+AL10,32,IOB_X1Y2,RIOB33_X105Y1,IO_L24P_T3_32
+AL14,113,OPAD_X1Y5,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPTXP2_113
+AL16,113,IPAD_X2Y7,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPRXP1_113
+AL18,213,IPAD_X1Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXP0_213
+AL20,213,IPAD_X1Y19,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXP2_213
+AL22,213,OPAD_X0Y5,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXP2_213
+AL24,12,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_12
+AL25,12,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_12
+AL27,12,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_12
+AL28,12,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_12
+AL29,12,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_12
+AL30,12,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_12
+AL32,12,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_12
+AL33,12,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_12
+AL34,12,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_12
+AM1,32,IOB_X1Y41,RIOB33_X105Y41,IO_L4N_T0_32
+AM2,32,IOB_X1Y44,RIOB33_X105Y43,IO_L3P_T0_DQS_32
+AM4,32,IOB_X1Y29,RIOB33_X105Y29,IO_L10N_T1_32
+AM5,32,IOB_X1Y27,RIOB33_X105Y27,IO_L11N_T1_SRCC_32
+AM6,32,IOB_X1Y21,RIOB33_X105Y21,IO_L14N_T2_SRCC_32
+AM7,32,IOB_X1Y22,RIOB33_X105Y21,IO_L14P_T2_SRCC_32
+AM9,32,IOB_X1Y7,RIOB33_X105Y7,IO_L21N_T3_DQS_32
+AM10,32,IOB_X1Y1,RIOB33_X105Y1,IO_L24N_T3_32
+AM11,32,IOB_X1Y6,RIOB33_X105Y5,IO_L22P_T3_32
+AM14,113,OPAD_X1Y4,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPTXN2_113
+AM16,113,IPAD_X2Y6,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPRXN1_113
+AM18,213,IPAD_X1Y0,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXN0_213
+AM20,213,IPAD_X1Y18,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXN2_213
+AM22,213,OPAD_X0Y4,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXN2_213
+AM25,12,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_12
+AM26,12,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_12
+AM27,12,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_12
+AM29,12,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_12
+AM30,12,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_12
+AM31,12,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_12
+AM32,12,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_VREF_12
+AM34,12,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_12
+AN1,32,IOB_X1Y48,RIOB33_X105Y47,IO_L1P_T0_32
+AN2,32,IOB_X1Y43,RIOB33_X105Y43,IO_L3N_T0_DQS_32
+AN3,32,IOB_X1Y40,RIOB33_X105Y39,IO_L5P_T0_32
+AN4,32,IOB_X1Y36,RIOB33_X105Y35,IO_L7P_T1_32
+AN6,32,IOB_X1Y15,RIOB33_X105Y15,IO_L17N_T2_32
+AN7,32,IOB_X1Y16,RIOB33_X105Y15,IO_L17P_T2_32
+AN8,32,IOB_X1Y18,RIOB33_X105Y17,IO_L16P_T2_32
+AN9,32,IOB_X1Y14,RIOB33_X105Y13,IO_L18P_T2_32
+AN11,32,IOB_X1Y5,RIOB33_X105Y5,IO_L22N_T3_32
+AN13,113,OPAD_X1Y7,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPTXP3_113
+AN15,113,OPAD_X1Y3,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPTXP1_113
+AN17,113,OPAD_X1Y1,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPTXP0_113
+AN19,213,OPAD_X0Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPTXP0_213
+AN21,213,OPAD_X0Y3,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXP1_213
+AN23,213,OPAD_X0Y7,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXP3_213
+AN26,12,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_12
+AN27,12,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_12
+AN28,12,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_12
+AN29,12,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_12
+AN31,12,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_12
+AN32,12,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_12
+AN33,12,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_12
+AN34,12,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_12
+AP1,32,IOB_X1Y47,RIOB33_X105Y47,IO_L1N_T0_32
+AP3,32,IOB_X1Y39,RIOB33_X105Y39,IO_L5N_T0_32
+AP4,32,IOB_X1Y35,RIOB33_X105Y35,IO_L7N_T1_32
+AP5,32,IOB_X1Y31,RIOB33_X105Y31,IO_L9N_T1_DQS_32
+AP6,32,IOB_X1Y32,RIOB33_X105Y31,IO_L9P_T1_DQS_32
+AP8,32,IOB_X1Y17,RIOB33_X105Y17,IO_L16N_T2_32
+AP9,32,IOB_X1Y13,RIOB33_X105Y13,IO_L18N_T2_32
+AP10,32,IOB_X1Y9,RIOB33_X105Y9,IO_L20N_T3_32
+AP11,32,IOB_X1Y10,RIOB33_X105Y9,IO_L20P_T3_32
+AP13,113,OPAD_X1Y6,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPTXN3_113
+AP15,113,OPAD_X1Y2,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPTXN1_113
+AP17,113,OPAD_X1Y0,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPTXN0_113
+AP19,213,OPAD_X0Y0,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPTXN0_213
+AP21,213,OPAD_X0Y2,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXN1_213
+AP23,213,OPAD_X0Y6,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXN3_213
+AP25,12,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_12
+AP26,12,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_12
+AP28,12,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_12
+AP29,12,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_12
+AP30,12,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_12
+AP31,12,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_12
+AP33,12,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_12
+AP34,12,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_12
+B13,116,OPAD_X1Y9,GTP_CHANNEL_0_MID_RIGHT_X167Y214,MGTPTXP0_116
+B15,116,OPAD_X1Y13,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPTXP2_116
+B17,116,OPAD_X1Y15,GTP_CHANNEL_3_MID_RIGHT_X167Y254,MGTPTXP3_116
+B19,216,OPAD_X0Y15,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXP3_216
+B21,216,OPAD_X0Y13,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXP2_216
+B23,216,OPAD_X0Y9,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXP0_216
+C14,116,OPAD_X1Y10,GTP_CHANNEL_1_MID_RIGHT_X167Y225,MGTPTXN1_116
+C16,116,IPAD_X2Y54,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPRXN2_116
+C18,216,IPAD_X1Y60,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXN3_216
+C20,216,IPAD_X1Y42,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXN1_216
+C22,216,OPAD_X0Y10,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPTXN1_216
+D14,116,OPAD_X1Y11,GTP_CHANNEL_1_MID_RIGHT_X167Y225,MGTPTXP1_116
+D16,116,IPAD_X2Y55,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPRXP2_116
+D18,216,IPAD_X1Y61,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXP3_216
+D20,216,IPAD_X1Y43,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXP1_216
+D22,216,OPAD_X0Y11,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPTXP1_216
+E13,116,IPAD_X2Y36,GTP_CHANNEL_0_MID_RIGHT_X167Y214,MGTPRXN0_116
+E15,116,IPAD_X2Y42,GTP_CHANNEL_1_MID_RIGHT_X167Y225,MGTPRXN1_116
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diff --git a/artix7/xc7a200tffg1156-2L/part.json b/artix7/xc7a200tffg1156-2L/part.json
new file mode 100644
index 0000000..8f37c63
--- /dev/null
+++ b/artix7/xc7a200tffg1156-2L/part.json
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+ "iobanks": {
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+ "12": "X1Y26",
+ "13": "X1Y78",
+ "14": "X1Y130",
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+ "36": "X263Y234",
+ "113": "X263Y26",
+ "116": "X263Y234",
+ "213": "X1Y26",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tffg1156-2L/part.yaml b/artix7/xc7a200tffg1156-2L/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tffg1156-2L/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 58: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 59: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 62: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 65: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 66: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
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diff --git a/artix7/xc7a200tffg1156-3/package_pins.csv b/artix7/xc7a200tffg1156-3/package_pins.csv
new file mode 100644
index 0000000..f1d64d7
--- /dev/null
+++ b/artix7/xc7a200tffg1156-3/package_pins.csv
@@ -0,0 +1,583 @@
+pin,bank,site,tile,pin_function
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+A23,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
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+AC34,14,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_DOUT_CSO_B_14
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+AD9,33,IOB_X1Y70,RIOB33_X105Y69,IO_L15P_T2_DQS_33
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+AE5,33,IOB_X1Y76,RIOB33_X105Y75,IO_L12P_T1_MRCC_33
+AE6,33,IOB_X1Y73,RIOB33_X105Y73,IO_L13N_T2_MRCC_33
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+AE25,13,IOB_X0Y51,LIOB33_X0Y51,IO_L24N_T3_13
+AE26,13,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_13
+AE27,13,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_13
+AE28,13,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_13
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+AF4,33,IOB_X1Y86,RIOB33_X105Y85,IO_L7P_T1_33
+AF5,33,IOB_X1Y75,RIOB33_X105Y75,IO_L12N_T1_MRCC_33
+AF7,33,IOB_X1Y72,RIOB33_X105Y71,IO_L14P_T2_SRCC_33
+AF8,33,IOB_X1Y63,RIOB33_X105Y63,IO_L18N_T2_33
+AF9,33,IOB_X1Y64,RIOB33_X105Y63,IO_L18P_T2_33
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+AF12,33,IOB_X1Y60,RIOB33_X105Y59,IO_L20P_T3_33
+AF23,13,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_13
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+AF25,13,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_13
+AF27,13,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_13
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+AF29,13,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_13
+AF30,13,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_13
+AF32,13,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_13
+AF33,13,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_13
+AF34,13,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_13
+AG1,33,IOB_X1Y98,RIOB33_X105Y97,IO_L1P_T0_33
+AG2,33,IOB_X1Y89,RIOB33_X105Y89,IO_L5N_T0_33
+AG4,33,IOB_X1Y85,RIOB33_X105Y85,IO_L7N_T1_33
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+AG6,33,IOB_X1Y78,RIOB33_X105Y77,IO_L11P_T1_SRCC_33
+AG7,33,IOB_X1Y71,RIOB33_X105Y71,IO_L14N_T2_SRCC_33
+AG9,33,IOB_X1Y57,RIOB33_X105Y57,IO_L21N_T3_DQS_33
+AG10,33,IOB_X1Y58,RIOB33_X105Y57,IO_L21P_T3_DQS_33
+AG11,33,IOB_X1Y54,RIOB33_X105Y53,IO_L23P_T3_33
+AG12,33,IOB_X1Y59,RIOB33_X105Y59,IO_L20N_T3_33
+AG14,113,IPAD_X2Y8,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK0P_113
+AG16,113,IPAD_X2Y10,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK1P_113
+AG18,213,IPAD_X1Y10,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1P_213
+AG20,213,IPAD_X1Y8,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0P_213
+AG24,13,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_13
+AG25,13,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_13
+AG26,13,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_13
+AG27,13,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_13
+AG29,13,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_13
+AG30,13,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_13
+AG31,13,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_13
+AG32,13,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_13
+AG34,13,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_13
+AH1,33,IOB_X1Y97,RIOB33_X105Y97,IO_L1N_T0_33
+AH2,33,IOB_X1Y94,RIOB33_X105Y93,IO_L3P_T0_DQS_33
+AH3,33,IOB_X1Y88,RIOB33_X105Y87,IO_L6P_T0_33
+AH4,33,IOB_X1Y82,RIOB33_X105Y81,IO_L9P_T1_DQS_33
+AH6,33,IOB_X1Y65,RIOB33_X105Y65,IO_L17N_T2_33
+AH7,33,IOB_X1Y66,RIOB33_X105Y65,IO_L17P_T2_33
+AH8,33,IOB_X1Y61,RIOB33_X105Y61,IO_L19N_T3_VREF_33
+AH9,33,IOB_X1Y62,RIOB33_X105Y61,IO_L19P_T3_33
+AH11,33,IOB_X1Y53,RIOB33_X105Y53,IO_L23N_T3_33
+AH14,113,IPAD_X2Y9,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK0N_113
+AH16,113,IPAD_X2Y11,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK1N_113
+AH18,213,IPAD_X1Y11,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1N_213
+AH20,213,IPAD_X1Y9,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0N_213
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+AH26,13,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_VREF_13
+AH27,13,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_13
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+AH29,13,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_13
+AH31,13,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_13
+AH32,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
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+AH34,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
+AJ1,33,IOB_X1Y93,RIOB33_X105Y93,IO_L3N_T0_DQS_33
+AJ3,33,IOB_X1Y87,RIOB33_X105Y87,IO_L6N_T0_VREF_33
+AJ4,33,IOB_X1Y81,RIOB33_X105Y81,IO_L9N_T1_DQS_33
+AJ5,32,IOB_X1Y34,RIOB33_X105Y33,IO_L8P_T1_32
+AJ6,32,IOB_X1Y26,RIOB33_X105Y25,IO_L12P_T1_MRCC_32
+AJ8,32,IOB_X1Y20,RIOB33_X105Y19,IO_L15P_T2_DQS_32
+AJ9,32,IOB_X1Y49,RIOB33_SING_X105Y49,IO_0_32
+AJ10,32,IOB_X1Y12,RIOB33_X105Y11,IO_L19P_T3_32
+AJ11,32,IOB_X1Y4,RIOB33_X105Y3,IO_L23P_T3_32
+AJ13,113,IPAD_X2Y25,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPRXP3_113
+AJ15,113,IPAD_X2Y19,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPRXP2_113
+AJ17,113,IPAD_X2Y1,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPRXP0_113
+AJ19,213,IPAD_X1Y7,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXP1_213
+AJ21,213,IPAD_X1Y25,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXP3_213
+AJ24,12,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_12
+AJ25,12,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_12
+AJ26,12,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_12
+AJ28,12,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_12
+AJ29,12,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_12
+AJ30,12,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_12
+AJ31,12,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_12
+AJ33,12,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_12
+AJ34,12,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_12
+AK1,32,IOB_X1Y45,RIOB33_X105Y45,IO_L2N_T0_32
+AK2,32,IOB_X1Y46,RIOB33_X105Y45,IO_L2P_T0_32
+AK3,32,IOB_X1Y38,RIOB33_X105Y37,IO_L6P_T0_32
+AK5,32,IOB_X1Y33,RIOB33_X105Y33,IO_L8N_T1_32
+AK6,32,IOB_X1Y25,RIOB33_X105Y25,IO_L12N_T1_MRCC_32
+AK7,32,IOB_X1Y24,RIOB33_X105Y23,IO_L13P_T2_MRCC_32
+AK8,32,IOB_X1Y19,RIOB33_X105Y19,IO_L15N_T2_DQS_32
+AK10,32,IOB_X1Y11,RIOB33_X105Y11,IO_L19N_T3_VREF_32
+AK11,32,IOB_X1Y3,RIOB33_X105Y3,IO_L23N_T3_32
+AK13,113,IPAD_X2Y24,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPRXN3_113
+AK15,113,IPAD_X2Y18,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPRXN2_113
+AK17,113,IPAD_X2Y0,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPRXN0_113
+AK19,213,IPAD_X1Y6,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXN1_213
+AK21,213,IPAD_X1Y24,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXN3_213
+AK25,12,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_12
+AK26,12,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_12
+AK27,12,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_12
+AK28,12,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_12
+AK30,12,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_12
+AK31,12,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_12
+AK32,12,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_12
+AK33,12,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_12
+AL2,32,IOB_X1Y42,RIOB33_X105Y41,IO_L4P_T0_32
+AL3,32,IOB_X1Y37,RIOB33_X105Y37,IO_L6N_T0_VREF_32
+AL4,32,IOB_X1Y30,RIOB33_X105Y29,IO_L10P_T1_32
+AL5,32,IOB_X1Y28,RIOB33_X105Y27,IO_L11P_T1_SRCC_32
+AL7,32,IOB_X1Y23,RIOB33_X105Y23,IO_L13N_T2_MRCC_32
+AL8,32,IOB_X1Y0,RIOB33_SING_X105Y0,IO_25_32
+AL9,32,IOB_X1Y8,RIOB33_X105Y7,IO_L21P_T3_DQS_32
+AL10,32,IOB_X1Y2,RIOB33_X105Y1,IO_L24P_T3_32
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+AL16,113,IPAD_X2Y7,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPRXP1_113
+AL18,213,IPAD_X1Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXP0_213
+AL20,213,IPAD_X1Y19,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXP2_213
+AL22,213,OPAD_X0Y5,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXP2_213
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+AL25,12,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_12
+AL27,12,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_12
+AL28,12,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_12
+AL29,12,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_12
+AL30,12,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_12
+AL32,12,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_12
+AL33,12,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_12
+AL34,12,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_12
+AM1,32,IOB_X1Y41,RIOB33_X105Y41,IO_L4N_T0_32
+AM2,32,IOB_X1Y44,RIOB33_X105Y43,IO_L3P_T0_DQS_32
+AM4,32,IOB_X1Y29,RIOB33_X105Y29,IO_L10N_T1_32
+AM5,32,IOB_X1Y27,RIOB33_X105Y27,IO_L11N_T1_SRCC_32
+AM6,32,IOB_X1Y21,RIOB33_X105Y21,IO_L14N_T2_SRCC_32
+AM7,32,IOB_X1Y22,RIOB33_X105Y21,IO_L14P_T2_SRCC_32
+AM9,32,IOB_X1Y7,RIOB33_X105Y7,IO_L21N_T3_DQS_32
+AM10,32,IOB_X1Y1,RIOB33_X105Y1,IO_L24N_T3_32
+AM11,32,IOB_X1Y6,RIOB33_X105Y5,IO_L22P_T3_32
+AM14,113,OPAD_X1Y4,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPTXN2_113
+AM16,113,IPAD_X2Y6,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPRXN1_113
+AM18,213,IPAD_X1Y0,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXN0_213
+AM20,213,IPAD_X1Y18,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXN2_213
+AM22,213,OPAD_X0Y4,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXN2_213
+AM25,12,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_12
+AM26,12,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_12
+AM27,12,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_12
+AM29,12,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_12
+AM30,12,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_12
+AM31,12,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_12
+AM32,12,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_VREF_12
+AM34,12,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_12
+AN1,32,IOB_X1Y48,RIOB33_X105Y47,IO_L1P_T0_32
+AN2,32,IOB_X1Y43,RIOB33_X105Y43,IO_L3N_T0_DQS_32
+AN3,32,IOB_X1Y40,RIOB33_X105Y39,IO_L5P_T0_32
+AN4,32,IOB_X1Y36,RIOB33_X105Y35,IO_L7P_T1_32
+AN6,32,IOB_X1Y15,RIOB33_X105Y15,IO_L17N_T2_32
+AN7,32,IOB_X1Y16,RIOB33_X105Y15,IO_L17P_T2_32
+AN8,32,IOB_X1Y18,RIOB33_X105Y17,IO_L16P_T2_32
+AN9,32,IOB_X1Y14,RIOB33_X105Y13,IO_L18P_T2_32
+AN11,32,IOB_X1Y5,RIOB33_X105Y5,IO_L22N_T3_32
+AN13,113,OPAD_X1Y7,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPTXP3_113
+AN15,113,OPAD_X1Y3,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPTXP1_113
+AN17,113,OPAD_X1Y1,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPTXP0_113
+AN19,213,OPAD_X0Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPTXP0_213
+AN21,213,OPAD_X0Y3,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXP1_213
+AN23,213,OPAD_X0Y7,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXP3_213
+AN26,12,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_12
+AN27,12,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_12
+AN28,12,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_12
+AN29,12,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_12
+AN31,12,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_12
+AN32,12,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_12
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diff --git a/artix7/xc7a200tffg1156-3/part.json b/artix7/xc7a200tffg1156-3/part.json
new file mode 100644
index 0000000..8f37c63
--- /dev/null
+++ b/artix7/xc7a200tffg1156-3/part.json
@@ -0,0 +1,1815 @@
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+ "12": "X1Y26",
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+ "36": "X263Y234",
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+ "116": "X263Y234",
+ "213": "X1Y26",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tffg1156-3/part.yaml b/artix7/xc7a200tffg1156-3/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tffg1156-3/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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diff --git a/artix7/xc7a200tffv1156-1/package_pins.csv b/artix7/xc7a200tffv1156-1/package_pins.csv
new file mode 100644
index 0000000..f1d64d7
--- /dev/null
+++ b/artix7/xc7a200tffv1156-1/package_pins.csv
@@ -0,0 +1,583 @@
+pin,bank,site,tile,pin_function
+A13,116,OPAD_X1Y8,GTP_CHANNEL_0_MID_RIGHT_X167Y214,MGTPTXN0_116
+A15,116,OPAD_X1Y12,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPTXN2_116
+A17,116,OPAD_X1Y14,GTP_CHANNEL_3_MID_RIGHT_X167Y254,MGTPTXN3_116
+A19,216,OPAD_X0Y14,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXN3_216
+A21,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A23,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+AA2,34,IOB_X1Y117,RIOB33_X105Y117,IO_L16N_T2_34
+AA3,34,IOB_X1Y118,RIOB33_X105Y117,IO_L16P_T2_34
+AA4,34,IOB_X1Y123,RIOB33_X105Y123,IO_L13N_T2_MRCC_34
+AA5,34,IOB_X1Y124,RIOB33_X105Y123,IO_L13P_T2_MRCC_34
+AA7,34,IOB_X1Y111,RIOB33_X105Y111,IO_L19N_T3_VREF_34
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+AB5,34,IOB_X1Y122,RIOB33_X105Y121,IO_L14P_T2_SRCC_34
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+AB7,34,IOB_X1Y108,RIOB33_X105Y107,IO_L21P_T3_DQS_34
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+AC9,34,IOB_X1Y106,RIOB33_X105Y105,IO_L22P_T3_34
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+AC34,14,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AD1,33,IOB_X1Y96,RIOB33_X105Y95,IO_L2P_T0_33
+AD3,33,IOB_X1Y80,RIOB33_X105Y79,IO_L10P_T1_33
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+AD6,33,IOB_X1Y74,RIOB33_X105Y73,IO_L13P_T2_MRCC_33
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+AD9,33,IOB_X1Y70,RIOB33_X105Y69,IO_L15P_T2_DQS_33
+AD10,33,IOB_X1Y52,RIOB33_X105Y51,IO_L24P_T3_33
+AD11,33,IOB_X1Y56,RIOB33_X105Y55,IO_L22P_T3_33
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+AD24,13,IOB_X0Y55,LIOB33_X0Y55,IO_L22N_T3_13
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+AD31,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AD33,13,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_13
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+AE2,33,IOB_X1Y92,RIOB33_X105Y91,IO_L4P_T0_33
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+AE6,33,IOB_X1Y73,RIOB33_X105Y73,IO_L13N_T2_MRCC_33
+AE7,33,IOB_X1Y67,RIOB33_X105Y67,IO_L16N_T2_33
+AE8,33,IOB_X1Y68,RIOB33_X105Y67,IO_L16P_T2_33
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+AE11,33,IOB_X1Y55,RIOB33_X105Y55,IO_L22N_T3_33
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+AE25,13,IOB_X0Y51,LIOB33_X0Y51,IO_L24N_T3_13
+AE26,13,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_13
+AE27,13,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_13
+AE28,13,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_13
+AE30,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AE31,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
+AE32,13,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_13
+AE33,13,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_13
+AF2,33,IOB_X1Y91,RIOB33_X105Y91,IO_L4N_T0_33
+AF3,33,IOB_X1Y90,RIOB33_X105Y89,IO_L5P_T0_33
+AF4,33,IOB_X1Y86,RIOB33_X105Y85,IO_L7P_T1_33
+AF5,33,IOB_X1Y75,RIOB33_X105Y75,IO_L12N_T1_MRCC_33
+AF7,33,IOB_X1Y72,RIOB33_X105Y71,IO_L14P_T2_SRCC_33
+AF8,33,IOB_X1Y63,RIOB33_X105Y63,IO_L18N_T2_33
+AF9,33,IOB_X1Y64,RIOB33_X105Y63,IO_L18P_T2_33
+AF10,33,IOB_X1Y50,RIOB33_SING_X105Y50,IO_25_33
+AF12,33,IOB_X1Y60,RIOB33_X105Y59,IO_L20P_T3_33
+AF23,13,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_13
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+AF25,13,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_13
+AF27,13,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_13
+AF28,13,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_13
+AF29,13,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_13
+AF30,13,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_13
+AF32,13,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_13
+AF33,13,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_13
+AF34,13,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_13
+AG1,33,IOB_X1Y98,RIOB33_X105Y97,IO_L1P_T0_33
+AG2,33,IOB_X1Y89,RIOB33_X105Y89,IO_L5N_T0_33
+AG4,33,IOB_X1Y85,RIOB33_X105Y85,IO_L7N_T1_33
+AG5,33,IOB_X1Y77,RIOB33_X105Y77,IO_L11N_T1_SRCC_33
+AG6,33,IOB_X1Y78,RIOB33_X105Y77,IO_L11P_T1_SRCC_33
+AG7,33,IOB_X1Y71,RIOB33_X105Y71,IO_L14N_T2_SRCC_33
+AG9,33,IOB_X1Y57,RIOB33_X105Y57,IO_L21N_T3_DQS_33
+AG10,33,IOB_X1Y58,RIOB33_X105Y57,IO_L21P_T3_DQS_33
+AG11,33,IOB_X1Y54,RIOB33_X105Y53,IO_L23P_T3_33
+AG12,33,IOB_X1Y59,RIOB33_X105Y59,IO_L20N_T3_33
+AG14,113,IPAD_X2Y8,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK0P_113
+AG16,113,IPAD_X2Y10,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK1P_113
+AG18,213,IPAD_X1Y10,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1P_213
+AG20,213,IPAD_X1Y8,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0P_213
+AG24,13,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_13
+AG25,13,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_13
+AG26,13,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_13
+AG27,13,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_13
+AG29,13,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_13
+AG30,13,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_13
+AG31,13,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_13
+AG32,13,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_13
+AG34,13,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_13
+AH1,33,IOB_X1Y97,RIOB33_X105Y97,IO_L1N_T0_33
+AH2,33,IOB_X1Y94,RIOB33_X105Y93,IO_L3P_T0_DQS_33
+AH3,33,IOB_X1Y88,RIOB33_X105Y87,IO_L6P_T0_33
+AH4,33,IOB_X1Y82,RIOB33_X105Y81,IO_L9P_T1_DQS_33
+AH6,33,IOB_X1Y65,RIOB33_X105Y65,IO_L17N_T2_33
+AH7,33,IOB_X1Y66,RIOB33_X105Y65,IO_L17P_T2_33
+AH8,33,IOB_X1Y61,RIOB33_X105Y61,IO_L19N_T3_VREF_33
+AH9,33,IOB_X1Y62,RIOB33_X105Y61,IO_L19P_T3_33
+AH11,33,IOB_X1Y53,RIOB33_X105Y53,IO_L23N_T3_33
+AH14,113,IPAD_X2Y9,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK0N_113
+AH16,113,IPAD_X2Y11,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK1N_113
+AH18,213,IPAD_X1Y11,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1N_213
+AH20,213,IPAD_X1Y9,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0N_213
+AH24,13,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_13
+AH26,13,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_VREF_13
+AH27,13,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_13
+AH28,13,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_13
+AH29,13,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_13
+AH31,13,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_13
+AH32,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
+AH33,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AH34,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
+AJ1,33,IOB_X1Y93,RIOB33_X105Y93,IO_L3N_T0_DQS_33
+AJ3,33,IOB_X1Y87,RIOB33_X105Y87,IO_L6N_T0_VREF_33
+AJ4,33,IOB_X1Y81,RIOB33_X105Y81,IO_L9N_T1_DQS_33
+AJ5,32,IOB_X1Y34,RIOB33_X105Y33,IO_L8P_T1_32
+AJ6,32,IOB_X1Y26,RIOB33_X105Y25,IO_L12P_T1_MRCC_32
+AJ8,32,IOB_X1Y20,RIOB33_X105Y19,IO_L15P_T2_DQS_32
+AJ9,32,IOB_X1Y49,RIOB33_SING_X105Y49,IO_0_32
+AJ10,32,IOB_X1Y12,RIOB33_X105Y11,IO_L19P_T3_32
+AJ11,32,IOB_X1Y4,RIOB33_X105Y3,IO_L23P_T3_32
+AJ13,113,IPAD_X2Y25,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPRXP3_113
+AJ15,113,IPAD_X2Y19,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPRXP2_113
+AJ17,113,IPAD_X2Y1,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPRXP0_113
+AJ19,213,IPAD_X1Y7,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXP1_213
+AJ21,213,IPAD_X1Y25,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXP3_213
+AJ24,12,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_12
+AJ25,12,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_12
+AJ26,12,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_12
+AJ28,12,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_12
+AJ29,12,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_12
+AJ30,12,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_12
+AJ31,12,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_12
+AJ33,12,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_12
+AJ34,12,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_12
+AK1,32,IOB_X1Y45,RIOB33_X105Y45,IO_L2N_T0_32
+AK2,32,IOB_X1Y46,RIOB33_X105Y45,IO_L2P_T0_32
+AK3,32,IOB_X1Y38,RIOB33_X105Y37,IO_L6P_T0_32
+AK5,32,IOB_X1Y33,RIOB33_X105Y33,IO_L8N_T1_32
+AK6,32,IOB_X1Y25,RIOB33_X105Y25,IO_L12N_T1_MRCC_32
+AK7,32,IOB_X1Y24,RIOB33_X105Y23,IO_L13P_T2_MRCC_32
+AK8,32,IOB_X1Y19,RIOB33_X105Y19,IO_L15N_T2_DQS_32
+AK10,32,IOB_X1Y11,RIOB33_X105Y11,IO_L19N_T3_VREF_32
+AK11,32,IOB_X1Y3,RIOB33_X105Y3,IO_L23N_T3_32
+AK13,113,IPAD_X2Y24,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPRXN3_113
+AK15,113,IPAD_X2Y18,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPRXN2_113
+AK17,113,IPAD_X2Y0,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPRXN0_113
+AK19,213,IPAD_X1Y6,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXN1_213
+AK21,213,IPAD_X1Y24,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXN3_213
+AK25,12,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_12
+AK26,12,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_12
+AK27,12,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_12
+AK28,12,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_12
+AK30,12,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_12
+AK31,12,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_12
+AK32,12,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_12
+AK33,12,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_12
+AL2,32,IOB_X1Y42,RIOB33_X105Y41,IO_L4P_T0_32
+AL3,32,IOB_X1Y37,RIOB33_X105Y37,IO_L6N_T0_VREF_32
+AL4,32,IOB_X1Y30,RIOB33_X105Y29,IO_L10P_T1_32
+AL5,32,IOB_X1Y28,RIOB33_X105Y27,IO_L11P_T1_SRCC_32
+AL7,32,IOB_X1Y23,RIOB33_X105Y23,IO_L13N_T2_MRCC_32
+AL8,32,IOB_X1Y0,RIOB33_SING_X105Y0,IO_25_32
+AL9,32,IOB_X1Y8,RIOB33_X105Y7,IO_L21P_T3_DQS_32
+AL10,32,IOB_X1Y2,RIOB33_X105Y1,IO_L24P_T3_32
+AL14,113,OPAD_X1Y5,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPTXP2_113
+AL16,113,IPAD_X2Y7,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPRXP1_113
+AL18,213,IPAD_X1Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXP0_213
+AL20,213,IPAD_X1Y19,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXP2_213
+AL22,213,OPAD_X0Y5,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXP2_213
+AL24,12,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_12
+AL25,12,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_12
+AL27,12,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_12
+AL28,12,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_12
+AL29,12,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_12
+AL30,12,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_12
+AL32,12,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_12
+AL33,12,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_12
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diff --git a/artix7/xc7a200tffv1156-1/part.json b/artix7/xc7a200tffv1156-1/part.json
new file mode 100644
index 0000000..8f37c63
--- /dev/null
+++ b/artix7/xc7a200tffv1156-1/part.json
@@ -0,0 +1,1815 @@
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+ "iobanks": {
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+ "12": "X1Y26",
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+ "36": "X263Y234",
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+ "116": "X263Y234",
+ "213": "X1Y26",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tffv1156-1/part.yaml b/artix7/xc7a200tffv1156-1/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tffv1156-1/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ 5: !<xilinx/xc7series/configuration_column>
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+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
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+ 11: !<xilinx/xc7series/configuration_column>
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+ 12: !<xilinx/xc7series/configuration_column>
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+ 13: !<xilinx/xc7series/configuration_column>
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+ 14: !<xilinx/xc7series/configuration_column>
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+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
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+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
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+ rows:
+ 0: !<xilinx/xc7series/row>
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+ 77: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 78: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 79: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 80: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 81: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 82: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 83: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 84: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 85: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 86: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 87: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 88: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 89: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 90: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 93: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 94: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 95: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 96: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 97: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 98: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 99: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 100: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a200tffv1156-2/package_pins.csv b/artix7/xc7a200tffv1156-2/package_pins.csv
new file mode 100644
index 0000000..f1d64d7
--- /dev/null
+++ b/artix7/xc7a200tffv1156-2/package_pins.csv
@@ -0,0 +1,583 @@
+pin,bank,site,tile,pin_function
+A13,116,OPAD_X1Y8,GTP_CHANNEL_0_MID_RIGHT_X167Y214,MGTPTXN0_116
+A15,116,OPAD_X1Y12,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPTXN2_116
+A17,116,OPAD_X1Y14,GTP_CHANNEL_3_MID_RIGHT_X167Y254,MGTPTXN3_116
+A19,216,OPAD_X0Y14,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXN3_216
+A21,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A23,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+AA2,34,IOB_X1Y117,RIOB33_X105Y117,IO_L16N_T2_34
+AA3,34,IOB_X1Y118,RIOB33_X105Y117,IO_L16P_T2_34
+AA4,34,IOB_X1Y123,RIOB33_X105Y123,IO_L13N_T2_MRCC_34
+AA5,34,IOB_X1Y124,RIOB33_X105Y123,IO_L13P_T2_MRCC_34
+AA7,34,IOB_X1Y111,RIOB33_X105Y111,IO_L19N_T3_VREF_34
+AA8,34,IOB_X1Y112,RIOB33_X105Y111,IO_L19P_T3_34
+AA9,34,IOB_X1Y103,RIOB33_X105Y103,IO_L23N_T3_34
+AA10,34,IOB_X1Y104,RIOB33_X105Y103,IO_L23P_T3_34
+AA24,14,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_A03_D19_14
+AA25,14,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_A02_D18_14
+AA27,14,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A08_D24_14
+AA28,14,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A07_D23_14
+AA29,14,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A05_D21_14
+AA30,14,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_14
+AA32,14,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_CSI_B_14
+AA33,14,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A15_D31_14
+AA34,14,IOB_X0Y114,LIOB33_X0Y113,IO_L18P_T2_A12_D28_14
+AB1,34,IOB_X1Y119,RIOB33_X105Y119,IO_L15N_T2_DQS_34
+AB2,34,IOB_X1Y120,RIOB33_X105Y119,IO_L15P_T2_DQS_34
+AB4,34,IOB_X1Y121,RIOB33_X105Y121,IO_L14N_T2_SRCC_34
+AB5,34,IOB_X1Y122,RIOB33_X105Y121,IO_L14P_T2_SRCC_34
+AB6,34,IOB_X1Y107,RIOB33_X105Y107,IO_L21N_T3_DQS_34
+AB7,34,IOB_X1Y108,RIOB33_X105Y107,IO_L21P_T3_DQS_34
+AB9,34,IOB_X1Y101,RIOB33_X105Y101,IO_L24N_T3_34
+AB10,34,IOB_X1Y102,RIOB33_X105Y101,IO_L24P_T3_34
+AB11,34,IOB_X1Y100,RIOB33_SING_X105Y100,IO_25_34
+AB24,14,IOB_X0Y102,LIOB33_X0Y101,IO_L24P_T3_A01_D17_14
+AB25,14,IOB_X0Y101,LIOB33_X0Y101,IO_L24N_T3_A00_D16_14
+AB26,14,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_14
+AB27,14,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_A06_D22_14
+AB29,14,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A04_D20_14
+AB30,14,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_14
+AB31,14,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_14
+AB32,14,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_14
+AB34,14,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_A11_D27_14
+AC1,34,IOB_X1Y115,RIOB33_X105Y115,IO_L17N_T2_34
+AC2,34,IOB_X1Y116,RIOB33_X105Y115,IO_L17P_T2_34
+AC3,34,IOB_X1Y113,RIOB33_X105Y113,IO_L18N_T2_34
+AC4,34,IOB_X1Y114,RIOB33_X105Y113,IO_L18P_T2_34
+AC6,34,IOB_X1Y109,RIOB33_X105Y109,IO_L20N_T3_34
+AC7,34,IOB_X1Y110,RIOB33_X105Y109,IO_L20P_T3_34
+AC8,34,IOB_X1Y105,RIOB33_X105Y105,IO_L22N_T3_34
+AC9,34,IOB_X1Y106,RIOB33_X105Y105,IO_L22P_T3_34
+AC11,33,IOB_X1Y99,RIOB33_SING_X105Y99,IO_0_33
+AC24,13,IOB_X0Y56,LIOB33_X0Y55,IO_L22P_T3_13
+AC26,13,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_13
+AC27,13,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_13
+AC28,14,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_A10_D26_14
+AC29,14,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_A09_D25_VREF_14
+AC31,14,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A14_D30_14
+AC32,14,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A13_D29_14
+AC33,14,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_RDWR_B_14
+AC34,14,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AD1,33,IOB_X1Y96,RIOB33_X105Y95,IO_L2P_T0_33
+AD3,33,IOB_X1Y80,RIOB33_X105Y79,IO_L10P_T1_33
+AD4,33,IOB_X1Y83,RIOB33_X105Y83,IO_L8N_T1_33
+AD5,33,IOB_X1Y84,RIOB33_X105Y83,IO_L8P_T1_33
+AD6,33,IOB_X1Y74,RIOB33_X105Y73,IO_L13P_T2_MRCC_33
+AD8,33,IOB_X1Y69,RIOB33_X105Y69,IO_L15N_T2_DQS_33
+AD9,33,IOB_X1Y70,RIOB33_X105Y69,IO_L15P_T2_DQS_33
+AD10,33,IOB_X1Y52,RIOB33_X105Y51,IO_L24P_T3_33
+AD11,33,IOB_X1Y56,RIOB33_X105Y55,IO_L22P_T3_33
+AD23,13,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_13
+AD24,13,IOB_X0Y55,LIOB33_X0Y55,IO_L22N_T3_13
+AD25,13,IOB_X0Y52,LIOB33_X0Y51,IO_L24P_T3_13
+AD26,13,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_13
+AD28,13,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_13
+AD29,13,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_13
+AD30,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
+AD31,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AD33,13,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_13
+AD34,13,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_13
+AE1,33,IOB_X1Y95,RIOB33_X105Y95,IO_L2N_T0_33
+AE2,33,IOB_X1Y92,RIOB33_X105Y91,IO_L4P_T0_33
+AE3,33,IOB_X1Y79,RIOB33_X105Y79,IO_L10N_T1_33
+AE5,33,IOB_X1Y76,RIOB33_X105Y75,IO_L12P_T1_MRCC_33
+AE6,33,IOB_X1Y73,RIOB33_X105Y73,IO_L13N_T2_MRCC_33
+AE7,33,IOB_X1Y67,RIOB33_X105Y67,IO_L16N_T2_33
+AE8,33,IOB_X1Y68,RIOB33_X105Y67,IO_L16P_T2_33
+AE10,33,IOB_X1Y51,RIOB33_X105Y51,IO_L24N_T3_33
+AE11,33,IOB_X1Y55,RIOB33_X105Y55,IO_L22N_T3_33
+AE23,13,IOB_X0Y60,LIOB33_X0Y59,IO_L20P_T3_13
+AE25,13,IOB_X0Y51,LIOB33_X0Y51,IO_L24N_T3_13
+AE26,13,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_13
+AE27,13,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_13
+AE28,13,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_13
+AE30,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AE31,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
+AE32,13,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_13
+AE33,13,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_13
+AF2,33,IOB_X1Y91,RIOB33_X105Y91,IO_L4N_T0_33
+AF3,33,IOB_X1Y90,RIOB33_X105Y89,IO_L5P_T0_33
+AF4,33,IOB_X1Y86,RIOB33_X105Y85,IO_L7P_T1_33
+AF5,33,IOB_X1Y75,RIOB33_X105Y75,IO_L12N_T1_MRCC_33
+AF7,33,IOB_X1Y72,RIOB33_X105Y71,IO_L14P_T2_SRCC_33
+AF8,33,IOB_X1Y63,RIOB33_X105Y63,IO_L18N_T2_33
+AF9,33,IOB_X1Y64,RIOB33_X105Y63,IO_L18P_T2_33
+AF10,33,IOB_X1Y50,RIOB33_SING_X105Y50,IO_25_33
+AF12,33,IOB_X1Y60,RIOB33_X105Y59,IO_L20P_T3_33
+AF23,13,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_13
+AF24,13,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_13
+AF25,13,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_13
+AF27,13,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_13
+AF28,13,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_13
+AF29,13,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_13
+AF30,13,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_13
+AF32,13,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_13
+AF33,13,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_13
+AF34,13,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_13
+AG1,33,IOB_X1Y98,RIOB33_X105Y97,IO_L1P_T0_33
+AG2,33,IOB_X1Y89,RIOB33_X105Y89,IO_L5N_T0_33
+AG4,33,IOB_X1Y85,RIOB33_X105Y85,IO_L7N_T1_33
+AG5,33,IOB_X1Y77,RIOB33_X105Y77,IO_L11N_T1_SRCC_33
+AG6,33,IOB_X1Y78,RIOB33_X105Y77,IO_L11P_T1_SRCC_33
+AG7,33,IOB_X1Y71,RIOB33_X105Y71,IO_L14N_T2_SRCC_33
+AG9,33,IOB_X1Y57,RIOB33_X105Y57,IO_L21N_T3_DQS_33
+AG10,33,IOB_X1Y58,RIOB33_X105Y57,IO_L21P_T3_DQS_33
+AG11,33,IOB_X1Y54,RIOB33_X105Y53,IO_L23P_T3_33
+AG12,33,IOB_X1Y59,RIOB33_X105Y59,IO_L20N_T3_33
+AG14,113,IPAD_X2Y8,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK0P_113
+AG16,113,IPAD_X2Y10,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK1P_113
+AG18,213,IPAD_X1Y10,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1P_213
+AG20,213,IPAD_X1Y8,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0P_213
+AG24,13,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_13
+AG25,13,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_13
+AG26,13,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_13
+AG27,13,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_13
+AG29,13,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_13
+AG30,13,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_13
+AG31,13,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_13
+AG32,13,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_13
+AG34,13,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_13
+AH1,33,IOB_X1Y97,RIOB33_X105Y97,IO_L1N_T0_33
+AH2,33,IOB_X1Y94,RIOB33_X105Y93,IO_L3P_T0_DQS_33
+AH3,33,IOB_X1Y88,RIOB33_X105Y87,IO_L6P_T0_33
+AH4,33,IOB_X1Y82,RIOB33_X105Y81,IO_L9P_T1_DQS_33
+AH6,33,IOB_X1Y65,RIOB33_X105Y65,IO_L17N_T2_33
+AH7,33,IOB_X1Y66,RIOB33_X105Y65,IO_L17P_T2_33
+AH8,33,IOB_X1Y61,RIOB33_X105Y61,IO_L19N_T3_VREF_33
+AH9,33,IOB_X1Y62,RIOB33_X105Y61,IO_L19P_T3_33
+AH11,33,IOB_X1Y53,RIOB33_X105Y53,IO_L23N_T3_33
+AH14,113,IPAD_X2Y9,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK0N_113
+AH16,113,IPAD_X2Y11,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK1N_113
+AH18,213,IPAD_X1Y11,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1N_213
+AH20,213,IPAD_X1Y9,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0N_213
+AH24,13,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_13
+AH26,13,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_VREF_13
+AH27,13,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_13
+AH28,13,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_13
+AH29,13,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_13
+AH31,13,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_13
+AH32,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
+AH33,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AH34,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
+AJ1,33,IOB_X1Y93,RIOB33_X105Y93,IO_L3N_T0_DQS_33
+AJ3,33,IOB_X1Y87,RIOB33_X105Y87,IO_L6N_T0_VREF_33
+AJ4,33,IOB_X1Y81,RIOB33_X105Y81,IO_L9N_T1_DQS_33
+AJ5,32,IOB_X1Y34,RIOB33_X105Y33,IO_L8P_T1_32
+AJ6,32,IOB_X1Y26,RIOB33_X105Y25,IO_L12P_T1_MRCC_32
+AJ8,32,IOB_X1Y20,RIOB33_X105Y19,IO_L15P_T2_DQS_32
+AJ9,32,IOB_X1Y49,RIOB33_SING_X105Y49,IO_0_32
+AJ10,32,IOB_X1Y12,RIOB33_X105Y11,IO_L19P_T3_32
+AJ11,32,IOB_X1Y4,RIOB33_X105Y3,IO_L23P_T3_32
+AJ13,113,IPAD_X2Y25,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPRXP3_113
+AJ15,113,IPAD_X2Y19,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPRXP2_113
+AJ17,113,IPAD_X2Y1,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPRXP0_113
+AJ19,213,IPAD_X1Y7,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXP1_213
+AJ21,213,IPAD_X1Y25,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXP3_213
+AJ24,12,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_12
+AJ25,12,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_12
+AJ26,12,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_12
+AJ28,12,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_12
+AJ29,12,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_12
+AJ30,12,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_12
+AJ31,12,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_12
+AJ33,12,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_12
+AJ34,12,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_12
+AK1,32,IOB_X1Y45,RIOB33_X105Y45,IO_L2N_T0_32
+AK2,32,IOB_X1Y46,RIOB33_X105Y45,IO_L2P_T0_32
+AK3,32,IOB_X1Y38,RIOB33_X105Y37,IO_L6P_T0_32
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diff --git a/artix7/xc7a200tffv1156-2/part.json b/artix7/xc7a200tffv1156-2/part.json
new file mode 100644
index 0000000..8f37c63
--- /dev/null
+++ b/artix7/xc7a200tffv1156-2/part.json
@@ -0,0 +1,1815 @@
+{
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+ "frame_count": 128
+ },
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+ },
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+ }
+ }
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+ "CLB_IO_CLK": {
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+ },
+ "1": {
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+ },
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+ },
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+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56844435,
+ "iobanks": {
+ "0": "X1Y182",
+ "12": "X1Y26",
+ "13": "X1Y78",
+ "14": "X1Y130",
+ "15": "X1Y182",
+ "16": "X1Y234",
+ "32": "X263Y26",
+ "33": "X263Y78",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "36": "X263Y234",
+ "113": "X263Y26",
+ "116": "X263Y234",
+ "213": "X1Y26",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tffv1156-2/part.yaml b/artix7/xc7a200tffv1156-2/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tffv1156-2/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
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+ 52: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
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+ frame_count: 36
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+ 79: !<xilinx/xc7series/configuration_column>
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+ 81: !<xilinx/xc7series/configuration_column>
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+ 82: !<xilinx/xc7series/configuration_column>
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+ 83: !<xilinx/xc7series/configuration_column>
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+ 84: !<xilinx/xc7series/configuration_column>
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+ 85: !<xilinx/xc7series/configuration_column>
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+ 86: !<xilinx/xc7series/configuration_column>
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+ 87: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 88: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 89: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 90: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 93: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 94: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 95: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 96: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 97: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 98: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 99: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 100: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
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+ 105: !<xilinx/xc7series/configuration_column>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
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diff --git a/artix7/xc7a200tffv1156-2L/package_pins.csv b/artix7/xc7a200tffv1156-2L/package_pins.csv
new file mode 100644
index 0000000..f1d64d7
--- /dev/null
+++ b/artix7/xc7a200tffv1156-2L/package_pins.csv
@@ -0,0 +1,583 @@
+pin,bank,site,tile,pin_function
+A13,116,OPAD_X1Y8,GTP_CHANNEL_0_MID_RIGHT_X167Y214,MGTPTXN0_116
+A15,116,OPAD_X1Y12,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPTXN2_116
+A17,116,OPAD_X1Y14,GTP_CHANNEL_3_MID_RIGHT_X167Y254,MGTPTXN3_116
+A19,216,OPAD_X0Y14,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXN3_216
+A21,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A23,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+AA2,34,IOB_X1Y117,RIOB33_X105Y117,IO_L16N_T2_34
+AA3,34,IOB_X1Y118,RIOB33_X105Y117,IO_L16P_T2_34
+AA4,34,IOB_X1Y123,RIOB33_X105Y123,IO_L13N_T2_MRCC_34
+AA5,34,IOB_X1Y124,RIOB33_X105Y123,IO_L13P_T2_MRCC_34
+AA7,34,IOB_X1Y111,RIOB33_X105Y111,IO_L19N_T3_VREF_34
+AA8,34,IOB_X1Y112,RIOB33_X105Y111,IO_L19P_T3_34
+AA9,34,IOB_X1Y103,RIOB33_X105Y103,IO_L23N_T3_34
+AA10,34,IOB_X1Y104,RIOB33_X105Y103,IO_L23P_T3_34
+AA24,14,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_A03_D19_14
+AA25,14,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_A02_D18_14
+AA27,14,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A08_D24_14
+AA28,14,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A07_D23_14
+AA29,14,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A05_D21_14
+AA30,14,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_14
+AA32,14,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_CSI_B_14
+AA33,14,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A15_D31_14
+AA34,14,IOB_X0Y114,LIOB33_X0Y113,IO_L18P_T2_A12_D28_14
+AB1,34,IOB_X1Y119,RIOB33_X105Y119,IO_L15N_T2_DQS_34
+AB2,34,IOB_X1Y120,RIOB33_X105Y119,IO_L15P_T2_DQS_34
+AB4,34,IOB_X1Y121,RIOB33_X105Y121,IO_L14N_T2_SRCC_34
+AB5,34,IOB_X1Y122,RIOB33_X105Y121,IO_L14P_T2_SRCC_34
+AB6,34,IOB_X1Y107,RIOB33_X105Y107,IO_L21N_T3_DQS_34
+AB7,34,IOB_X1Y108,RIOB33_X105Y107,IO_L21P_T3_DQS_34
+AB9,34,IOB_X1Y101,RIOB33_X105Y101,IO_L24N_T3_34
+AB10,34,IOB_X1Y102,RIOB33_X105Y101,IO_L24P_T3_34
+AB11,34,IOB_X1Y100,RIOB33_SING_X105Y100,IO_25_34
+AB24,14,IOB_X0Y102,LIOB33_X0Y101,IO_L24P_T3_A01_D17_14
+AB25,14,IOB_X0Y101,LIOB33_X0Y101,IO_L24N_T3_A00_D16_14
+AB26,14,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_14
+AB27,14,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_A06_D22_14
+AB29,14,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A04_D20_14
+AB30,14,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_14
+AB31,14,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_14
+AB32,14,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_14
+AB34,14,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_A11_D27_14
+AC1,34,IOB_X1Y115,RIOB33_X105Y115,IO_L17N_T2_34
+AC2,34,IOB_X1Y116,RIOB33_X105Y115,IO_L17P_T2_34
+AC3,34,IOB_X1Y113,RIOB33_X105Y113,IO_L18N_T2_34
+AC4,34,IOB_X1Y114,RIOB33_X105Y113,IO_L18P_T2_34
+AC6,34,IOB_X1Y109,RIOB33_X105Y109,IO_L20N_T3_34
+AC7,34,IOB_X1Y110,RIOB33_X105Y109,IO_L20P_T3_34
+AC8,34,IOB_X1Y105,RIOB33_X105Y105,IO_L22N_T3_34
+AC9,34,IOB_X1Y106,RIOB33_X105Y105,IO_L22P_T3_34
+AC11,33,IOB_X1Y99,RIOB33_SING_X105Y99,IO_0_33
+AC24,13,IOB_X0Y56,LIOB33_X0Y55,IO_L22P_T3_13
+AC26,13,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_13
+AC27,13,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_13
+AC28,14,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_A10_D26_14
+AC29,14,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_A09_D25_VREF_14
+AC31,14,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A14_D30_14
+AC32,14,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A13_D29_14
+AC33,14,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_RDWR_B_14
+AC34,14,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AD1,33,IOB_X1Y96,RIOB33_X105Y95,IO_L2P_T0_33
+AD3,33,IOB_X1Y80,RIOB33_X105Y79,IO_L10P_T1_33
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+AD8,33,IOB_X1Y69,RIOB33_X105Y69,IO_L15N_T2_DQS_33
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+AD11,33,IOB_X1Y56,RIOB33_X105Y55,IO_L22P_T3_33
+AD23,13,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_13
+AD24,13,IOB_X0Y55,LIOB33_X0Y55,IO_L22N_T3_13
+AD25,13,IOB_X0Y52,LIOB33_X0Y51,IO_L24P_T3_13
+AD26,13,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_13
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+AD29,13,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_13
+AD30,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
+AD31,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AD33,13,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_13
+AD34,13,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_13
+AE1,33,IOB_X1Y95,RIOB33_X105Y95,IO_L2N_T0_33
+AE2,33,IOB_X1Y92,RIOB33_X105Y91,IO_L4P_T0_33
+AE3,33,IOB_X1Y79,RIOB33_X105Y79,IO_L10N_T1_33
+AE5,33,IOB_X1Y76,RIOB33_X105Y75,IO_L12P_T1_MRCC_33
+AE6,33,IOB_X1Y73,RIOB33_X105Y73,IO_L13N_T2_MRCC_33
+AE7,33,IOB_X1Y67,RIOB33_X105Y67,IO_L16N_T2_33
+AE8,33,IOB_X1Y68,RIOB33_X105Y67,IO_L16P_T2_33
+AE10,33,IOB_X1Y51,RIOB33_X105Y51,IO_L24N_T3_33
+AE11,33,IOB_X1Y55,RIOB33_X105Y55,IO_L22N_T3_33
+AE23,13,IOB_X0Y60,LIOB33_X0Y59,IO_L20P_T3_13
+AE25,13,IOB_X0Y51,LIOB33_X0Y51,IO_L24N_T3_13
+AE26,13,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_13
+AE27,13,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_13
+AE28,13,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_13
+AE30,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AE31,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
+AE32,13,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_13
+AE33,13,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_13
+AF2,33,IOB_X1Y91,RIOB33_X105Y91,IO_L4N_T0_33
+AF3,33,IOB_X1Y90,RIOB33_X105Y89,IO_L5P_T0_33
+AF4,33,IOB_X1Y86,RIOB33_X105Y85,IO_L7P_T1_33
+AF5,33,IOB_X1Y75,RIOB33_X105Y75,IO_L12N_T1_MRCC_33
+AF7,33,IOB_X1Y72,RIOB33_X105Y71,IO_L14P_T2_SRCC_33
+AF8,33,IOB_X1Y63,RIOB33_X105Y63,IO_L18N_T2_33
+AF9,33,IOB_X1Y64,RIOB33_X105Y63,IO_L18P_T2_33
+AF10,33,IOB_X1Y50,RIOB33_SING_X105Y50,IO_25_33
+AF12,33,IOB_X1Y60,RIOB33_X105Y59,IO_L20P_T3_33
+AF23,13,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_13
+AF24,13,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_13
+AF25,13,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_13
+AF27,13,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_13
+AF28,13,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_13
+AF29,13,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_13
+AF30,13,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_13
+AF32,13,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_13
+AF33,13,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_13
+AF34,13,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_13
+AG1,33,IOB_X1Y98,RIOB33_X105Y97,IO_L1P_T0_33
+AG2,33,IOB_X1Y89,RIOB33_X105Y89,IO_L5N_T0_33
+AG4,33,IOB_X1Y85,RIOB33_X105Y85,IO_L7N_T1_33
+AG5,33,IOB_X1Y77,RIOB33_X105Y77,IO_L11N_T1_SRCC_33
+AG6,33,IOB_X1Y78,RIOB33_X105Y77,IO_L11P_T1_SRCC_33
+AG7,33,IOB_X1Y71,RIOB33_X105Y71,IO_L14N_T2_SRCC_33
+AG9,33,IOB_X1Y57,RIOB33_X105Y57,IO_L21N_T3_DQS_33
+AG10,33,IOB_X1Y58,RIOB33_X105Y57,IO_L21P_T3_DQS_33
+AG11,33,IOB_X1Y54,RIOB33_X105Y53,IO_L23P_T3_33
+AG12,33,IOB_X1Y59,RIOB33_X105Y59,IO_L20N_T3_33
+AG14,113,IPAD_X2Y8,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK0P_113
+AG16,113,IPAD_X2Y10,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK1P_113
+AG18,213,IPAD_X1Y10,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1P_213
+AG20,213,IPAD_X1Y8,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0P_213
+AG24,13,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_13
+AG25,13,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_13
+AG26,13,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_13
+AG27,13,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_13
+AG29,13,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_13
+AG30,13,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_13
+AG31,13,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_13
+AG32,13,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_13
+AG34,13,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_13
+AH1,33,IOB_X1Y97,RIOB33_X105Y97,IO_L1N_T0_33
+AH2,33,IOB_X1Y94,RIOB33_X105Y93,IO_L3P_T0_DQS_33
+AH3,33,IOB_X1Y88,RIOB33_X105Y87,IO_L6P_T0_33
+AH4,33,IOB_X1Y82,RIOB33_X105Y81,IO_L9P_T1_DQS_33
+AH6,33,IOB_X1Y65,RIOB33_X105Y65,IO_L17N_T2_33
+AH7,33,IOB_X1Y66,RIOB33_X105Y65,IO_L17P_T2_33
+AH8,33,IOB_X1Y61,RIOB33_X105Y61,IO_L19N_T3_VREF_33
+AH9,33,IOB_X1Y62,RIOB33_X105Y61,IO_L19P_T3_33
+AH11,33,IOB_X1Y53,RIOB33_X105Y53,IO_L23N_T3_33
+AH14,113,IPAD_X2Y9,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK0N_113
+AH16,113,IPAD_X2Y11,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK1N_113
+AH18,213,IPAD_X1Y11,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1N_213
+AH20,213,IPAD_X1Y9,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0N_213
+AH24,13,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_13
+AH26,13,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_VREF_13
+AH27,13,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_13
+AH28,13,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_13
+AH29,13,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_13
+AH31,13,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_13
+AH32,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
+AH33,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AH34,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
+AJ1,33,IOB_X1Y93,RIOB33_X105Y93,IO_L3N_T0_DQS_33
+AJ3,33,IOB_X1Y87,RIOB33_X105Y87,IO_L6N_T0_VREF_33
+AJ4,33,IOB_X1Y81,RIOB33_X105Y81,IO_L9N_T1_DQS_33
+AJ5,32,IOB_X1Y34,RIOB33_X105Y33,IO_L8P_T1_32
+AJ6,32,IOB_X1Y26,RIOB33_X105Y25,IO_L12P_T1_MRCC_32
+AJ8,32,IOB_X1Y20,RIOB33_X105Y19,IO_L15P_T2_DQS_32
+AJ9,32,IOB_X1Y49,RIOB33_SING_X105Y49,IO_0_32
+AJ10,32,IOB_X1Y12,RIOB33_X105Y11,IO_L19P_T3_32
+AJ11,32,IOB_X1Y4,RIOB33_X105Y3,IO_L23P_T3_32
+AJ13,113,IPAD_X2Y25,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPRXP3_113
+AJ15,113,IPAD_X2Y19,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPRXP2_113
+AJ17,113,IPAD_X2Y1,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPRXP0_113
+AJ19,213,IPAD_X1Y7,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXP1_213
+AJ21,213,IPAD_X1Y25,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXP3_213
+AJ24,12,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_12
+AJ25,12,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_12
+AJ26,12,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_12
+AJ28,12,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_12
+AJ29,12,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_12
+AJ30,12,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_12
+AJ31,12,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_12
+AJ33,12,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_12
+AJ34,12,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_12
+AK1,32,IOB_X1Y45,RIOB33_X105Y45,IO_L2N_T0_32
+AK2,32,IOB_X1Y46,RIOB33_X105Y45,IO_L2P_T0_32
+AK3,32,IOB_X1Y38,RIOB33_X105Y37,IO_L6P_T0_32
+AK5,32,IOB_X1Y33,RIOB33_X105Y33,IO_L8N_T1_32
+AK6,32,IOB_X1Y25,RIOB33_X105Y25,IO_L12N_T1_MRCC_32
+AK7,32,IOB_X1Y24,RIOB33_X105Y23,IO_L13P_T2_MRCC_32
+AK8,32,IOB_X1Y19,RIOB33_X105Y19,IO_L15N_T2_DQS_32
+AK10,32,IOB_X1Y11,RIOB33_X105Y11,IO_L19N_T3_VREF_32
+AK11,32,IOB_X1Y3,RIOB33_X105Y3,IO_L23N_T3_32
+AK13,113,IPAD_X2Y24,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPRXN3_113
+AK15,113,IPAD_X2Y18,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPRXN2_113
+AK17,113,IPAD_X2Y0,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPRXN0_113
+AK19,213,IPAD_X1Y6,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXN1_213
+AK21,213,IPAD_X1Y24,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXN3_213
+AK25,12,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_12
+AK26,12,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_12
+AK27,12,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_12
+AK28,12,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_12
+AK30,12,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_12
+AK31,12,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_12
+AK32,12,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_12
+AK33,12,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_12
+AL2,32,IOB_X1Y42,RIOB33_X105Y41,IO_L4P_T0_32
+AL3,32,IOB_X1Y37,RIOB33_X105Y37,IO_L6N_T0_VREF_32
+AL4,32,IOB_X1Y30,RIOB33_X105Y29,IO_L10P_T1_32
+AL5,32,IOB_X1Y28,RIOB33_X105Y27,IO_L11P_T1_SRCC_32
+AL7,32,IOB_X1Y23,RIOB33_X105Y23,IO_L13N_T2_MRCC_32
+AL8,32,IOB_X1Y0,RIOB33_SING_X105Y0,IO_25_32
+AL9,32,IOB_X1Y8,RIOB33_X105Y7,IO_L21P_T3_DQS_32
+AL10,32,IOB_X1Y2,RIOB33_X105Y1,IO_L24P_T3_32
+AL14,113,OPAD_X1Y5,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPTXP2_113
+AL16,113,IPAD_X2Y7,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPRXP1_113
+AL18,213,IPAD_X1Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXP0_213
+AL20,213,IPAD_X1Y19,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXP2_213
+AL22,213,OPAD_X0Y5,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXP2_213
+AL24,12,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_12
+AL25,12,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_12
+AL27,12,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_12
+AL28,12,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_12
+AL29,12,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_12
+AL30,12,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_12
+AL32,12,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_12
+AL33,12,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_12
+AL34,12,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_12
+AM1,32,IOB_X1Y41,RIOB33_X105Y41,IO_L4N_T0_32
+AM2,32,IOB_X1Y44,RIOB33_X105Y43,IO_L3P_T0_DQS_32
+AM4,32,IOB_X1Y29,RIOB33_X105Y29,IO_L10N_T1_32
+AM5,32,IOB_X1Y27,RIOB33_X105Y27,IO_L11N_T1_SRCC_32
+AM6,32,IOB_X1Y21,RIOB33_X105Y21,IO_L14N_T2_SRCC_32
+AM7,32,IOB_X1Y22,RIOB33_X105Y21,IO_L14P_T2_SRCC_32
+AM9,32,IOB_X1Y7,RIOB33_X105Y7,IO_L21N_T3_DQS_32
+AM10,32,IOB_X1Y1,RIOB33_X105Y1,IO_L24N_T3_32
+AM11,32,IOB_X1Y6,RIOB33_X105Y5,IO_L22P_T3_32
+AM14,113,OPAD_X1Y4,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPTXN2_113
+AM16,113,IPAD_X2Y6,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPRXN1_113
+AM18,213,IPAD_X1Y0,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXN0_213
+AM20,213,IPAD_X1Y18,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXN2_213
+AM22,213,OPAD_X0Y4,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXN2_213
+AM25,12,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_12
+AM26,12,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_12
+AM27,12,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_12
+AM29,12,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_12
+AM30,12,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_12
+AM31,12,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_12
+AM32,12,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_VREF_12
+AM34,12,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_12
+AN1,32,IOB_X1Y48,RIOB33_X105Y47,IO_L1P_T0_32
+AN2,32,IOB_X1Y43,RIOB33_X105Y43,IO_L3N_T0_DQS_32
+AN3,32,IOB_X1Y40,RIOB33_X105Y39,IO_L5P_T0_32
+AN4,32,IOB_X1Y36,RIOB33_X105Y35,IO_L7P_T1_32
+AN6,32,IOB_X1Y15,RIOB33_X105Y15,IO_L17N_T2_32
+AN7,32,IOB_X1Y16,RIOB33_X105Y15,IO_L17P_T2_32
+AN8,32,IOB_X1Y18,RIOB33_X105Y17,IO_L16P_T2_32
+AN9,32,IOB_X1Y14,RIOB33_X105Y13,IO_L18P_T2_32
+AN11,32,IOB_X1Y5,RIOB33_X105Y5,IO_L22N_T3_32
+AN13,113,OPAD_X1Y7,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPTXP3_113
+AN15,113,OPAD_X1Y3,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPTXP1_113
+AN17,113,OPAD_X1Y1,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPTXP0_113
+AN19,213,OPAD_X0Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPTXP0_213
+AN21,213,OPAD_X0Y3,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXP1_213
+AN23,213,OPAD_X0Y7,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXP3_213
+AN26,12,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_12
+AN27,12,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_12
+AN28,12,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_12
+AN29,12,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_12
+AN31,12,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_12
+AN32,12,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_12
+AN33,12,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_12
+AN34,12,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_12
+AP1,32,IOB_X1Y47,RIOB33_X105Y47,IO_L1N_T0_32
+AP3,32,IOB_X1Y39,RIOB33_X105Y39,IO_L5N_T0_32
+AP4,32,IOB_X1Y35,RIOB33_X105Y35,IO_L7N_T1_32
+AP5,32,IOB_X1Y31,RIOB33_X105Y31,IO_L9N_T1_DQS_32
+AP6,32,IOB_X1Y32,RIOB33_X105Y31,IO_L9P_T1_DQS_32
+AP8,32,IOB_X1Y17,RIOB33_X105Y17,IO_L16N_T2_32
+AP9,32,IOB_X1Y13,RIOB33_X105Y13,IO_L18N_T2_32
+AP10,32,IOB_X1Y9,RIOB33_X105Y9,IO_L20N_T3_32
+AP11,32,IOB_X1Y10,RIOB33_X105Y9,IO_L20P_T3_32
+AP13,113,OPAD_X1Y6,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPTXN3_113
+AP15,113,OPAD_X1Y2,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPTXN1_113
+AP17,113,OPAD_X1Y0,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPTXN0_113
+AP19,213,OPAD_X0Y0,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPTXN0_213
+AP21,213,OPAD_X0Y2,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXN1_213
+AP23,213,OPAD_X0Y6,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXN3_213
+AP25,12,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_12
+AP26,12,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_12
+AP28,12,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_12
+AP29,12,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_12
+AP30,12,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_12
+AP31,12,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_12
+AP33,12,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_12
+AP34,12,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_12
+B13,116,OPAD_X1Y9,GTP_CHANNEL_0_MID_RIGHT_X167Y214,MGTPTXP0_116
+B15,116,OPAD_X1Y13,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPTXP2_116
+B17,116,OPAD_X1Y15,GTP_CHANNEL_3_MID_RIGHT_X167Y254,MGTPTXP3_116
+B19,216,OPAD_X0Y15,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXP3_216
+B21,216,OPAD_X0Y13,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXP2_216
+B23,216,OPAD_X0Y9,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXP0_216
+C14,116,OPAD_X1Y10,GTP_CHANNEL_1_MID_RIGHT_X167Y225,MGTPTXN1_116
+C16,116,IPAD_X2Y54,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPRXN2_116
+C18,216,IPAD_X1Y60,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXN3_216
+C20,216,IPAD_X1Y42,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXN1_216
+C22,216,OPAD_X0Y10,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPTXN1_216
+D14,116,OPAD_X1Y11,GTP_CHANNEL_1_MID_RIGHT_X167Y225,MGTPTXP1_116
+D16,116,IPAD_X2Y55,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPRXP2_116
+D18,216,IPAD_X1Y61,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXP3_216
+D20,216,IPAD_X1Y43,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXP1_216
+D22,216,OPAD_X0Y11,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPTXP1_216
+E13,116,IPAD_X2Y36,GTP_CHANNEL_0_MID_RIGHT_X167Y214,MGTPRXN0_116
+E15,116,IPAD_X2Y42,GTP_CHANNEL_1_MID_RIGHT_X167Y225,MGTPRXN1_116
+E17,116,IPAD_X2Y60,GTP_CHANNEL_3_MID_RIGHT_X167Y254,MGTPRXN3_116
+E19,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+E21,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+F2,36,IOB_X1Y219,RIOB33_X105Y219,IO_L15N_T2_DQS_36
+F3,36,IOB_X1Y220,RIOB33_X105Y219,IO_L15P_T2_DQS_36
+F13,116,IPAD_X2Y37,GTP_CHANNEL_0_MID_RIGHT_X167Y214,MGTPRXP0_116
+F15,116,IPAD_X2Y43,GTP_CHANNEL_1_MID_RIGHT_X167Y225,MGTPRXP1_116
+F17,116,IPAD_X2Y61,GTP_CHANNEL_3_MID_RIGHT_X167Y254,MGTPRXP3_116
+F19,216,IPAD_X1Y55,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXP2_216
+F21,216,IPAD_X1Y37,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXP0_216
+G1,36,IOB_X1Y205,RIOB33_X105Y205,IO_L22N_T3_36
+G2,36,IOB_X1Y209,RIOB33_X105Y209,IO_L20N_T3_36
+G4,36,IOB_X1Y223,RIOB33_X105Y223,IO_L13N_T2_MRCC_36
+G5,36,IOB_X1Y224,RIOB33_X105Y223,IO_L13P_T2_MRCC_36
+G6,36,IOB_X1Y229,RIOB33_X105Y229,IO_L10N_T1_36
+G7,36,IOB_X1Y230,RIOB33_X105Y229,IO_L10P_T1_36
+G9,36,IOB_X1Y245,RIOB33_X105Y245,IO_L2N_T0_36
+G10,36,IOB_X1Y246,RIOB33_X105Y245,IO_L2P_T0_36
+G11,36,IOB_X1Y241,RIOB33_X105Y241,IO_L4N_T0_36
+G14,116,IPAD_X2Y47,GTP_COMMON_MID_RIGHT_X167Y231,MGTREFCLK1N_116
+G16,116,IPAD_X2Y45,GTP_COMMON_MID_RIGHT_X167Y231,MGTREFCLK0N_116
+G18,216,IPAD_X1Y45,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0N_216
+G20,216,IPAD_X1Y47,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1N_216
+G24,16,IOB_X0Y244,LIOB33_X0Y243,IO_L3P_T0_DQS_16
+G25,16,IOB_X0Y243,LIOB33_X0Y243,IO_L3N_T0_DQS_16
+G26,16,IOB_X0Y233,LIOB33_X0Y233,IO_L8N_T1_16
+G27,16,IOB_X0Y235,LIOB33_X0Y235,IO_L7N_T1_16
+G29,16,IOB_X0Y220,LIOB33_X0Y219,IO_L15P_T2_DQS_16
+G30,16,IOB_X0Y219,LIOB33_X0Y219,IO_L15N_T2_DQS_16
+G31,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+G32,16,IOB_X0Y211,LIOB33_X0Y211,IO_L19N_T3_VREF_16
+G34,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+H1,36,IOB_X1Y206,RIOB33_X105Y205,IO_L22P_T3_36
+H2,36,IOB_X1Y210,RIOB33_X105Y209,IO_L20P_T3_36
+H3,36,IOB_X1Y215,RIOB33_X105Y215,IO_L17N_T2_36
+H4,36,IOB_X1Y216,RIOB33_X105Y215,IO_L17P_T2_36
+H6,36,IOB_X1Y225,RIOB33_X105Y225,IO_L12N_T1_MRCC_36
+H7,36,IOB_X1Y226,RIOB33_X105Y225,IO_L12P_T1_MRCC_36
+H8,36,IOB_X1Y233,RIOB33_X105Y233,IO_L8N_T1_36
+H9,36,IOB_X1Y234,RIOB33_X105Y233,IO_L8P_T1_36
+H11,36,IOB_X1Y242,RIOB33_X105Y241,IO_L4P_T0_36
+H12,36,IOB_X1Y249,RIOB33_SING_X105Y249,IO_0_36
+H14,116,IPAD_X2Y46,GTP_COMMON_MID_RIGHT_X167Y231,MGTREFCLK1P_116
+H16,116,IPAD_X2Y44,GTP_COMMON_MID_RIGHT_X167Y231,MGTREFCLK0P_116
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new file mode 100644
index 0000000..8f37c63
--- /dev/null
+++ b/artix7/xc7a200tffv1156-2L/part.json
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+ "iobanks": {
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+ "12": "X1Y26",
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+ "36": "X263Y234",
+ "113": "X263Y26",
+ "116": "X263Y234",
+ "213": "X1Y26",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tffv1156-2L/part.yaml b/artix7/xc7a200tffv1156-2L/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tffv1156-2L/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
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+ 32: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
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+ 58: !<xilinx/xc7series/configuration_column>
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+ 59: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 62: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 65: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 66: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 67: !<xilinx/xc7series/configuration_column>
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+ 68: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 69: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 70: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 71: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 72: !<xilinx/xc7series/configuration_column>
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+ 73: !<xilinx/xc7series/configuration_column>
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+ 74: !<xilinx/xc7series/configuration_column>
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+ 75: !<xilinx/xc7series/configuration_column>
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+ 76: !<xilinx/xc7series/configuration_column>
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+ 77: !<xilinx/xc7series/configuration_column>
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+ 78: !<xilinx/xc7series/configuration_column>
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+ 79: !<xilinx/xc7series/configuration_column>
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+ 80: !<xilinx/xc7series/configuration_column>
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+ 81: !<xilinx/xc7series/configuration_column>
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+ 82: !<xilinx/xc7series/configuration_column>
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+ 83: !<xilinx/xc7series/configuration_column>
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+ 84: !<xilinx/xc7series/configuration_column>
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+ 85: !<xilinx/xc7series/configuration_column>
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+ 86: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 87: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 88: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 89: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 90: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 93: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 94: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 95: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 96: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 97: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 98: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 99: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 100: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
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+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
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diff --git a/artix7/xc7a200tffv1156-3/package_pins.csv b/artix7/xc7a200tffv1156-3/package_pins.csv
new file mode 100644
index 0000000..f1d64d7
--- /dev/null
+++ b/artix7/xc7a200tffv1156-3/package_pins.csv
@@ -0,0 +1,583 @@
+pin,bank,site,tile,pin_function
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+AF2,33,IOB_X1Y91,RIOB33_X105Y91,IO_L4N_T0_33
+AF3,33,IOB_X1Y90,RIOB33_X105Y89,IO_L5P_T0_33
+AF4,33,IOB_X1Y86,RIOB33_X105Y85,IO_L7P_T1_33
+AF5,33,IOB_X1Y75,RIOB33_X105Y75,IO_L12N_T1_MRCC_33
+AF7,33,IOB_X1Y72,RIOB33_X105Y71,IO_L14P_T2_SRCC_33
+AF8,33,IOB_X1Y63,RIOB33_X105Y63,IO_L18N_T2_33
+AF9,33,IOB_X1Y64,RIOB33_X105Y63,IO_L18P_T2_33
+AF10,33,IOB_X1Y50,RIOB33_SING_X105Y50,IO_25_33
+AF12,33,IOB_X1Y60,RIOB33_X105Y59,IO_L20P_T3_33
+AF23,13,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_13
+AF24,13,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_13
+AF25,13,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_13
+AF27,13,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_13
+AF28,13,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_13
+AF29,13,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_13
+AF30,13,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_13
+AF32,13,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_13
+AF33,13,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_13
+AF34,13,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_13
+AG1,33,IOB_X1Y98,RIOB33_X105Y97,IO_L1P_T0_33
+AG2,33,IOB_X1Y89,RIOB33_X105Y89,IO_L5N_T0_33
+AG4,33,IOB_X1Y85,RIOB33_X105Y85,IO_L7N_T1_33
+AG5,33,IOB_X1Y77,RIOB33_X105Y77,IO_L11N_T1_SRCC_33
+AG6,33,IOB_X1Y78,RIOB33_X105Y77,IO_L11P_T1_SRCC_33
+AG7,33,IOB_X1Y71,RIOB33_X105Y71,IO_L14N_T2_SRCC_33
+AG9,33,IOB_X1Y57,RIOB33_X105Y57,IO_L21N_T3_DQS_33
+AG10,33,IOB_X1Y58,RIOB33_X105Y57,IO_L21P_T3_DQS_33
+AG11,33,IOB_X1Y54,RIOB33_X105Y53,IO_L23P_T3_33
+AG12,33,IOB_X1Y59,RIOB33_X105Y59,IO_L20N_T3_33
+AG14,113,IPAD_X2Y8,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK0P_113
+AG16,113,IPAD_X2Y10,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK1P_113
+AG18,213,IPAD_X1Y10,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1P_213
+AG20,213,IPAD_X1Y8,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0P_213
+AG24,13,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_13
+AG25,13,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_13
+AG26,13,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_13
+AG27,13,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_13
+AG29,13,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_13
+AG30,13,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_13
+AG31,13,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_13
+AG32,13,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_13
+AG34,13,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_13
+AH1,33,IOB_X1Y97,RIOB33_X105Y97,IO_L1N_T0_33
+AH2,33,IOB_X1Y94,RIOB33_X105Y93,IO_L3P_T0_DQS_33
+AH3,33,IOB_X1Y88,RIOB33_X105Y87,IO_L6P_T0_33
+AH4,33,IOB_X1Y82,RIOB33_X105Y81,IO_L9P_T1_DQS_33
+AH6,33,IOB_X1Y65,RIOB33_X105Y65,IO_L17N_T2_33
+AH7,33,IOB_X1Y66,RIOB33_X105Y65,IO_L17P_T2_33
+AH8,33,IOB_X1Y61,RIOB33_X105Y61,IO_L19N_T3_VREF_33
+AH9,33,IOB_X1Y62,RIOB33_X105Y61,IO_L19P_T3_33
+AH11,33,IOB_X1Y53,RIOB33_X105Y53,IO_L23N_T3_33
+AH14,113,IPAD_X2Y9,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK0N_113
+AH16,113,IPAD_X2Y11,GTP_COMMON_MID_RIGHT_X167Y23,MGTREFCLK1N_113
+AH18,213,IPAD_X1Y11,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK1N_213
+AH20,213,IPAD_X1Y9,GTP_COMMON_MID_LEFT_X103Y23,MGTREFCLK0N_213
+AH24,13,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_13
+AH26,13,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_VREF_13
+AH27,13,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_13
+AH28,13,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_13
+AH29,13,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_13
+AH31,13,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_13
+AH32,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
+AH33,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AH34,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
+AJ1,33,IOB_X1Y93,RIOB33_X105Y93,IO_L3N_T0_DQS_33
+AJ3,33,IOB_X1Y87,RIOB33_X105Y87,IO_L6N_T0_VREF_33
+AJ4,33,IOB_X1Y81,RIOB33_X105Y81,IO_L9N_T1_DQS_33
+AJ5,32,IOB_X1Y34,RIOB33_X105Y33,IO_L8P_T1_32
+AJ6,32,IOB_X1Y26,RIOB33_X105Y25,IO_L12P_T1_MRCC_32
+AJ8,32,IOB_X1Y20,RIOB33_X105Y19,IO_L15P_T2_DQS_32
+AJ9,32,IOB_X1Y49,RIOB33_SING_X105Y49,IO_0_32
+AJ10,32,IOB_X1Y12,RIOB33_X105Y11,IO_L19P_T3_32
+AJ11,32,IOB_X1Y4,RIOB33_X105Y3,IO_L23P_T3_32
+AJ13,113,IPAD_X2Y25,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPRXP3_113
+AJ15,113,IPAD_X2Y19,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPRXP2_113
+AJ17,113,IPAD_X2Y1,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPRXP0_113
+AJ19,213,IPAD_X1Y7,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXP1_213
+AJ21,213,IPAD_X1Y25,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXP3_213
+AJ24,12,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_12
+AJ25,12,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_12
+AJ26,12,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_12
+AJ28,12,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_12
+AJ29,12,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_12
+AJ30,12,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_12
+AJ31,12,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_12
+AJ33,12,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_12
+AJ34,12,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_12
+AK1,32,IOB_X1Y45,RIOB33_X105Y45,IO_L2N_T0_32
+AK2,32,IOB_X1Y46,RIOB33_X105Y45,IO_L2P_T0_32
+AK3,32,IOB_X1Y38,RIOB33_X105Y37,IO_L6P_T0_32
+AK5,32,IOB_X1Y33,RIOB33_X105Y33,IO_L8N_T1_32
+AK6,32,IOB_X1Y25,RIOB33_X105Y25,IO_L12N_T1_MRCC_32
+AK7,32,IOB_X1Y24,RIOB33_X105Y23,IO_L13P_T2_MRCC_32
+AK8,32,IOB_X1Y19,RIOB33_X105Y19,IO_L15N_T2_DQS_32
+AK10,32,IOB_X1Y11,RIOB33_X105Y11,IO_L19N_T3_VREF_32
+AK11,32,IOB_X1Y3,RIOB33_X105Y3,IO_L23N_T3_32
+AK13,113,IPAD_X2Y24,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPRXN3_113
+AK15,113,IPAD_X2Y18,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPRXN2_113
+AK17,113,IPAD_X2Y0,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPRXN0_113
+AK19,213,IPAD_X1Y6,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPRXN1_213
+AK21,213,IPAD_X1Y24,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPRXN3_213
+AK25,12,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_12
+AK26,12,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_12
+AK27,12,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_12
+AK28,12,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_12
+AK30,12,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_12
+AK31,12,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_12
+AK32,12,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_12
+AK33,12,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_12
+AL2,32,IOB_X1Y42,RIOB33_X105Y41,IO_L4P_T0_32
+AL3,32,IOB_X1Y37,RIOB33_X105Y37,IO_L6N_T0_VREF_32
+AL4,32,IOB_X1Y30,RIOB33_X105Y29,IO_L10P_T1_32
+AL5,32,IOB_X1Y28,RIOB33_X105Y27,IO_L11P_T1_SRCC_32
+AL7,32,IOB_X1Y23,RIOB33_X105Y23,IO_L13N_T2_MRCC_32
+AL8,32,IOB_X1Y0,RIOB33_SING_X105Y0,IO_25_32
+AL9,32,IOB_X1Y8,RIOB33_X105Y7,IO_L21P_T3_DQS_32
+AL10,32,IOB_X1Y2,RIOB33_X105Y1,IO_L24P_T3_32
+AL14,113,OPAD_X1Y5,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPTXP2_113
+AL16,113,IPAD_X2Y7,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPRXP1_113
+AL18,213,IPAD_X1Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXP0_213
+AL20,213,IPAD_X1Y19,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXP2_213
+AL22,213,OPAD_X0Y5,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXP2_213
+AL24,12,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_12
+AL25,12,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_12
+AL27,12,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_12
+AL28,12,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_12
+AL29,12,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_12
+AL30,12,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_12
+AL32,12,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_12
+AL33,12,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_12
+AL34,12,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_12
+AM1,32,IOB_X1Y41,RIOB33_X105Y41,IO_L4N_T0_32
+AM2,32,IOB_X1Y44,RIOB33_X105Y43,IO_L3P_T0_DQS_32
+AM4,32,IOB_X1Y29,RIOB33_X105Y29,IO_L10N_T1_32
+AM5,32,IOB_X1Y27,RIOB33_X105Y27,IO_L11N_T1_SRCC_32
+AM6,32,IOB_X1Y21,RIOB33_X105Y21,IO_L14N_T2_SRCC_32
+AM7,32,IOB_X1Y22,RIOB33_X105Y21,IO_L14P_T2_SRCC_32
+AM9,32,IOB_X1Y7,RIOB33_X105Y7,IO_L21N_T3_DQS_32
+AM10,32,IOB_X1Y1,RIOB33_X105Y1,IO_L24N_T3_32
+AM11,32,IOB_X1Y6,RIOB33_X105Y5,IO_L22P_T3_32
+AM14,113,OPAD_X1Y4,GTP_CHANNEL_2_MID_RIGHT_X167Y35,MGTPTXN2_113
+AM16,113,IPAD_X2Y6,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPRXN1_113
+AM18,213,IPAD_X1Y0,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPRXN0_213
+AM20,213,IPAD_X1Y18,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPRXN2_213
+AM22,213,OPAD_X0Y4,GTP_CHANNEL_2_MID_LEFT_X103Y35,MGTPTXN2_213
+AM25,12,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_12
+AM26,12,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_12
+AM27,12,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_12
+AM29,12,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_12
+AM30,12,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_12
+AM31,12,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_12
+AM32,12,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_VREF_12
+AM34,12,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_12
+AN1,32,IOB_X1Y48,RIOB33_X105Y47,IO_L1P_T0_32
+AN2,32,IOB_X1Y43,RIOB33_X105Y43,IO_L3N_T0_DQS_32
+AN3,32,IOB_X1Y40,RIOB33_X105Y39,IO_L5P_T0_32
+AN4,32,IOB_X1Y36,RIOB33_X105Y35,IO_L7P_T1_32
+AN6,32,IOB_X1Y15,RIOB33_X105Y15,IO_L17N_T2_32
+AN7,32,IOB_X1Y16,RIOB33_X105Y15,IO_L17P_T2_32
+AN8,32,IOB_X1Y18,RIOB33_X105Y17,IO_L16P_T2_32
+AN9,32,IOB_X1Y14,RIOB33_X105Y13,IO_L18P_T2_32
+AN11,32,IOB_X1Y5,RIOB33_X105Y5,IO_L22N_T3_32
+AN13,113,OPAD_X1Y7,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPTXP3_113
+AN15,113,OPAD_X1Y3,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPTXP1_113
+AN17,113,OPAD_X1Y1,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPTXP0_113
+AN19,213,OPAD_X0Y1,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPTXP0_213
+AN21,213,OPAD_X0Y3,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXP1_213
+AN23,213,OPAD_X0Y7,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXP3_213
+AN26,12,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_12
+AN27,12,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_12
+AN28,12,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_12
+AN29,12,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_12
+AN31,12,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_12
+AN32,12,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_12
+AN33,12,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_12
+AN34,12,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_12
+AP1,32,IOB_X1Y47,RIOB33_X105Y47,IO_L1N_T0_32
+AP3,32,IOB_X1Y39,RIOB33_X105Y39,IO_L5N_T0_32
+AP4,32,IOB_X1Y35,RIOB33_X105Y35,IO_L7N_T1_32
+AP5,32,IOB_X1Y31,RIOB33_X105Y31,IO_L9N_T1_DQS_32
+AP6,32,IOB_X1Y32,RIOB33_X105Y31,IO_L9P_T1_DQS_32
+AP8,32,IOB_X1Y17,RIOB33_X105Y17,IO_L16N_T2_32
+AP9,32,IOB_X1Y13,RIOB33_X105Y13,IO_L18N_T2_32
+AP10,32,IOB_X1Y9,RIOB33_X105Y9,IO_L20N_T3_32
+AP11,32,IOB_X1Y10,RIOB33_X105Y9,IO_L20P_T3_32
+AP13,113,OPAD_X1Y6,GTP_CHANNEL_3_MID_RIGHT_X167Y46,MGTPTXN3_113
+AP15,113,OPAD_X1Y2,GTP_CHANNEL_1_MID_RIGHT_X167Y17,MGTPTXN1_113
+AP17,113,OPAD_X1Y0,GTP_CHANNEL_0_MID_RIGHT_X167Y6,MGTPTXN0_113
+AP19,213,OPAD_X0Y0,GTP_CHANNEL_0_MID_LEFT_X103Y6,MGTPTXN0_213
+AP21,213,OPAD_X0Y2,GTP_CHANNEL_1_MID_LEFT_X103Y17,MGTPTXN1_213
+AP23,213,OPAD_X0Y6,GTP_CHANNEL_3_MID_LEFT_X103Y46,MGTPTXN3_213
+AP25,12,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_12
+AP26,12,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_12
+AP28,12,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_12
+AP29,12,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_12
+AP30,12,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_12
+AP31,12,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_12
+AP33,12,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_12
+AP34,12,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_12
+B13,116,OPAD_X1Y9,GTP_CHANNEL_0_MID_RIGHT_X167Y214,MGTPTXP0_116
+B15,116,OPAD_X1Y13,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPTXP2_116
+B17,116,OPAD_X1Y15,GTP_CHANNEL_3_MID_RIGHT_X167Y254,MGTPTXP3_116
+B19,216,OPAD_X0Y15,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXP3_216
+B21,216,OPAD_X0Y13,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXP2_216
+B23,216,OPAD_X0Y9,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXP0_216
+C14,116,OPAD_X1Y10,GTP_CHANNEL_1_MID_RIGHT_X167Y225,MGTPTXN1_116
+C16,116,IPAD_X2Y54,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPRXN2_116
+C18,216,IPAD_X1Y60,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXN3_216
+C20,216,IPAD_X1Y42,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXN1_216
+C22,216,OPAD_X0Y10,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPTXN1_216
+D14,116,OPAD_X1Y11,GTP_CHANNEL_1_MID_RIGHT_X167Y225,MGTPTXP1_116
+D16,116,IPAD_X2Y55,GTP_CHANNEL_2_MID_RIGHT_X167Y243,MGTPRXP2_116
+D18,216,IPAD_X1Y61,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXP3_216
+D20,216,IPAD_X1Y43,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXP1_216
+D22,216,OPAD_X0Y11,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPTXP1_216
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+E15,116,IPAD_X2Y42,GTP_CHANNEL_1_MID_RIGHT_X167Y225,MGTPRXN1_116
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diff --git a/artix7/xc7a200tffv1156-3/part.json b/artix7/xc7a200tffv1156-3/part.json
new file mode 100644
index 0000000..8f37c63
--- /dev/null
+++ b/artix7/xc7a200tffv1156-3/part.json
@@ -0,0 +1,1815 @@
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+ "116": "X263Y234",
+ "213": "X1Y26",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tffv1156-3/part.yaml b/artix7/xc7a200tffv1156-3/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tffv1156-3/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 58: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 59: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 62: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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diff --git a/artix7/xc7a200tsbg484-2/package_pins.csv b/artix7/xc7a200tsbg484-2/package_pins.csv
new file mode 100644
index 0000000..4bd6953
--- /dev/null
+++ b/artix7/xc7a200tsbg484-2/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
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diff --git a/artix7/xc7a200tsbg484-2/part.json b/artix7/xc7a200tsbg484-2/part.json
new file mode 100644
index 0000000..44ab6a4
--- /dev/null
+++ b/artix7/xc7a200tsbg484-2/part.json
@@ -0,0 +1,1808 @@
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+ "iobanks": {
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+ "13": "X1Y78",
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+ "15": "X1Y182",
+ "16": "X1Y234",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tsbg484-2/part.yaml b/artix7/xc7a200tsbg484-2/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tsbg484-2/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 32: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 58: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 59: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 62: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 65: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 66: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 67: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 68: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 69: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 70: !<xilinx/xc7series/configuration_column>
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+ 71: !<xilinx/xc7series/configuration_column>
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+ 72: !<xilinx/xc7series/configuration_column>
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+ 73: !<xilinx/xc7series/configuration_column>
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+ 75: !<xilinx/xc7series/configuration_column>
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+ 76: !<xilinx/xc7series/configuration_column>
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+ 78: !<xilinx/xc7series/configuration_column>
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+ 79: !<xilinx/xc7series/configuration_column>
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+ 80: !<xilinx/xc7series/configuration_column>
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+ 81: !<xilinx/xc7series/configuration_column>
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+ 82: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 83: !<xilinx/xc7series/configuration_column>
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diff --git a/artix7/xc7a200tsbg484-2L/package_pins.csv b/artix7/xc7a200tsbg484-2L/package_pins.csv
new file mode 100644
index 0000000..4bd6953
--- /dev/null
+++ b/artix7/xc7a200tsbg484-2L/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
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diff --git a/artix7/xc7a200tsbg484-2L/part.json b/artix7/xc7a200tsbg484-2L/part.json
new file mode 100644
index 0000000..44ab6a4
--- /dev/null
+++ b/artix7/xc7a200tsbg484-2L/part.json
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+ }
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+ "iobanks": {
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+ "13": "X1Y78",
+ "14": "X1Y130",
+ "15": "X1Y182",
+ "16": "X1Y234",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tsbg484-2L/part.yaml b/artix7/xc7a200tsbg484-2L/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tsbg484-2L/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 32: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
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+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
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+ 39: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
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+ 41: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
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+ 45: !<xilinx/xc7series/configuration_column>
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+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
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+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
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+ 58: !<xilinx/xc7series/configuration_column>
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+ 59: !<xilinx/xc7series/configuration_column>
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+ 60: !<xilinx/xc7series/configuration_column>
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+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 62: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 65: !<xilinx/xc7series/configuration_column>
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+ 66: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 67: !<xilinx/xc7series/configuration_column>
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+ 69: !<xilinx/xc7series/configuration_column>
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+ 71: !<xilinx/xc7series/configuration_column>
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+ 72: !<xilinx/xc7series/configuration_column>
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+ 73: !<xilinx/xc7series/configuration_column>
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+ 76: !<xilinx/xc7series/configuration_column>
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+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
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diff --git a/artix7/xc7a200tsbg484-3/package_pins.csv b/artix7/xc7a200tsbg484-3/package_pins.csv
new file mode 100644
index 0000000..4bd6953
--- /dev/null
+++ b/artix7/xc7a200tsbg484-3/package_pins.csv
@@ -0,0 +1,308 @@
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new file mode 100644
index 0000000..44ab6a4
--- /dev/null
+++ b/artix7/xc7a200tsbg484-3/part.json
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+ }
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+ "iobanks": {
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+ "13": "X1Y78",
+ "14": "X1Y130",
+ "15": "X1Y182",
+ "16": "X1Y234",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tsbg484-3/part.yaml b/artix7/xc7a200tsbg484-3/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tsbg484-3/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 58: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 59: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 62: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 65: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 66: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 67: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 68: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 69: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 70: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 71: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 72: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 73: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 74: !<xilinx/xc7series/configuration_column>
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+ 75: !<xilinx/xc7series/configuration_column>
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+ 76: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 77: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 78: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 79: !<xilinx/xc7series/configuration_column>
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+ 80: !<xilinx/xc7series/configuration_column>
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+ 81: !<xilinx/xc7series/configuration_column>
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+ 82: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 83: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 84: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 85: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 86: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 87: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 88: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 89: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 90: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 93: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 94: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 95: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 96: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 97: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 98: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 99: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 100: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
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diff --git a/artix7/xc7a200tsbv484-1/package_pins.csv b/artix7/xc7a200tsbv484-1/package_pins.csv
new file mode 100644
index 0000000..4bd6953
--- /dev/null
+++ b/artix7/xc7a200tsbv484-1/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
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diff --git a/artix7/xc7a200tsbv484-1/part.json b/artix7/xc7a200tsbv484-1/part.json
new file mode 100644
index 0000000..44ab6a4
--- /dev/null
+++ b/artix7/xc7a200tsbv484-1/part.json
@@ -0,0 +1,1808 @@
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+ }
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+ }
+ }
+ }
+ },
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+ "iobanks": {
+ "0": "X1Y182",
+ "13": "X1Y78",
+ "14": "X1Y130",
+ "15": "X1Y182",
+ "16": "X1Y234",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tsbv484-1/part.yaml b/artix7/xc7a200tsbv484-1/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tsbv484-1/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
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+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
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+ 58: !<xilinx/xc7series/configuration_column>
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+ 59: !<xilinx/xc7series/configuration_column>
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+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
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+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
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+ 65: !<xilinx/xc7series/configuration_column>
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+ 66: !<xilinx/xc7series/configuration_column>
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+ 69: !<xilinx/xc7series/configuration_column>
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+ 81: !<xilinx/xc7series/configuration_column>
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+ 82: !<xilinx/xc7series/configuration_column>
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+ 83: !<xilinx/xc7series/configuration_column>
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+ 84: !<xilinx/xc7series/configuration_column>
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+ 85: !<xilinx/xc7series/configuration_column>
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+ 86: !<xilinx/xc7series/configuration_column>
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+ 87: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 88: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 89: !<xilinx/xc7series/configuration_column>
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+ 90: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 93: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 94: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 95: !<xilinx/xc7series/configuration_column>
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+ 96: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 97: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 98: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 99: !<xilinx/xc7series/configuration_column>
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+ 100: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
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+ 3: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
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+ 22: !<xilinx/xc7series/configuration_column>
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+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
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+ frame_count: 128
+ 2: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
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+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
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+ frame_count: 128
diff --git a/artix7/xc7a200tsbv484-2/package_pins.csv b/artix7/xc7a200tsbv484-2/package_pins.csv
new file mode 100644
index 0000000..4bd6953
--- /dev/null
+++ b/artix7/xc7a200tsbv484-2/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y197,RIOB33_X105Y197,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+A6,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A8,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A10,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A13,16,IOB_X0Y230,LIOB33_X0Y229,IO_L10P_T1_16
+A14,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16
+A15,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y216,LIOB33_X0Y215,IO_L17P_T2_16
+A19,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+A20,16,IOB_X0Y217,LIOB33_X0Y217,IO_L16N_T2_16
+A21,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y136,RIOB33_X105Y135,IO_L7P_T1_34
+AA3,34,IOB_X1Y131,RIOB33_X105Y131,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y127,RIOB33_X105Y127,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y130,RIOB33_X105Y129,IO_L10P_T1_34
+AA6,34,IOB_X1Y113,RIOB33_X105Y113,IO_L18N_T2_34
+AA8,34,IOB_X1Y106,RIOB33_X105Y105,IO_L22P_T3_34
+AA9,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
+AA10,13,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_13
+AA11,13,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_13
+AA13,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AA14,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
+AA15,13,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_13
+AA16,13,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_13
+AA18,14,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y135,RIOB33_X105Y135,IO_L7N_T1_34
+AB2,34,IOB_X1Y133,RIOB33_X105Y133,IO_L8N_T1_34
+AB3,34,IOB_X1Y134,RIOB33_X105Y133,IO_L8P_T1_34
+AB5,34,IOB_X1Y129,RIOB33_X105Y129,IO_L10N_T1_34
+AB6,34,IOB_X1Y109,RIOB33_X105Y109,IO_L20N_T3_34
+AB7,34,IOB_X1Y110,RIOB33_X105Y109,IO_L20P_T3_34
+AB8,34,IOB_X1Y105,RIOB33_X105Y105,IO_L22N_T3_34
+AB10,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AB11,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AB12,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
+AB13,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
+AB15,13,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_13
+AB16,13,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_13
+AB17,13,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_13
+AB18,14,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_D14_14
+AB22,14,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_D15_14
+B1,35,IOB_X1Y198,RIOB33_X105Y197,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y195,RIOB33_X105Y195,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y9,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXP0_216
+B6,216,OPAD_X0Y13,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXP2_216
+B8,216,IPAD_X1Y37,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXP0_216
+B10,216,IPAD_X1Y55,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXP2_216
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+D5,216,OPAD_X0Y11,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPTXP1_216
+D7,216,OPAD_X0Y15,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXP3_216
+D9,216,IPAD_X1Y61,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXP3_216
+D11,216,IPAD_X1Y43,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXP1_216
+D14,16,IOB_X0Y238,LIOB33_X0Y237,IO_L6P_T0_16
+D15,16,IOB_X0Y237,LIOB33_X0Y237,IO_L6N_T0_VREF_16
+D16,16,IOB_X0Y239,LIOB33_X0Y239,IO_L5N_T0_16
+D17,16,IOB_X0Y226,LIOB33_X0Y225,IO_L12P_T1_MRCC_16
+D19,16,IOB_X0Y221,LIOB33_X0Y221,IO_L14N_T2_SRCC_16
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+D22,16,IOB_X0Y205,LIOB33_X0Y205,IO_L22N_T3_16
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+E3,35,IOB_X1Y187,RIOB33_X105Y187,IO_L6N_T0_VREF_35
+E6,216,IPAD_X1Y45,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0N_216
+E10,216,IPAD_X1Y47,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1N_216
+E13,16,IOB_X0Y242,LIOB33_X0Y241,IO_L4P_T0_16
+E14,16,IOB_X0Y241,LIOB33_X0Y241,IO_L4N_T0_16
+E16,16,IOB_X0Y240,LIOB33_X0Y239,IO_L5P_T0_16
+E17,16,IOB_X0Y245,LIOB33_X0Y245,IO_L2N_T0_16
+E18,16,IOB_X0Y219,LIOB33_X0Y219,IO_L15N_T2_DQS_16
+E19,16,IOB_X0Y222,LIOB33_X0Y221,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y204,LIOB33_X0Y203,IO_L23P_T3_16
+E22,16,IOB_X0Y206,LIOB33_X0Y205,IO_L22P_T3_16
+F1,35,IOB_X1Y189,RIOB33_X105Y189,IO_L5N_T0_AD13N_35
+F3,35,IOB_X1Y188,RIOB33_X105Y187,IO_L6P_T0_35
+F4,35,IOB_X1Y199,RIOB33_SING_X105Y199,IO_0_35
+F6,216,IPAD_X1Y44,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0P_216
+F10,216,IPAD_X1Y46,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1P_216
+F13,16,IOB_X0Y248,LIOB33_X0Y247,IO_L1P_T0_16
+F14,16,IOB_X0Y247,LIOB33_X0Y247,IO_L1N_T0_16
+F15,16,IOB_X0Y249,LIOB33_SING_X0Y249,IO_0_16
+F16,16,IOB_X0Y246,LIOB33_X0Y245,IO_L2P_T0_16
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diff --git a/artix7/xc7a200tsbv484-2/part.json b/artix7/xc7a200tsbv484-2/part.json
new file mode 100644
index 0000000..44ab6a4
--- /dev/null
+++ b/artix7/xc7a200tsbv484-2/part.json
@@ -0,0 +1,1808 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
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+ },
+ "2": {
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+ },
+ "3": {
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+ },
+ "4": {
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+ },
+ "5": {
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+ },
+ "6": {
+ "frame_count": 128
+ },
+ "7": {
+ "frame_count": 128
+ },
+ "8": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
+ "4": {
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+ },
+ "5": {
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+ },
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+ },
+ "7": {
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+ },
+ "8": {
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+ },
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+ },
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+ },
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+ },
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+ },
+ "13": {
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+ },
+ "14": {
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+ },
+ "15": {
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+ }
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+ "CLB_IO_CLK": {
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+ },
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+ },
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+ },
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+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56844435,
+ "iobanks": {
+ "0": "X1Y182",
+ "13": "X1Y78",
+ "14": "X1Y130",
+ "15": "X1Y182",
+ "16": "X1Y234",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tsbv484-2/part.yaml b/artix7/xc7a200tsbv484-2/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tsbv484-2/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
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+ 58: !<xilinx/xc7series/configuration_column>
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+ 59: !<xilinx/xc7series/configuration_column>
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+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
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+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 65: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 66: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 67: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 68: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 69: !<xilinx/xc7series/configuration_column>
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+ 70: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ 83: !<xilinx/xc7series/configuration_column>
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+ 84: !<xilinx/xc7series/configuration_column>
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+ 85: !<xilinx/xc7series/configuration_column>
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+ 86: !<xilinx/xc7series/configuration_column>
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+ 87: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 88: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 89: !<xilinx/xc7series/configuration_column>
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+ 90: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 93: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 94: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 95: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 96: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 97: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 98: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 99: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 100: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
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diff --git a/artix7/xc7a200tsbv484-2L/package_pins.csv b/artix7/xc7a200tsbv484-2L/package_pins.csv
new file mode 100644
index 0000000..4bd6953
--- /dev/null
+++ b/artix7/xc7a200tsbv484-2L/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
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+AA1,34,IOB_X1Y136,RIOB33_X105Y135,IO_L7P_T1_34
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+F4,35,IOB_X1Y199,RIOB33_SING_X105Y199,IO_0_35
+F6,216,IPAD_X1Y44,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0P_216
+F10,216,IPAD_X1Y46,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1P_216
+F13,16,IOB_X0Y248,LIOB33_X0Y247,IO_L1P_T0_16
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+G4,35,IOB_X1Y175,RIOB33_X105Y175,IO_L12N_T1_MRCC_35
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diff --git a/artix7/xc7a200tsbv484-2L/part.json b/artix7/xc7a200tsbv484-2L/part.json
new file mode 100644
index 0000000..44ab6a4
--- /dev/null
+++ b/artix7/xc7a200tsbv484-2L/part.json
@@ -0,0 +1,1808 @@
+{
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+ },
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+ "CLB_IO_CLK": {
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+ },
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+ },
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+ },
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+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56844435,
+ "iobanks": {
+ "0": "X1Y182",
+ "13": "X1Y78",
+ "14": "X1Y130",
+ "15": "X1Y182",
+ "16": "X1Y234",
+ "34": "X263Y130",
+ "35": "X263Y182",
+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tsbv484-2L/part.yaml b/artix7/xc7a200tsbv484-2L/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tsbv484-2L/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
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+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 41: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
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+ 52: !<xilinx/xc7series/configuration_column>
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+ 53: !<xilinx/xc7series/configuration_column>
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+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
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+ 58: !<xilinx/xc7series/configuration_column>
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+ 60: !<xilinx/xc7series/configuration_column>
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+ frame_count: 36
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+ frame_count: 36
+ 69: !<xilinx/xc7series/configuration_column>
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+ 83: !<xilinx/xc7series/configuration_column>
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+ 84: !<xilinx/xc7series/configuration_column>
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+ 85: !<xilinx/xc7series/configuration_column>
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+ 86: !<xilinx/xc7series/configuration_column>
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+ 87: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 88: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 89: !<xilinx/xc7series/configuration_column>
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+ 90: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 93: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 94: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 95: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 96: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 97: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 98: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 99: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 100: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
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diff --git a/artix7/xc7a200tsbv484-3/package_pins.csv b/artix7/xc7a200tsbv484-3/package_pins.csv
new file mode 100644
index 0000000..4bd6953
--- /dev/null
+++ b/artix7/xc7a200tsbv484-3/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y197,RIOB33_X105Y197,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y8,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXN0_216
+A6,216,OPAD_X0Y12,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPTXN2_216
+A8,216,IPAD_X1Y36,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXN0_216
+A10,216,IPAD_X1Y54,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXN2_216
+A13,16,IOB_X0Y230,LIOB33_X0Y229,IO_L10P_T1_16
+A14,16,IOB_X0Y229,LIOB33_X0Y229,IO_L10N_T1_16
+A15,16,IOB_X0Y232,LIOB33_X0Y231,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y231,LIOB33_X0Y231,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y216,LIOB33_X0Y215,IO_L17P_T2_16
+A19,16,IOB_X0Y215,LIOB33_X0Y215,IO_L17N_T2_16
+A20,16,IOB_X0Y217,LIOB33_X0Y217,IO_L16N_T2_16
+A21,16,IOB_X0Y207,LIOB33_X0Y207,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y136,RIOB33_X105Y135,IO_L7P_T1_34
+AA3,34,IOB_X1Y131,RIOB33_X105Y131,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y127,RIOB33_X105Y127,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y130,RIOB33_X105Y129,IO_L10P_T1_34
+AA6,34,IOB_X1Y113,RIOB33_X105Y113,IO_L18N_T2_34
+AA8,34,IOB_X1Y106,RIOB33_X105Y105,IO_L22P_T3_34
+AA9,13,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_13
+AA10,13,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_13
+AA11,13,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_13
+AA13,13,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_13
+AA14,13,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_13
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+AA16,13,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_13
+AA18,14,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y135,RIOB33_X105Y135,IO_L7N_T1_34
+AB2,34,IOB_X1Y133,RIOB33_X105Y133,IO_L8N_T1_34
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+AB7,34,IOB_X1Y110,RIOB33_X105Y109,IO_L20P_T3_34
+AB8,34,IOB_X1Y105,RIOB33_X105Y105,IO_L22N_T3_34
+AB10,13,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_13
+AB11,13,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_13
+AB12,13,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_13
+AB13,13,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_13
+AB15,13,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_13
+AB16,13,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_13
+AB17,13,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_13
+AB18,14,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_D14_14
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+B2,35,IOB_X1Y195,RIOB33_X105Y195,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y9,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPTXP0_216
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+B8,216,IPAD_X1Y37,GTP_CHANNEL_0_MID_LEFT_X103Y214,MGTPRXP0_216
+B10,216,IPAD_X1Y55,GTP_CHANNEL_2_MID_LEFT_X103Y243,MGTPRXP2_216
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+D7,216,OPAD_X0Y15,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPTXP3_216
+D9,216,IPAD_X1Y61,GTP_CHANNEL_3_MID_LEFT_X103Y254,MGTPRXP3_216
+D11,216,IPAD_X1Y43,GTP_CHANNEL_1_MID_LEFT_X103Y225,MGTPRXP1_216
+D14,16,IOB_X0Y238,LIOB33_X0Y237,IO_L6P_T0_16
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+D17,16,IOB_X0Y226,LIOB33_X0Y225,IO_L12P_T1_MRCC_16
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+E3,35,IOB_X1Y187,RIOB33_X105Y187,IO_L6N_T0_VREF_35
+E6,216,IPAD_X1Y45,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0N_216
+E10,216,IPAD_X1Y47,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1N_216
+E13,16,IOB_X0Y242,LIOB33_X0Y241,IO_L4P_T0_16
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+E17,16,IOB_X0Y245,LIOB33_X0Y245,IO_L2N_T0_16
+E18,16,IOB_X0Y219,LIOB33_X0Y219,IO_L15N_T2_DQS_16
+E19,16,IOB_X0Y222,LIOB33_X0Y221,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y204,LIOB33_X0Y203,IO_L23P_T3_16
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+F4,35,IOB_X1Y199,RIOB33_SING_X105Y199,IO_0_35
+F6,216,IPAD_X1Y44,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK0P_216
+F10,216,IPAD_X1Y46,GTP_COMMON_MID_LEFT_X103Y231,MGTREFCLK1P_216
+F13,16,IOB_X0Y248,LIOB33_X0Y247,IO_L1P_T0_16
+F14,16,IOB_X0Y247,LIOB33_X0Y247,IO_L1N_T0_16
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+F16,16,IOB_X0Y246,LIOB33_X0Y245,IO_L2P_T0_16
+F18,16,IOB_X0Y220,LIOB33_X0Y219,IO_L15P_T2_DQS_16
+F19,16,IOB_X0Y214,LIOB33_X0Y213,IO_L18P_T2_16
+F20,16,IOB_X0Y213,LIOB33_X0Y213,IO_L18N_T2_16
+F21,16,IOB_X0Y200,LIOB33_SING_X0Y200,IO_25_16
+G1,35,IOB_X1Y190,RIOB33_X105Y189,IO_L5P_T0_AD13P_35
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+G4,35,IOB_X1Y175,RIOB33_X105Y175,IO_L12N_T1_MRCC_35
+G13,15,IOB_X0Y197,LIOB33_X0Y197,IO_L1N_T0_AD0N_15
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diff --git a/artix7/xc7a200tsbv484-3/part.json b/artix7/xc7a200tsbv484-3/part.json
new file mode 100644
index 0000000..44ab6a4
--- /dev/null
+++ b/artix7/xc7a200tsbv484-3/part.json
@@ -0,0 +1,1808 @@
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+ "216": "X1Y234"
+ }
+}
diff --git a/artix7/xc7a200tsbv484-3/part.yaml b/artix7/xc7a200tsbv484-3/part.yaml
new file mode 100644
index 0000000..2b77fa3
--- /dev/null
+++ b/artix7/xc7a200tsbv484-3/part.yaml
@@ -0,0 +1,1187 @@
+!<xilinx/xc7series/part>
+idcode: 0x3636093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
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+ 2: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
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+ 11: !<xilinx/xc7series/configuration_column>
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+ 105: !<xilinx/xc7series/configuration_column>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
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+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
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+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 58: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 59: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 62: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 65: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 66: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 67: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 68: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 69: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 70: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 71: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 72: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 73: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 74: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 75: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 76: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 77: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 78: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 79: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 80: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 81: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 82: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 83: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 84: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 85: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 86: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 87: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 88: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 89: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 90: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 91: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 92: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 93: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 94: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 95: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 96: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 97: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 98: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 99: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 100: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 101: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 102: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 103: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 104: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 105: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tcpg236-2/package_pins.csv b/artix7/xc7a35tcpg236-2/package_pins.csv
new file mode 100644
index 0000000..55efcab
--- /dev/null
+++ b/artix7/xc7a35tcpg236-2/package_pins.csv
@@ -0,0 +1,121 @@
+pin,bank,site,tile,pin_function
+A2,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+A4,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+A6,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+A8,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+A10,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+A12,0,IPAD_X0Y0,MONITOR_BOT_X46Y79,VP_0
+A14,16,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_16
+A15,16,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_16
+A16,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+A17,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+A18,16,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_VREF_16
+B2,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+B4,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+B6,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+B8,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+B10,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+B13,0,IPAD_X0Y1,MONITOR_BOT_X46Y79,VN_0
+B15,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B16,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+B17,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+B18,16,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_16
+C15,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+C16,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
+C17,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+D1,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+D2,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+D17,14,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_14
+D18,14,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_D00_MOSI_14
+D19,14,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_D01_DIN_14
+E18,14,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_PUDC_B_14
+E19,14,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_EMCCLK_14
+F18,14,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_D03_14
+G2,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+G3,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+G17,14,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_D07_14
+G18,14,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_D02_14
+G19,14,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_D05_14
+H1,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+H2,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+H17,14,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_D06_14
+H19,14,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_D04_14
+J1,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+J2,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+J3,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+J17,14,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_D09_14
+J18,14,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_D10_14
+J19,14,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_D08_VREF_14
+K2,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+K3,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+K17,14,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_14
+K18,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+K19,14,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_FCS_B_14
+L1,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+L2,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+L3,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+L17,14,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_14
+L18,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+M1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+M2,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+M3,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+M18,14,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_14
+M19,14,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_14
+N1,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+N2,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
+N3,35,IOB_X1Y76,RIOB33_X43Y75,IO_L12P_T1_MRCC_35
+N17,14,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_14
+N18,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+N19,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
+P1,35,IOB_X1Y61,RIOB33_X43Y61,IO_L19N_T3_VREF_35
+P3,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+P17,14,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_14
+P18,14,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_14
+P19,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+R2,34,IOB_X1Y48,RIOB33_X43Y47,IO_L1P_T0_34
+R3,34,IOB_X1Y46,RIOB33_X43Y45,IO_L2P_T0_34
+R18,14,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_14
+R19,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
+T1,34,IOB_X1Y44,RIOB33_X43Y43,IO_L3P_T0_DQS_34
+T2,34,IOB_X1Y47,RIOB33_X43Y47,IO_L1N_T0_34
+T3,34,IOB_X1Y45,RIOB33_X43Y45,IO_L2N_T0_34
+T17,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+T18,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+U1,34,IOB_X1Y43,RIOB33_X43Y43,IO_L3N_T0_DQS_34
+U2,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+U3,34,IOB_X1Y32,RIOB33_X43Y31,IO_L9P_T1_DQS_34
+U4,34,IOB_X1Y28,RIOB33_X43Y27,IO_L11P_T1_SRCC_34
+U5,34,IOB_X1Y18,RIOB33_X43Y17,IO_L16P_T2_34
+U7,34,IOB_X1Y12,RIOB33_X43Y11,IO_L19P_T3_34
+U8,34,IOB_X1Y22,RIOB33_X43Y21,IO_L14P_T2_SRCC_34
+U14,14,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_14
+U15,14,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_A03_D19_14
+U16,14,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_A02_D18_14
+U17,14,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_A12_D28_14
+U18,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
+U19,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+V2,34,IOB_X1Y40,RIOB33_X43Y39,IO_L5P_T0_34
+V3,34,IOB_X1Y38,RIOB33_X43Y37,IO_L6P_T0_34
+V4,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+V5,34,IOB_X1Y17,RIOB33_X43Y17,IO_L16N_T2_34
+V7,34,IOB_X1Y11,RIOB33_X43Y11,IO_L19N_T3_VREF_34
+V8,34,IOB_X1Y21,RIOB33_X43Y21,IO_L14N_T2_SRCC_34
+V13,14,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_A01_D17_14
+V14,14,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_A00_D16_14
+V15,14,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_14
+V16,14,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_A10_D26_14
+V17,14,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_A09_D25_VREF_14
+V19,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+W2,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
+W3,34,IOB_X1Y37,RIOB33_X43Y37,IO_L6N_T0_VREF_34
+W4,34,IOB_X1Y25,RIOB33_X43Y25,IO_L12N_T1_MRCC_34
+W5,34,IOB_X1Y26,RIOB33_X43Y25,IO_L12P_T1_MRCC_34
+W6,34,IOB_X1Y23,RIOB33_X43Y23,IO_L13N_T2_MRCC_34
+W7,34,IOB_X1Y24,RIOB33_X43Y23,IO_L13P_T2_MRCC_34
+W13,14,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_A05_D21_14
+W14,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
+W15,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+W16,14,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_A08_D24_14
+W17,14,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_A07_D23_14
+W18,14,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_CSI_B_14
+W19,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
diff --git a/artix7/xc7a35tcpg236-2/part.json b/artix7/xc7a35tcpg236-2/part.json
new file mode 100644
index 0000000..6443c42
--- /dev/null
+++ b/artix7/xc7a35tcpg236-2/part.json
@@ -0,0 +1,458 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a35tcpg236-2/part.yaml b/artix7/xc7a35tcpg236-2/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tcpg236-2/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tcpg236-2L/package_pins.csv b/artix7/xc7a35tcpg236-2L/package_pins.csv
new file mode 100644
index 0000000..55efcab
--- /dev/null
+++ b/artix7/xc7a35tcpg236-2L/package_pins.csv
@@ -0,0 +1,121 @@
+pin,bank,site,tile,pin_function
+A2,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+A4,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+A6,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+A8,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+A10,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+A12,0,IPAD_X0Y0,MONITOR_BOT_X46Y79,VP_0
+A14,16,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_16
+A15,16,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_16
+A16,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+A17,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+A18,16,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_VREF_16
+B2,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+B4,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+B6,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+B8,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+B10,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+B13,0,IPAD_X0Y1,MONITOR_BOT_X46Y79,VN_0
+B15,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B16,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+B17,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+B18,16,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_16
+C15,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+C16,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
+C17,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+D1,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+D2,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+D17,14,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_14
+D18,14,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_D00_MOSI_14
+D19,14,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_D01_DIN_14
+E18,14,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_PUDC_B_14
+E19,14,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_EMCCLK_14
+F18,14,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_D03_14
+G2,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+G3,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+G17,14,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_D07_14
+G18,14,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_D02_14
+G19,14,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_D05_14
+H1,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+H2,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+H17,14,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_D06_14
+H19,14,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_D04_14
+J1,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+J2,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+J3,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+J17,14,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_D09_14
+J18,14,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_D10_14
+J19,14,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_D08_VREF_14
+K2,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+K3,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+K17,14,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_14
+K18,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+K19,14,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_FCS_B_14
+L1,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+L2,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+L3,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+L17,14,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_14
+L18,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+M1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+M2,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+M3,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+M18,14,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_14
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+N3,35,IOB_X1Y76,RIOB33_X43Y75,IO_L12P_T1_MRCC_35
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+N18,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+N19,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
+P1,35,IOB_X1Y61,RIOB33_X43Y61,IO_L19N_T3_VREF_35
+P3,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
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+U14,14,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_14
+U15,14,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_A03_D19_14
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+U18,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
+U19,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+V2,34,IOB_X1Y40,RIOB33_X43Y39,IO_L5P_T0_34
+V3,34,IOB_X1Y38,RIOB33_X43Y37,IO_L6P_T0_34
+V4,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+V5,34,IOB_X1Y17,RIOB33_X43Y17,IO_L16N_T2_34
+V7,34,IOB_X1Y11,RIOB33_X43Y11,IO_L19N_T3_VREF_34
+V8,34,IOB_X1Y21,RIOB33_X43Y21,IO_L14N_T2_SRCC_34
+V13,14,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_A01_D17_14
+V14,14,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_A00_D16_14
+V15,14,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_14
+V16,14,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_A10_D26_14
+V17,14,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_A09_D25_VREF_14
+V19,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+W2,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
+W3,34,IOB_X1Y37,RIOB33_X43Y37,IO_L6N_T0_VREF_34
+W4,34,IOB_X1Y25,RIOB33_X43Y25,IO_L12N_T1_MRCC_34
+W5,34,IOB_X1Y26,RIOB33_X43Y25,IO_L12P_T1_MRCC_34
+W6,34,IOB_X1Y23,RIOB33_X43Y23,IO_L13N_T2_MRCC_34
+W7,34,IOB_X1Y24,RIOB33_X43Y23,IO_L13P_T2_MRCC_34
+W13,14,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_A05_D21_14
+W14,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
+W15,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+W16,14,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_A08_D24_14
+W17,14,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_A07_D23_14
+W18,14,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_CSI_B_14
+W19,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
diff --git a/artix7/xc7a35tcpg236-2L/part.json b/artix7/xc7a35tcpg236-2L/part.json
new file mode 100644
index 0000000..6443c42
--- /dev/null
+++ b/artix7/xc7a35tcpg236-2L/part.json
@@ -0,0 +1,458 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
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+ },
+ "39": {
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+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
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+ },
+ "5": {
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+ },
+ "6": {
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+ },
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+ },
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+ },
+ "12": {
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+ "13": {
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+ },
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+ "15": {
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+ },
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+ },
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+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
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+ },
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+ },
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+ },
+ "25": {
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+ },
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+ },
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+ },
+ "28": {
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+ },
+ "29": {
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+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
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+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
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+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
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+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a35tcpg236-2L/part.yaml b/artix7/xc7a35tcpg236-2L/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tcpg236-2L/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tcpg236-3/package_pins.csv b/artix7/xc7a35tcpg236-3/package_pins.csv
new file mode 100644
index 0000000..55efcab
--- /dev/null
+++ b/artix7/xc7a35tcpg236-3/package_pins.csv
@@ -0,0 +1,121 @@
+pin,bank,site,tile,pin_function
+A2,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+A4,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+A6,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+A8,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+A10,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+A12,0,IPAD_X0Y0,MONITOR_BOT_X46Y79,VP_0
+A14,16,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_16
+A15,16,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_16
+A16,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+A17,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+A18,16,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_VREF_16
+B2,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+B4,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+B6,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+B8,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+B10,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+B13,0,IPAD_X0Y1,MONITOR_BOT_X46Y79,VN_0
+B15,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B16,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+B17,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+B18,16,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_16
+C15,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+C16,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
+C17,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+D1,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+D2,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+D17,14,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_14
+D18,14,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_D00_MOSI_14
+D19,14,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_D01_DIN_14
+E18,14,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_PUDC_B_14
+E19,14,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_EMCCLK_14
+F18,14,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_D03_14
+G2,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+G3,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+G17,14,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_D07_14
+G18,14,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_D02_14
+G19,14,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_D05_14
+H1,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+H2,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+H17,14,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_D06_14
+H19,14,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_D04_14
+J1,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+J2,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+J3,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+J17,14,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_D09_14
+J18,14,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_D10_14
+J19,14,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_D08_VREF_14
+K2,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+K3,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+K17,14,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_14
+K18,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+K19,14,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_FCS_B_14
+L1,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+L2,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+L3,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+L17,14,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_14
+L18,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+M1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+M2,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+M3,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+M18,14,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_14
+M19,14,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_14
+N1,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+N2,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
+N3,35,IOB_X1Y76,RIOB33_X43Y75,IO_L12P_T1_MRCC_35
+N17,14,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_14
+N18,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+N19,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
+P1,35,IOB_X1Y61,RIOB33_X43Y61,IO_L19N_T3_VREF_35
+P3,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+P17,14,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_14
+P18,14,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_14
+P19,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+R2,34,IOB_X1Y48,RIOB33_X43Y47,IO_L1P_T0_34
+R3,34,IOB_X1Y46,RIOB33_X43Y45,IO_L2P_T0_34
+R18,14,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_14
+R19,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
+T1,34,IOB_X1Y44,RIOB33_X43Y43,IO_L3P_T0_DQS_34
+T2,34,IOB_X1Y47,RIOB33_X43Y47,IO_L1N_T0_34
+T3,34,IOB_X1Y45,RIOB33_X43Y45,IO_L2N_T0_34
+T17,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+T18,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+U1,34,IOB_X1Y43,RIOB33_X43Y43,IO_L3N_T0_DQS_34
+U2,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+U3,34,IOB_X1Y32,RIOB33_X43Y31,IO_L9P_T1_DQS_34
+U4,34,IOB_X1Y28,RIOB33_X43Y27,IO_L11P_T1_SRCC_34
+U5,34,IOB_X1Y18,RIOB33_X43Y17,IO_L16P_T2_34
+U7,34,IOB_X1Y12,RIOB33_X43Y11,IO_L19P_T3_34
+U8,34,IOB_X1Y22,RIOB33_X43Y21,IO_L14P_T2_SRCC_34
+U14,14,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_14
+U15,14,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_A03_D19_14
+U16,14,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_A02_D18_14
+U17,14,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_A12_D28_14
+U18,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
+U19,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+V2,34,IOB_X1Y40,RIOB33_X43Y39,IO_L5P_T0_34
+V3,34,IOB_X1Y38,RIOB33_X43Y37,IO_L6P_T0_34
+V4,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+V5,34,IOB_X1Y17,RIOB33_X43Y17,IO_L16N_T2_34
+V7,34,IOB_X1Y11,RIOB33_X43Y11,IO_L19N_T3_VREF_34
+V8,34,IOB_X1Y21,RIOB33_X43Y21,IO_L14N_T2_SRCC_34
+V13,14,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_A01_D17_14
+V14,14,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_A00_D16_14
+V15,14,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_14
+V16,14,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_A10_D26_14
+V17,14,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_A09_D25_VREF_14
+V19,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+W2,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
+W3,34,IOB_X1Y37,RIOB33_X43Y37,IO_L6N_T0_VREF_34
+W4,34,IOB_X1Y25,RIOB33_X43Y25,IO_L12N_T1_MRCC_34
+W5,34,IOB_X1Y26,RIOB33_X43Y25,IO_L12P_T1_MRCC_34
+W6,34,IOB_X1Y23,RIOB33_X43Y23,IO_L13N_T2_MRCC_34
+W7,34,IOB_X1Y24,RIOB33_X43Y23,IO_L13P_T2_MRCC_34
+W13,14,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_A05_D21_14
+W14,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
+W15,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+W16,14,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_A08_D24_14
+W17,14,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_A07_D23_14
+W18,14,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_CSI_B_14
+W19,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
diff --git a/artix7/xc7a35tcpg236-3/part.json b/artix7/xc7a35tcpg236-3/part.json
new file mode 100644
index 0000000..6443c42
--- /dev/null
+++ b/artix7/xc7a35tcpg236-3/part.json
@@ -0,0 +1,458 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a35tcpg236-3/part.yaml b/artix7/xc7a35tcpg236-3/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tcpg236-3/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tcsg324-2/package_pins.csv b/artix7/xc7a35tcsg324-2/package_pins.csv
new file mode 100644
index 0000000..c4786e7
--- /dev/null
+++ b/artix7/xc7a35tcsg324-2/package_pins.csv
@@ -0,0 +1,213 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+A3,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+A4,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+A5,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+A6,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+A8,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+A9,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+A10,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+A11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+A13,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+A14,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+A15,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+A16,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+A18,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+B1,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+B2,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+B3,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
+B4,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+B6,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+B7,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+B8,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+B9,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B11,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+B12,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+B13,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+B14,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+B16,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+B17,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+B18,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+C1,35,IOB_X1Y67,RIOB33_X43Y67,IO_L16N_T2_35
+C2,35,IOB_X1Y68,RIOB33_X43Y67,IO_L16P_T2_35
+C4,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+C5,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+C6,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+C7,35,IOB_X1Y91,RIOB33_X43Y91,IO_L4N_T0_35
+C9,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+C10,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+C11,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
+C12,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
+C14,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+C15,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+C16,15,IOB_X0Y60,LIOB33_X0Y59,IO_L20P_T3_A20_15
+C17,15,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_A19_15
+D2,35,IOB_X1Y71,RIOB33_X43Y71,IO_L14N_T2_SRCC_35
+D3,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+D4,35,IOB_X1Y77,RIOB33_X43Y77,IO_L11N_T1_SRCC_35
+D5,35,IOB_X1Y78,RIOB33_X43Y77,IO_L11P_T1_SRCC_35
+D7,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+D8,35,IOB_X1Y92,RIOB33_X43Y91,IO_L4P_T0_35
+D9,16,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_16
+D10,16,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_VREF_16
+D12,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+D13,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+D14,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+D15,15,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_15
+D17,15,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A27_15
+D18,15,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_A18_15
+E1,35,IOB_X1Y63,RIOB33_X43Y63,IO_L18N_T2_35
+E2,35,IOB_X1Y72,RIOB33_X43Y71,IO_L14P_T2_SRCC_35
+E3,35,IOB_X1Y76,RIOB33_X43Y75,IO_L12P_T1_MRCC_35
+E5,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+E6,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+E7,35,IOB_X1Y88,RIOB33_X43Y87,IO_L6P_T0_35
+E15,15,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_15
+E16,15,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_15
+E17,15,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_A28_15
+E18,15,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_15
+F1,35,IOB_X1Y64,RIOB33_X43Y63,IO_L18P_T2_35
+F3,35,IOB_X1Y73,RIOB33_X43Y73,IO_L13N_T2_MRCC_35
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diff --git a/artix7/xc7a35tcsg324-2/part.json b/artix7/xc7a35tcsg324-2/part.json
new file mode 100644
index 0000000..4ecd6db
--- /dev/null
+++ b/artix7/xc7a35tcsg324-2/part.json
@@ -0,0 +1,459 @@
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+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a35tcsg324-2/part.yaml b/artix7/xc7a35tcsg324-2/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tcsg324-2/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tcsg324-2L/package_pins.csv b/artix7/xc7a35tcsg324-2L/package_pins.csv
new file mode 100644
index 0000000..c4786e7
--- /dev/null
+++ b/artix7/xc7a35tcsg324-2L/package_pins.csv
@@ -0,0 +1,213 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+A3,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+A4,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+A5,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+A6,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+A8,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+A9,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+A10,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+A11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+A13,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+A14,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+A15,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+A16,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+A18,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+B1,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+B2,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+B3,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
+B4,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+B6,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+B7,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+B8,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+B9,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B11,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+B12,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+B13,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+B14,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+B16,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+B17,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+B18,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+C1,35,IOB_X1Y67,RIOB33_X43Y67,IO_L16N_T2_35
+C2,35,IOB_X1Y68,RIOB33_X43Y67,IO_L16P_T2_35
+C4,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+C5,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+C6,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+C7,35,IOB_X1Y91,RIOB33_X43Y91,IO_L4N_T0_35
+C9,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+C10,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+C11,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
+C12,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
+C14,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+C15,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+C16,15,IOB_X0Y60,LIOB33_X0Y59,IO_L20P_T3_A20_15
+C17,15,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_A19_15
+D2,35,IOB_X1Y71,RIOB33_X43Y71,IO_L14N_T2_SRCC_35
+D3,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+D4,35,IOB_X1Y77,RIOB33_X43Y77,IO_L11N_T1_SRCC_35
+D5,35,IOB_X1Y78,RIOB33_X43Y77,IO_L11P_T1_SRCC_35
+D7,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+D8,35,IOB_X1Y92,RIOB33_X43Y91,IO_L4P_T0_35
+D9,16,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_16
+D10,16,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_VREF_16
+D12,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+D13,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+D14,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+D15,15,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_15
+D17,15,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A27_15
+D18,15,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_A18_15
+E1,35,IOB_X1Y63,RIOB33_X43Y63,IO_L18N_T2_35
+E2,35,IOB_X1Y72,RIOB33_X43Y71,IO_L14P_T2_SRCC_35
+E3,35,IOB_X1Y76,RIOB33_X43Y75,IO_L12P_T1_MRCC_35
+E5,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+E6,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+E7,35,IOB_X1Y88,RIOB33_X43Y87,IO_L6P_T0_35
+E15,15,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_15
+E16,15,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_15
+E17,15,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_A28_15
+E18,15,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_15
+F1,35,IOB_X1Y64,RIOB33_X43Y63,IO_L18P_T2_35
+F3,35,IOB_X1Y73,RIOB33_X43Y73,IO_L13N_T2_MRCC_35
+F4,35,IOB_X1Y74,RIOB33_X43Y73,IO_L13P_T2_MRCC_35
+F5,35,IOB_X1Y99,RIOB33_SING_X43Y99,IO_0_35
+F6,35,IOB_X1Y61,RIOB33_X43Y61,IO_L19N_T3_VREF_35
+F13,15,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_AD9P_15
+F14,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+F15,15,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_15
+F16,15,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_15
+F18,15,IOB_X0Y55,LIOB33_X0Y55,IO_L22N_T3_A16_15
+G1,35,IOB_X1Y65,RIOB33_X43Y65,IO_L17N_T2_35
+G2,35,IOB_X1Y69,RIOB33_X43Y69,IO_L15N_T2_DQS_35
+G3,35,IOB_X1Y59,RIOB33_X43Y59,IO_L20N_T3_35
+G4,35,IOB_X1Y60,RIOB33_X43Y59,IO_L20P_T3_35
+G6,35,IOB_X1Y62,RIOB33_X43Y61,IO_L19P_T3_35
+G13,15,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_15
+G14,15,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_ADV_B_15
+G16,15,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_15
+G17,15,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_A23_15
+G18,15,IOB_X0Y56,LIOB33_X0Y55,IO_L22P_T3_A17_15
+H1,35,IOB_X1Y66,RIOB33_X43Y65,IO_L17P_T2_35
+H2,35,IOB_X1Y70,RIOB33_X43Y69,IO_L15P_T2_DQS_35
+H4,35,IOB_X1Y57,RIOB33_X43Y57,IO_L21N_T3_DQS_35
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diff --git a/artix7/xc7a35tcsg324-2L/part.json b/artix7/xc7a35tcsg324-2L/part.json
new file mode 100644
index 0000000..4ecd6db
--- /dev/null
+++ b/artix7/xc7a35tcsg324-2L/part.json
@@ -0,0 +1,459 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
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+ },
+ "25": {
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+ },
+ "26": {
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+ },
+ "27": {
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+ },
+ "28": {
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+ },
+ "29": {
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+ },
+ "30": {
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+ },
+ "31": {
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+ "32": {
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+ },
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+ },
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+ },
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+ },
+ "41": {
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+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
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+ },
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+ },
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+ },
+ "19": {
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+ },
+ "20": {
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+ },
+ "21": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "28": {
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+ },
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+ },
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+ },
+ "32": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a35tcsg324-2L/part.yaml b/artix7/xc7a35tcsg324-2L/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tcsg324-2L/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
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+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
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+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
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+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
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+ 2: !<xilinx/xc7series/configuration_column>
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diff --git a/artix7/xc7a35tcsg324-3/package_pins.csv b/artix7/xc7a35tcsg324-3/package_pins.csv
new file mode 100644
index 0000000..c4786e7
--- /dev/null
+++ b/artix7/xc7a35tcsg324-3/package_pins.csv
@@ -0,0 +1,213 @@
+pin,bank,site,tile,pin_function
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diff --git a/artix7/xc7a35tcsg324-3/part.json b/artix7/xc7a35tcsg324-3/part.json
new file mode 100644
index 0000000..4ecd6db
--- /dev/null
+++ b/artix7/xc7a35tcsg324-3/part.json
@@ -0,0 +1,459 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
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+ },
+ "7": {
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+ },
+ "8": {
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+ },
+ "9": {
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+ },
+ "10": {
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+ },
+ "11": {
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+ "12": {
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+ },
+ "13": {
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+ },
+ "14": {
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+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
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+ },
+ "17": {
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+ },
+ "18": {
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+ },
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+ },
+ "20": {
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+ },
+ "21": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "42": {
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+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
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+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
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+ "0": {
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+ },
+ "1": {
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+ },
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+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
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+ },
+ "11": {
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+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a35tcsg324-3/part.yaml b/artix7/xc7a35tcsg324-3/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tcsg324-3/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tcsg325-1/package_pins.csv b/artix7/xc7a35tcsg325-1/package_pins.csv
new file mode 100644
index 0000000..2477b7e
--- /dev/null
+++ b/artix7/xc7a35tcsg325-1/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A3,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+A4,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+A9,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+A10,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+A12,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+A13,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+A14,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+A15,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+A17,15,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_ADV_B_15
+B1,216,OPAD_X0Y6,GTP_CHANNEL_3_X97Y150,MGTPTXN3_216
+B2,216,OPAD_X0Y7,GTP_CHANNEL_3_X97Y150,MGTPTXP3_216
+B5,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+B6,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+B9,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
+B10,15,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_AD9P_15
+B11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+B12,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+B14,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+B15,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+B16,15,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_15
+B17,15,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A27_15
+C3,216,IPAD_X1Y24,GTP_CHANNEL_2_X97Y139,MGTPRXN2_216
+C4,216,IPAD_X1Y25,GTP_CHANNEL_2_X97Y139,MGTPRXP2_216
+C8,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+C9,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+C11,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+C12,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+C13,15,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_15
+C14,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+C16,15,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_A28_15
+C17,15,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_A24_15
+C18,15,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_A23_15
+D1,216,OPAD_X0Y4,GTP_CHANNEL_2_X97Y139,MGTPTXN2_216
+D2,216,OPAD_X0Y5,GTP_CHANNEL_2_X97Y139,MGTPTXP2_216
+D5,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+D6,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+D8,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+D9,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+D10,15,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_15
+D11,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+D13,15,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_15
+D14,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+D15,15,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_15
+D16,15,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_15
+D18,15,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A25_15
+E3,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+E4,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+E13,15,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_15
+E15,15,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_15
+E16,15,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_15
+E17,15,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A26_15
+E18,15,IOB_X0Y51,LIOB33_X0Y51,IO_L24N_T3_RS0_15
+F1,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+F2,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+F14,15,IOB_X0Y55,LIOB33_X0Y55,IO_L22N_T3_A16_15
+F15,15,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_A18_15
+F17,15,IOB_X0Y52,LIOB33_X0Y51,IO_L24P_T3_RS1_15
+F18,15,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_A21_VREF_15
+G3,216,IPAD_X1Y30,GTP_CHANNEL_3_X97Y150,MGTPRXN3_216
+G4,216,IPAD_X1Y31,GTP_CHANNEL_3_X97Y150,MGTPRXP3_216
+G14,15,IOB_X0Y56,LIOB33_X0Y55,IO_L22P_T3_A17_15
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+G16,15,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_A19_15
+G17,15,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_A22_15
+H1,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+H2,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+H14,15,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_15
+H16,15,IOB_X0Y60,LIOB33_X0Y59,IO_L20P_T3_A20_15
+H17,15,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_FOE_B_15
+H18,15,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_FWE_B_15
+J4,34,IOB_X1Y45,RIOB33_X43Y45,IO_L2N_T0_34
+J5,34,IOB_X1Y46,RIOB33_X43Y45,IO_L2P_T0_34
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+J14,14,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_D06_14
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+J16,14,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_D03_14
+J18,14,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_PUDC_B_14
+K1,34,IOB_X1Y43,RIOB33_X43Y43,IO_L3N_T0_DQS_34
+K2,34,IOB_X1Y44,RIOB33_X43Y43,IO_L3P_T0_DQS_34
+K3,34,IOB_X1Y42,RIOB33_X43Y41,IO_L4P_T0_34
+K5,34,IOB_X1Y47,RIOB33_X43Y47,IO_L1N_T0_34
+K6,34,IOB_X1Y48,RIOB33_X43Y47,IO_L1P_T0_34
+K10,0,IPAD_X0Y0,MONITOR_BOT_X46Y79,VP_0
+K15,14,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_D07_14
+K16,14,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_D00_MOSI_14
+K17,14,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_D04_14
+K18,14,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_EMCCLK_14
+L2,34,IOB_X1Y41,RIOB33_X43Y41,IO_L4N_T0_34
+L3,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
+L4,34,IOB_X1Y40,RIOB33_X43Y39,IO_L5P_T0_34
+L5,34,IOB_X1Y38,RIOB33_X43Y37,IO_L6P_T0_34
+L9,0,IPAD_X0Y1,MONITOR_BOT_X46Y79,VN_0
+L14,14,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_14
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+L17,14,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_D01_DIN_14
+L18,14,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_D05_14
+M1,34,IOB_X1Y35,RIOB33_X43Y35,IO_L7N_T1_34
+M2,34,IOB_X1Y36,RIOB33_X43Y35,IO_L7P_T1_34
+M4,34,IOB_X1Y30,RIOB33_X43Y29,IO_L10P_T1_34
+M5,34,IOB_X1Y37,RIOB33_X43Y37,IO_L6N_T0_VREF_34
+M6,34,IOB_X1Y34,RIOB33_X43Y33,IO_L8P_T1_34
+M14,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+M15,14,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_D08_VREF_14
+M16,14,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_D09_14
+M17,14,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_D10_14
+N1,34,IOB_X1Y32,RIOB33_X43Y31,IO_L9P_T1_DQS_34
+N2,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+N3,34,IOB_X1Y28,RIOB33_X43Y27,IO_L11P_T1_SRCC_34
+N4,34,IOB_X1Y29,RIOB33_X43Y29,IO_L10N_T1_34
+N6,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
+N14,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+N16,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+N17,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
+N18,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
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+P3,34,IOB_X1Y25,RIOB33_X43Y25,IO_L12N_T1_MRCC_34
+P4,34,IOB_X1Y26,RIOB33_X43Y25,IO_L12P_T1_MRCC_34
+P5,34,IOB_X1Y11,RIOB33_X43Y11,IO_L19N_T3_VREF_34
+P6,34,IOB_X1Y12,RIOB33_X43Y11,IO_L19P_T3_34
+P14,14,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_14
+P15,14,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_14
+P16,14,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_14
+P18,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
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+R3,34,IOB_X1Y22,RIOB33_X43Y21,IO_L14P_T2_SRCC_34
+R5,34,IOB_X1Y8,RIOB33_X43Y7,IO_L21P_T3_DQS_34
+R6,34,IOB_X1Y0,RIOB33_SING_X43Y0,IO_25_34
+R7,34,IOB_X1Y6,RIOB33_X43Y5,IO_L22P_T3_34
+R13,14,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_A10_D26_14
+R15,14,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_14
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+R17,14,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_14
+R18,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
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+T4,34,IOB_X1Y16,RIOB33_X43Y15,IO_L17P_T2_34
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+T12,14,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_A05_D21_14
+T13,14,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_A09_D25_VREF_14
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+T15,14,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_14
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+T18,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+U1,34,IOB_X1Y19,RIOB33_X43Y19,IO_L15N_T2_DQS_34
+U2,34,IOB_X1Y20,RIOB33_X43Y19,IO_L15P_T2_DQS_34
+U4,34,IOB_X1Y14,RIOB33_X43Y13,IO_L18P_T2_34
+U5,34,IOB_X1Y9,RIOB33_X43Y9,IO_L20N_T3_34
+U6,34,IOB_X1Y10,RIOB33_X43Y9,IO_L20P_T3_34
+U7,34,IOB_X1Y4,RIOB33_X43Y3,IO_L23P_T3_34
+U9,14,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_A01_D17_14
+U10,14,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_14
+U11,14,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_A03_D19_14
+U12,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
+U14,14,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_A08_D24_14
+U15,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+U16,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+U17,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
+V2,34,IOB_X1Y17,RIOB33_X43Y17,IO_L16N_T2_34
+V3,34,IOB_X1Y18,RIOB33_X43Y17,IO_L16P_T2_34
+V4,34,IOB_X1Y13,RIOB33_X43Y13,IO_L18N_T2_34
+V6,34,IOB_X1Y3,RIOB33_X43Y3,IO_L23N_T3_34
+V7,34,IOB_X1Y1,RIOB33_X43Y1,IO_L24N_T3_34
+V8,34,IOB_X1Y2,RIOB33_X43Y1,IO_L24P_T3_34
+V9,14,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_A00_D16_14
+V11,14,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_A02_D18_14
+V12,14,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_14
+V13,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+V14,14,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_A07_D23_14
+V16,14,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_A12_D28_14
+V17,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
diff --git a/artix7/xc7a35tcsg325-1/part.json b/artix7/xc7a35tcsg325-1/part.json
new file mode 100644
index 0000000..258dcd2
--- /dev/null
+++ b/artix7/xc7a35tcsg325-1/part.json
@@ -0,0 +1,457 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
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+ "frame_count": 28
+ },
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+ "frame_count": 36
+ },
+ "36": {
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+ },
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+ },
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+ },
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+ },
+ "41": {
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+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
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+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "34": "X113Y26"
+ }
+}
diff --git a/artix7/xc7a35tcsg325-1/part.yaml b/artix7/xc7a35tcsg325-1/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tcsg325-1/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tcsg325-2/package_pins.csv b/artix7/xc7a35tcsg325-2/package_pins.csv
new file mode 100644
index 0000000..2477b7e
--- /dev/null
+++ b/artix7/xc7a35tcsg325-2/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A3,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+A4,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+A9,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+A10,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+A12,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+A13,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+A14,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+A15,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+A17,15,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_ADV_B_15
+B1,216,OPAD_X0Y6,GTP_CHANNEL_3_X97Y150,MGTPTXN3_216
+B2,216,OPAD_X0Y7,GTP_CHANNEL_3_X97Y150,MGTPTXP3_216
+B5,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+B6,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+B9,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
+B10,15,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_AD9P_15
+B11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+B12,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+B14,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+B15,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+B16,15,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_15
+B17,15,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A27_15
+C3,216,IPAD_X1Y24,GTP_CHANNEL_2_X97Y139,MGTPRXN2_216
+C4,216,IPAD_X1Y25,GTP_CHANNEL_2_X97Y139,MGTPRXP2_216
+C8,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+C9,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+C11,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+C12,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+C13,15,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_15
+C14,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+C16,15,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_A28_15
+C17,15,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_A24_15
+C18,15,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_A23_15
+D1,216,OPAD_X0Y4,GTP_CHANNEL_2_X97Y139,MGTPTXN2_216
+D2,216,OPAD_X0Y5,GTP_CHANNEL_2_X97Y139,MGTPTXP2_216
+D5,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+D6,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+D8,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+D9,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+D10,15,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_15
+D11,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+D13,15,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_15
+D14,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+D15,15,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_15
+D16,15,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_15
+D18,15,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A25_15
+E3,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+E4,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+E13,15,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_15
+E15,15,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_15
+E16,15,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_15
+E17,15,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A26_15
+E18,15,IOB_X0Y51,LIOB33_X0Y51,IO_L24N_T3_RS0_15
+F1,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+F2,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+F14,15,IOB_X0Y55,LIOB33_X0Y55,IO_L22N_T3_A16_15
+F15,15,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_A18_15
+F17,15,IOB_X0Y52,LIOB33_X0Y51,IO_L24P_T3_RS1_15
+F18,15,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_A21_VREF_15
+G3,216,IPAD_X1Y30,GTP_CHANNEL_3_X97Y150,MGTPRXN3_216
+G4,216,IPAD_X1Y31,GTP_CHANNEL_3_X97Y150,MGTPRXP3_216
+G14,15,IOB_X0Y56,LIOB33_X0Y55,IO_L22P_T3_A17_15
+G15,15,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_15
+G16,15,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_A19_15
+G17,15,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_A22_15
+H1,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+H2,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+H14,15,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_15
+H16,15,IOB_X0Y60,LIOB33_X0Y59,IO_L20P_T3_A20_15
+H17,15,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_FOE_B_15
+H18,15,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_FWE_B_15
+J4,34,IOB_X1Y45,RIOB33_X43Y45,IO_L2N_T0_34
+J5,34,IOB_X1Y46,RIOB33_X43Y45,IO_L2P_T0_34
+J6,34,IOB_X1Y49,RIOB33_SING_X43Y49,IO_0_34
+J14,14,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_D06_14
+J15,14,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_D02_14
+J16,14,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_D03_14
+J18,14,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_PUDC_B_14
+K1,34,IOB_X1Y43,RIOB33_X43Y43,IO_L3N_T0_DQS_34
+K2,34,IOB_X1Y44,RIOB33_X43Y43,IO_L3P_T0_DQS_34
+K3,34,IOB_X1Y42,RIOB33_X43Y41,IO_L4P_T0_34
+K5,34,IOB_X1Y47,RIOB33_X43Y47,IO_L1N_T0_34
+K6,34,IOB_X1Y48,RIOB33_X43Y47,IO_L1P_T0_34
+K10,0,IPAD_X0Y0,MONITOR_BOT_X46Y79,VP_0
+K15,14,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_D07_14
+K16,14,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_D00_MOSI_14
+K17,14,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_D04_14
+K18,14,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_EMCCLK_14
+L2,34,IOB_X1Y41,RIOB33_X43Y41,IO_L4N_T0_34
+L3,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
+L4,34,IOB_X1Y40,RIOB33_X43Y39,IO_L5P_T0_34
+L5,34,IOB_X1Y38,RIOB33_X43Y37,IO_L6P_T0_34
+L9,0,IPAD_X0Y1,MONITOR_BOT_X46Y79,VN_0
+L14,14,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_14
+L15,14,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_FCS_B_14
+L17,14,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_D01_DIN_14
+L18,14,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_D05_14
+M1,34,IOB_X1Y35,RIOB33_X43Y35,IO_L7N_T1_34
+M2,34,IOB_X1Y36,RIOB33_X43Y35,IO_L7P_T1_34
+M4,34,IOB_X1Y30,RIOB33_X43Y29,IO_L10P_T1_34
+M5,34,IOB_X1Y37,RIOB33_X43Y37,IO_L6N_T0_VREF_34
+M6,34,IOB_X1Y34,RIOB33_X43Y33,IO_L8P_T1_34
+M14,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+M15,14,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_D08_VREF_14
+M16,14,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_D09_14
+M17,14,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_D10_14
+N1,34,IOB_X1Y32,RIOB33_X43Y31,IO_L9P_T1_DQS_34
+N2,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+N3,34,IOB_X1Y28,RIOB33_X43Y27,IO_L11P_T1_SRCC_34
+N4,34,IOB_X1Y29,RIOB33_X43Y29,IO_L10N_T1_34
+N6,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
+N14,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+N16,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+N17,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
+N18,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+P1,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+P3,34,IOB_X1Y25,RIOB33_X43Y25,IO_L12N_T1_MRCC_34
+P4,34,IOB_X1Y26,RIOB33_X43Y25,IO_L12P_T1_MRCC_34
+P5,34,IOB_X1Y11,RIOB33_X43Y11,IO_L19N_T3_VREF_34
+P6,34,IOB_X1Y12,RIOB33_X43Y11,IO_L19P_T3_34
+P14,14,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_14
+P15,14,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_14
+P16,14,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_14
+P18,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
+R1,34,IOB_X1Y23,RIOB33_X43Y23,IO_L13N_T2_MRCC_34
+R2,34,IOB_X1Y24,RIOB33_X43Y23,IO_L13P_T2_MRCC_34
+R3,34,IOB_X1Y22,RIOB33_X43Y21,IO_L14P_T2_SRCC_34
+R5,34,IOB_X1Y8,RIOB33_X43Y7,IO_L21P_T3_DQS_34
+R6,34,IOB_X1Y0,RIOB33_SING_X43Y0,IO_25_34
+R7,34,IOB_X1Y6,RIOB33_X43Y5,IO_L22P_T3_34
+R13,14,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_A10_D26_14
+R15,14,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_14
+R16,14,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_14
+R17,14,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_14
+R18,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+T2,34,IOB_X1Y21,RIOB33_X43Y21,IO_L14N_T2_SRCC_34
+T3,34,IOB_X1Y15,RIOB33_X43Y15,IO_L17N_T2_34
+T4,34,IOB_X1Y16,RIOB33_X43Y15,IO_L17P_T2_34
+T5,34,IOB_X1Y7,RIOB33_X43Y7,IO_L21N_T3_DQS_34
+T7,34,IOB_X1Y5,RIOB33_X43Y5,IO_L22N_T3_34
+T12,14,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_A05_D21_14
+T13,14,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_A09_D25_VREF_14
+T14,14,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_14
+T15,14,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_14
+T17,14,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_CSI_B_14
+T18,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+U1,34,IOB_X1Y19,RIOB33_X43Y19,IO_L15N_T2_DQS_34
+U2,34,IOB_X1Y20,RIOB33_X43Y19,IO_L15P_T2_DQS_34
+U4,34,IOB_X1Y14,RIOB33_X43Y13,IO_L18P_T2_34
+U5,34,IOB_X1Y9,RIOB33_X43Y9,IO_L20N_T3_34
+U6,34,IOB_X1Y10,RIOB33_X43Y9,IO_L20P_T3_34
+U7,34,IOB_X1Y4,RIOB33_X43Y3,IO_L23P_T3_34
+U9,14,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_A01_D17_14
+U10,14,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_14
+U11,14,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_A03_D19_14
+U12,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
+U14,14,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_A08_D24_14
+U15,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+U16,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+U17,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
+V2,34,IOB_X1Y17,RIOB33_X43Y17,IO_L16N_T2_34
+V3,34,IOB_X1Y18,RIOB33_X43Y17,IO_L16P_T2_34
+V4,34,IOB_X1Y13,RIOB33_X43Y13,IO_L18N_T2_34
+V6,34,IOB_X1Y3,RIOB33_X43Y3,IO_L23N_T3_34
+V7,34,IOB_X1Y1,RIOB33_X43Y1,IO_L24N_T3_34
+V8,34,IOB_X1Y2,RIOB33_X43Y1,IO_L24P_T3_34
+V9,14,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_A00_D16_14
+V11,14,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_A02_D18_14
+V12,14,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_14
+V13,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+V14,14,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_A07_D23_14
+V16,14,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_A12_D28_14
+V17,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
diff --git a/artix7/xc7a35tcsg325-2/part.json b/artix7/xc7a35tcsg325-2/part.json
new file mode 100644
index 0000000..258dcd2
--- /dev/null
+++ b/artix7/xc7a35tcsg325-2/part.json
@@ -0,0 +1,457 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "34": "X113Y26"
+ }
+}
diff --git a/artix7/xc7a35tcsg325-2/part.yaml b/artix7/xc7a35tcsg325-2/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tcsg325-2/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tcsg325-2L/package_pins.csv b/artix7/xc7a35tcsg325-2L/package_pins.csv
new file mode 100644
index 0000000..2477b7e
--- /dev/null
+++ b/artix7/xc7a35tcsg325-2L/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A3,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+A4,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+A9,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+A10,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+A12,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+A13,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+A14,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+A15,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+A17,15,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_ADV_B_15
+B1,216,OPAD_X0Y6,GTP_CHANNEL_3_X97Y150,MGTPTXN3_216
+B2,216,OPAD_X0Y7,GTP_CHANNEL_3_X97Y150,MGTPTXP3_216
+B5,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+B6,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+B9,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
+B10,15,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_AD9P_15
+B11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+B12,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+B14,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+B15,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+B16,15,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_15
+B17,15,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A27_15
+C3,216,IPAD_X1Y24,GTP_CHANNEL_2_X97Y139,MGTPRXN2_216
+C4,216,IPAD_X1Y25,GTP_CHANNEL_2_X97Y139,MGTPRXP2_216
+C8,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+C9,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+C11,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+C12,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+C13,15,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_15
+C14,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+C16,15,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_A28_15
+C17,15,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_A24_15
+C18,15,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_A23_15
+D1,216,OPAD_X0Y4,GTP_CHANNEL_2_X97Y139,MGTPTXN2_216
+D2,216,OPAD_X0Y5,GTP_CHANNEL_2_X97Y139,MGTPTXP2_216
+D5,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+D6,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+D8,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+D9,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+D10,15,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_15
+D11,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
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diff --git a/artix7/xc7a35tcsg325-2L/part.json b/artix7/xc7a35tcsg325-2L/part.json
new file mode 100644
index 0000000..258dcd2
--- /dev/null
+++ b/artix7/xc7a35tcsg325-2L/part.json
@@ -0,0 +1,457 @@
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+ "14": "X1Y26",
+ "15": "X1Y78",
+ "34": "X113Y26"
+ }
+}
diff --git a/artix7/xc7a35tcsg325-2L/part.yaml b/artix7/xc7a35tcsg325-2L/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tcsg325-2L/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tcsg325-3/package_pins.csv b/artix7/xc7a35tcsg325-3/package_pins.csv
new file mode 100644
index 0000000..2477b7e
--- /dev/null
+++ b/artix7/xc7a35tcsg325-3/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A3,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+A4,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+A9,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+A10,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+A12,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+A13,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+A14,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+A15,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+A17,15,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_ADV_B_15
+B1,216,OPAD_X0Y6,GTP_CHANNEL_3_X97Y150,MGTPTXN3_216
+B2,216,OPAD_X0Y7,GTP_CHANNEL_3_X97Y150,MGTPTXP3_216
+B5,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+B6,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+B9,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
+B10,15,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_AD9P_15
+B11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+B12,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+B14,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+B15,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+B16,15,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_15
+B17,15,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A27_15
+C3,216,IPAD_X1Y24,GTP_CHANNEL_2_X97Y139,MGTPRXN2_216
+C4,216,IPAD_X1Y25,GTP_CHANNEL_2_X97Y139,MGTPRXP2_216
+C8,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+C9,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+C11,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+C12,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+C13,15,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_15
+C14,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+C16,15,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_A28_15
+C17,15,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_A24_15
+C18,15,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_A23_15
+D1,216,OPAD_X0Y4,GTP_CHANNEL_2_X97Y139,MGTPTXN2_216
+D2,216,OPAD_X0Y5,GTP_CHANNEL_2_X97Y139,MGTPTXP2_216
+D5,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+D6,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+D8,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+D9,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+D10,15,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_15
+D11,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+D13,15,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_15
+D14,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+D15,15,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_15
+D16,15,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_15
+D18,15,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A25_15
+E3,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+E4,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+E13,15,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_15
+E15,15,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_15
+E16,15,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_15
+E17,15,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A26_15
+E18,15,IOB_X0Y51,LIOB33_X0Y51,IO_L24N_T3_RS0_15
+F1,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+F2,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+F14,15,IOB_X0Y55,LIOB33_X0Y55,IO_L22N_T3_A16_15
+F15,15,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_A18_15
+F17,15,IOB_X0Y52,LIOB33_X0Y51,IO_L24P_T3_RS1_15
+F18,15,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_A21_VREF_15
+G3,216,IPAD_X1Y30,GTP_CHANNEL_3_X97Y150,MGTPRXN3_216
+G4,216,IPAD_X1Y31,GTP_CHANNEL_3_X97Y150,MGTPRXP3_216
+G14,15,IOB_X0Y56,LIOB33_X0Y55,IO_L22P_T3_A17_15
+G15,15,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_15
+G16,15,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_A19_15
+G17,15,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_A22_15
+H1,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+H2,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+H14,15,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_15
+H16,15,IOB_X0Y60,LIOB33_X0Y59,IO_L20P_T3_A20_15
+H17,15,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_FOE_B_15
+H18,15,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_FWE_B_15
+J4,34,IOB_X1Y45,RIOB33_X43Y45,IO_L2N_T0_34
+J5,34,IOB_X1Y46,RIOB33_X43Y45,IO_L2P_T0_34
+J6,34,IOB_X1Y49,RIOB33_SING_X43Y49,IO_0_34
+J14,14,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_D06_14
+J15,14,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_D02_14
+J16,14,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_D03_14
+J18,14,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_PUDC_B_14
+K1,34,IOB_X1Y43,RIOB33_X43Y43,IO_L3N_T0_DQS_34
+K2,34,IOB_X1Y44,RIOB33_X43Y43,IO_L3P_T0_DQS_34
+K3,34,IOB_X1Y42,RIOB33_X43Y41,IO_L4P_T0_34
+K5,34,IOB_X1Y47,RIOB33_X43Y47,IO_L1N_T0_34
+K6,34,IOB_X1Y48,RIOB33_X43Y47,IO_L1P_T0_34
+K10,0,IPAD_X0Y0,MONITOR_BOT_X46Y79,VP_0
+K15,14,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_D07_14
+K16,14,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_D00_MOSI_14
+K17,14,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_D04_14
+K18,14,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_EMCCLK_14
+L2,34,IOB_X1Y41,RIOB33_X43Y41,IO_L4N_T0_34
+L3,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
+L4,34,IOB_X1Y40,RIOB33_X43Y39,IO_L5P_T0_34
+L5,34,IOB_X1Y38,RIOB33_X43Y37,IO_L6P_T0_34
+L9,0,IPAD_X0Y1,MONITOR_BOT_X46Y79,VN_0
+L14,14,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_14
+L15,14,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_FCS_B_14
+L17,14,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_D01_DIN_14
+L18,14,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_D05_14
+M1,34,IOB_X1Y35,RIOB33_X43Y35,IO_L7N_T1_34
+M2,34,IOB_X1Y36,RIOB33_X43Y35,IO_L7P_T1_34
+M4,34,IOB_X1Y30,RIOB33_X43Y29,IO_L10P_T1_34
+M5,34,IOB_X1Y37,RIOB33_X43Y37,IO_L6N_T0_VREF_34
+M6,34,IOB_X1Y34,RIOB33_X43Y33,IO_L8P_T1_34
+M14,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+M15,14,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_D08_VREF_14
+M16,14,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_D09_14
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+U9,14,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_A01_D17_14
+U10,14,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_14
+U11,14,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_A03_D19_14
+U12,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
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+U16,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+U17,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
+V2,34,IOB_X1Y17,RIOB33_X43Y17,IO_L16N_T2_34
+V3,34,IOB_X1Y18,RIOB33_X43Y17,IO_L16P_T2_34
+V4,34,IOB_X1Y13,RIOB33_X43Y13,IO_L18N_T2_34
+V6,34,IOB_X1Y3,RIOB33_X43Y3,IO_L23N_T3_34
+V7,34,IOB_X1Y1,RIOB33_X43Y1,IO_L24N_T3_34
+V8,34,IOB_X1Y2,RIOB33_X43Y1,IO_L24P_T3_34
+V9,14,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_A00_D16_14
+V11,14,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_A02_D18_14
+V12,14,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_14
+V13,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+V14,14,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_A07_D23_14
+V16,14,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_A12_D28_14
+V17,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
diff --git a/artix7/xc7a35tcsg325-3/part.json b/artix7/xc7a35tcsg325-3/part.json
new file mode 100644
index 0000000..258dcd2
--- /dev/null
+++ b/artix7/xc7a35tcsg325-3/part.json
@@ -0,0 +1,457 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
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+ },
+ "34": {
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+ },
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+ },
+ "36": {
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+ },
+ "41": {
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+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
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+ },
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+ },
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+ },
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+ "frame_count": 30
+ },
+ "19": {
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+ },
+ "20": {
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+ },
+ "21": {
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+ },
+ "22": {
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+ },
+ "23": {
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+ },
+ "24": {
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+ },
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+ },
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+ },
+ "27": {
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+ },
+ "28": {
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+ },
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+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
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+ },
+ "33": {
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+ },
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+ },
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+ },
+ "36": {
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+ },
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+ },
+ "38": {
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+ },
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+ },
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+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "34": "X113Y26"
+ }
+}
diff --git a/artix7/xc7a35tcsg325-3/part.yaml b/artix7/xc7a35tcsg325-3/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tcsg325-3/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tfgg484-1/package_pins.csv b/artix7/xc7a35tfgg484-1/package_pins.csv
new file mode 100644
index 0000000..f256b51
--- /dev/null
+++ b/artix7/xc7a35tfgg484-1/package_pins.csv
@@ -0,0 +1,273 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+A6,216,OPAD_X0Y4,GTP_CHANNEL_2_X97Y139,MGTPTXN2_216
+A8,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+A10,216,IPAD_X1Y24,GTP_CHANNEL_2_X97Y139,MGTPRXN2_216
+A13,16,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_16
+A14,16,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_16
+A15,16,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_16
+A19,16,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_16
+A20,16,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_16
+A21,16,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y36,RIOB33_X43Y35,IO_L7P_T1_34
+AA3,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y30,RIOB33_X43Y29,IO_L10P_T1_34
+AA6,34,IOB_X1Y13,RIOB33_X43Y13,IO_L18N_T2_34
+AA8,34,IOB_X1Y6,RIOB33_X43Y5,IO_L22P_T3_34
+AA18,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y35,RIOB33_X43Y35,IO_L7N_T1_34
+AB2,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
+AB3,34,IOB_X1Y34,RIOB33_X43Y33,IO_L8P_T1_34
+AB5,34,IOB_X1Y29,RIOB33_X43Y29,IO_L10N_T1_34
+AB6,34,IOB_X1Y9,RIOB33_X43Y9,IO_L20N_T3_34
+AB7,34,IOB_X1Y10,RIOB33_X43Y9,IO_L20P_T3_34
+AB8,34,IOB_X1Y5,RIOB33_X43Y5,IO_L22N_T3_34
+AB18,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+AB22,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
+B1,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+B6,216,OPAD_X0Y5,GTP_CHANNEL_2_X97Y139,MGTPTXP2_216
+B8,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+B10,216,IPAD_X1Y25,GTP_CHANNEL_2_X97Y139,MGTPRXP2_216
+B13,16,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_16
+B15,16,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_16
+B16,16,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_16
+B17,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+B18,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B20,16,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_16
+B21,16,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_16
+B22,16,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_16
+C2,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+C5,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+C7,216,OPAD_X0Y6,GTP_CHANNEL_3_X97Y150,MGTPTXN3_216
+C9,216,IPAD_X1Y30,GTP_CHANNEL_3_X97Y150,MGTPRXN3_216
+C11,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+C13,16,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_16
+C14,16,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_16
+C15,16,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_16
+C17,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+C18,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
+C19,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+C20,16,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_VREF_16
+C22,16,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_16
+D1,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+D2,35,IOB_X1Y91,RIOB33_X43Y91,IO_L4N_T0_35
+D5,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+D7,216,OPAD_X0Y7,GTP_CHANNEL_3_X97Y150,MGTPTXP3_216
+D9,216,IPAD_X1Y31,GTP_CHANNEL_3_X97Y150,MGTPRXP3_216
+D11,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+D14,16,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_16
+D15,16,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_16
+D16,16,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_16
+D17,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+D19,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+D20,16,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_16
+D21,16,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_16
+D22,16,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_16
+E1,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+E2,35,IOB_X1Y92,RIOB33_X43Y91,IO_L4P_T0_35
+E3,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+E6,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+E10,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+E13,16,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_16
+E14,16,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_16
+E16,16,IOB_X0Y140,LIOB33_X0Y139,IO_L5P_T0_16
+E17,16,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_16
+E18,16,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_16
+E19,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_16
+E22,16,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_16
+F1,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+F3,35,IOB_X1Y88,RIOB33_X43Y87,IO_L6P_T0_35
+F4,35,IOB_X1Y99,RIOB33_SING_X43Y99,IO_0_35
+F6,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+F10,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+F13,16,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_16
+F14,16,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_16
+F15,16,IOB_X0Y149,LIOB33_SING_X0Y149,IO_0_16
+F16,16,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_16
+F18,16,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_16
+F19,16,IOB_X0Y114,LIOB33_X0Y113,IO_L18P_T2_16
+F20,16,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_16
+F21,16,IOB_X0Y100,LIOB33_SING_X0Y100,IO_25_16
+G1,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+G2,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+G3,35,IOB_X1Y77,RIOB33_X43Y77,IO_L11N_T1_SRCC_35
+G4,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+G13,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+G15,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+G16,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+G17,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+G18,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+G20,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+G21,16,IOB_X0Y102,LIOB33_X0Y101,IO_L24P_T3_16
+G22,16,IOB_X0Y101,LIOB33_X0Y101,IO_L24N_T3_16
+H2,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+H3,35,IOB_X1Y78,RIOB33_X43Y77,IO_L11P_T1_SRCC_35
+H4,35,IOB_X1Y76,RIOB33_X43Y75,IO_L12P_T1_MRCC_35
+H5,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+H13,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+H14,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+H15,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+H17,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+H18,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+H19,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+H20,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+H22,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+J1,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+J2,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+J4,35,IOB_X1Y73,RIOB33_X43Y73,IO_L13N_T2_MRCC_35
+J5,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
+J6,35,IOB_X1Y65,RIOB33_X43Y65,IO_L17N_T2_35
+J14,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
+J15,15,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_AD9P_15
+J16,15,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_15
+J17,15,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_A18_15
+J19,15,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_15
+J20,15,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_15
+J21,15,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_15
+J22,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+K1,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+K2,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+K3,35,IOB_X1Y71,RIOB33_X43Y71,IO_L14N_T2_SRCC_35
+K4,35,IOB_X1Y74,RIOB33_X43Y73,IO_L13P_T2_MRCC_35
+K6,35,IOB_X1Y66,RIOB33_X43Y65,IO_L17P_T2_35
+K13,15,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_A22_15
+K14,15,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_A21_VREF_15
+K16,15,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_FWE_B_15
+K17,15,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_15
+K18,15,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_15
+K19,15,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_15
+K21,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+K22,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+L1,35,IOB_X1Y69,RIOB33_X43Y69,IO_L15N_T2_DQS_35
+L3,35,IOB_X1Y72,RIOB33_X43Y71,IO_L14P_T2_SRCC_35
+L4,35,IOB_X1Y63,RIOB33_X43Y63,IO_L18N_T2_35
+L5,35,IOB_X1Y64,RIOB33_X43Y63,IO_L18P_T2_35
+L6,35,IOB_X1Y50,RIOB33_SING_X43Y50,IO_25_35
+L10,0,IPAD_X0Y0,MONITOR_BOT_X46Y79,VP_0
+L13,15,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_A19_15
+L14,15,IOB_X0Y56,LIOB33_X0Y55,IO_L22P_T3_A17_15
+L15,15,IOB_X0Y55,LIOB33_X0Y55,IO_L22N_T3_A16_15
+L16,15,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_FOE_B_15
+L18,15,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A27_15
+L19,15,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_15
+L20,15,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_15
+L21,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
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+Y1,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
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+Y22,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
diff --git a/artix7/xc7a35tfgg484-1/part.json b/artix7/xc7a35tfgg484-1/part.json
new file mode 100644
index 0000000..4ecd6db
--- /dev/null
+++ b/artix7/xc7a35tfgg484-1/part.json
@@ -0,0 +1,459 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
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+ },
+ "25": {
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+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
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+ },
+ "28": {
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+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
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+ },
+ "31": {
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+ },
+ "32": {
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+ },
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+ },
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+ },
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+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "41": {
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+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a35tfgg484-1/part.yaml b/artix7/xc7a35tfgg484-1/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tfgg484-1/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
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+ 4: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
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+ 6: !<xilinx/xc7series/configuration_column>
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+ 7: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
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+ 10: !<xilinx/xc7series/configuration_column>
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+ 11: !<xilinx/xc7series/configuration_column>
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+ 12: !<xilinx/xc7series/configuration_column>
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+ 13: !<xilinx/xc7series/configuration_column>
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+ 14: !<xilinx/xc7series/configuration_column>
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+ 15: !<xilinx/xc7series/configuration_column>
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+ 16: !<xilinx/xc7series/configuration_column>
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+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
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+ 23: !<xilinx/xc7series/configuration_column>
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+ 24: !<xilinx/xc7series/configuration_column>
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+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
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+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 32: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
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+ 6: !<xilinx/xc7series/configuration_column>
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+ 7: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
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+ 10: !<xilinx/xc7series/configuration_column>
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+ 11: !<xilinx/xc7series/configuration_column>
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+ 12: !<xilinx/xc7series/configuration_column>
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+ 13: !<xilinx/xc7series/configuration_column>
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+ 14: !<xilinx/xc7series/configuration_column>
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+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tfgg484-2/package_pins.csv b/artix7/xc7a35tfgg484-2/package_pins.csv
new file mode 100644
index 0000000..f256b51
--- /dev/null
+++ b/artix7/xc7a35tfgg484-2/package_pins.csv
@@ -0,0 +1,273 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+A6,216,OPAD_X0Y4,GTP_CHANNEL_2_X97Y139,MGTPTXN2_216
+A8,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+A10,216,IPAD_X1Y24,GTP_CHANNEL_2_X97Y139,MGTPRXN2_216
+A13,16,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_16
+A14,16,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_16
+A15,16,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_16
+A19,16,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_16
+A20,16,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_16
+A21,16,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y36,RIOB33_X43Y35,IO_L7P_T1_34
+AA3,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y30,RIOB33_X43Y29,IO_L10P_T1_34
+AA6,34,IOB_X1Y13,RIOB33_X43Y13,IO_L18N_T2_34
+AA8,34,IOB_X1Y6,RIOB33_X43Y5,IO_L22P_T3_34
+AA18,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y35,RIOB33_X43Y35,IO_L7N_T1_34
+AB2,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
+AB3,34,IOB_X1Y34,RIOB33_X43Y33,IO_L8P_T1_34
+AB5,34,IOB_X1Y29,RIOB33_X43Y29,IO_L10N_T1_34
+AB6,34,IOB_X1Y9,RIOB33_X43Y9,IO_L20N_T3_34
+AB7,34,IOB_X1Y10,RIOB33_X43Y9,IO_L20P_T3_34
+AB8,34,IOB_X1Y5,RIOB33_X43Y5,IO_L22N_T3_34
+AB18,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+AB22,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
+B1,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+B6,216,OPAD_X0Y5,GTP_CHANNEL_2_X97Y139,MGTPTXP2_216
+B8,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+B10,216,IPAD_X1Y25,GTP_CHANNEL_2_X97Y139,MGTPRXP2_216
+B13,16,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_16
+B15,16,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_16
+B16,16,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_16
+B17,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+B18,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B20,16,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_16
+B21,16,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_16
+B22,16,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_16
+C2,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+C5,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+C7,216,OPAD_X0Y6,GTP_CHANNEL_3_X97Y150,MGTPTXN3_216
+C9,216,IPAD_X1Y30,GTP_CHANNEL_3_X97Y150,MGTPRXN3_216
+C11,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+C13,16,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_16
+C14,16,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_16
+C15,16,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_16
+C17,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+C18,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
+C19,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+C20,16,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_VREF_16
+C22,16,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_16
+D1,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+D2,35,IOB_X1Y91,RIOB33_X43Y91,IO_L4N_T0_35
+D5,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+D7,216,OPAD_X0Y7,GTP_CHANNEL_3_X97Y150,MGTPTXP3_216
+D9,216,IPAD_X1Y31,GTP_CHANNEL_3_X97Y150,MGTPRXP3_216
+D11,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+D14,16,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_16
+D15,16,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_16
+D16,16,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_16
+D17,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+D19,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+D20,16,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_16
+D21,16,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_16
+D22,16,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_16
+E1,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+E2,35,IOB_X1Y92,RIOB33_X43Y91,IO_L4P_T0_35
+E3,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+E6,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+E10,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+E13,16,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_16
+E14,16,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_16
+E16,16,IOB_X0Y140,LIOB33_X0Y139,IO_L5P_T0_16
+E17,16,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_16
+E18,16,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_16
+E19,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_16
+E22,16,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_16
+F1,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+F3,35,IOB_X1Y88,RIOB33_X43Y87,IO_L6P_T0_35
+F4,35,IOB_X1Y99,RIOB33_SING_X43Y99,IO_0_35
+F6,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+F10,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+F13,16,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_16
+F14,16,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_16
+F15,16,IOB_X0Y149,LIOB33_SING_X0Y149,IO_0_16
+F16,16,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_16
+F18,16,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_16
+F19,16,IOB_X0Y114,LIOB33_X0Y113,IO_L18P_T2_16
+F20,16,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_16
+F21,16,IOB_X0Y100,LIOB33_SING_X0Y100,IO_25_16
+G1,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+G2,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+G3,35,IOB_X1Y77,RIOB33_X43Y77,IO_L11N_T1_SRCC_35
+G4,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+G13,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+G15,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+G16,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+G17,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+G18,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+G20,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+G21,16,IOB_X0Y102,LIOB33_X0Y101,IO_L24P_T3_16
+G22,16,IOB_X0Y101,LIOB33_X0Y101,IO_L24N_T3_16
+H2,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+H3,35,IOB_X1Y78,RIOB33_X43Y77,IO_L11P_T1_SRCC_35
+H4,35,IOB_X1Y76,RIOB33_X43Y75,IO_L12P_T1_MRCC_35
+H5,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+H13,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+H14,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+H15,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+H17,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+H18,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+H19,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+H20,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+H22,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+J1,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+J2,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+J4,35,IOB_X1Y73,RIOB33_X43Y73,IO_L13N_T2_MRCC_35
+J5,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
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diff --git a/artix7/xc7a35tfgg484-2/part.json b/artix7/xc7a35tfgg484-2/part.json
new file mode 100644
index 0000000..4ecd6db
--- /dev/null
+++ b/artix7/xc7a35tfgg484-2/part.json
@@ -0,0 +1,459 @@
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+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a35tfgg484-2/part.yaml b/artix7/xc7a35tfgg484-2/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tfgg484-2/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tfgg484-2L/package_pins.csv b/artix7/xc7a35tfgg484-2L/package_pins.csv
new file mode 100644
index 0000000..f256b51
--- /dev/null
+++ b/artix7/xc7a35tfgg484-2L/package_pins.csv
@@ -0,0 +1,273 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+A6,216,OPAD_X0Y4,GTP_CHANNEL_2_X97Y139,MGTPTXN2_216
+A8,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+A10,216,IPAD_X1Y24,GTP_CHANNEL_2_X97Y139,MGTPRXN2_216
+A13,16,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_16
+A14,16,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_16
+A15,16,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_16
+A19,16,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_16
+A20,16,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_16
+A21,16,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y36,RIOB33_X43Y35,IO_L7P_T1_34
+AA3,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y30,RIOB33_X43Y29,IO_L10P_T1_34
+AA6,34,IOB_X1Y13,RIOB33_X43Y13,IO_L18N_T2_34
+AA8,34,IOB_X1Y6,RIOB33_X43Y5,IO_L22P_T3_34
+AA18,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y35,RIOB33_X43Y35,IO_L7N_T1_34
+AB2,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
+AB3,34,IOB_X1Y34,RIOB33_X43Y33,IO_L8P_T1_34
+AB5,34,IOB_X1Y29,RIOB33_X43Y29,IO_L10N_T1_34
+AB6,34,IOB_X1Y9,RIOB33_X43Y9,IO_L20N_T3_34
+AB7,34,IOB_X1Y10,RIOB33_X43Y9,IO_L20P_T3_34
+AB8,34,IOB_X1Y5,RIOB33_X43Y5,IO_L22N_T3_34
+AB18,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+AB22,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
+B1,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+B6,216,OPAD_X0Y5,GTP_CHANNEL_2_X97Y139,MGTPTXP2_216
+B8,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+B10,216,IPAD_X1Y25,GTP_CHANNEL_2_X97Y139,MGTPRXP2_216
+B13,16,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_16
+B15,16,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_16
+B16,16,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_16
+B17,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+B18,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B20,16,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_16
+B21,16,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_16
+B22,16,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_16
+C2,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+C5,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+C7,216,OPAD_X0Y6,GTP_CHANNEL_3_X97Y150,MGTPTXN3_216
+C9,216,IPAD_X1Y30,GTP_CHANNEL_3_X97Y150,MGTPRXN3_216
+C11,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+C13,16,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_16
+C14,16,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_16
+C15,16,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_16
+C17,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+C18,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
+C19,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+C20,16,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_VREF_16
+C22,16,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_16
+D1,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+D2,35,IOB_X1Y91,RIOB33_X43Y91,IO_L4N_T0_35
+D5,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+D7,216,OPAD_X0Y7,GTP_CHANNEL_3_X97Y150,MGTPTXP3_216
+D9,216,IPAD_X1Y31,GTP_CHANNEL_3_X97Y150,MGTPRXP3_216
+D11,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+D14,16,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_16
+D15,16,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_16
+D16,16,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_16
+D17,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+D19,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+D20,16,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_16
+D21,16,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_16
+D22,16,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_16
+E1,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+E2,35,IOB_X1Y92,RIOB33_X43Y91,IO_L4P_T0_35
+E3,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+E6,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+E10,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+E13,16,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_16
+E14,16,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_16
+E16,16,IOB_X0Y140,LIOB33_X0Y139,IO_L5P_T0_16
+E17,16,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_16
+E18,16,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_16
+E19,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_16
+E22,16,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_16
+F1,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+F3,35,IOB_X1Y88,RIOB33_X43Y87,IO_L6P_T0_35
+F4,35,IOB_X1Y99,RIOB33_SING_X43Y99,IO_0_35
+F6,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+F10,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
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diff --git a/artix7/xc7a35tfgg484-2L/part.json b/artix7/xc7a35tfgg484-2L/part.json
new file mode 100644
index 0000000..4ecd6db
--- /dev/null
+++ b/artix7/xc7a35tfgg484-2L/part.json
@@ -0,0 +1,459 @@
+{
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+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a35tfgg484-2L/part.yaml b/artix7/xc7a35tfgg484-2L/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tfgg484-2L/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tfgg484-3/package_pins.csv b/artix7/xc7a35tfgg484-3/package_pins.csv
new file mode 100644
index 0000000..f256b51
--- /dev/null
+++ b/artix7/xc7a35tfgg484-3/package_pins.csv
@@ -0,0 +1,273 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+A6,216,OPAD_X0Y4,GTP_CHANNEL_2_X97Y139,MGTPTXN2_216
+A8,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+A10,216,IPAD_X1Y24,GTP_CHANNEL_2_X97Y139,MGTPRXN2_216
+A13,16,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_16
+A14,16,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_16
+A15,16,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_16
+A19,16,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_16
+A20,16,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_16
+A21,16,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y36,RIOB33_X43Y35,IO_L7P_T1_34
+AA3,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y30,RIOB33_X43Y29,IO_L10P_T1_34
+AA6,34,IOB_X1Y13,RIOB33_X43Y13,IO_L18N_T2_34
+AA8,34,IOB_X1Y6,RIOB33_X43Y5,IO_L22P_T3_34
+AA18,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y35,RIOB33_X43Y35,IO_L7N_T1_34
+AB2,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
+AB3,34,IOB_X1Y34,RIOB33_X43Y33,IO_L8P_T1_34
+AB5,34,IOB_X1Y29,RIOB33_X43Y29,IO_L10N_T1_34
+AB6,34,IOB_X1Y9,RIOB33_X43Y9,IO_L20N_T3_34
+AB7,34,IOB_X1Y10,RIOB33_X43Y9,IO_L20P_T3_34
+AB8,34,IOB_X1Y5,RIOB33_X43Y5,IO_L22N_T3_34
+AB18,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+AB22,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
+B1,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+B6,216,OPAD_X0Y5,GTP_CHANNEL_2_X97Y139,MGTPTXP2_216
+B8,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+B10,216,IPAD_X1Y25,GTP_CHANNEL_2_X97Y139,MGTPRXP2_216
+B13,16,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_16
+B15,16,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_16
+B16,16,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_16
+B17,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+B18,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B20,16,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_16
+B21,16,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_16
+B22,16,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_16
+C2,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+C5,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+C7,216,OPAD_X0Y6,GTP_CHANNEL_3_X97Y150,MGTPTXN3_216
+C9,216,IPAD_X1Y30,GTP_CHANNEL_3_X97Y150,MGTPRXN3_216
+C11,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+C13,16,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_16
+C14,16,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_16
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+Y21,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+Y22,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
diff --git a/artix7/xc7a35tfgg484-3/part.json b/artix7/xc7a35tfgg484-3/part.json
new file mode 100644
index 0000000..4ecd6db
--- /dev/null
+++ b/artix7/xc7a35tfgg484-3/part.json
@@ -0,0 +1,459 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a35tfgg484-3/part.yaml b/artix7/xc7a35tfgg484-3/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tfgg484-3/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tftg256-2/package_pins.csv b/artix7/xc7a35tftg256-2/package_pins.csv
new file mode 100644
index 0000000..4a93b60
--- /dev/null
+++ b/artix7/xc7a35tftg256-2/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+A3,35,IOB_X1Y91,RIOB33_X43Y91,IO_L4N_T0_35
+A4,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+A5,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+A7,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+A8,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+A9,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+A10,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+A12,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+A13,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+A14,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+A15,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+B1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+B2,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
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diff --git a/artix7/xc7a35tftg256-2/part.json b/artix7/xc7a35tftg256-2/part.json
new file mode 100644
index 0000000..f1a2510
--- /dev/null
+++ b/artix7/xc7a35tftg256-2/part.json
@@ -0,0 +1,458 @@
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+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a35tftg256-2/part.yaml b/artix7/xc7a35tftg256-2/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tftg256-2/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tftg256-2L/package_pins.csv b/artix7/xc7a35tftg256-2L/package_pins.csv
new file mode 100644
index 0000000..4a93b60
--- /dev/null
+++ b/artix7/xc7a35tftg256-2L/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+A3,35,IOB_X1Y91,RIOB33_X43Y91,IO_L4N_T0_35
+A4,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+A5,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+A7,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+A8,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+A9,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+A10,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+A12,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+A13,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+A14,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+A15,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+B1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+B2,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+B4,35,IOB_X1Y92,RIOB33_X43Y91,IO_L4P_T0_35
+B5,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+B6,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+B7,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+B9,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
+B10,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+B11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+B12,15,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_AD9P_15
+B14,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+B15,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+B16,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+C1,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+C2,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+C3,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+C4,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+C6,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+C7,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+C8,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+C9,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+C11,15,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_15
+C12,15,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_15
+C13,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+C14,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+C16,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+D1,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+D3,35,IOB_X1Y77,RIOB33_X43Y77,IO_L11N_T1_SRCC_35
+D4,35,IOB_X1Y76,RIOB33_X43Y75,IO_L12P_T1_MRCC_35
+D5,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+D6,35,IOB_X1Y88,RIOB33_X43Y87,IO_L6P_T0_35
+D8,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+D9,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+D10,15,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_15
+D11,15,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_15
+D13,15,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_15
+D14,15,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_15
+D15,15,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_ADV_B_15
+D16,15,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A25_15
+E1,35,IOB_X1Y69,RIOB33_X43Y69,IO_L15N_T2_DQS_35
+E2,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
+E3,35,IOB_X1Y78,RIOB33_X43Y77,IO_L11P_T1_SRCC_35
+E5,35,IOB_X1Y73,RIOB33_X43Y73,IO_L13N_T2_MRCC_35
+E6,35,IOB_X1Y99,RIOB33_SING_X43Y99,IO_0_35
+E11,15,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_15
+E12,15,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_15
+E13,15,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_15
+E15,15,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_A23_15
+E16,15,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A26_15
+F2,35,IOB_X1Y70,RIOB33_X43Y69,IO_L15P_T2_DQS_35
+F3,35,IOB_X1Y71,RIOB33_X43Y71,IO_L14N_T2_SRCC_35
+F4,35,IOB_X1Y72,RIOB33_X43Y71,IO_L14P_T2_SRCC_35
+F5,35,IOB_X1Y74,RIOB33_X43Y73,IO_L13P_T2_MRCC_35
+F12,15,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_A28_15
+F13,15,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A27_15
+F14,15,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_A18_15
+F15,15,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_A24_15
+G1,35,IOB_X1Y65,RIOB33_X43Y65,IO_L17N_T2_35
+G2,35,IOB_X1Y66,RIOB33_X43Y65,IO_L17P_T2_35
+G4,35,IOB_X1Y67,RIOB33_X43Y67,IO_L16N_T2_35
+G5,35,IOB_X1Y68,RIOB33_X43Y67,IO_L16P_T2_35
+G11,15,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_15
+G12,15,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_A21_VREF_15
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+R13,14,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_CSI_B_14
+R15,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+R16,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
+T2,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
+T3,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+T4,34,IOB_X1Y32,RIOB33_X43Y31,IO_L9P_T1_DQS_34
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+T7,14,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_14
+T8,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+T9,14,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_A05_D21_14
+T10,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
+T12,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+T13,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
+T14,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+T15,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
diff --git a/artix7/xc7a35tftg256-2L/part.json b/artix7/xc7a35tftg256-2L/part.json
new file mode 100644
index 0000000..f1a2510
--- /dev/null
+++ b/artix7/xc7a35tftg256-2L/part.json
@@ -0,0 +1,458 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
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+ },
+ "25": {
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+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
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+ },
+ "29": {
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+ },
+ "30": {
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+ },
+ "31": {
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+ },
+ "32": {
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+ },
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+ },
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+ },
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+ "40": {
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+ },
+ "41": {
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+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
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+ },
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+ },
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+ },
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+ },
+ "18": {
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+ },
+ "19": {
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+ },
+ "20": {
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+ },
+ "21": {
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+ },
+ "22": {
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+ },
+ "23": {
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+ },
+ "24": {
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+ },
+ "25": {
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+ },
+ "26": {
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+ },
+ "27": {
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+ },
+ "28": {
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+ },
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+ },
+ "30": {
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+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
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+ },
+ "33": {
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+ },
+ "34": {
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+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a35tftg256-2L/part.yaml b/artix7/xc7a35tftg256-2L/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tftg256-2L/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a35tftg256-3/package_pins.csv b/artix7/xc7a35tftg256-3/package_pins.csv
new file mode 100644
index 0000000..4a93b60
--- /dev/null
+++ b/artix7/xc7a35tftg256-3/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+A3,35,IOB_X1Y91,RIOB33_X43Y91,IO_L4N_T0_35
+A4,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+A5,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+A7,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+A8,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+A9,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+A10,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+A12,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+A13,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+A14,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+A15,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+B1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+B2,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+B4,35,IOB_X1Y92,RIOB33_X43Y91,IO_L4P_T0_35
+B5,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+B6,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+B7,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+B9,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
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+B12,15,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_AD9P_15
+B14,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+B15,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+B16,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
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+C2,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+C3,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+C4,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+C6,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+C7,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+C8,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+C9,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+C11,15,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_15
+C12,15,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_15
+C13,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+C14,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+C16,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+D1,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+D3,35,IOB_X1Y77,RIOB33_X43Y77,IO_L11N_T1_SRCC_35
+D4,35,IOB_X1Y76,RIOB33_X43Y75,IO_L12P_T1_MRCC_35
+D5,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+D6,35,IOB_X1Y88,RIOB33_X43Y87,IO_L6P_T0_35
+D8,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+D9,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+D10,15,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_15
+D11,15,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_15
+D13,15,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_15
+D14,15,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_15
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+H8,0,IPAD_X0Y0,MONITOR_BOT_X46Y79,VP_0
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+J15,15,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_FOE_B_15
+J16,15,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_FWE_B_15
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+L12,14,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_FCS_B_14
+L13,14,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_D07_14
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+N14,14,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_14
+N16,14,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_D10_14
+P1,34,IOB_X1Y41,RIOB33_X43Y41,IO_L4N_T0_34
+P3,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
+P4,34,IOB_X1Y40,RIOB33_X43Y39,IO_L5P_T0_34
+P5,34,IOB_X1Y30,RIOB33_X43Y29,IO_L10P_T1_34
+P6,14,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_14
+P8,14,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_A08_D24_14
+P9,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
+P10,14,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_14
+P11,14,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_14
+P13,14,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_14
+P14,14,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_14
+P15,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+P16,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+R1,34,IOB_X1Y35,RIOB33_X43Y35,IO_L7N_T1_34
+R2,34,IOB_X1Y36,RIOB33_X43Y35,IO_L7P_T1_34
+R3,34,IOB_X1Y34,RIOB33_X43Y33,IO_L8P_T1_34
+R5,14,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_A03_D19_14
+R6,14,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_A01_D17_14
+R7,14,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_A00_D16_14
+R8,14,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_A07_D23_14
+R10,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+R11,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+R12,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+R13,14,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_CSI_B_14
+R15,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+R16,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
+T2,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
+T3,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+T4,34,IOB_X1Y32,RIOB33_X43Y31,IO_L9P_T1_DQS_34
+T5,14,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_A02_D18_14
+T7,14,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_14
+T8,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+T9,14,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_A05_D21_14
+T10,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
+T12,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+T13,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
+T14,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+T15,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
diff --git a/artix7/xc7a35tftg256-3/part.json b/artix7/xc7a35tftg256-3/part.json
new file mode 100644
index 0000000..f1a2510
--- /dev/null
+++ b/artix7/xc7a35tftg256-3/part.json
@@ -0,0 +1,458 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56807571,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a35tftg256-3/part.yaml b/artix7/xc7a35tftg256-3/part.yaml
new file mode 100644
index 0000000..ad2e0ba
--- /dev/null
+++ b/artix7/xc7a35tftg256-3/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362d093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tcpg236-1/package_pins.csv b/artix7/xc7a50tcpg236-1/package_pins.csv
new file mode 100644
index 0000000..55efcab
--- /dev/null
+++ b/artix7/xc7a50tcpg236-1/package_pins.csv
@@ -0,0 +1,121 @@
+pin,bank,site,tile,pin_function
+A2,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+A4,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+A6,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+A8,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+A10,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+A12,0,IPAD_X0Y0,MONITOR_BOT_X46Y79,VP_0
+A14,16,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_16
+A15,16,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_16
+A16,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+A17,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+A18,16,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_VREF_16
+B2,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+B4,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+B6,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+B8,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+B10,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+B13,0,IPAD_X0Y1,MONITOR_BOT_X46Y79,VN_0
+B15,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B16,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+B17,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+B18,16,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_16
+C15,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+C16,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
+C17,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+D1,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+D2,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+D17,14,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_14
+D18,14,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_D00_MOSI_14
+D19,14,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_D01_DIN_14
+E18,14,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_PUDC_B_14
+E19,14,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_EMCCLK_14
+F18,14,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_D03_14
+G2,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+G3,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+G17,14,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_D07_14
+G18,14,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_D02_14
+G19,14,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_D05_14
+H1,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+H2,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+H17,14,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_D06_14
+H19,14,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_D04_14
+J1,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+J2,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+J3,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+J17,14,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_D09_14
+J18,14,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_D10_14
+J19,14,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_D08_VREF_14
+K2,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+K3,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+K17,14,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_14
+K18,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+K19,14,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_FCS_B_14
+L1,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+L2,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+L3,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+L17,14,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_14
+L18,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+M1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+M2,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+M3,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+M18,14,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_14
+M19,14,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_14
+N1,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+N2,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
+N3,35,IOB_X1Y76,RIOB33_X43Y75,IO_L12P_T1_MRCC_35
+N17,14,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_14
+N18,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+N19,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
+P1,35,IOB_X1Y61,RIOB33_X43Y61,IO_L19N_T3_VREF_35
+P3,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+P17,14,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_14
+P18,14,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_14
+P19,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+R2,34,IOB_X1Y48,RIOB33_X43Y47,IO_L1P_T0_34
+R3,34,IOB_X1Y46,RIOB33_X43Y45,IO_L2P_T0_34
+R18,14,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_14
+R19,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
+T1,34,IOB_X1Y44,RIOB33_X43Y43,IO_L3P_T0_DQS_34
+T2,34,IOB_X1Y47,RIOB33_X43Y47,IO_L1N_T0_34
+T3,34,IOB_X1Y45,RIOB33_X43Y45,IO_L2N_T0_34
+T17,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+T18,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+U1,34,IOB_X1Y43,RIOB33_X43Y43,IO_L3N_T0_DQS_34
+U2,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+U3,34,IOB_X1Y32,RIOB33_X43Y31,IO_L9P_T1_DQS_34
+U4,34,IOB_X1Y28,RIOB33_X43Y27,IO_L11P_T1_SRCC_34
+U5,34,IOB_X1Y18,RIOB33_X43Y17,IO_L16P_T2_34
+U7,34,IOB_X1Y12,RIOB33_X43Y11,IO_L19P_T3_34
+U8,34,IOB_X1Y22,RIOB33_X43Y21,IO_L14P_T2_SRCC_34
+U14,14,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_14
+U15,14,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_A03_D19_14
+U16,14,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_A02_D18_14
+U17,14,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_A12_D28_14
+U18,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
+U19,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+V2,34,IOB_X1Y40,RIOB33_X43Y39,IO_L5P_T0_34
+V3,34,IOB_X1Y38,RIOB33_X43Y37,IO_L6P_T0_34
+V4,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+V5,34,IOB_X1Y17,RIOB33_X43Y17,IO_L16N_T2_34
+V7,34,IOB_X1Y11,RIOB33_X43Y11,IO_L19N_T3_VREF_34
+V8,34,IOB_X1Y21,RIOB33_X43Y21,IO_L14N_T2_SRCC_34
+V13,14,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_A01_D17_14
+V14,14,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_A00_D16_14
+V15,14,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_14
+V16,14,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_A10_D26_14
+V17,14,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_A09_D25_VREF_14
+V19,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+W2,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
+W3,34,IOB_X1Y37,RIOB33_X43Y37,IO_L6N_T0_VREF_34
+W4,34,IOB_X1Y25,RIOB33_X43Y25,IO_L12N_T1_MRCC_34
+W5,34,IOB_X1Y26,RIOB33_X43Y25,IO_L12P_T1_MRCC_34
+W6,34,IOB_X1Y23,RIOB33_X43Y23,IO_L13N_T2_MRCC_34
+W7,34,IOB_X1Y24,RIOB33_X43Y23,IO_L13P_T2_MRCC_34
+W13,14,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_A05_D21_14
+W14,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
+W15,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+W16,14,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_A08_D24_14
+W17,14,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_A07_D23_14
+W18,14,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_CSI_B_14
+W19,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
diff --git a/artix7/xc7a50tcpg236-1/part.json b/artix7/xc7a50tcpg236-1/part.json
new file mode 100644
index 0000000..8e72dea
--- /dev/null
+++ b/artix7/xc7a50tcpg236-1/part.json
@@ -0,0 +1,458 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a50tcpg236-1/part.yaml b/artix7/xc7a50tcpg236-1/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tcpg236-1/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tcpg236-2/package_pins.csv b/artix7/xc7a50tcpg236-2/package_pins.csv
new file mode 100644
index 0000000..55efcab
--- /dev/null
+++ b/artix7/xc7a50tcpg236-2/package_pins.csv
@@ -0,0 +1,121 @@
+pin,bank,site,tile,pin_function
+A2,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+A4,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+A6,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+A8,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+A10,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+A12,0,IPAD_X0Y0,MONITOR_BOT_X46Y79,VP_0
+A14,16,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_16
+A15,16,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_16
+A16,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+A17,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+A18,16,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_VREF_16
+B2,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+B4,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+B6,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+B8,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+B10,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+B13,0,IPAD_X0Y1,MONITOR_BOT_X46Y79,VN_0
+B15,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B16,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+B17,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+B18,16,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_16
+C15,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+C16,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
+C17,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+D1,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+D2,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+D17,14,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_14
+D18,14,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_D00_MOSI_14
+D19,14,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_D01_DIN_14
+E18,14,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_PUDC_B_14
+E19,14,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_EMCCLK_14
+F18,14,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_D03_14
+G2,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+G3,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+G17,14,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_D07_14
+G18,14,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_D02_14
+G19,14,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_D05_14
+H1,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+H2,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+H17,14,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_D06_14
+H19,14,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_D04_14
+J1,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+J2,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+J3,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+J17,14,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_D09_14
+J18,14,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_D10_14
+J19,14,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_D08_VREF_14
+K2,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+K3,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+K17,14,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_14
+K18,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+K19,14,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_FCS_B_14
+L1,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+L2,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+L3,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+L17,14,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_14
+L18,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+M1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+M2,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+M3,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+M18,14,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_14
+M19,14,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_14
+N1,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+N2,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
+N3,35,IOB_X1Y76,RIOB33_X43Y75,IO_L12P_T1_MRCC_35
+N17,14,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_14
+N18,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+N19,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
+P1,35,IOB_X1Y61,RIOB33_X43Y61,IO_L19N_T3_VREF_35
+P3,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+P17,14,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_14
+P18,14,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_14
+P19,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+R2,34,IOB_X1Y48,RIOB33_X43Y47,IO_L1P_T0_34
+R3,34,IOB_X1Y46,RIOB33_X43Y45,IO_L2P_T0_34
+R18,14,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_14
+R19,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
+T1,34,IOB_X1Y44,RIOB33_X43Y43,IO_L3P_T0_DQS_34
+T2,34,IOB_X1Y47,RIOB33_X43Y47,IO_L1N_T0_34
+T3,34,IOB_X1Y45,RIOB33_X43Y45,IO_L2N_T0_34
+T17,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+T18,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+U1,34,IOB_X1Y43,RIOB33_X43Y43,IO_L3N_T0_DQS_34
+U2,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+U3,34,IOB_X1Y32,RIOB33_X43Y31,IO_L9P_T1_DQS_34
+U4,34,IOB_X1Y28,RIOB33_X43Y27,IO_L11P_T1_SRCC_34
+U5,34,IOB_X1Y18,RIOB33_X43Y17,IO_L16P_T2_34
+U7,34,IOB_X1Y12,RIOB33_X43Y11,IO_L19P_T3_34
+U8,34,IOB_X1Y22,RIOB33_X43Y21,IO_L14P_T2_SRCC_34
+U14,14,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_14
+U15,14,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_A03_D19_14
+U16,14,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_A02_D18_14
+U17,14,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_A12_D28_14
+U18,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
+U19,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+V2,34,IOB_X1Y40,RIOB33_X43Y39,IO_L5P_T0_34
+V3,34,IOB_X1Y38,RIOB33_X43Y37,IO_L6P_T0_34
+V4,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+V5,34,IOB_X1Y17,RIOB33_X43Y17,IO_L16N_T2_34
+V7,34,IOB_X1Y11,RIOB33_X43Y11,IO_L19N_T3_VREF_34
+V8,34,IOB_X1Y21,RIOB33_X43Y21,IO_L14N_T2_SRCC_34
+V13,14,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_A01_D17_14
+V14,14,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_A00_D16_14
+V15,14,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_14
+V16,14,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_A10_D26_14
+V17,14,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_A09_D25_VREF_14
+V19,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+W2,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
+W3,34,IOB_X1Y37,RIOB33_X43Y37,IO_L6N_T0_VREF_34
+W4,34,IOB_X1Y25,RIOB33_X43Y25,IO_L12N_T1_MRCC_34
+W5,34,IOB_X1Y26,RIOB33_X43Y25,IO_L12P_T1_MRCC_34
+W6,34,IOB_X1Y23,RIOB33_X43Y23,IO_L13N_T2_MRCC_34
+W7,34,IOB_X1Y24,RIOB33_X43Y23,IO_L13P_T2_MRCC_34
+W13,14,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_A05_D21_14
+W14,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
+W15,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+W16,14,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_A08_D24_14
+W17,14,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_A07_D23_14
+W18,14,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_CSI_B_14
+W19,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
diff --git a/artix7/xc7a50tcpg236-2/part.json b/artix7/xc7a50tcpg236-2/part.json
new file mode 100644
index 0000000..8e72dea
--- /dev/null
+++ b/artix7/xc7a50tcpg236-2/part.json
@@ -0,0 +1,458 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a50tcpg236-2/part.yaml b/artix7/xc7a50tcpg236-2/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tcpg236-2/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tcpg236-2L/package_pins.csv b/artix7/xc7a50tcpg236-2L/package_pins.csv
new file mode 100644
index 0000000..55efcab
--- /dev/null
+++ b/artix7/xc7a50tcpg236-2L/package_pins.csv
@@ -0,0 +1,121 @@
+pin,bank,site,tile,pin_function
+A2,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+A4,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+A6,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+A8,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+A10,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+A12,0,IPAD_X0Y0,MONITOR_BOT_X46Y79,VP_0
+A14,16,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_16
+A15,16,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_16
+A16,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+A17,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+A18,16,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_VREF_16
+B2,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+B4,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+B6,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+B8,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+B10,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+B13,0,IPAD_X0Y1,MONITOR_BOT_X46Y79,VN_0
+B15,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B16,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+B17,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+B18,16,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_16
+C15,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+C16,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
+C17,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+D1,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+D2,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+D17,14,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_14
+D18,14,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_D00_MOSI_14
+D19,14,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_D01_DIN_14
+E18,14,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_PUDC_B_14
+E19,14,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_EMCCLK_14
+F18,14,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_D03_14
+G2,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+G3,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+G17,14,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_D07_14
+G18,14,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_D02_14
+G19,14,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_D05_14
+H1,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+H2,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+H17,14,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_D06_14
+H19,14,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_D04_14
+J1,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+J2,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+J3,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+J17,14,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_D09_14
+J18,14,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_D10_14
+J19,14,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_D08_VREF_14
+K2,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+K3,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+K17,14,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_14
+K18,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+K19,14,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_FCS_B_14
+L1,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+L2,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+L3,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+L17,14,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_14
+L18,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+M1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+M2,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+M3,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+M18,14,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_14
+M19,14,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_14
+N1,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+N2,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
+N3,35,IOB_X1Y76,RIOB33_X43Y75,IO_L12P_T1_MRCC_35
+N17,14,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_14
+N18,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+N19,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
+P1,35,IOB_X1Y61,RIOB33_X43Y61,IO_L19N_T3_VREF_35
+P3,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+P17,14,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_14
+P18,14,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_14
+P19,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+R2,34,IOB_X1Y48,RIOB33_X43Y47,IO_L1P_T0_34
+R3,34,IOB_X1Y46,RIOB33_X43Y45,IO_L2P_T0_34
+R18,14,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_14
+R19,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
+T1,34,IOB_X1Y44,RIOB33_X43Y43,IO_L3P_T0_DQS_34
+T2,34,IOB_X1Y47,RIOB33_X43Y47,IO_L1N_T0_34
+T3,34,IOB_X1Y45,RIOB33_X43Y45,IO_L2N_T0_34
+T17,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+T18,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+U1,34,IOB_X1Y43,RIOB33_X43Y43,IO_L3N_T0_DQS_34
+U2,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+U3,34,IOB_X1Y32,RIOB33_X43Y31,IO_L9P_T1_DQS_34
+U4,34,IOB_X1Y28,RIOB33_X43Y27,IO_L11P_T1_SRCC_34
+U5,34,IOB_X1Y18,RIOB33_X43Y17,IO_L16P_T2_34
+U7,34,IOB_X1Y12,RIOB33_X43Y11,IO_L19P_T3_34
+U8,34,IOB_X1Y22,RIOB33_X43Y21,IO_L14P_T2_SRCC_34
+U14,14,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_14
+U15,14,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_A03_D19_14
+U16,14,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_A02_D18_14
+U17,14,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_A12_D28_14
+U18,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
+U19,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+V2,34,IOB_X1Y40,RIOB33_X43Y39,IO_L5P_T0_34
+V3,34,IOB_X1Y38,RIOB33_X43Y37,IO_L6P_T0_34
+V4,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+V5,34,IOB_X1Y17,RIOB33_X43Y17,IO_L16N_T2_34
+V7,34,IOB_X1Y11,RIOB33_X43Y11,IO_L19N_T3_VREF_34
+V8,34,IOB_X1Y21,RIOB33_X43Y21,IO_L14N_T2_SRCC_34
+V13,14,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_A01_D17_14
+V14,14,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_A00_D16_14
+V15,14,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_14
+V16,14,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_A10_D26_14
+V17,14,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_A09_D25_VREF_14
+V19,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+W2,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
+W3,34,IOB_X1Y37,RIOB33_X43Y37,IO_L6N_T0_VREF_34
+W4,34,IOB_X1Y25,RIOB33_X43Y25,IO_L12N_T1_MRCC_34
+W5,34,IOB_X1Y26,RIOB33_X43Y25,IO_L12P_T1_MRCC_34
+W6,34,IOB_X1Y23,RIOB33_X43Y23,IO_L13N_T2_MRCC_34
+W7,34,IOB_X1Y24,RIOB33_X43Y23,IO_L13P_T2_MRCC_34
+W13,14,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_A05_D21_14
+W14,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
+W15,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+W16,14,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_A08_D24_14
+W17,14,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_A07_D23_14
+W18,14,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_CSI_B_14
+W19,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
diff --git a/artix7/xc7a50tcpg236-2L/part.json b/artix7/xc7a50tcpg236-2L/part.json
new file mode 100644
index 0000000..8e72dea
--- /dev/null
+++ b/artix7/xc7a50tcpg236-2L/part.json
@@ -0,0 +1,458 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a50tcpg236-2L/part.yaml b/artix7/xc7a50tcpg236-2L/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tcpg236-2L/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tcpg236-3/package_pins.csv b/artix7/xc7a50tcpg236-3/package_pins.csv
new file mode 100644
index 0000000..55efcab
--- /dev/null
+++ b/artix7/xc7a50tcpg236-3/package_pins.csv
@@ -0,0 +1,121 @@
+pin,bank,site,tile,pin_function
+A2,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+A4,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+A6,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+A8,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+A10,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+A12,0,IPAD_X0Y0,MONITOR_BOT_X46Y79,VP_0
+A14,16,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_16
+A15,16,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_16
+A16,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+A17,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+A18,16,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_VREF_16
+B2,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+B4,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+B6,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+B8,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+B10,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+B13,0,IPAD_X0Y1,MONITOR_BOT_X46Y79,VN_0
+B15,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B16,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+B17,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+B18,16,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_16
+C15,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+C16,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
+C17,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+D1,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+D2,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+D17,14,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_14
+D18,14,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_D00_MOSI_14
+D19,14,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_D01_DIN_14
+E18,14,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_PUDC_B_14
+E19,14,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_EMCCLK_14
+F18,14,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_D03_14
+G2,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+G3,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+G17,14,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_D07_14
+G18,14,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_D02_14
+G19,14,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_D05_14
+H1,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+H2,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+H17,14,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_D06_14
+H19,14,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_D04_14
+J1,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+J2,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+J3,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+J17,14,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_D09_14
+J18,14,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_D10_14
+J19,14,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_D08_VREF_14
+K2,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+K3,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+K17,14,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_14
+K18,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+K19,14,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_FCS_B_14
+L1,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+L2,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+L3,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+L17,14,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_14
+L18,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+M1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+M2,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+M3,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+M18,14,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_14
+M19,14,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_14
+N1,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+N2,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
+N3,35,IOB_X1Y76,RIOB33_X43Y75,IO_L12P_T1_MRCC_35
+N17,14,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_14
+N18,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+N19,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
+P1,35,IOB_X1Y61,RIOB33_X43Y61,IO_L19N_T3_VREF_35
+P3,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+P17,14,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_14
+P18,14,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_14
+P19,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+R2,34,IOB_X1Y48,RIOB33_X43Y47,IO_L1P_T0_34
+R3,34,IOB_X1Y46,RIOB33_X43Y45,IO_L2P_T0_34
+R18,14,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_14
+R19,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
+T1,34,IOB_X1Y44,RIOB33_X43Y43,IO_L3P_T0_DQS_34
+T2,34,IOB_X1Y47,RIOB33_X43Y47,IO_L1N_T0_34
+T3,34,IOB_X1Y45,RIOB33_X43Y45,IO_L2N_T0_34
+T17,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+T18,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+U1,34,IOB_X1Y43,RIOB33_X43Y43,IO_L3N_T0_DQS_34
+U2,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+U3,34,IOB_X1Y32,RIOB33_X43Y31,IO_L9P_T1_DQS_34
+U4,34,IOB_X1Y28,RIOB33_X43Y27,IO_L11P_T1_SRCC_34
+U5,34,IOB_X1Y18,RIOB33_X43Y17,IO_L16P_T2_34
+U7,34,IOB_X1Y12,RIOB33_X43Y11,IO_L19P_T3_34
+U8,34,IOB_X1Y22,RIOB33_X43Y21,IO_L14P_T2_SRCC_34
+U14,14,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_14
+U15,14,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_A03_D19_14
+U16,14,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_A02_D18_14
+U17,14,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_A12_D28_14
+U18,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
+U19,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+V2,34,IOB_X1Y40,RIOB33_X43Y39,IO_L5P_T0_34
+V3,34,IOB_X1Y38,RIOB33_X43Y37,IO_L6P_T0_34
+V4,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+V5,34,IOB_X1Y17,RIOB33_X43Y17,IO_L16N_T2_34
+V7,34,IOB_X1Y11,RIOB33_X43Y11,IO_L19N_T3_VREF_34
+V8,34,IOB_X1Y21,RIOB33_X43Y21,IO_L14N_T2_SRCC_34
+V13,14,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_A01_D17_14
+V14,14,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_A00_D16_14
+V15,14,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_14
+V16,14,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_A10_D26_14
+V17,14,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_A09_D25_VREF_14
+V19,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+W2,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
+W3,34,IOB_X1Y37,RIOB33_X43Y37,IO_L6N_T0_VREF_34
+W4,34,IOB_X1Y25,RIOB33_X43Y25,IO_L12N_T1_MRCC_34
+W5,34,IOB_X1Y26,RIOB33_X43Y25,IO_L12P_T1_MRCC_34
+W6,34,IOB_X1Y23,RIOB33_X43Y23,IO_L13N_T2_MRCC_34
+W7,34,IOB_X1Y24,RIOB33_X43Y23,IO_L13P_T2_MRCC_34
+W13,14,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_A05_D21_14
+W14,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
+W15,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+W16,14,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_A08_D24_14
+W17,14,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_A07_D23_14
+W18,14,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_CSI_B_14
+W19,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
diff --git a/artix7/xc7a50tcpg236-3/part.json b/artix7/xc7a50tcpg236-3/part.json
new file mode 100644
index 0000000..8e72dea
--- /dev/null
+++ b/artix7/xc7a50tcpg236-3/part.json
@@ -0,0 +1,458 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a50tcpg236-3/part.yaml b/artix7/xc7a50tcpg236-3/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tcpg236-3/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tcsg324-1/package_pins.csv b/artix7/xc7a50tcsg324-1/package_pins.csv
new file mode 100644
index 0000000..c4786e7
--- /dev/null
+++ b/artix7/xc7a50tcsg324-1/package_pins.csv
@@ -0,0 +1,213 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
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diff --git a/artix7/xc7a50tcsg324-1/part.json b/artix7/xc7a50tcsg324-1/part.json
new file mode 100644
index 0000000..a20d3a0
--- /dev/null
+++ b/artix7/xc7a50tcsg324-1/part.json
@@ -0,0 +1,459 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a50tcsg324-1/part.yaml b/artix7/xc7a50tcsg324-1/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tcsg324-1/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tcsg324-2/package_pins.csv b/artix7/xc7a50tcsg324-2/package_pins.csv
new file mode 100644
index 0000000..c4786e7
--- /dev/null
+++ b/artix7/xc7a50tcsg324-2/package_pins.csv
@@ -0,0 +1,213 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+A3,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+A4,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+A5,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+A6,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+A8,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+A9,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+A10,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+A11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+A13,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+A14,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+A15,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+A16,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+A18,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+B1,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+B2,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+B3,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
+B4,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
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diff --git a/artix7/xc7a50tcsg324-2/part.json b/artix7/xc7a50tcsg324-2/part.json
new file mode 100644
index 0000000..a20d3a0
--- /dev/null
+++ b/artix7/xc7a50tcsg324-2/part.json
@@ -0,0 +1,459 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
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+ },
+ "1": {
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+ },
+ "2": {
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+ }
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+ },
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+ },
+ "1": {
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+ },
+ "2": {
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+ },
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+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a50tcsg324-2/part.yaml b/artix7/xc7a50tcsg324-2/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tcsg324-2/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tcsg324-2L/package_pins.csv b/artix7/xc7a50tcsg324-2L/package_pins.csv
new file mode 100644
index 0000000..c4786e7
--- /dev/null
+++ b/artix7/xc7a50tcsg324-2L/package_pins.csv
@@ -0,0 +1,213 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+A3,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+A4,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+A5,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+A6,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+A8,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+A9,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+A10,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+A11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+A13,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+A14,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+A15,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+A16,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+A18,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+B1,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+B2,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+B3,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
+B4,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+B6,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+B7,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+B8,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+B9,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B11,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+B12,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+B13,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+B14,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+B16,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+B17,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+B18,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+C1,35,IOB_X1Y67,RIOB33_X43Y67,IO_L16N_T2_35
+C2,35,IOB_X1Y68,RIOB33_X43Y67,IO_L16P_T2_35
+C4,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+C5,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+C6,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+C7,35,IOB_X1Y91,RIOB33_X43Y91,IO_L4N_T0_35
+C9,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+C10,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+C11,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
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diff --git a/artix7/xc7a50tcsg324-2L/part.json b/artix7/xc7a50tcsg324-2L/part.json
new file mode 100644
index 0000000..a20d3a0
--- /dev/null
+++ b/artix7/xc7a50tcsg324-2L/part.json
@@ -0,0 +1,459 @@
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+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a50tcsg324-2L/part.yaml b/artix7/xc7a50tcsg324-2L/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tcsg324-2L/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tcsg324-3/package_pins.csv b/artix7/xc7a50tcsg324-3/package_pins.csv
new file mode 100644
index 0000000..c4786e7
--- /dev/null
+++ b/artix7/xc7a50tcsg324-3/package_pins.csv
@@ -0,0 +1,213 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+A3,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+A4,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+A5,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+A6,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+A8,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+A9,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+A10,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+A11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+A13,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+A14,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+A15,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+A16,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+A18,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+B1,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+B2,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+B3,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
+B4,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+B6,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+B7,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+B8,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+B9,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B11,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+B12,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+B13,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+B14,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+B16,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+B17,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+B18,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+C1,35,IOB_X1Y67,RIOB33_X43Y67,IO_L16N_T2_35
+C2,35,IOB_X1Y68,RIOB33_X43Y67,IO_L16P_T2_35
+C4,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+C5,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+C6,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+C7,35,IOB_X1Y91,RIOB33_X43Y91,IO_L4N_T0_35
+C9,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+C10,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+C11,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
+C12,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
+C14,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+C15,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+C16,15,IOB_X0Y60,LIOB33_X0Y59,IO_L20P_T3_A20_15
+C17,15,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_A19_15
+D2,35,IOB_X1Y71,RIOB33_X43Y71,IO_L14N_T2_SRCC_35
+D3,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+D4,35,IOB_X1Y77,RIOB33_X43Y77,IO_L11N_T1_SRCC_35
+D5,35,IOB_X1Y78,RIOB33_X43Y77,IO_L11P_T1_SRCC_35
+D7,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+D8,35,IOB_X1Y92,RIOB33_X43Y91,IO_L4P_T0_35
+D9,16,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_16
+D10,16,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_VREF_16
+D12,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+D13,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+D14,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+D15,15,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_15
+D17,15,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A27_15
+D18,15,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_A18_15
+E1,35,IOB_X1Y63,RIOB33_X43Y63,IO_L18N_T2_35
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diff --git a/artix7/xc7a50tcsg324-3/part.json b/artix7/xc7a50tcsg324-3/part.json
new file mode 100644
index 0000000..a20d3a0
--- /dev/null
+++ b/artix7/xc7a50tcsg324-3/part.json
@@ -0,0 +1,459 @@
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+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a50tcsg324-3/part.yaml b/artix7/xc7a50tcsg324-3/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tcsg324-3/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tcsg325-1/package_pins.csv b/artix7/xc7a50tcsg325-1/package_pins.csv
new file mode 100644
index 0000000..2477b7e
--- /dev/null
+++ b/artix7/xc7a50tcsg325-1/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A3,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+A4,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+A9,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+A10,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+A12,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+A13,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+A14,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+A15,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+A17,15,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_ADV_B_15
+B1,216,OPAD_X0Y6,GTP_CHANNEL_3_X97Y150,MGTPTXN3_216
+B2,216,OPAD_X0Y7,GTP_CHANNEL_3_X97Y150,MGTPTXP3_216
+B5,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+B6,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+B9,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
+B10,15,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_AD9P_15
+B11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+B12,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+B14,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+B15,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+B16,15,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_15
+B17,15,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A27_15
+C3,216,IPAD_X1Y24,GTP_CHANNEL_2_X97Y139,MGTPRXN2_216
+C4,216,IPAD_X1Y25,GTP_CHANNEL_2_X97Y139,MGTPRXP2_216
+C8,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+C9,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+C11,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+C12,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+C13,15,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_15
+C14,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+C16,15,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_A28_15
+C17,15,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_A24_15
+C18,15,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_A23_15
+D1,216,OPAD_X0Y4,GTP_CHANNEL_2_X97Y139,MGTPTXN2_216
+D2,216,OPAD_X0Y5,GTP_CHANNEL_2_X97Y139,MGTPTXP2_216
+D5,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+D6,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+D8,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+D9,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+D10,15,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_15
+D11,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+D13,15,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_15
+D14,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+D15,15,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_15
+D16,15,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_15
+D18,15,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A25_15
+E3,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+E4,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+E13,15,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_15
+E15,15,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_15
+E16,15,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_15
+E17,15,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A26_15
+E18,15,IOB_X0Y51,LIOB33_X0Y51,IO_L24N_T3_RS0_15
+F1,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+F2,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+F14,15,IOB_X0Y55,LIOB33_X0Y55,IO_L22N_T3_A16_15
+F15,15,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_A18_15
+F17,15,IOB_X0Y52,LIOB33_X0Y51,IO_L24P_T3_RS1_15
+F18,15,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_A21_VREF_15
+G3,216,IPAD_X1Y30,GTP_CHANNEL_3_X97Y150,MGTPRXN3_216
+G4,216,IPAD_X1Y31,GTP_CHANNEL_3_X97Y150,MGTPRXP3_216
+G14,15,IOB_X0Y56,LIOB33_X0Y55,IO_L22P_T3_A17_15
+G15,15,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_15
+G16,15,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_A19_15
+G17,15,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_A22_15
+H1,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+H2,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+H14,15,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_15
+H16,15,IOB_X0Y60,LIOB33_X0Y59,IO_L20P_T3_A20_15
+H17,15,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_FOE_B_15
+H18,15,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_FWE_B_15
+J4,34,IOB_X1Y45,RIOB33_X43Y45,IO_L2N_T0_34
+J5,34,IOB_X1Y46,RIOB33_X43Y45,IO_L2P_T0_34
+J6,34,IOB_X1Y49,RIOB33_SING_X43Y49,IO_0_34
+J14,14,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_D06_14
+J15,14,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_D02_14
+J16,14,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_D03_14
+J18,14,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_PUDC_B_14
+K1,34,IOB_X1Y43,RIOB33_X43Y43,IO_L3N_T0_DQS_34
+K2,34,IOB_X1Y44,RIOB33_X43Y43,IO_L3P_T0_DQS_34
+K3,34,IOB_X1Y42,RIOB33_X43Y41,IO_L4P_T0_34
+K5,34,IOB_X1Y47,RIOB33_X43Y47,IO_L1N_T0_34
+K6,34,IOB_X1Y48,RIOB33_X43Y47,IO_L1P_T0_34
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+V3,34,IOB_X1Y18,RIOB33_X43Y17,IO_L16P_T2_34
+V4,34,IOB_X1Y13,RIOB33_X43Y13,IO_L18N_T2_34
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+V17,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
diff --git a/artix7/xc7a50tcsg325-1/part.json b/artix7/xc7a50tcsg325-1/part.json
new file mode 100644
index 0000000..a3f2702
--- /dev/null
+++ b/artix7/xc7a50tcsg325-1/part.json
@@ -0,0 +1,457 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
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+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
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+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
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+ },
+ "23": {
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+ },
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+ },
+ "25": {
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+ },
+ "26": {
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+ },
+ "27": {
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+ },
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+ },
+ "29": {
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+ },
+ "30": {
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+ },
+ "31": {
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+ },
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+ },
+ "41": {
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+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
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+ },
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+ },
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+ },
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+ },
+ "19": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "30": {
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+ },
+ "31": {
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+ },
+ "32": {
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+ },
+ "33": {
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+ },
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+ },
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+ },
+ "36": {
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+ },
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+ },
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+ },
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+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "34": "X113Y26"
+ }
+}
diff --git a/artix7/xc7a50tcsg325-1/part.yaml b/artix7/xc7a50tcsg325-1/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tcsg325-1/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tcsg325-2/package_pins.csv b/artix7/xc7a50tcsg325-2/package_pins.csv
new file mode 100644
index 0000000..2477b7e
--- /dev/null
+++ b/artix7/xc7a50tcsg325-2/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A3,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+A4,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+A9,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+A10,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+A12,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+A13,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+A14,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+A15,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+A17,15,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_ADV_B_15
+B1,216,OPAD_X0Y6,GTP_CHANNEL_3_X97Y150,MGTPTXN3_216
+B2,216,OPAD_X0Y7,GTP_CHANNEL_3_X97Y150,MGTPTXP3_216
+B5,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+B6,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+B9,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
+B10,15,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_AD9P_15
+B11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+B12,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+B14,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+B15,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+B16,15,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_15
+B17,15,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A27_15
+C3,216,IPAD_X1Y24,GTP_CHANNEL_2_X97Y139,MGTPRXN2_216
+C4,216,IPAD_X1Y25,GTP_CHANNEL_2_X97Y139,MGTPRXP2_216
+C8,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+C9,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+C11,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+C12,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+C13,15,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_15
+C14,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+C16,15,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_A28_15
+C17,15,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_A24_15
+C18,15,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_A23_15
+D1,216,OPAD_X0Y4,GTP_CHANNEL_2_X97Y139,MGTPTXN2_216
+D2,216,OPAD_X0Y5,GTP_CHANNEL_2_X97Y139,MGTPTXP2_216
+D5,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+D6,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+D8,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+D9,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+D10,15,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_15
+D11,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+D13,15,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_15
+D14,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+D15,15,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_15
+D16,15,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_15
+D18,15,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A25_15
+E3,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+E4,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+E13,15,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_15
+E15,15,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_15
+E16,15,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_15
+E17,15,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A26_15
+E18,15,IOB_X0Y51,LIOB33_X0Y51,IO_L24N_T3_RS0_15
+F1,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+F2,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+F14,15,IOB_X0Y55,LIOB33_X0Y55,IO_L22N_T3_A16_15
+F15,15,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_A18_15
+F17,15,IOB_X0Y52,LIOB33_X0Y51,IO_L24P_T3_RS1_15
+F18,15,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_A21_VREF_15
+G3,216,IPAD_X1Y30,GTP_CHANNEL_3_X97Y150,MGTPRXN3_216
+G4,216,IPAD_X1Y31,GTP_CHANNEL_3_X97Y150,MGTPRXP3_216
+G14,15,IOB_X0Y56,LIOB33_X0Y55,IO_L22P_T3_A17_15
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+G16,15,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_A19_15
+G17,15,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_A22_15
+H1,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+H2,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
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+H17,15,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_FOE_B_15
+H18,15,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_FWE_B_15
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+J16,14,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_D03_14
+J18,14,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_PUDC_B_14
+K1,34,IOB_X1Y43,RIOB33_X43Y43,IO_L3N_T0_DQS_34
+K2,34,IOB_X1Y44,RIOB33_X43Y43,IO_L3P_T0_DQS_34
+K3,34,IOB_X1Y42,RIOB33_X43Y41,IO_L4P_T0_34
+K5,34,IOB_X1Y47,RIOB33_X43Y47,IO_L1N_T0_34
+K6,34,IOB_X1Y48,RIOB33_X43Y47,IO_L1P_T0_34
+K10,0,IPAD_X0Y0,MONITOR_BOT_X46Y79,VP_0
+K15,14,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_D07_14
+K16,14,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_D00_MOSI_14
+K17,14,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_D04_14
+K18,14,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_EMCCLK_14
+L2,34,IOB_X1Y41,RIOB33_X43Y41,IO_L4N_T0_34
+L3,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
+L4,34,IOB_X1Y40,RIOB33_X43Y39,IO_L5P_T0_34
+L5,34,IOB_X1Y38,RIOB33_X43Y37,IO_L6P_T0_34
+L9,0,IPAD_X0Y1,MONITOR_BOT_X46Y79,VN_0
+L14,14,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_14
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+L17,14,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_D01_DIN_14
+L18,14,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_D05_14
+M1,34,IOB_X1Y35,RIOB33_X43Y35,IO_L7N_T1_34
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+M4,34,IOB_X1Y30,RIOB33_X43Y29,IO_L10P_T1_34
+M5,34,IOB_X1Y37,RIOB33_X43Y37,IO_L6N_T0_VREF_34
+M6,34,IOB_X1Y34,RIOB33_X43Y33,IO_L8P_T1_34
+M14,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
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+M16,14,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_D09_14
+M17,14,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_D10_14
+N1,34,IOB_X1Y32,RIOB33_X43Y31,IO_L9P_T1_DQS_34
+N2,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
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+N4,34,IOB_X1Y29,RIOB33_X43Y29,IO_L10N_T1_34
+N6,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
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+N16,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+N17,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
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+P5,34,IOB_X1Y11,RIOB33_X43Y11,IO_L19N_T3_VREF_34
+P6,34,IOB_X1Y12,RIOB33_X43Y11,IO_L19P_T3_34
+P14,14,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_14
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+R6,34,IOB_X1Y0,RIOB33_SING_X43Y0,IO_25_34
+R7,34,IOB_X1Y6,RIOB33_X43Y5,IO_L22P_T3_34
+R13,14,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_A10_D26_14
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+R17,14,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_14
+R18,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
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+T5,34,IOB_X1Y7,RIOB33_X43Y7,IO_L21N_T3_DQS_34
+T7,34,IOB_X1Y5,RIOB33_X43Y5,IO_L22N_T3_34
+T12,14,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_A05_D21_14
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+T15,14,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_14
+T17,14,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_CSI_B_14
+T18,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+U1,34,IOB_X1Y19,RIOB33_X43Y19,IO_L15N_T2_DQS_34
+U2,34,IOB_X1Y20,RIOB33_X43Y19,IO_L15P_T2_DQS_34
+U4,34,IOB_X1Y14,RIOB33_X43Y13,IO_L18P_T2_34
+U5,34,IOB_X1Y9,RIOB33_X43Y9,IO_L20N_T3_34
+U6,34,IOB_X1Y10,RIOB33_X43Y9,IO_L20P_T3_34
+U7,34,IOB_X1Y4,RIOB33_X43Y3,IO_L23P_T3_34
+U9,14,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_A01_D17_14
+U10,14,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_14
+U11,14,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_A03_D19_14
+U12,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
+U14,14,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_A08_D24_14
+U15,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+U16,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+U17,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
+V2,34,IOB_X1Y17,RIOB33_X43Y17,IO_L16N_T2_34
+V3,34,IOB_X1Y18,RIOB33_X43Y17,IO_L16P_T2_34
+V4,34,IOB_X1Y13,RIOB33_X43Y13,IO_L18N_T2_34
+V6,34,IOB_X1Y3,RIOB33_X43Y3,IO_L23N_T3_34
+V7,34,IOB_X1Y1,RIOB33_X43Y1,IO_L24N_T3_34
+V8,34,IOB_X1Y2,RIOB33_X43Y1,IO_L24P_T3_34
+V9,14,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_A00_D16_14
+V11,14,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_A02_D18_14
+V12,14,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_14
+V13,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+V14,14,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_A07_D23_14
+V16,14,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_A12_D28_14
+V17,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
diff --git a/artix7/xc7a50tcsg325-2/part.json b/artix7/xc7a50tcsg325-2/part.json
new file mode 100644
index 0000000..a3f2702
--- /dev/null
+++ b/artix7/xc7a50tcsg325-2/part.json
@@ -0,0 +1,457 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "34": "X113Y26"
+ }
+}
diff --git a/artix7/xc7a50tcsg325-2/part.yaml b/artix7/xc7a50tcsg325-2/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tcsg325-2/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tcsg325-2L/package_pins.csv b/artix7/xc7a50tcsg325-2L/package_pins.csv
new file mode 100644
index 0000000..2477b7e
--- /dev/null
+++ b/artix7/xc7a50tcsg325-2L/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A3,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+A4,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+A9,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+A10,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+A12,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+A13,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+A14,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+A15,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+A17,15,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_ADV_B_15
+B1,216,OPAD_X0Y6,GTP_CHANNEL_3_X97Y150,MGTPTXN3_216
+B2,216,OPAD_X0Y7,GTP_CHANNEL_3_X97Y150,MGTPTXP3_216
+B5,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+B6,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+B9,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
+B10,15,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_AD9P_15
+B11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+B12,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+B14,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+B15,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+B16,15,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_15
+B17,15,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A27_15
+C3,216,IPAD_X1Y24,GTP_CHANNEL_2_X97Y139,MGTPRXN2_216
+C4,216,IPAD_X1Y25,GTP_CHANNEL_2_X97Y139,MGTPRXP2_216
+C8,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+C9,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+C11,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+C12,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+C13,15,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_15
+C14,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+C16,15,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_A28_15
+C17,15,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_A24_15
+C18,15,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_A23_15
+D1,216,OPAD_X0Y4,GTP_CHANNEL_2_X97Y139,MGTPTXN2_216
+D2,216,OPAD_X0Y5,GTP_CHANNEL_2_X97Y139,MGTPTXP2_216
+D5,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+D6,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+D8,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+D9,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+D10,15,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_15
+D11,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+D13,15,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_15
+D14,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+D15,15,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_15
+D16,15,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_15
+D18,15,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A25_15
+E3,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+E4,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+E13,15,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_15
+E15,15,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_15
+E16,15,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_15
+E17,15,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A26_15
+E18,15,IOB_X0Y51,LIOB33_X0Y51,IO_L24N_T3_RS0_15
+F1,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+F2,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+F14,15,IOB_X0Y55,LIOB33_X0Y55,IO_L22N_T3_A16_15
+F15,15,IOB_X0Y57,LIOB33_X0Y57,IO_L21N_T3_DQS_A18_15
+F17,15,IOB_X0Y52,LIOB33_X0Y51,IO_L24P_T3_RS1_15
+F18,15,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_A21_VREF_15
+G3,216,IPAD_X1Y30,GTP_CHANNEL_3_X97Y150,MGTPRXN3_216
+G4,216,IPAD_X1Y31,GTP_CHANNEL_3_X97Y150,MGTPRXP3_216
+G14,15,IOB_X0Y56,LIOB33_X0Y55,IO_L22P_T3_A17_15
+G15,15,IOB_X0Y58,LIOB33_X0Y57,IO_L21P_T3_DQS_15
+G16,15,IOB_X0Y59,LIOB33_X0Y59,IO_L20N_T3_A19_15
+G17,15,IOB_X0Y62,LIOB33_X0Y61,IO_L19P_T3_A22_15
+H1,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+H2,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+H14,15,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_15
+H16,15,IOB_X0Y60,LIOB33_X0Y59,IO_L20P_T3_A20_15
+H17,15,IOB_X0Y54,LIOB33_X0Y53,IO_L23P_T3_FOE_B_15
+H18,15,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_FWE_B_15
+J4,34,IOB_X1Y45,RIOB33_X43Y45,IO_L2N_T0_34
+J5,34,IOB_X1Y46,RIOB33_X43Y45,IO_L2P_T0_34
+J6,34,IOB_X1Y49,RIOB33_SING_X43Y49,IO_0_34
+J14,14,IOB_X0Y40,LIOB33_X0Y39,IO_L5P_T0_D06_14
+J15,14,IOB_X0Y46,LIOB33_X0Y45,IO_L2P_T0_D02_14
+J16,14,IOB_X0Y45,LIOB33_X0Y45,IO_L2N_T0_D03_14
+J18,14,IOB_X0Y44,LIOB33_X0Y43,IO_L3P_T0_DQS_PUDC_B_14
+K1,34,IOB_X1Y43,RIOB33_X43Y43,IO_L3N_T0_DQS_34
+K2,34,IOB_X1Y44,RIOB33_X43Y43,IO_L3P_T0_DQS_34
+K3,34,IOB_X1Y42,RIOB33_X43Y41,IO_L4P_T0_34
+K5,34,IOB_X1Y47,RIOB33_X43Y47,IO_L1N_T0_34
+K6,34,IOB_X1Y48,RIOB33_X43Y47,IO_L1P_T0_34
+K10,0,IPAD_X0Y0,MONITOR_BOT_X46Y79,VP_0
+K15,14,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_D07_14
+K16,14,IOB_X0Y48,LIOB33_X0Y47,IO_L1P_T0_D00_MOSI_14
+K17,14,IOB_X0Y42,LIOB33_X0Y41,IO_L4P_T0_D04_14
+K18,14,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_EMCCLK_14
+L2,34,IOB_X1Y41,RIOB33_X43Y41,IO_L4N_T0_34
+L3,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
+L4,34,IOB_X1Y40,RIOB33_X43Y39,IO_L5P_T0_34
+L5,34,IOB_X1Y38,RIOB33_X43Y37,IO_L6P_T0_34
+L9,0,IPAD_X0Y1,MONITOR_BOT_X46Y79,VN_0
+L14,14,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_14
+L15,14,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_FCS_B_14
+L17,14,IOB_X0Y47,LIOB33_X0Y47,IO_L1N_T0_D01_DIN_14
+L18,14,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_D05_14
+M1,34,IOB_X1Y35,RIOB33_X43Y35,IO_L7N_T1_34
+M2,34,IOB_X1Y36,RIOB33_X43Y35,IO_L7P_T1_34
+M4,34,IOB_X1Y30,RIOB33_X43Y29,IO_L10P_T1_34
+M5,34,IOB_X1Y37,RIOB33_X43Y37,IO_L6N_T0_VREF_34
+M6,34,IOB_X1Y34,RIOB33_X43Y33,IO_L8P_T1_34
+M14,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+M15,14,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_D08_VREF_14
+M16,14,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_D09_14
+M17,14,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_D10_14
+N1,34,IOB_X1Y32,RIOB33_X43Y31,IO_L9P_T1_DQS_34
+N2,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+N3,34,IOB_X1Y28,RIOB33_X43Y27,IO_L11P_T1_SRCC_34
+N4,34,IOB_X1Y29,RIOB33_X43Y29,IO_L10N_T1_34
+N6,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
+N14,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+N16,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+N17,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
+N18,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+P1,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+P3,34,IOB_X1Y25,RIOB33_X43Y25,IO_L12N_T1_MRCC_34
+P4,34,IOB_X1Y26,RIOB33_X43Y25,IO_L12P_T1_MRCC_34
+P5,34,IOB_X1Y11,RIOB33_X43Y11,IO_L19N_T3_VREF_34
+P6,34,IOB_X1Y12,RIOB33_X43Y11,IO_L19P_T3_34
+P14,14,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_14
+P15,14,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_14
+P16,14,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_14
+P18,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
+R1,34,IOB_X1Y23,RIOB33_X43Y23,IO_L13N_T2_MRCC_34
+R2,34,IOB_X1Y24,RIOB33_X43Y23,IO_L13P_T2_MRCC_34
+R3,34,IOB_X1Y22,RIOB33_X43Y21,IO_L14P_T2_SRCC_34
+R5,34,IOB_X1Y8,RIOB33_X43Y7,IO_L21P_T3_DQS_34
+R6,34,IOB_X1Y0,RIOB33_SING_X43Y0,IO_25_34
+R7,34,IOB_X1Y6,RIOB33_X43Y5,IO_L22P_T3_34
+R13,14,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_A10_D26_14
+R15,14,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_14
+R16,14,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_14
+R17,14,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_14
+R18,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+T2,34,IOB_X1Y21,RIOB33_X43Y21,IO_L14N_T2_SRCC_34
+T3,34,IOB_X1Y15,RIOB33_X43Y15,IO_L17N_T2_34
+T4,34,IOB_X1Y16,RIOB33_X43Y15,IO_L17P_T2_34
+T5,34,IOB_X1Y7,RIOB33_X43Y7,IO_L21N_T3_DQS_34
+T7,34,IOB_X1Y5,RIOB33_X43Y5,IO_L22N_T3_34
+T12,14,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_A05_D21_14
+T13,14,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_A09_D25_VREF_14
+T14,14,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_14
+T15,14,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_14
+T17,14,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_CSI_B_14
+T18,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+U1,34,IOB_X1Y19,RIOB33_X43Y19,IO_L15N_T2_DQS_34
+U2,34,IOB_X1Y20,RIOB33_X43Y19,IO_L15P_T2_DQS_34
+U4,34,IOB_X1Y14,RIOB33_X43Y13,IO_L18P_T2_34
+U5,34,IOB_X1Y9,RIOB33_X43Y9,IO_L20N_T3_34
+U6,34,IOB_X1Y10,RIOB33_X43Y9,IO_L20P_T3_34
+U7,34,IOB_X1Y4,RIOB33_X43Y3,IO_L23P_T3_34
+U9,14,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_A01_D17_14
+U10,14,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_14
+U11,14,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_A03_D19_14
+U12,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
+U14,14,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_A08_D24_14
+U15,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+U16,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+U17,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
+V2,34,IOB_X1Y17,RIOB33_X43Y17,IO_L16N_T2_34
+V3,34,IOB_X1Y18,RIOB33_X43Y17,IO_L16P_T2_34
+V4,34,IOB_X1Y13,RIOB33_X43Y13,IO_L18N_T2_34
+V6,34,IOB_X1Y3,RIOB33_X43Y3,IO_L23N_T3_34
+V7,34,IOB_X1Y1,RIOB33_X43Y1,IO_L24N_T3_34
+V8,34,IOB_X1Y2,RIOB33_X43Y1,IO_L24P_T3_34
+V9,14,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_A00_D16_14
+V11,14,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_A02_D18_14
+V12,14,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_14
+V13,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+V14,14,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_A07_D23_14
+V16,14,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_A12_D28_14
+V17,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
diff --git a/artix7/xc7a50tcsg325-2L/part.json b/artix7/xc7a50tcsg325-2L/part.json
new file mode 100644
index 0000000..a3f2702
--- /dev/null
+++ b/artix7/xc7a50tcsg325-2L/part.json
@@ -0,0 +1,457 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "34": "X113Y26"
+ }
+}
diff --git a/artix7/xc7a50tcsg325-2L/part.yaml b/artix7/xc7a50tcsg325-2L/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tcsg325-2L/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tcsg325-3/package_pins.csv b/artix7/xc7a50tcsg325-3/package_pins.csv
new file mode 100644
index 0000000..2477b7e
--- /dev/null
+++ b/artix7/xc7a50tcsg325-3/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A3,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+A4,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+A9,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+A10,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+A12,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+A13,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+A14,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+A15,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+A17,15,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_ADV_B_15
+B1,216,OPAD_X0Y6,GTP_CHANNEL_3_X97Y150,MGTPTXN3_216
+B2,216,OPAD_X0Y7,GTP_CHANNEL_3_X97Y150,MGTPTXP3_216
+B5,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+B6,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+B9,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
+B10,15,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_AD9P_15
+B11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+B12,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+B14,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+B15,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+B16,15,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_15
+B17,15,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A27_15
+C3,216,IPAD_X1Y24,GTP_CHANNEL_2_X97Y139,MGTPRXN2_216
+C4,216,IPAD_X1Y25,GTP_CHANNEL_2_X97Y139,MGTPRXP2_216
+C8,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+C9,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+C11,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+C12,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+C13,15,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_15
+C14,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+C16,15,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_A28_15
+C17,15,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_A24_15
+C18,15,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_A23_15
+D1,216,OPAD_X0Y4,GTP_CHANNEL_2_X97Y139,MGTPTXN2_216
+D2,216,OPAD_X0Y5,GTP_CHANNEL_2_X97Y139,MGTPTXP2_216
+D5,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+D6,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+D8,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+D9,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+D10,15,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_15
+D11,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+D13,15,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_15
+D14,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+D15,15,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_15
+D16,15,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_15
+D18,15,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A25_15
+E3,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+E4,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+E13,15,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_15
+E15,15,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_15
+E16,15,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_15
+E17,15,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A26_15
+E18,15,IOB_X0Y51,LIOB33_X0Y51,IO_L24N_T3_RS0_15
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+U12,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
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+V4,34,IOB_X1Y13,RIOB33_X43Y13,IO_L18N_T2_34
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+V17,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
diff --git a/artix7/xc7a50tcsg325-3/part.json b/artix7/xc7a50tcsg325-3/part.json
new file mode 100644
index 0000000..a3f2702
--- /dev/null
+++ b/artix7/xc7a50tcsg325-3/part.json
@@ -0,0 +1,457 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
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+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
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+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
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+ },
+ "31": {
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+ },
+ "32": {
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+ },
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+ },
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+ },
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+ "36": {
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+ },
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+ "38": {
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+ },
+ "39": {
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+ },
+ "40": {
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+ },
+ "41": {
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+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
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+ },
+ "3": {
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+ },
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+ },
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+ },
+ "13": {
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+ },
+ "14": {
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+ },
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+ },
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+ },
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+ },
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+ },
+ "20": {
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+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
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+ },
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+ },
+ "24": {
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+ },
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+ "frame_count": 36
+ },
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+ },
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+ },
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+ },
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+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
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+ },
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+ },
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+ },
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+ },
+ "36": {
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+ },
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+ },
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+ },
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+ },
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+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "34": "X113Y26"
+ }
+}
diff --git a/artix7/xc7a50tcsg325-3/part.yaml b/artix7/xc7a50tcsg325-3/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tcsg325-3/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ frame_count: 36
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
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+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
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+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
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+ 10: !<xilinx/xc7series/configuration_column>
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+ 13: !<xilinx/xc7series/configuration_column>
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+ 14: !<xilinx/xc7series/configuration_column>
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+ 15: !<xilinx/xc7series/configuration_column>
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+ 16: !<xilinx/xc7series/configuration_column>
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+ 17: !<xilinx/xc7series/configuration_column>
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+ 18: !<xilinx/xc7series/configuration_column>
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+ 20: !<xilinx/xc7series/configuration_column>
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+ 21: !<xilinx/xc7series/configuration_column>
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+ 22: !<xilinx/xc7series/configuration_column>
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+ 23: !<xilinx/xc7series/configuration_column>
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+ 24: !<xilinx/xc7series/configuration_column>
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+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
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+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
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+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
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+ 39: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tfgg484-2/package_pins.csv b/artix7/xc7a50tfgg484-2/package_pins.csv
new file mode 100644
index 0000000..f256b51
--- /dev/null
+++ b/artix7/xc7a50tfgg484-2/package_pins.csv
@@ -0,0 +1,273 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+A6,216,OPAD_X0Y4,GTP_CHANNEL_2_X97Y139,MGTPTXN2_216
+A8,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+A10,216,IPAD_X1Y24,GTP_CHANNEL_2_X97Y139,MGTPRXN2_216
+A13,16,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_16
+A14,16,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_16
+A15,16,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_16
+A19,16,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_16
+A20,16,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_16
+A21,16,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y36,RIOB33_X43Y35,IO_L7P_T1_34
+AA3,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y30,RIOB33_X43Y29,IO_L10P_T1_34
+AA6,34,IOB_X1Y13,RIOB33_X43Y13,IO_L18N_T2_34
+AA8,34,IOB_X1Y6,RIOB33_X43Y5,IO_L22P_T3_34
+AA18,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y35,RIOB33_X43Y35,IO_L7N_T1_34
+AB2,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
+AB3,34,IOB_X1Y34,RIOB33_X43Y33,IO_L8P_T1_34
+AB5,34,IOB_X1Y29,RIOB33_X43Y29,IO_L10N_T1_34
+AB6,34,IOB_X1Y9,RIOB33_X43Y9,IO_L20N_T3_34
+AB7,34,IOB_X1Y10,RIOB33_X43Y9,IO_L20P_T3_34
+AB8,34,IOB_X1Y5,RIOB33_X43Y5,IO_L22N_T3_34
+AB18,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+AB22,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
+B1,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+B6,216,OPAD_X0Y5,GTP_CHANNEL_2_X97Y139,MGTPTXP2_216
+B8,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+B10,216,IPAD_X1Y25,GTP_CHANNEL_2_X97Y139,MGTPRXP2_216
+B13,16,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_16
+B15,16,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_16
+B16,16,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_16
+B17,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+B18,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B20,16,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_16
+B21,16,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_16
+B22,16,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_16
+C2,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+C5,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+C7,216,OPAD_X0Y6,GTP_CHANNEL_3_X97Y150,MGTPTXN3_216
+C9,216,IPAD_X1Y30,GTP_CHANNEL_3_X97Y150,MGTPRXN3_216
+C11,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+C13,16,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_16
+C14,16,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_16
+C15,16,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_16
+C17,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+C18,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
+C19,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+C20,16,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_VREF_16
+C22,16,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_16
+D1,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+D2,35,IOB_X1Y91,RIOB33_X43Y91,IO_L4N_T0_35
+D5,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+D7,216,OPAD_X0Y7,GTP_CHANNEL_3_X97Y150,MGTPTXP3_216
+D9,216,IPAD_X1Y31,GTP_CHANNEL_3_X97Y150,MGTPRXP3_216
+D11,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+D14,16,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_16
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+D16,16,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_16
+D17,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+D19,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+D20,16,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_16
+D21,16,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_16
+D22,16,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_16
+E1,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+E2,35,IOB_X1Y92,RIOB33_X43Y91,IO_L4P_T0_35
+E3,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+E6,216,IPAD_X1Y15,GTP_COMMON_X97Y127,MGTREFCLK0N_216
+E10,216,IPAD_X1Y17,GTP_COMMON_X97Y127,MGTREFCLK1N_216
+E13,16,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_16
+E14,16,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_16
+E16,16,IOB_X0Y140,LIOB33_X0Y139,IO_L5P_T0_16
+E17,16,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_16
+E18,16,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_16
+E19,16,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_16
+E21,16,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_16
+E22,16,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_16
+F1,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+F3,35,IOB_X1Y88,RIOB33_X43Y87,IO_L6P_T0_35
+F4,35,IOB_X1Y99,RIOB33_SING_X43Y99,IO_0_35
+F6,216,IPAD_X1Y14,GTP_COMMON_X97Y127,MGTREFCLK0P_216
+F10,216,IPAD_X1Y16,GTP_COMMON_X97Y127,MGTREFCLK1P_216
+F13,16,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_16
+F14,16,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_16
+F15,16,IOB_X0Y149,LIOB33_SING_X0Y149,IO_0_16
+F16,16,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_16
+F18,16,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_16
+F19,16,IOB_X0Y114,LIOB33_X0Y113,IO_L18P_T2_16
+F20,16,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_16
+F21,16,IOB_X0Y100,LIOB33_SING_X0Y100,IO_25_16
+G1,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+G2,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+G3,35,IOB_X1Y77,RIOB33_X43Y77,IO_L11N_T1_SRCC_35
+G4,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+G13,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+G15,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+G16,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+G17,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+G18,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+G20,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+G21,16,IOB_X0Y102,LIOB33_X0Y101,IO_L24P_T3_16
+G22,16,IOB_X0Y101,LIOB33_X0Y101,IO_L24N_T3_16
+H2,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
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diff --git a/artix7/xc7a50tfgg484-2/part.json b/artix7/xc7a50tfgg484-2/part.json
new file mode 100644
index 0000000..a20d3a0
--- /dev/null
+++ b/artix7/xc7a50tfgg484-2/part.json
@@ -0,0 +1,459 @@
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+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a50tfgg484-2/part.yaml b/artix7/xc7a50tfgg484-2/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tfgg484-2/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tfgg484-2L/package_pins.csv b/artix7/xc7a50tfgg484-2L/package_pins.csv
new file mode 100644
index 0000000..f256b51
--- /dev/null
+++ b/artix7/xc7a50tfgg484-2L/package_pins.csv
@@ -0,0 +1,273 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+A6,216,OPAD_X0Y4,GTP_CHANNEL_2_X97Y139,MGTPTXN2_216
+A8,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+A10,216,IPAD_X1Y24,GTP_CHANNEL_2_X97Y139,MGTPRXN2_216
+A13,16,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_16
+A14,16,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_16
+A15,16,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_16
+A19,16,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_16
+A20,16,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_16
+A21,16,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y36,RIOB33_X43Y35,IO_L7P_T1_34
+AA3,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y30,RIOB33_X43Y29,IO_L10P_T1_34
+AA6,34,IOB_X1Y13,RIOB33_X43Y13,IO_L18N_T2_34
+AA8,34,IOB_X1Y6,RIOB33_X43Y5,IO_L22P_T3_34
+AA18,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y35,RIOB33_X43Y35,IO_L7N_T1_34
+AB2,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
+AB3,34,IOB_X1Y34,RIOB33_X43Y33,IO_L8P_T1_34
+AB5,34,IOB_X1Y29,RIOB33_X43Y29,IO_L10N_T1_34
+AB6,34,IOB_X1Y9,RIOB33_X43Y9,IO_L20N_T3_34
+AB7,34,IOB_X1Y10,RIOB33_X43Y9,IO_L20P_T3_34
+AB8,34,IOB_X1Y5,RIOB33_X43Y5,IO_L22N_T3_34
+AB18,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+AB22,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
+B1,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+B6,216,OPAD_X0Y5,GTP_CHANNEL_2_X97Y139,MGTPTXP2_216
+B8,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
+B10,216,IPAD_X1Y25,GTP_CHANNEL_2_X97Y139,MGTPRXP2_216
+B13,16,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_16
+B15,16,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_16
+B16,16,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_16
+B17,16,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_16
+B18,16,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_16
+B20,16,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_16
+B21,16,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_16
+B22,16,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_16
+C2,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+C5,216,OPAD_X0Y2,GTP_CHANNEL_1_X97Y121,MGTPTXN1_216
+C7,216,OPAD_X0Y6,GTP_CHANNEL_3_X97Y150,MGTPTXN3_216
+C9,216,IPAD_X1Y30,GTP_CHANNEL_3_X97Y150,MGTPRXN3_216
+C11,216,IPAD_X1Y12,GTP_CHANNEL_1_X97Y121,MGTPRXN1_216
+C13,16,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_16
+C14,16,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_16
+C15,16,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_16
+C17,16,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_16
+C18,16,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_16
+C19,16,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_16
+C20,16,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_VREF_16
+C22,16,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_16
+D1,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+D2,35,IOB_X1Y91,RIOB33_X43Y91,IO_L4N_T0_35
+D5,216,OPAD_X0Y3,GTP_CHANNEL_1_X97Y121,MGTPTXP1_216
+D7,216,OPAD_X0Y7,GTP_CHANNEL_3_X97Y150,MGTPTXP3_216
+D9,216,IPAD_X1Y31,GTP_CHANNEL_3_X97Y150,MGTPRXP3_216
+D11,216,IPAD_X1Y13,GTP_CHANNEL_1_X97Y121,MGTPRXP1_216
+D14,16,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_16
+D15,16,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_16
+D16,16,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_16
+D17,16,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_16
+D19,16,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_16
+D20,16,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_16
+D21,16,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_16
+D22,16,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_16
+E1,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
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diff --git a/artix7/xc7a50tfgg484-2L/part.json b/artix7/xc7a50tfgg484-2L/part.json
new file mode 100644
index 0000000..a20d3a0
--- /dev/null
+++ b/artix7/xc7a50tfgg484-2L/part.json
@@ -0,0 +1,459 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
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+ },
+ "5": {
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+ },
+ "6": {
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+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
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+ },
+ "10": {
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+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a50tfgg484-2L/part.yaml b/artix7/xc7a50tfgg484-2L/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tfgg484-2L/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tfgg484-3/package_pins.csv b/artix7/xc7a50tfgg484-3/package_pins.csv
new file mode 100644
index 0000000..f256b51
--- /dev/null
+++ b/artix7/xc7a50tfgg484-3/package_pins.csv
@@ -0,0 +1,273 @@
+pin,bank,site,tile,pin_function
+A1,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+A4,216,OPAD_X0Y0,GTP_CHANNEL_0_X97Y110,MGTPTXN0_216
+A6,216,OPAD_X0Y4,GTP_CHANNEL_2_X97Y139,MGTPTXN2_216
+A8,216,IPAD_X1Y6,GTP_CHANNEL_0_X97Y110,MGTPRXN0_216
+A10,216,IPAD_X1Y24,GTP_CHANNEL_2_X97Y139,MGTPRXN2_216
+A13,16,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_16
+A14,16,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_16
+A15,16,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_16
+A16,16,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_16
+A18,16,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_16
+A19,16,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_16
+A20,16,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_16
+A21,16,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_16
+AA1,34,IOB_X1Y36,RIOB33_X43Y35,IO_L7P_T1_34
+AA3,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+AA4,34,IOB_X1Y27,RIOB33_X43Y27,IO_L11N_T1_SRCC_34
+AA5,34,IOB_X1Y30,RIOB33_X43Y29,IO_L10P_T1_34
+AA6,34,IOB_X1Y13,RIOB33_X43Y13,IO_L18N_T2_34
+AA8,34,IOB_X1Y6,RIOB33_X43Y5,IO_L22P_T3_34
+AA18,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+AA19,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+AA20,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+AA21,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+AB1,34,IOB_X1Y35,RIOB33_X43Y35,IO_L7N_T1_34
+AB2,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
+AB3,34,IOB_X1Y34,RIOB33_X43Y33,IO_L8P_T1_34
+AB5,34,IOB_X1Y29,RIOB33_X43Y29,IO_L10N_T1_34
+AB6,34,IOB_X1Y9,RIOB33_X43Y9,IO_L20N_T3_34
+AB7,34,IOB_X1Y10,RIOB33_X43Y9,IO_L20P_T3_34
+AB8,34,IOB_X1Y5,RIOB33_X43Y5,IO_L22N_T3_34
+AB18,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+AB20,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+AB21,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+AB22,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
+B1,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+B2,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+B4,216,OPAD_X0Y1,GTP_CHANNEL_0_X97Y110,MGTPTXP0_216
+B6,216,OPAD_X0Y5,GTP_CHANNEL_2_X97Y139,MGTPTXP2_216
+B8,216,IPAD_X1Y7,GTP_CHANNEL_0_X97Y110,MGTPRXP0_216
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+W17,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
+W19,14,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_14
+W20,14,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_14
+W21,14,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_D09_14
+W22,14,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_D10_14
+Y1,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
+Y2,34,IOB_X1Y41,RIOB33_X43Y41,IO_L4N_T0_34
+Y3,34,IOB_X1Y32,RIOB33_X43Y31,IO_L9P_T1_DQS_34
+Y4,34,IOB_X1Y28,RIOB33_X43Y27,IO_L11P_T1_SRCC_34
+Y6,34,IOB_X1Y14,RIOB33_X43Y13,IO_L18P_T2_34
+Y7,34,IOB_X1Y3,RIOB33_X43Y3,IO_L23N_T3_34
+Y8,34,IOB_X1Y4,RIOB33_X43Y3,IO_L23P_T3_34
+Y9,34,IOB_X1Y1,RIOB33_X43Y1,IO_L24N_T3_34
+Y18,14,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_14
+Y19,14,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_14
+Y21,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+Y22,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
diff --git a/artix7/xc7a50tfgg484-3/part.json b/artix7/xc7a50tfgg484-3/part.json
new file mode 100644
index 0000000..a20d3a0
--- /dev/null
+++ b/artix7/xc7a50tfgg484-3/part.json
@@ -0,0 +1,459 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "16": "X1Y130",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a50tfgg484-3/part.yaml b/artix7/xc7a50tfgg484-3/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tfgg484-3/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tftg256-1/package_pins.csv b/artix7/xc7a50tftg256-1/package_pins.csv
new file mode 100644
index 0000000..4a93b60
--- /dev/null
+++ b/artix7/xc7a50tftg256-1/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
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diff --git a/artix7/xc7a50tftg256-1/part.json b/artix7/xc7a50tftg256-1/part.json
new file mode 100644
index 0000000..63575f0
--- /dev/null
+++ b/artix7/xc7a50tftg256-1/part.json
@@ -0,0 +1,458 @@
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+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a50tftg256-1/part.yaml b/artix7/xc7a50tftg256-1/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tftg256-1/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tftg256-2/package_pins.csv b/artix7/xc7a50tftg256-2/package_pins.csv
new file mode 100644
index 0000000..4a93b60
--- /dev/null
+++ b/artix7/xc7a50tftg256-2/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+A3,35,IOB_X1Y91,RIOB33_X43Y91,IO_L4N_T0_35
+A4,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+A5,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+A7,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+A8,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+A9,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+A10,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+A12,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+A13,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+A14,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+A15,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+B1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+B2,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+B4,35,IOB_X1Y92,RIOB33_X43Y91,IO_L4P_T0_35
+B5,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+B6,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+B7,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+B9,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
+B10,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+B11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+B12,15,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_AD9P_15
+B14,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+B15,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+B16,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+C1,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+C2,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+C3,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+C4,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+C6,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+C7,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+C8,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+C9,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+C11,15,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_15
+C12,15,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_15
+C13,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+C14,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+C16,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+D1,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+D3,35,IOB_X1Y77,RIOB33_X43Y77,IO_L11N_T1_SRCC_35
+D4,35,IOB_X1Y76,RIOB33_X43Y75,IO_L12P_T1_MRCC_35
+D5,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+D6,35,IOB_X1Y88,RIOB33_X43Y87,IO_L6P_T0_35
+D8,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+D9,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+D10,15,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_15
+D11,15,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_15
+D13,15,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_15
+D14,15,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_15
+D15,15,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_ADV_B_15
+D16,15,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A25_15
+E1,35,IOB_X1Y69,RIOB33_X43Y69,IO_L15N_T2_DQS_35
+E2,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
+E3,35,IOB_X1Y78,RIOB33_X43Y77,IO_L11P_T1_SRCC_35
+E5,35,IOB_X1Y73,RIOB33_X43Y73,IO_L13N_T2_MRCC_35
+E6,35,IOB_X1Y99,RIOB33_SING_X43Y99,IO_0_35
+E11,15,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_15
+E12,15,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_15
+E13,15,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_15
+E15,15,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_A23_15
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+R15,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+R16,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
+T2,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
+T3,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+T4,34,IOB_X1Y32,RIOB33_X43Y31,IO_L9P_T1_DQS_34
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+T12,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
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+T15,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
diff --git a/artix7/xc7a50tftg256-2/part.json b/artix7/xc7a50tftg256-2/part.json
new file mode 100644
index 0000000..63575f0
--- /dev/null
+++ b/artix7/xc7a50tftg256-2/part.json
@@ -0,0 +1,458 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
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+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
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+ },
+ "31": {
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+ },
+ "32": {
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+ },
+ "33": {
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+ },
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+ },
+ "36": {
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+ },
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+ },
+ "40": {
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+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
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+ },
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+ },
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+ },
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+ },
+ "19": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "25": {
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+ },
+ "26": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "33": {
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+ },
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+ },
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+ },
+ "36": {
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+ },
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+ },
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+ },
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+ },
+ "40": {
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+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a50tftg256-2/part.yaml b/artix7/xc7a50tftg256-2/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tftg256-2/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
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+ 20: !<xilinx/xc7series/configuration_column>
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+ 22: !<xilinx/xc7series/configuration_column>
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+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 32: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
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+ 37: !<xilinx/xc7series/configuration_column>
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+ 38: !<xilinx/xc7series/configuration_column>
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+ 39: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
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+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
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+ 2: !<xilinx/xc7series/configuration_column>
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+ 20: !<xilinx/xc7series/configuration_column>
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+ 21: !<xilinx/xc7series/configuration_column>
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+ 22: !<xilinx/xc7series/configuration_column>
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+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
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+ 10: !<xilinx/xc7series/configuration_column>
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+ 11: !<xilinx/xc7series/configuration_column>
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+ 12: !<xilinx/xc7series/configuration_column>
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+ 13: !<xilinx/xc7series/configuration_column>
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+ 14: !<xilinx/xc7series/configuration_column>
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+ 15: !<xilinx/xc7series/configuration_column>
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+ 16: !<xilinx/xc7series/configuration_column>
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+ 17: !<xilinx/xc7series/configuration_column>
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+ 18: !<xilinx/xc7series/configuration_column>
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+ 19: !<xilinx/xc7series/configuration_column>
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+ 20: !<xilinx/xc7series/configuration_column>
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+ 21: !<xilinx/xc7series/configuration_column>
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+ 22: !<xilinx/xc7series/configuration_column>
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+ 23: !<xilinx/xc7series/configuration_column>
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+ 24: !<xilinx/xc7series/configuration_column>
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+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
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+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
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+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tftg256-2L/package_pins.csv b/artix7/xc7a50tftg256-2L/package_pins.csv
new file mode 100644
index 0000000..4a93b60
--- /dev/null
+++ b/artix7/xc7a50tftg256-2L/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
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+M12,14,IOB_X0Y37,LIOB33_X0Y37,IO_L6N_T0_D08_VREF_14
+M14,14,IOB_X0Y41,LIOB33_X0Y41,IO_L4N_T0_D05_14
+M15,14,IOB_X0Y43,LIOB33_X0Y43,IO_L3N_T0_DQS_EMCCLK_14
+M16,14,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_D09_14
+N1,34,IOB_X1Y42,RIOB33_X43Y41,IO_L4P_T0_34
+N2,34,IOB_X1Y43,RIOB33_X43Y43,IO_L3N_T0_DQS_34
+N3,34,IOB_X1Y44,RIOB33_X43Y43,IO_L3P_T0_DQS_34
+N4,34,IOB_X1Y37,RIOB33_X43Y37,IO_L6N_T0_VREF_34
+N6,14,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_A09_D25_VREF_14
+N9,14,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_A12_D28_14
+N11,14,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_14
+N12,14,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_14
+N13,14,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_14
+N14,14,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_14
+N16,14,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_D10_14
+P1,34,IOB_X1Y41,RIOB33_X43Y41,IO_L4N_T0_34
+P3,34,IOB_X1Y39,RIOB33_X43Y39,IO_L5N_T0_34
+P4,34,IOB_X1Y40,RIOB33_X43Y39,IO_L5P_T0_34
+P5,34,IOB_X1Y30,RIOB33_X43Y29,IO_L10P_T1_34
+P6,14,IOB_X0Y0,LIOB33_SING_X0Y0,IO_25_14
+P8,14,IOB_X0Y10,LIOB33_X0Y9,IO_L20P_T3_A08_D24_14
+P9,14,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_A11_D27_14
+P10,14,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_14
+P11,14,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_14
+P13,14,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_14
+P14,14,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_14
+P15,14,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_D11_14
+P16,14,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_D12_14
+R1,34,IOB_X1Y35,RIOB33_X43Y35,IO_L7N_T1_34
+R2,34,IOB_X1Y36,RIOB33_X43Y35,IO_L7P_T1_34
+R3,34,IOB_X1Y34,RIOB33_X43Y33,IO_L8P_T1_34
+R5,14,IOB_X0Y4,LIOB33_X0Y3,IO_L23P_T3_A03_D19_14
+R6,14,IOB_X0Y2,LIOB33_X0Y1,IO_L24P_T3_A01_D17_14
+R7,14,IOB_X0Y1,LIOB33_X0Y1,IO_L24N_T3_A00_D16_14
+R8,14,IOB_X0Y9,LIOB33_X0Y9,IO_L20N_T3_A07_D23_14
+R10,14,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_A14_D30_14
+R11,14,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_A13_D29_14
+R12,14,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_RDWR_B_14
+R13,14,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_CSI_B_14
+R15,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
+R16,14,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_D13_14
+T2,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
+T3,34,IOB_X1Y31,RIOB33_X43Y31,IO_L9N_T1_DQS_34
+T4,34,IOB_X1Y32,RIOB33_X43Y31,IO_L9P_T1_DQS_34
+T5,14,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_A02_D18_14
+T7,14,IOB_X0Y8,LIOB33_X0Y7,IO_L21P_T3_DQS_14
+T8,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+T9,14,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_A05_D21_14
+T10,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
+T12,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+T13,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
+T14,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+T15,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
diff --git a/artix7/xc7a50tftg256-2L/part.json b/artix7/xc7a50tftg256-2L/part.json
new file mode 100644
index 0000000..63575f0
--- /dev/null
+++ b/artix7/xc7a50tftg256-2L/part.json
@@ -0,0 +1,458 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a50tftg256-2L/part.yaml b/artix7/xc7a50tftg256-2L/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tftg256-2L/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/artix7/xc7a50tftg256-3/package_pins.csv b/artix7/xc7a50tftg256-3/package_pins.csv
new file mode 100644
index 0000000..4a93b60
--- /dev/null
+++ b/artix7/xc7a50tftg256-3/package_pins.csv
@@ -0,0 +1,173 @@
+pin,bank,site,tile,pin_function
+A2,35,IOB_X1Y83,RIOB33_X43Y83,IO_L8N_T1_AD14N_35
+A3,35,IOB_X1Y91,RIOB33_X43Y91,IO_L4N_T0_35
+A4,35,IOB_X1Y93,RIOB33_X43Y93,IO_L3N_T0_DQS_AD5N_35
+A5,35,IOB_X1Y94,RIOB33_X43Y93,IO_L3P_T0_DQS_AD5P_35
+A7,35,IOB_X1Y97,RIOB33_X43Y97,IO_L1N_T0_AD4N_35
+A8,15,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_AD8P_15
+A9,15,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_AD8N_15
+A10,15,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_AD1N_15
+A12,15,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_AD9N_15
+A13,15,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_AD2P_15
+A14,15,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_AD2N_15
+A15,15,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_AD3N_15
+B1,35,IOB_X1Y81,RIOB33_X43Y81,IO_L9N_T1_DQS_AD7N_35
+B2,35,IOB_X1Y84,RIOB33_X43Y83,IO_L8P_T1_AD14P_35
+B4,35,IOB_X1Y92,RIOB33_X43Y91,IO_L4P_T0_35
+B5,35,IOB_X1Y95,RIOB33_X43Y95,IO_L2N_T0_AD12N_35
+B6,35,IOB_X1Y96,RIOB33_X43Y95,IO_L2P_T0_AD12P_35
+B7,35,IOB_X1Y98,RIOB33_X43Y97,IO_L1P_T0_AD4P_35
+B9,15,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_AD1P_15
+B10,15,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_15
+B11,15,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_15
+B12,15,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_AD9P_15
+B14,15,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_AD10N_15
+B15,15,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_AD3P_15
+B16,15,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_AD11N_15
+C1,35,IOB_X1Y82,RIOB33_X43Y81,IO_L9P_T1_DQS_AD7P_35
+C2,35,IOB_X1Y85,RIOB33_X43Y85,IO_L7N_T1_AD6N_35
+C3,35,IOB_X1Y86,RIOB33_X43Y85,IO_L7P_T1_AD6P_35
+C4,35,IOB_X1Y75,RIOB33_X43Y75,IO_L12N_T1_MRCC_35
+C6,35,IOB_X1Y89,RIOB33_X43Y89,IO_L5N_T0_AD13N_35
+C7,35,IOB_X1Y90,RIOB33_X43Y89,IO_L5P_T0_AD13P_35
+C8,15,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_AD0P_15
+C9,15,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_AD0N_15
+C11,15,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_15
+C12,15,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_15
+C13,15,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_15
+C14,15,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_AD10P_15
+C16,15,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_AD11P_15
+D1,35,IOB_X1Y79,RIOB33_X43Y79,IO_L10N_T1_AD15N_35
+D3,35,IOB_X1Y77,RIOB33_X43Y77,IO_L11N_T1_SRCC_35
+D4,35,IOB_X1Y76,RIOB33_X43Y75,IO_L12P_T1_MRCC_35
+D5,35,IOB_X1Y87,RIOB33_X43Y87,IO_L6N_T0_VREF_35
+D6,35,IOB_X1Y88,RIOB33_X43Y87,IO_L6P_T0_35
+D8,15,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_15
+D9,15,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_VREF_15
+D10,15,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_15
+D11,15,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_15
+D13,15,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_15
+D14,15,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_15
+D15,15,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_ADV_B_15
+D16,15,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A25_15
+E1,35,IOB_X1Y69,RIOB33_X43Y69,IO_L15N_T2_DQS_35
+E2,35,IOB_X1Y80,RIOB33_X43Y79,IO_L10P_T1_AD15P_35
+E3,35,IOB_X1Y78,RIOB33_X43Y77,IO_L11P_T1_SRCC_35
+E5,35,IOB_X1Y73,RIOB33_X43Y73,IO_L13N_T2_MRCC_35
+E6,35,IOB_X1Y99,RIOB33_SING_X43Y99,IO_0_35
+E11,15,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_15
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+G5,35,IOB_X1Y68,RIOB33_X43Y67,IO_L16P_T2_35
+G11,15,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_15
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+H4,35,IOB_X1Y63,RIOB33_X43Y63,IO_L18N_T2_35
+H5,35,IOB_X1Y64,RIOB33_X43Y63,IO_L18P_T2_35
+H8,0,IPAD_X0Y0,MONITOR_BOT_X46Y79,VP_0
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+J7,0,IPAD_X0Y1,MONITOR_BOT_X46Y79,VN_0
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+J16,15,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_FWE_B_15
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+K5,35,IOB_X1Y50,RIOB33_SING_X43Y50,IO_25_35
+K12,14,IOB_X0Y49,LIOB33_SING_X0Y49,IO_0_14
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+L12,14,IOB_X0Y38,LIOB33_X0Y37,IO_L6P_T0_FCS_B_14
+L13,14,IOB_X0Y39,LIOB33_X0Y39,IO_L5N_T0_D07_14
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+M2,34,IOB_X1Y46,RIOB33_X43Y45,IO_L2P_T0_34
+M4,34,IOB_X1Y47,RIOB33_X43Y47,IO_L1N_T0_34
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+R13,14,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_CSI_B_14
+R15,14,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_14
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+T2,34,IOB_X1Y33,RIOB33_X43Y33,IO_L8N_T1_34
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+T5,14,IOB_X0Y3,LIOB33_X0Y3,IO_L23N_T3_A02_D18_14
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+T8,14,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_A06_D22_14
+T9,14,IOB_X0Y6,LIOB33_X0Y5,IO_L22P_T3_A05_D21_14
+T10,14,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_A04_D20_14
+T12,14,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_DOUT_CSO_B_14
+T13,14,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_A15_D31_14
+T14,14,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_D14_14
+T15,14,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_D15_14
diff --git a/artix7/xc7a50tftg256-3/part.json b/artix7/xc7a50tftg256-3/part.json
new file mode 100644
index 0000000..63575f0
--- /dev/null
+++ b/artix7/xc7a50tftg256-3/part.json
@@ -0,0 +1,458 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 36
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 36
+ },
+ "18": {
+ "frame_count": 30
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 30
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 36
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 28
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56803475,
+ "iobanks": {
+ "0": "X1Y78",
+ "14": "X1Y26",
+ "15": "X1Y78",
+ "34": "X113Y26",
+ "35": "X113Y78"
+ }
+}
diff --git a/artix7/xc7a50tftg256-3/part.yaml b/artix7/xc7a50tftg256-3/part.yaml
new file mode 100644
index 0000000..6da0e7b
--- /dev/null
+++ b/artix7/xc7a50tftg256-3/part.yaml
@@ -0,0 +1,293 @@
+!<xilinx/xc7series/part>
+idcode: 0x362c093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/kintex7/mapping/parts.yaml b/kintex7/mapping/parts.yaml
index 7fb1803..8aa53cc 100644
--- a/kintex7/mapping/parts.yaml
+++ b/kintex7/mapping/parts.yaml
@@ -1,5 +1,64 @@
-# part number to device, package and speed grade mapping
-"xc7k70tfbg676-2":
- device: "xc7k70t"
- package: "fbg676"
- speedgrade: "2"
+xc7k70tfbg484-1:
+ device: xc7k70t
+ package: fbg484
+ speedgrade: '1'
+xc7k70tfbg484-2:
+ device: xc7k70t
+ package: fbg484
+ speedgrade: '2'
+xc7k70tfbg484-2L:
+ device: xc7k70t
+ package: fbg484
+ speedgrade: 2L
+xc7k70tfbg484-3:
+ device: xc7k70t
+ package: fbg484
+ speedgrade: '3'
+xc7k70tfbg676-1:
+ device: xc7k70t
+ package: fbg676
+ speedgrade: '1'
+xc7k70tfbg676-2:
+ device: xc7k70t
+ package: fbg676
+ speedgrade: '2'
+xc7k70tfbg676-2L:
+ device: xc7k70t
+ package: fbg676
+ speedgrade: 2L
+xc7k70tfbg676-3:
+ device: xc7k70t
+ package: fbg676
+ speedgrade: '3'
+xc7k70tfbv484-1:
+ device: xc7k70t
+ package: fbv484
+ speedgrade: '1'
+xc7k70tfbv484-2:
+ device: xc7k70t
+ package: fbv484
+ speedgrade: '2'
+xc7k70tfbv484-2L:
+ device: xc7k70t
+ package: fbv484
+ speedgrade: 2L
+xc7k70tfbv484-3:
+ device: xc7k70t
+ package: fbv484
+ speedgrade: '3'
+xc7k70tfbv676-1:
+ device: xc7k70t
+ package: fbv676
+ speedgrade: '1'
+xc7k70tfbv676-2:
+ device: xc7k70t
+ package: fbv676
+ speedgrade: '2'
+xc7k70tfbv676-2L:
+ device: xc7k70t
+ package: fbv676
+ speedgrade: 2L
+xc7k70tfbv676-3:
+ device: xc7k70t
+ package: fbv676
+ speedgrade: '3'
diff --git a/kintex7/mask_bram_l.db b/kintex7/mask_bram_l.db
index 69afd71..9bba2dd 100644
--- a/kintex7/mask_bram_l.db
+++ b/kintex7/mask_bram_l.db
@@ -1,67 +1,26 @@
-bit 00_11
-bit 00_14
-bit 00_17
-bit 00_19
-bit 00_22
bit 00_25
bit 00_26
bit 00_27
-bit 00_29
bit 00_30
-bit 00_34
-bit 00_35
-bit 00_37
-bit 00_39
-bit 00_41
bit 00_42
-bit 00_78
-bit 00_81
-bit 00_83
-bit 00_86
bit 00_89
bit 00_90
bit 00_91
bit 00_94
-bit 00_97
-bit 00_98
-bit 00_101
-bit 00_103
-bit 00_105
bit 00_106
bit 00_139
bit 00_145
-bit 00_203
-bit 00_214
bit 00_217
bit 00_218
bit 00_219
-bit 00_221
bit 00_222
-bit 00_226
-bit 00_227
-bit 00_229
-bit 00_230
-bit 00_231
bit 00_234
-bit 00_266
-bit 00_267
-bit 00_270
-bit 00_273
-bit 00_275
-bit 00_278
bit 00_281
bit 00_282
bit 00_283
bit 00_286
-bit 00_290
-bit 00_291
-bit 00_293
-bit 00_295
-bit 00_297
bit 00_298
-bit 01_09
bit 01_10
-bit 01_13
bit 01_14
bit 01_20
bit 01_21
@@ -70,11 +29,16 @@
bit 01_26
bit 01_29
bit 01_32
+bit 01_33
bit 01_34
+bit 01_36
bit 01_37
bit 01_38
+bit 01_40
bit 01_41
-bit 01_77
+bit 01_73
+bit 01_74
+bit 01_78
bit 01_84
bit 01_85
bit 01_88
@@ -120,75 +84,79 @@
bit 01_292
bit 01_293
bit 01_294
+bit 01_296
bit 01_297
-bit 02_109
-bit 02_142
+bit 02_39
+bit 02_251
bit 02_253
bit 02_278
-bit 03_05
+bit 03_28
bit 03_102
bit 03_134
bit 03_150
bit 03_166
bit 03_198
-bit 03_206
bit 03_214
bit 03_230
+bit 03_242
bit 03_246
+bit 03_250
+bit 03_252
bit 03_262
bit 03_278
-bit 04_204
+bit 04_36
bit 04_254
bit 04_260
-bit 05_04
+bit 05_31
bit 05_102
-bit 05_111
bit 05_134
bit 05_150
bit 05_166
bit 05_198
bit 05_214
bit 05_230
+bit 05_241
bit 05_246
+bit 05_249
bit 06_03
bit 06_05
bit 06_11
+bit 06_17
bit 06_19
bit 06_21
bit 06_27
+bit 06_33
bit 06_35
bit 06_37
bit 06_49
bit 06_51
bit 06_53
-bit 06_65
+bit 06_61
bit 06_67
bit 06_69
-bit 06_77
bit 06_81
bit 06_83
+bit 06_85
+bit 06_97
bit 06_99
bit 06_101
bit 06_115
+bit 06_125
bit 06_131
-bit 06_137
-bit 06_141
bit 06_147
-bit 06_149
-bit 06_157
bit 06_163
bit 06_195
bit 06_211
+bit 06_213
bit 06_227
+bit 06_229
bit 06_243
bit 06_251
bit 06_259
bit 06_267
bit 06_275
-bit 06_277
bit 06_283
bit 06_291
-bit 06_293
bit 06_299
bit 06_307
bit 06_309
@@ -198,51 +166,56 @@
bit 07_10
bit 07_12
bit 07_14
-bit 07_16
-bit 07_18
bit 07_22
+bit 07_26
+bit 07_28
bit 07_30
bit 07_32
bit 07_38
bit 07_42
+bit 07_44
+bit 07_46
bit 07_48
+bit 07_52
bit 07_54
bit 07_56
bit 07_58
-bit 07_62
bit 07_64
+bit 07_66
bit 07_70
bit 07_72
+bit 07_74
bit 07_76
bit 07_78
bit 07_80
+bit 07_82
bit 07_86
+bit 07_88
bit 07_94
bit 07_96
bit 07_102
-bit 07_106
bit 07_112
bit 07_114
bit 07_118
bit 07_120
-bit 07_122
bit 07_126
bit 07_128
bit 07_134
+bit 07_138
bit 07_142
-bit 07_143
bit 07_144
bit 07_150
bit 07_152
+bit 07_154
bit 07_158
bit 07_160
bit 07_164
bit 07_166
bit 07_168
+bit 07_170
bit 07_174
bit 07_176
bit 07_178
-bit 07_180
bit 07_182
bit 07_184
bit 07_186
@@ -261,14 +234,11 @@
bit 07_232
bit 07_234
bit 07_238
-bit 07_244
bit 07_246
-bit 07_248
bit 07_250
bit 07_254
bit 07_256
bit 07_262
-bit 07_266
bit 07_270
bit 07_280
bit 07_282
@@ -276,37 +246,36 @@
bit 07_288
bit 07_294
bit 07_296
-bit 07_304
-bit 07_308
+bit 07_298
bit 07_310
bit 07_314
-bit 07_318
bit 08_00
bit 08_06
bit 08_07
+bit 08_11
bit 08_12
bit 08_16
bit 08_17
-bit 08_18
-bit 08_19
bit 08_22
bit 08_23
-bit 08_29
+bit 08_27
bit 08_32
bit 08_33
bit 08_34
-bit 08_36
+bit 08_37
bit 08_38
bit 08_39
bit 08_42
bit 08_45
bit 08_48
bit 08_49
+bit 08_50
bit 08_51
bit 08_52
bit 08_53
bit 08_54
bit 08_55
+bit 08_58
bit 08_60
bit 08_61
bit 08_62
@@ -316,74 +285,69 @@
bit 08_71
bit 08_75
bit 08_78
-bit 08_79
bit 08_80
bit 08_81
-bit 08_84
+bit 08_83
bit 08_86
bit 08_87
-bit 08_90
-bit 08_93
+bit 08_94
bit 08_96
bit 08_97
+bit 08_100
bit 08_101
bit 08_102
bit 08_103
-bit 08_105
-bit 08_110
bit 08_112
bit 08_113
bit 08_116
-bit 08_117
bit 08_118
bit 08_119
+bit 08_124
bit 08_126
bit 08_127
bit 08_128
bit 08_129
-bit 08_131
bit 08_134
bit 08_135
bit 08_136
bit 08_138
-bit 08_139
-bit 08_142
bit 08_143
bit 08_144
bit 08_145
bit 08_150
bit 08_151
bit 08_152
+bit 08_153
+bit 08_158
bit 08_160
bit 08_161
-bit 08_164
bit 08_165
bit 08_166
bit 08_167
bit 08_168
+bit 08_174
bit 08_175
bit 08_176
bit 08_177
+bit 08_178
bit 08_182
bit 08_183
bit 08_184
-bit 08_188
bit 08_191
bit 08_192
bit 08_193
bit 08_200
bit 08_201
-bit 08_203
bit 08_207
bit 08_213
bit 08_216
bit 08_217
-bit 08_221
bit 08_222
bit 08_223
bit 08_224
-bit 08_228
+bit 08_229
bit 08_230
+bit 08_231
bit 08_232
bit 08_233
bit 08_238
@@ -396,54 +360,52 @@
bit 08_264
bit 08_270
bit 08_271
-bit 08_272
bit 08_279
bit 08_280
-bit 08_282
+bit 08_283
bit 08_286
bit 08_288
-bit 08_292
-bit 08_293
bit 08_295
bit 08_296
-bit 08_297
-bit 08_298
bit 08_304
-bit 08_307
bit 08_308
+bit 08_309
bit 08_311
bit 08_312
bit 09_00
bit 09_02
bit 09_03
bit 09_04
-bit 09_05
+bit 09_06
bit 09_08
bit 09_11
+bit 09_14
bit 09_16
bit 09_18
bit 09_19
-bit 09_20
+bit 09_32
+bit 09_33
bit 09_34
bit 09_35
bit 09_36
bit 09_48
-bit 09_49
bit 09_50
bit 09_51
bit 09_59
+bit 09_65
bit 09_66
bit 09_67
bit 09_72
bit 09_76
+bit 09_77
bit 09_78
-bit 09_80
bit 09_82
bit 09_83
-bit 09_85
+bit 09_93
bit 09_96
bit 09_98
bit 09_99
+bit 09_107
bit 09_112
bit 09_114
bit 09_115
@@ -456,63 +418,62 @@
bit 09_144
bit 09_146
bit 09_147
+bit 09_176
bit 09_184
bit 09_186
bit 09_188
+bit 09_211
bit 09_237
bit 09_248
bit 09_250
+bit 09_252
bit 09_258
bit 09_259
-bit 09_269
bit 09_274
bit 09_275
-bit 09_285
-bit 09_288
+bit 09_277
bit 09_290
bit 09_291
bit 09_304
bit 09_306
bit 09_307
+bit 09_309
bit 10_00
bit 10_01
bit 10_02
bit 10_03
-bit 10_05
bit 10_07
bit 10_11
bit 10_13
-bit 10_15
bit 10_16
bit 10_17
bit 10_18
bit 10_23
+bit 10_32
bit 10_33
bit 10_34
+bit 10_35
bit 10_39
bit 10_48
bit 10_49
bit 10_50
bit 10_52
bit 10_55
-bit 10_59
-bit 10_64
bit 10_65
bit 10_66
bit 10_68
bit 10_69
bit 10_71
+bit 10_73
+bit 10_77
bit 10_79
bit 10_81
bit 10_82
-bit 10_84
+bit 10_96
bit 10_97
bit 10_98
-bit 10_101
bit 10_103
-bit 10_112
bit 10_113
-bit 10_123
bit 10_124
bit 10_128
bit 10_129
@@ -520,18 +481,19 @@
bit 10_145
bit 10_146
bit 10_148
-bit 10_151
bit 10_161
bit 10_177
+bit 10_179
bit 10_181
bit 10_185
-bit 10_191
+bit 10_187
bit 10_193
bit 10_194
+bit 10_196
bit 10_210
bit 10_226
bit 10_242
-bit 10_251
+bit 10_245
bit 10_257
bit 10_258
bit 10_263
@@ -539,44 +501,41 @@
bit 10_274
bit 10_289
bit 10_290
-bit 10_292
+bit 10_301
bit 10_304
bit 10_305
bit 10_306
-bit 10_308
-bit 11_00
bit 11_01
bit 11_02
bit 11_04
+bit 11_05
+bit 11_06
bit 11_07
+bit 11_08
bit 11_11
-bit 11_12
bit 11_14
bit 11_15
-bit 11_16
bit 11_17
bit 11_18
bit 11_21
bit 11_23
bit 11_27
+bit 11_31
bit 11_32
bit 11_33
bit 11_34
-bit 11_37
bit 11_39
-bit 11_45
bit 11_48
bit 11_49
bit 11_50
bit 11_52
bit 11_55
+bit 11_61
bit 11_64
bit 11_65
bit 11_66
-bit 11_67
bit 11_68
bit 11_71
-bit 11_75
bit 11_76
bit 11_78
bit 11_79
@@ -585,27 +544,24 @@
bit 11_82
bit 11_85
bit 11_87
+bit 11_95
bit 11_96
bit 11_97
bit 11_98
bit 11_100
-bit 11_101
bit 11_103
-bit 11_111
bit 11_112
bit 11_113
bit 11_114
bit 11_119
bit 11_127
bit 11_129
-bit 11_130
+bit 11_131
bit 11_135
bit 11_143
bit 11_145
-bit 11_148
-bit 11_149
+bit 11_146
bit 11_151
-bit 11_155
bit 11_159
bit 11_160
bit 11_161
@@ -614,17 +570,17 @@
bit 11_175
bit 11_177
bit 11_183
+bit 11_184
bit 11_185
bit 11_186
bit 11_191
bit 11_193
-bit 11_205
bit 11_207
bit 11_215
bit 11_223
+bit 11_226
bit 11_231
bit 11_239
-bit 11_246
bit 11_247
bit 11_248
bit 11_250
@@ -632,17 +588,18 @@
bit 11_255
bit 11_257
bit 11_263
-bit 11_267
bit 11_271
bit 11_273
+bit 11_277
bit 11_279
-bit 11_281
bit 11_287
bit 11_289
bit 11_295
+bit 11_299
bit 11_303
bit 11_305
bit 11_311
+bit 11_315
bit 11_319
bit 12_00
bit 12_02
@@ -653,7 +610,7 @@
bit 12_18
bit 12_20
bit 12_26
-bit 12_31
+bit 12_32
bit 12_34
bit 12_36
bit 12_48
@@ -662,33 +619,35 @@
bit 12_64
bit 12_66
bit 12_68
-bit 12_80
+bit 12_76
bit 12_82
-bit 12_84
+bit 12_92
+bit 12_95
bit 12_96
bit 12_98
bit 12_100
+bit 12_106
bit 12_112
bit 12_114
bit 12_120
bit 12_124
bit 12_130
-bit 12_136
-bit 12_140
bit 12_144
+bit 12_145
bit 12_146
-bit 12_148
-bit 12_156
bit 12_159
bit 12_162
bit 12_193
bit 12_194
+bit 12_196
bit 12_201
bit 12_207
bit 12_210
+bit 12_212
bit 12_217
bit 12_223
bit 12_226
+bit 12_228
bit 12_233
bit 12_239
bit 12_242
@@ -701,13 +660,10 @@
bit 12_271
bit 12_272
bit 12_274
-bit 12_276
bit 12_281
bit 12_282
bit 12_287
-bit 12_288
bit 12_290
-bit 12_292
bit 12_297
bit 12_298
bit 12_303
@@ -715,20 +671,18 @@
bit 12_306
bit 12_308
bit 12_313
-bit 12_315
bit 12_319
bit 13_01
+bit 13_05
bit 13_07
bit 13_11
bit 13_13
bit 13_17
-bit 13_19
bit 13_21
bit 13_23
bit 13_27
bit 13_29
bit 13_33
-bit 13_35
bit 13_37
bit 13_39
bit 13_43
@@ -737,37 +691,33 @@
bit 13_51
bit 13_53
bit 13_55
+bit 13_59
bit 13_61
bit 13_65
-bit 13_67
bit 13_71
bit 13_75
-bit 13_76
bit 13_79
bit 13_81
+bit 13_83
bit 13_85
bit 13_87
-bit 13_91
-bit 13_93
+bit 13_89
+bit 13_95
bit 13_97
+bit 13_100
bit 13_101
bit 13_103
-bit 13_105
-bit 13_111
bit 13_113
-bit 13_117
bit 13_119
-bit 13_123
+bit 13_125
bit 13_127
bit 13_129
bit 13_131
bit 13_135
-bit 13_137
bit 13_139
-bit 13_140
bit 13_143
bit 13_145
-bit 13_149
+bit 13_146
bit 13_151
bit 13_153
bit 13_155
@@ -778,22 +728,18 @@
bit 13_169
bit 13_175
bit 13_177
+bit 13_179
bit 13_183
bit 13_185
-bit 13_187
bit 13_191
bit 13_193
bit 13_199
bit 13_201
-bit 13_203
-bit 13_205
bit 13_207
bit 13_209
bit 13_213
bit 13_215
bit 13_217
-bit 13_219
-bit 13_221
bit 13_223
bit 13_225
bit 13_229
@@ -806,33 +752,24 @@
bit 13_257
bit 13_263
bit 13_265
-bit 13_267
bit 13_271
-bit 13_273
bit 13_279
bit 13_281
-bit 13_283
-bit 13_284
bit 13_287
bit 13_289
-bit 13_293
bit 13_295
bit 13_297
bit 13_299
bit 13_303
bit 13_305
-bit 13_307
bit 13_309
bit 13_311
bit 13_313
bit 13_315
-bit 13_319
bit 14_00
bit 14_01
bit 14_02
bit 14_03
-bit 14_05
-bit 14_07
bit 14_10
bit 14_11
bit 14_13
@@ -845,20 +782,26 @@
bit 14_50
bit 14_52
bit 14_58
+bit 14_60
bit 14_64
bit 14_66
bit 14_68
bit 14_69
+bit 14_71
bit 14_73
+bit 14_75
bit 14_77
+bit 14_79
bit 14_80
bit 14_82
+bit 14_84
bit 14_96
bit 14_98
bit 14_100
bit 14_112
bit 14_114
bit 14_120
+bit 14_124
bit 14_128
bit 14_130
bit 14_140
@@ -866,36 +809,39 @@
bit 14_148
bit 14_160
bit 14_162
+bit 14_176
bit 14_181
bit 14_185
-bit 14_191
+bit 14_187
bit 14_210
+bit 14_226
bit 14_236
bit 14_245
-bit 14_249
bit 14_251
bit 14_258
-bit 14_268
+bit 14_272
bit 14_274
+bit 14_276
bit 14_290
bit 14_304
bit 14_306
-bit 15_00
bit 15_01
-bit 15_03
bit 15_04
+bit 15_06
bit 15_07
bit 15_08
-bit 15_12
bit 15_14
bit 15_15
bit 15_17
-bit 15_19
bit 15_23
+bit 15_27
+bit 15_29
+bit 15_31
bit 15_33
-bit 15_37
+bit 15_35
bit 15_39
bit 15_43
+bit 15_47
bit 15_49
bit 15_53
bit 15_55
@@ -904,28 +850,29 @@
bit 15_61
bit 15_63
bit 15_65
+bit 15_67
bit 15_71
bit 15_72
+bit 15_75
bit 15_76
bit 15_78
bit 15_79
bit 15_81
+bit 15_83
bit 15_87
bit 15_95
bit 15_97
-bit 15_101
bit 15_103
-bit 15_107
bit 15_113
bit 15_115
bit 15_117
bit 15_119
bit 15_121
-bit 15_123
bit 15_127
bit 15_129
bit 15_135
bit 15_137
+bit 15_139
bit 15_143
bit 15_145
bit 15_151
@@ -935,6 +882,7 @@
bit 15_165
bit 15_167
bit 15_169
+bit 15_171
bit 15_175
bit 15_177
bit 15_179
@@ -943,7 +891,6 @@
bit 15_185
bit 15_186
bit 15_188
-bit 15_189
bit 15_191
bit 15_193
bit 15_199
@@ -959,35 +906,31 @@
bit 15_235
bit 15_239
bit 15_241
-bit 15_246
bit 15_247
bit 15_248
bit 15_249
bit 15_250
-bit 15_251
bit 15_252
bit 15_255
bit 15_257
bit 15_263
bit 15_265
-bit 15_267
bit 15_271
bit 15_273
+bit 15_277
bit 15_279
bit 15_281
bit 15_283
bit 15_287
bit 15_289
bit 15_295
-bit 15_297
+bit 15_299
+bit 15_301
bit 15_305
bit 15_311
-bit 15_315
bit 16_23
-bit 16_39
bit 16_40
bit 16_48
-bit 16_55
bit 16_63
bit 16_66
bit 16_67
@@ -1004,6 +947,7 @@
bit 16_83
bit 16_84
bit 16_85
+bit 16_87
bit 16_90
bit 16_91
bit 16_92
@@ -1031,7 +975,6 @@
bit 16_123
bit 16_124
bit 16_125
-bit 16_127
bit 16_128
bit 16_130
bit 16_131
@@ -1121,20 +1064,24 @@
bit 16_271
bit 16_279
bit 16_296
+bit 17_15
bit 17_23
bit 17_40
+bit 17_48
bit 17_55
bit 17_66
bit 17_67
+bit 17_68
+bit 17_69
bit 17_71
-bit 17_80
bit 17_82
bit 17_83
-bit 17_84
+bit 17_85
+bit 17_87
bit 17_96
bit 17_104
-bit 17_112
bit 17_119
+bit 17_127
bit 17_135
bit 17_143
bit 17_146
@@ -1142,28 +1089,28 @@
bit 17_148
bit 17_149
bit 17_150
-bit 17_151
bit 17_153
bit 17_154
bit 17_155
bit 17_156
bit 17_157
bit 17_158
+bit 17_159
bit 17_161
bit 17_168
bit 17_169
+bit 17_170
+bit 17_171
bit 17_173
bit 17_174
-bit 17_175
bit 17_184
bit 17_232
-bit 17_296
-bit 18_22
+bit 18_14
+bit 18_38
bit 18_41
bit 18_62
bit 18_66
bit 18_67
-bit 18_68
bit 18_69
bit 18_70
bit 18_74
@@ -1181,6 +1128,7 @@
bit 18_92
bit 18_93
bit 18_94
+bit 18_97
bit 18_98
bit 18_99
bit 18_100
@@ -1199,7 +1147,6 @@
bit 18_123
bit 18_124
bit 18_125
-bit 18_126
bit 18_129
bit 18_130
bit 18_131
@@ -1216,7 +1163,6 @@
bit 18_146
bit 18_147
bit 18_148
-bit 18_149
bit 18_150
bit 18_151
bit 18_152
@@ -1226,6 +1172,7 @@
bit 18_157
bit 18_158
bit 18_159
+bit 18_160
bit 18_161
bit 18_162
bit 18_163
@@ -1275,7 +1222,6 @@
bit 18_228
bit 18_229
bit 18_230
-bit 18_233
bit 18_234
bit 18_235
bit 18_236
@@ -1288,8 +1234,8 @@
bit 18_294
bit 18_297
bit 19_22
-bit 19_33
bit 19_41
+bit 19_49
bit 19_54
bit 19_62
bit 19_66
@@ -1307,7 +1253,6 @@
bit 19_83
bit 19_84
bit 19_85
-bit 19_86
bit 19_90
bit 19_91
bit 19_92
@@ -1323,7 +1268,6 @@
bit 19_107
bit 19_108
bit 19_109
-bit 19_113
bit 19_114
bit 19_115
bit 19_116
@@ -1350,6 +1294,7 @@
bit 19_149
bit 19_150
bit 19_151
+bit 19_152
bit 19_154
bit 19_155
bit 19_156
@@ -1416,7 +1361,6 @@
bit 19_245
bit 19_249
bit 19_278
-bit 19_297
bit 19_305
bit 20_74
bit 20_76
@@ -1550,8 +1494,8 @@
bit 21_243
bit 21_245
bit 22_23
-bit 22_32
bit 22_40
+bit 22_48
bit 22_55
bit 22_63
bit 22_66
@@ -1568,6 +1512,7 @@
bit 22_83
bit 22_84
bit 22_85
+bit 22_87
bit 22_90
bit 22_91
bit 22_92
@@ -1671,7 +1616,6 @@
bit 22_228
bit 22_229
bit 22_231
-bit 22_232
bit 22_234
bit 22_235
bit 22_236
@@ -1682,51 +1626,53 @@
bit 22_244
bit 22_245
bit 22_296
+bit 23_15
bit 23_23
bit 23_39
bit 23_40
bit 23_48
-bit 23_55
bit 23_66
bit 23_67
bit 23_68
bit 23_69
bit 23_79
bit 23_80
+bit 23_82
bit 23_83
bit 23_84
bit 23_85
bit 23_87
-bit 23_96
bit 23_104
-bit 23_112
+bit 23_127
bit 23_135
bit 23_143
-bit 23_146
bit 23_147
bit 23_148
bit 23_149
bit 23_150
-bit 23_151
bit 23_153
bit 23_154
bit 23_155
bit 23_156
bit 23_157
bit 23_158
+bit 23_159
bit 23_161
bit 23_168
+bit 23_169
bit 23_170
+bit 23_171
bit 23_172
+bit 23_173
bit 23_174
+bit 23_175
bit 23_184
-bit 23_232
bit 23_240
bit 23_279
bit 23_295
bit 23_304
+bit 24_15
bit 24_23
-bit 24_32
bit 24_39
bit 24_40
bit 24_47
@@ -1776,6 +1722,7 @@
bit 24_123
bit 24_124
bit 24_125
+bit 24_127
bit 24_128
bit 24_130
bit 24_131
@@ -1874,12 +1821,11 @@
bit 24_295
bit 24_296
bit 24_304
+bit 25_15
bit 25_23
-bit 25_32
bit 25_39
bit 25_40
bit 25_48
-bit 25_55
bit 25_66
bit 25_67
bit 25_68
@@ -1895,13 +1841,11 @@
bit 25_95
bit 25_96
bit 25_104
-bit 25_112
bit 25_119
bit 25_127
bit 25_130
bit 25_132
bit 25_135
-bit 25_136
bit 25_138
bit 25_140
bit 25_143
@@ -1918,7 +1862,6 @@
bit 25_157
bit 25_158
bit 25_159
-bit 25_160
bit 25_161
bit 25_167
bit 25_168
@@ -1936,7 +1879,7 @@
bit 25_184
bit 25_188
bit 25_215
-bit 25_231
+bit 25_223
bit 25_232
bit 25_240
bit 25_279
diff --git a/kintex7/mask_bram_r.db b/kintex7/mask_bram_r.db
index 69afd71..9bba2dd 100644
--- a/kintex7/mask_bram_r.db
+++ b/kintex7/mask_bram_r.db
@@ -1,67 +1,26 @@
-bit 00_11
-bit 00_14
-bit 00_17
-bit 00_19
-bit 00_22
bit 00_25
bit 00_26
bit 00_27
-bit 00_29
bit 00_30
-bit 00_34
-bit 00_35
-bit 00_37
-bit 00_39
-bit 00_41
bit 00_42
-bit 00_78
-bit 00_81
-bit 00_83
-bit 00_86
bit 00_89
bit 00_90
bit 00_91
bit 00_94
-bit 00_97
-bit 00_98
-bit 00_101
-bit 00_103
-bit 00_105
bit 00_106
bit 00_139
bit 00_145
-bit 00_203
-bit 00_214
bit 00_217
bit 00_218
bit 00_219
-bit 00_221
bit 00_222
-bit 00_226
-bit 00_227
-bit 00_229
-bit 00_230
-bit 00_231
bit 00_234
-bit 00_266
-bit 00_267
-bit 00_270
-bit 00_273
-bit 00_275
-bit 00_278
bit 00_281
bit 00_282
bit 00_283
bit 00_286
-bit 00_290
-bit 00_291
-bit 00_293
-bit 00_295
-bit 00_297
bit 00_298
-bit 01_09
bit 01_10
-bit 01_13
bit 01_14
bit 01_20
bit 01_21
@@ -70,11 +29,16 @@
bit 01_26
bit 01_29
bit 01_32
+bit 01_33
bit 01_34
+bit 01_36
bit 01_37
bit 01_38
+bit 01_40
bit 01_41
-bit 01_77
+bit 01_73
+bit 01_74
+bit 01_78
bit 01_84
bit 01_85
bit 01_88
@@ -120,75 +84,79 @@
bit 01_292
bit 01_293
bit 01_294
+bit 01_296
bit 01_297
-bit 02_109
-bit 02_142
+bit 02_39
+bit 02_251
bit 02_253
bit 02_278
-bit 03_05
+bit 03_28
bit 03_102
bit 03_134
bit 03_150
bit 03_166
bit 03_198
-bit 03_206
bit 03_214
bit 03_230
+bit 03_242
bit 03_246
+bit 03_250
+bit 03_252
bit 03_262
bit 03_278
-bit 04_204
+bit 04_36
bit 04_254
bit 04_260
-bit 05_04
+bit 05_31
bit 05_102
-bit 05_111
bit 05_134
bit 05_150
bit 05_166
bit 05_198
bit 05_214
bit 05_230
+bit 05_241
bit 05_246
+bit 05_249
bit 06_03
bit 06_05
bit 06_11
+bit 06_17
bit 06_19
bit 06_21
bit 06_27
+bit 06_33
bit 06_35
bit 06_37
bit 06_49
bit 06_51
bit 06_53
-bit 06_65
+bit 06_61
bit 06_67
bit 06_69
-bit 06_77
bit 06_81
bit 06_83
+bit 06_85
+bit 06_97
bit 06_99
bit 06_101
bit 06_115
+bit 06_125
bit 06_131
-bit 06_137
-bit 06_141
bit 06_147
-bit 06_149
-bit 06_157
bit 06_163
bit 06_195
bit 06_211
+bit 06_213
bit 06_227
+bit 06_229
bit 06_243
bit 06_251
bit 06_259
bit 06_267
bit 06_275
-bit 06_277
bit 06_283
bit 06_291
-bit 06_293
bit 06_299
bit 06_307
bit 06_309
@@ -198,51 +166,56 @@
bit 07_10
bit 07_12
bit 07_14
-bit 07_16
-bit 07_18
bit 07_22
+bit 07_26
+bit 07_28
bit 07_30
bit 07_32
bit 07_38
bit 07_42
+bit 07_44
+bit 07_46
bit 07_48
+bit 07_52
bit 07_54
bit 07_56
bit 07_58
-bit 07_62
bit 07_64
+bit 07_66
bit 07_70
bit 07_72
+bit 07_74
bit 07_76
bit 07_78
bit 07_80
+bit 07_82
bit 07_86
+bit 07_88
bit 07_94
bit 07_96
bit 07_102
-bit 07_106
bit 07_112
bit 07_114
bit 07_118
bit 07_120
-bit 07_122
bit 07_126
bit 07_128
bit 07_134
+bit 07_138
bit 07_142
-bit 07_143
bit 07_144
bit 07_150
bit 07_152
+bit 07_154
bit 07_158
bit 07_160
bit 07_164
bit 07_166
bit 07_168
+bit 07_170
bit 07_174
bit 07_176
bit 07_178
-bit 07_180
bit 07_182
bit 07_184
bit 07_186
@@ -261,14 +234,11 @@
bit 07_232
bit 07_234
bit 07_238
-bit 07_244
bit 07_246
-bit 07_248
bit 07_250
bit 07_254
bit 07_256
bit 07_262
-bit 07_266
bit 07_270
bit 07_280
bit 07_282
@@ -276,37 +246,36 @@
bit 07_288
bit 07_294
bit 07_296
-bit 07_304
-bit 07_308
+bit 07_298
bit 07_310
bit 07_314
-bit 07_318
bit 08_00
bit 08_06
bit 08_07
+bit 08_11
bit 08_12
bit 08_16
bit 08_17
-bit 08_18
-bit 08_19
bit 08_22
bit 08_23
-bit 08_29
+bit 08_27
bit 08_32
bit 08_33
bit 08_34
-bit 08_36
+bit 08_37
bit 08_38
bit 08_39
bit 08_42
bit 08_45
bit 08_48
bit 08_49
+bit 08_50
bit 08_51
bit 08_52
bit 08_53
bit 08_54
bit 08_55
+bit 08_58
bit 08_60
bit 08_61
bit 08_62
@@ -316,74 +285,69 @@
bit 08_71
bit 08_75
bit 08_78
-bit 08_79
bit 08_80
bit 08_81
-bit 08_84
+bit 08_83
bit 08_86
bit 08_87
-bit 08_90
-bit 08_93
+bit 08_94
bit 08_96
bit 08_97
+bit 08_100
bit 08_101
bit 08_102
bit 08_103
-bit 08_105
-bit 08_110
bit 08_112
bit 08_113
bit 08_116
-bit 08_117
bit 08_118
bit 08_119
+bit 08_124
bit 08_126
bit 08_127
bit 08_128
bit 08_129
-bit 08_131
bit 08_134
bit 08_135
bit 08_136
bit 08_138
-bit 08_139
-bit 08_142
bit 08_143
bit 08_144
bit 08_145
bit 08_150
bit 08_151
bit 08_152
+bit 08_153
+bit 08_158
bit 08_160
bit 08_161
-bit 08_164
bit 08_165
bit 08_166
bit 08_167
bit 08_168
+bit 08_174
bit 08_175
bit 08_176
bit 08_177
+bit 08_178
bit 08_182
bit 08_183
bit 08_184
-bit 08_188
bit 08_191
bit 08_192
bit 08_193
bit 08_200
bit 08_201
-bit 08_203
bit 08_207
bit 08_213
bit 08_216
bit 08_217
-bit 08_221
bit 08_222
bit 08_223
bit 08_224
-bit 08_228
+bit 08_229
bit 08_230
+bit 08_231
bit 08_232
bit 08_233
bit 08_238
@@ -396,54 +360,52 @@
bit 08_264
bit 08_270
bit 08_271
-bit 08_272
bit 08_279
bit 08_280
-bit 08_282
+bit 08_283
bit 08_286
bit 08_288
-bit 08_292
-bit 08_293
bit 08_295
bit 08_296
-bit 08_297
-bit 08_298
bit 08_304
-bit 08_307
bit 08_308
+bit 08_309
bit 08_311
bit 08_312
bit 09_00
bit 09_02
bit 09_03
bit 09_04
-bit 09_05
+bit 09_06
bit 09_08
bit 09_11
+bit 09_14
bit 09_16
bit 09_18
bit 09_19
-bit 09_20
+bit 09_32
+bit 09_33
bit 09_34
bit 09_35
bit 09_36
bit 09_48
-bit 09_49
bit 09_50
bit 09_51
bit 09_59
+bit 09_65
bit 09_66
bit 09_67
bit 09_72
bit 09_76
+bit 09_77
bit 09_78
-bit 09_80
bit 09_82
bit 09_83
-bit 09_85
+bit 09_93
bit 09_96
bit 09_98
bit 09_99
+bit 09_107
bit 09_112
bit 09_114
bit 09_115
@@ -456,63 +418,62 @@
bit 09_144
bit 09_146
bit 09_147
+bit 09_176
bit 09_184
bit 09_186
bit 09_188
+bit 09_211
bit 09_237
bit 09_248
bit 09_250
+bit 09_252
bit 09_258
bit 09_259
-bit 09_269
bit 09_274
bit 09_275
-bit 09_285
-bit 09_288
+bit 09_277
bit 09_290
bit 09_291
bit 09_304
bit 09_306
bit 09_307
+bit 09_309
bit 10_00
bit 10_01
bit 10_02
bit 10_03
-bit 10_05
bit 10_07
bit 10_11
bit 10_13
-bit 10_15
bit 10_16
bit 10_17
bit 10_18
bit 10_23
+bit 10_32
bit 10_33
bit 10_34
+bit 10_35
bit 10_39
bit 10_48
bit 10_49
bit 10_50
bit 10_52
bit 10_55
-bit 10_59
-bit 10_64
bit 10_65
bit 10_66
bit 10_68
bit 10_69
bit 10_71
+bit 10_73
+bit 10_77
bit 10_79
bit 10_81
bit 10_82
-bit 10_84
+bit 10_96
bit 10_97
bit 10_98
-bit 10_101
bit 10_103
-bit 10_112
bit 10_113
-bit 10_123
bit 10_124
bit 10_128
bit 10_129
@@ -520,18 +481,19 @@
bit 10_145
bit 10_146
bit 10_148
-bit 10_151
bit 10_161
bit 10_177
+bit 10_179
bit 10_181
bit 10_185
-bit 10_191
+bit 10_187
bit 10_193
bit 10_194
+bit 10_196
bit 10_210
bit 10_226
bit 10_242
-bit 10_251
+bit 10_245
bit 10_257
bit 10_258
bit 10_263
@@ -539,44 +501,41 @@
bit 10_274
bit 10_289
bit 10_290
-bit 10_292
+bit 10_301
bit 10_304
bit 10_305
bit 10_306
-bit 10_308
-bit 11_00
bit 11_01
bit 11_02
bit 11_04
+bit 11_05
+bit 11_06
bit 11_07
+bit 11_08
bit 11_11
-bit 11_12
bit 11_14
bit 11_15
-bit 11_16
bit 11_17
bit 11_18
bit 11_21
bit 11_23
bit 11_27
+bit 11_31
bit 11_32
bit 11_33
bit 11_34
-bit 11_37
bit 11_39
-bit 11_45
bit 11_48
bit 11_49
bit 11_50
bit 11_52
bit 11_55
+bit 11_61
bit 11_64
bit 11_65
bit 11_66
-bit 11_67
bit 11_68
bit 11_71
-bit 11_75
bit 11_76
bit 11_78
bit 11_79
@@ -585,27 +544,24 @@
bit 11_82
bit 11_85
bit 11_87
+bit 11_95
bit 11_96
bit 11_97
bit 11_98
bit 11_100
-bit 11_101
bit 11_103
-bit 11_111
bit 11_112
bit 11_113
bit 11_114
bit 11_119
bit 11_127
bit 11_129
-bit 11_130
+bit 11_131
bit 11_135
bit 11_143
bit 11_145
-bit 11_148
-bit 11_149
+bit 11_146
bit 11_151
-bit 11_155
bit 11_159
bit 11_160
bit 11_161
@@ -614,17 +570,17 @@
bit 11_175
bit 11_177
bit 11_183
+bit 11_184
bit 11_185
bit 11_186
bit 11_191
bit 11_193
-bit 11_205
bit 11_207
bit 11_215
bit 11_223
+bit 11_226
bit 11_231
bit 11_239
-bit 11_246
bit 11_247
bit 11_248
bit 11_250
@@ -632,17 +588,18 @@
bit 11_255
bit 11_257
bit 11_263
-bit 11_267
bit 11_271
bit 11_273
+bit 11_277
bit 11_279
-bit 11_281
bit 11_287
bit 11_289
bit 11_295
+bit 11_299
bit 11_303
bit 11_305
bit 11_311
+bit 11_315
bit 11_319
bit 12_00
bit 12_02
@@ -653,7 +610,7 @@
bit 12_18
bit 12_20
bit 12_26
-bit 12_31
+bit 12_32
bit 12_34
bit 12_36
bit 12_48
@@ -662,33 +619,35 @@
bit 12_64
bit 12_66
bit 12_68
-bit 12_80
+bit 12_76
bit 12_82
-bit 12_84
+bit 12_92
+bit 12_95
bit 12_96
bit 12_98
bit 12_100
+bit 12_106
bit 12_112
bit 12_114
bit 12_120
bit 12_124
bit 12_130
-bit 12_136
-bit 12_140
bit 12_144
+bit 12_145
bit 12_146
-bit 12_148
-bit 12_156
bit 12_159
bit 12_162
bit 12_193
bit 12_194
+bit 12_196
bit 12_201
bit 12_207
bit 12_210
+bit 12_212
bit 12_217
bit 12_223
bit 12_226
+bit 12_228
bit 12_233
bit 12_239
bit 12_242
@@ -701,13 +660,10 @@
bit 12_271
bit 12_272
bit 12_274
-bit 12_276
bit 12_281
bit 12_282
bit 12_287
-bit 12_288
bit 12_290
-bit 12_292
bit 12_297
bit 12_298
bit 12_303
@@ -715,20 +671,18 @@
bit 12_306
bit 12_308
bit 12_313
-bit 12_315
bit 12_319
bit 13_01
+bit 13_05
bit 13_07
bit 13_11
bit 13_13
bit 13_17
-bit 13_19
bit 13_21
bit 13_23
bit 13_27
bit 13_29
bit 13_33
-bit 13_35
bit 13_37
bit 13_39
bit 13_43
@@ -737,37 +691,33 @@
bit 13_51
bit 13_53
bit 13_55
+bit 13_59
bit 13_61
bit 13_65
-bit 13_67
bit 13_71
bit 13_75
-bit 13_76
bit 13_79
bit 13_81
+bit 13_83
bit 13_85
bit 13_87
-bit 13_91
-bit 13_93
+bit 13_89
+bit 13_95
bit 13_97
+bit 13_100
bit 13_101
bit 13_103
-bit 13_105
-bit 13_111
bit 13_113
-bit 13_117
bit 13_119
-bit 13_123
+bit 13_125
bit 13_127
bit 13_129
bit 13_131
bit 13_135
-bit 13_137
bit 13_139
-bit 13_140
bit 13_143
bit 13_145
-bit 13_149
+bit 13_146
bit 13_151
bit 13_153
bit 13_155
@@ -778,22 +728,18 @@
bit 13_169
bit 13_175
bit 13_177
+bit 13_179
bit 13_183
bit 13_185
-bit 13_187
bit 13_191
bit 13_193
bit 13_199
bit 13_201
-bit 13_203
-bit 13_205
bit 13_207
bit 13_209
bit 13_213
bit 13_215
bit 13_217
-bit 13_219
-bit 13_221
bit 13_223
bit 13_225
bit 13_229
@@ -806,33 +752,24 @@
bit 13_257
bit 13_263
bit 13_265
-bit 13_267
bit 13_271
-bit 13_273
bit 13_279
bit 13_281
-bit 13_283
-bit 13_284
bit 13_287
bit 13_289
-bit 13_293
bit 13_295
bit 13_297
bit 13_299
bit 13_303
bit 13_305
-bit 13_307
bit 13_309
bit 13_311
bit 13_313
bit 13_315
-bit 13_319
bit 14_00
bit 14_01
bit 14_02
bit 14_03
-bit 14_05
-bit 14_07
bit 14_10
bit 14_11
bit 14_13
@@ -845,20 +782,26 @@
bit 14_50
bit 14_52
bit 14_58
+bit 14_60
bit 14_64
bit 14_66
bit 14_68
bit 14_69
+bit 14_71
bit 14_73
+bit 14_75
bit 14_77
+bit 14_79
bit 14_80
bit 14_82
+bit 14_84
bit 14_96
bit 14_98
bit 14_100
bit 14_112
bit 14_114
bit 14_120
+bit 14_124
bit 14_128
bit 14_130
bit 14_140
@@ -866,36 +809,39 @@
bit 14_148
bit 14_160
bit 14_162
+bit 14_176
bit 14_181
bit 14_185
-bit 14_191
+bit 14_187
bit 14_210
+bit 14_226
bit 14_236
bit 14_245
-bit 14_249
bit 14_251
bit 14_258
-bit 14_268
+bit 14_272
bit 14_274
+bit 14_276
bit 14_290
bit 14_304
bit 14_306
-bit 15_00
bit 15_01
-bit 15_03
bit 15_04
+bit 15_06
bit 15_07
bit 15_08
-bit 15_12
bit 15_14
bit 15_15
bit 15_17
-bit 15_19
bit 15_23
+bit 15_27
+bit 15_29
+bit 15_31
bit 15_33
-bit 15_37
+bit 15_35
bit 15_39
bit 15_43
+bit 15_47
bit 15_49
bit 15_53
bit 15_55
@@ -904,28 +850,29 @@
bit 15_61
bit 15_63
bit 15_65
+bit 15_67
bit 15_71
bit 15_72
+bit 15_75
bit 15_76
bit 15_78
bit 15_79
bit 15_81
+bit 15_83
bit 15_87
bit 15_95
bit 15_97
-bit 15_101
bit 15_103
-bit 15_107
bit 15_113
bit 15_115
bit 15_117
bit 15_119
bit 15_121
-bit 15_123
bit 15_127
bit 15_129
bit 15_135
bit 15_137
+bit 15_139
bit 15_143
bit 15_145
bit 15_151
@@ -935,6 +882,7 @@
bit 15_165
bit 15_167
bit 15_169
+bit 15_171
bit 15_175
bit 15_177
bit 15_179
@@ -943,7 +891,6 @@
bit 15_185
bit 15_186
bit 15_188
-bit 15_189
bit 15_191
bit 15_193
bit 15_199
@@ -959,35 +906,31 @@
bit 15_235
bit 15_239
bit 15_241
-bit 15_246
bit 15_247
bit 15_248
bit 15_249
bit 15_250
-bit 15_251
bit 15_252
bit 15_255
bit 15_257
bit 15_263
bit 15_265
-bit 15_267
bit 15_271
bit 15_273
+bit 15_277
bit 15_279
bit 15_281
bit 15_283
bit 15_287
bit 15_289
bit 15_295
-bit 15_297
+bit 15_299
+bit 15_301
bit 15_305
bit 15_311
-bit 15_315
bit 16_23
-bit 16_39
bit 16_40
bit 16_48
-bit 16_55
bit 16_63
bit 16_66
bit 16_67
@@ -1004,6 +947,7 @@
bit 16_83
bit 16_84
bit 16_85
+bit 16_87
bit 16_90
bit 16_91
bit 16_92
@@ -1031,7 +975,6 @@
bit 16_123
bit 16_124
bit 16_125
-bit 16_127
bit 16_128
bit 16_130
bit 16_131
@@ -1121,20 +1064,24 @@
bit 16_271
bit 16_279
bit 16_296
+bit 17_15
bit 17_23
bit 17_40
+bit 17_48
bit 17_55
bit 17_66
bit 17_67
+bit 17_68
+bit 17_69
bit 17_71
-bit 17_80
bit 17_82
bit 17_83
-bit 17_84
+bit 17_85
+bit 17_87
bit 17_96
bit 17_104
-bit 17_112
bit 17_119
+bit 17_127
bit 17_135
bit 17_143
bit 17_146
@@ -1142,28 +1089,28 @@
bit 17_148
bit 17_149
bit 17_150
-bit 17_151
bit 17_153
bit 17_154
bit 17_155
bit 17_156
bit 17_157
bit 17_158
+bit 17_159
bit 17_161
bit 17_168
bit 17_169
+bit 17_170
+bit 17_171
bit 17_173
bit 17_174
-bit 17_175
bit 17_184
bit 17_232
-bit 17_296
-bit 18_22
+bit 18_14
+bit 18_38
bit 18_41
bit 18_62
bit 18_66
bit 18_67
-bit 18_68
bit 18_69
bit 18_70
bit 18_74
@@ -1181,6 +1128,7 @@
bit 18_92
bit 18_93
bit 18_94
+bit 18_97
bit 18_98
bit 18_99
bit 18_100
@@ -1199,7 +1147,6 @@
bit 18_123
bit 18_124
bit 18_125
-bit 18_126
bit 18_129
bit 18_130
bit 18_131
@@ -1216,7 +1163,6 @@
bit 18_146
bit 18_147
bit 18_148
-bit 18_149
bit 18_150
bit 18_151
bit 18_152
@@ -1226,6 +1172,7 @@
bit 18_157
bit 18_158
bit 18_159
+bit 18_160
bit 18_161
bit 18_162
bit 18_163
@@ -1275,7 +1222,6 @@
bit 18_228
bit 18_229
bit 18_230
-bit 18_233
bit 18_234
bit 18_235
bit 18_236
@@ -1288,8 +1234,8 @@
bit 18_294
bit 18_297
bit 19_22
-bit 19_33
bit 19_41
+bit 19_49
bit 19_54
bit 19_62
bit 19_66
@@ -1307,7 +1253,6 @@
bit 19_83
bit 19_84
bit 19_85
-bit 19_86
bit 19_90
bit 19_91
bit 19_92
@@ -1323,7 +1268,6 @@
bit 19_107
bit 19_108
bit 19_109
-bit 19_113
bit 19_114
bit 19_115
bit 19_116
@@ -1350,6 +1294,7 @@
bit 19_149
bit 19_150
bit 19_151
+bit 19_152
bit 19_154
bit 19_155
bit 19_156
@@ -1416,7 +1361,6 @@
bit 19_245
bit 19_249
bit 19_278
-bit 19_297
bit 19_305
bit 20_74
bit 20_76
@@ -1550,8 +1494,8 @@
bit 21_243
bit 21_245
bit 22_23
-bit 22_32
bit 22_40
+bit 22_48
bit 22_55
bit 22_63
bit 22_66
@@ -1568,6 +1512,7 @@
bit 22_83
bit 22_84
bit 22_85
+bit 22_87
bit 22_90
bit 22_91
bit 22_92
@@ -1671,7 +1616,6 @@
bit 22_228
bit 22_229
bit 22_231
-bit 22_232
bit 22_234
bit 22_235
bit 22_236
@@ -1682,51 +1626,53 @@
bit 22_244
bit 22_245
bit 22_296
+bit 23_15
bit 23_23
bit 23_39
bit 23_40
bit 23_48
-bit 23_55
bit 23_66
bit 23_67
bit 23_68
bit 23_69
bit 23_79
bit 23_80
+bit 23_82
bit 23_83
bit 23_84
bit 23_85
bit 23_87
-bit 23_96
bit 23_104
-bit 23_112
+bit 23_127
bit 23_135
bit 23_143
-bit 23_146
bit 23_147
bit 23_148
bit 23_149
bit 23_150
-bit 23_151
bit 23_153
bit 23_154
bit 23_155
bit 23_156
bit 23_157
bit 23_158
+bit 23_159
bit 23_161
bit 23_168
+bit 23_169
bit 23_170
+bit 23_171
bit 23_172
+bit 23_173
bit 23_174
+bit 23_175
bit 23_184
-bit 23_232
bit 23_240
bit 23_279
bit 23_295
bit 23_304
+bit 24_15
bit 24_23
-bit 24_32
bit 24_39
bit 24_40
bit 24_47
@@ -1776,6 +1722,7 @@
bit 24_123
bit 24_124
bit 24_125
+bit 24_127
bit 24_128
bit 24_130
bit 24_131
@@ -1874,12 +1821,11 @@
bit 24_295
bit 24_296
bit 24_304
+bit 25_15
bit 25_23
-bit 25_32
bit 25_39
bit 25_40
bit 25_48
-bit 25_55
bit 25_66
bit 25_67
bit 25_68
@@ -1895,13 +1841,11 @@
bit 25_95
bit 25_96
bit 25_104
-bit 25_112
bit 25_119
bit 25_127
bit 25_130
bit 25_132
bit 25_135
-bit 25_136
bit 25_138
bit 25_140
bit 25_143
@@ -1918,7 +1862,6 @@
bit 25_157
bit 25_158
bit 25_159
-bit 25_160
bit 25_161
bit 25_167
bit 25_168
@@ -1936,7 +1879,7 @@
bit 25_184
bit 25_188
bit 25_215
-bit 25_231
+bit 25_223
bit 25_232
bit 25_240
bit 25_279
diff --git a/kintex7/mask_dsp_l.db b/kintex7/mask_dsp_l.db
index de174cf..6579fb8 100644
--- a/kintex7/mask_dsp_l.db
+++ b/kintex7/mask_dsp_l.db
@@ -1,7 +1,11 @@
bit 00_42
+bit 00_78
+bit 00_81
+bit 00_83
bit 00_86
bit 00_89
bit 00_106
+bit 00_127
bit 00_138
bit 00_139
bit 00_142
@@ -18,7 +22,6 @@
bit 00_234
bit 00_247
bit 00_253
-bit 00_266
bit 00_267
bit 00_273
bit 00_295
@@ -27,11 +30,13 @@
bit 01_32
bit 01_37
bit 01_38
+bit 01_77
bit 01_85
bit 01_88
bit 01_96
bit 01_101
bit 01_102
+bit 01_124
bit 01_138
bit 01_141
bit 01_142
@@ -46,6 +51,8 @@
bit 01_224
bit 01_229
bit 01_230
+bit 01_249
+bit 01_252
bit 01_265
bit 01_266
bit 01_269
@@ -53,11 +60,10 @@
bit 01_288
bit 01_293
bit 01_297
-bit 02_02
bit 02_06
bit 02_07
-bit 02_22
-bit 02_33
+bit 02_14
+bit 02_25
bit 02_38
bit 02_39
bit 02_46
@@ -68,451 +74,438 @@
bit 02_70
bit 02_71
bit 02_78
+bit 02_79
bit 02_86
bit 02_87
-bit 02_102
-bit 02_103
-bit 02_110
-bit 02_111
-bit 02_118
-bit 02_119
+bit 02_94
+bit 02_95
+bit 02_126
bit 02_134
-bit 02_135
+bit 02_139
bit 02_142
bit 02_143
+bit 02_145
bit 02_150
-bit 02_151
+bit 02_154
+bit 02_155
+bit 02_158
bit 02_159
-bit 02_161
bit 02_166
bit 02_167
-bit 02_182
+bit 02_187
bit 02_190
bit 02_191
bit 02_198
-bit 02_214
+bit 02_206
+bit 02_207
+bit 02_222
bit 02_230
bit 02_231
bit 02_238
-bit 02_242
+bit 02_239
bit 02_246
+bit 02_247
bit 02_254
bit 02_255
-bit 02_261
bit 02_262
bit 02_263
-bit 02_266
-bit 02_269
bit 02_270
bit 02_271
-bit 02_278
+bit 02_286
+bit 02_287
bit 02_294
-bit 02_295
+bit 02_302
+bit 02_303
bit 02_307
bit 02_310
bit 02_311
+bit 02_317
bit 02_318
bit 02_319
-bit 03_02
bit 03_06
-bit 03_14
-bit 03_38
-bit 03_54
+bit 03_16
bit 03_64
-bit 03_69
-bit 03_110
+bit 03_94
+bit 03_96
bit 03_112
-bit 03_134
+bit 03_141
bit 03_144
-bit 03_150
+bit 03_158
bit 03_160
-bit 03_173
-bit 03_176
-bit 03_189
+bit 03_166
bit 03_190
bit 03_192
-bit 03_198
-bit 03_204
-bit 03_214
-bit 03_218
-bit 03_220
-bit 03_221
+bit 03_205
+bit 03_208
+bit 03_222
bit 03_224
+bit 03_225
bit 03_228
bit 03_229
-bit 03_238
bit 03_242
bit 03_246
+bit 03_252
+bit 03_253
bit 03_254
-bit 03_256
-bit 03_260
-bit 03_261
bit 03_262
-bit 03_266
bit 03_268
+bit 03_269
bit 03_270
-bit 03_286
bit 03_288
-bit 03_294
-bit 03_304
bit 04_04
-bit 04_12
-bit 04_47
+bit 04_17
+bit 04_25
+bit 04_33
+bit 04_60
+bit 04_65
bit 04_97
-bit 04_108
-bit 04_113
bit 04_145
bit 04_156
+bit 04_164
bit 04_188
-bit 04_209
+bit 04_225
bit 04_228
bit 04_229
-bit 04_236
+bit 04_244
bit 04_252
-bit 04_261
+bit 04_257
+bit 04_267
bit 04_268
bit 04_269
-bit 04_284
-bit 04_300
+bit 04_271
bit 04_305
-bit 05_02
-bit 05_34
-bit 05_35
-bit 05_54
+bit 05_38
bit 05_67
-bit 05_68
bit 05_99
bit 05_115
-bit 05_147
-bit 05_150
+bit 05_138
bit 05_163
-bit 05_166
-bit 05_179
+bit 05_186
bit 05_195
-bit 05_207
-bit 05_218
+bit 05_211
bit 05_227
-bit 05_234
+bit 05_242
bit 05_246
-bit 05_259
-bit 05_262
+bit 05_266
bit 05_290
bit 05_291
bit 05_306
-bit 05_307
+bit 05_319
bit 06_09
-bit 06_37
-bit 06_53
+bit 06_11
+bit 06_32
+bit 06_59
bit 06_61
-bit 06_73
+bit 06_64
bit 06_75
bit 06_77
-bit 06_85
+bit 06_93
bit 06_96
-bit 06_99
bit 06_101
+bit 06_103
+bit 06_112
+bit 06_123
+bit 06_125
bit 06_129
bit 06_133
+bit 06_139
+bit 06_140
bit 06_141
-bit 06_144
-bit 06_160
+bit 06_155
bit 06_163
bit 06_165
bit 06_171
-bit 06_172
-bit 06_177
bit 06_181
bit 06_187
-bit 06_188
-bit 06_197
+bit 06_189
+bit 06_204
+bit 06_205
bit 06_208
+bit 06_211
bit 06_224
+bit 06_228
bit 06_233
-bit 06_249
+bit 06_245
bit 06_253
+bit 06_256
bit 06_259
-bit 06_275
-bit 06_277
-bit 06_283
-bit 06_289
+bit 06_265
+bit 06_267
+bit 06_268
+bit 06_269
bit 06_291
-bit 06_293
-bit 06_303
+bit 06_299
bit 06_304
-bit 06_309
+bit 06_315
+bit 06_319
bit 07_00
-bit 07_03
bit 07_08
-bit 07_23
+bit 07_15
bit 07_24
-bit 07_32
-bit 07_35
bit 07_39
bit 07_40
-bit 07_47
bit 07_48
bit 07_55
bit 07_56
+bit 07_63
bit 07_64
bit 07_70
bit 07_71
bit 07_72
bit 07_79
bit 07_80
-bit 07_88
-bit 07_103
+bit 07_102
bit 07_112
+bit 07_118
bit 07_120
+bit 07_127
bit 07_128
bit 07_135
bit 07_136
+bit 07_143
bit 07_144
bit 07_151
bit 07_152
+bit 07_154
bit 07_158
-bit 07_160
bit 07_166
bit 07_168
bit 07_176
-bit 07_178
-bit 07_183
bit 07_184
+bit 07_192
+bit 07_198
+bit 07_199
bit 07_200
-bit 07_208
-bit 07_210
-bit 07_215
+bit 07_207
+bit 07_214
bit 07_216
-bit 07_218
+bit 07_222
bit 07_224
-bit 07_230
bit 07_232
-bit 07_235
bit 07_236
-bit 07_238
-bit 07_247
+bit 07_239
bit 07_248
bit 07_256
bit 07_262
bit 07_264
-bit 07_279
+bit 07_272
bit 07_280
bit 07_291
bit 07_295
bit 07_296
bit 07_303
-bit 07_308
+bit 07_307
bit 07_312
bit 07_318
-bit 07_319
bit 08_01
bit 08_06
bit 08_08
bit 08_09
+bit 08_10
bit 08_14
-bit 08_22
-bit 08_31
+bit 08_15
+bit 08_23
+bit 08_24
+bit 08_25
+bit 08_30
bit 08_38
-bit 08_39
-bit 08_55
+bit 08_46
bit 08_62
bit 08_63
bit 08_70
-bit 08_71
-bit 08_72
bit 08_73
+bit 08_75
+bit 08_78
bit 08_86
-bit 08_87
+bit 08_89
bit 08_94
+bit 08_95
bit 08_102
-bit 08_103
-bit 08_104
bit 08_110
-bit 08_113
bit 08_118
bit 08_119
-bit 08_126
-bit 08_128
bit 08_129
bit 08_134
bit 08_142
bit 08_150
-bit 08_157
+bit 08_151
bit 08_161
bit 08_166
-bit 08_167
-bit 08_174
+bit 08_168
+bit 08_176
bit 08_177
bit 08_182
bit 08_183
+bit 08_184
bit 08_190
bit 08_191
bit 08_193
bit 08_198
bit 08_199
+bit 08_205
bit 08_206
bit 08_207
bit 08_208
bit 08_209
bit 08_214
bit 08_215
-bit 08_216
bit 08_217
+bit 08_218
bit 08_222
bit 08_223
bit 08_224
bit 08_225
-bit 08_230
bit 08_231
-bit 08_232
-bit 08_237
+bit 08_234
bit 08_238
bit 08_241
+bit 08_248
bit 08_249
-bit 08_253
bit 08_256
bit 08_262
-bit 08_264
+bit 08_263
+bit 08_265
bit 08_270
bit 08_271
-bit 08_273
-bit 08_280
+bit 08_272
+bit 08_282
bit 08_286
bit 08_294
-bit 08_296
+bit 08_295
bit 08_297
-bit 08_298
-bit 08_299
bit 08_302
-bit 08_310
bit 08_311
bit 08_312
+bit 08_313
bit 08_318
bit 08_319
bit 09_02
bit 09_03
bit 09_04
bit 09_10
-bit 09_18
-bit 09_26
-bit 09_34
+bit 09_24
+bit 09_27
bit 09_35
bit 09_36
-bit 09_42
+bit 09_40
bit 09_43
bit 09_50
bit 09_51
bit 09_58
bit 09_59
-bit 09_63
bit 09_67
+bit 09_72
bit 09_73
bit 09_74
-bit 09_82
bit 09_90
bit 09_91
bit 09_99
-bit 09_115
+bit 09_106
+bit 09_107
bit 09_122
-bit 09_123
-bit 09_130
bit 09_131
bit 09_132
-bit 09_137
-bit 09_138
bit 09_139
bit 09_147
bit 09_148
-bit 09_151
+bit 09_152
bit 09_154
+bit 09_155
bit 09_162
bit 09_163
+bit 09_167
bit 09_170
-bit 09_176
+bit 09_171
bit 09_177
bit 09_178
-bit 09_179
bit 09_180
-bit 09_181
bit 09_186
+bit 09_187
bit 09_191
-bit 09_194
bit 09_195
+bit 09_199
bit 09_202
-bit 09_208
-bit 09_209
bit 09_211
-bit 09_218
-bit 09_219
+bit 09_226
bit 09_227
+bit 09_228
bit 09_232
bit 09_233
-bit 09_234
bit 09_242
bit 09_243
-bit 09_251
+bit 09_250
+bit 09_257
bit 09_258
bit 09_259
-bit 09_262
+bit 09_264
+bit 09_265
bit 09_266
bit 09_267
-bit 09_269
bit 09_274
bit 09_275
-bit 09_276
+bit 09_281
bit 09_282
+bit 09_283
bit 09_285
-bit 09_291
+bit 09_290
bit 09_298
bit 09_306
+bit 09_312
bit 09_314
bit 09_317
-bit 10_07
bit 10_08
bit 10_09
bit 10_14
-bit 10_24
+bit 10_23
+bit 10_41
bit 10_57
-bit 10_73
bit 10_76
bit 10_121
+bit 10_122
bit 10_130
-bit 10_150
-bit 10_153
-bit 10_169
-bit 10_170
+bit 10_140
bit 10_174
-bit 10_177
-bit 10_180
-bit 10_216
+bit 10_185
+bit 10_186
+bit 10_194
+bit 10_199
bit 10_217
-bit 10_223
bit 10_226
-bit 10_231
+bit 10_233
+bit 10_234
bit 10_249
bit 10_252
-bit 10_256
bit 10_263
bit 10_264
-bit 10_275
-bit 10_276
-bit 10_292
-bit 10_312
-bit 10_318
+bit 10_266
+bit 10_270
+bit 10_272
+bit 10_290
+bit 10_298
+bit 10_313
bit 11_01
-bit 11_02
+bit 11_08
+bit 11_09
+bit 11_10
+bit 11_17
bit 11_18
-bit 11_24
+bit 11_23
+bit 11_25
+bit 11_26
bit 11_31
bit 11_34
-bit 11_39
bit 11_41
bit 11_42
-bit 11_47
bit 11_50
+bit 11_51
bit 11_55
+bit 11_57
bit 11_58
bit 11_63
+bit 11_65
bit 11_66
+bit 11_71
+bit 11_72
bit 11_73
bit 11_74
bit 11_82
@@ -520,79 +513,83 @@
bit 11_90
bit 11_97
bit 11_98
-bit 11_103
bit 11_105
+bit 11_111
bit 11_113
+bit 11_114
bit 11_119
+bit 11_127
bit 11_129
bit 11_130
bit 11_135
bit 11_137
+bit 11_138
+bit 11_143
bit 11_145
bit 11_146
+bit 11_151
+bit 11_153
bit 11_154
bit 11_161
-bit 11_162
bit 11_167
+bit 11_169
bit 11_170
bit 11_177
-bit 11_178
bit 11_180
bit 11_183
bit 11_185
bit 11_186
-bit 11_192
bit 11_193
bit 11_194
bit 11_199
+bit 11_202
bit 11_207
bit 11_209
bit 11_215
bit 11_216
-bit 11_219
+bit 11_217
+bit 11_218
bit 11_223
bit 11_225
bit 11_226
bit 11_231
-bit 11_232
-bit 11_245
+bit 11_233
+bit 11_241
+bit 11_249
bit 11_250
-bit 11_255
bit 11_257
bit 11_258
bit 11_263
+bit 11_264
bit 11_265
bit 11_266
+bit 11_268
bit 11_271
bit 11_273
bit 11_274
-bit 11_282
+bit 11_280
bit 11_287
-bit 11_289
bit 11_290
-bit 11_291
-bit 11_295
bit 11_303
-bit 11_305
bit 11_306
bit 11_311
bit 11_313
bit 11_314
bit 11_319
-bit 12_01
bit 12_02
bit 12_04
+bit 12_08
bit 12_09
-bit 12_18
+bit 12_10
+bit 12_15
bit 12_23
+bit 12_25
bit 12_26
bit 12_31
-bit 12_33
-bit 12_34
bit 12_36
bit 12_39
+bit 12_41
bit 12_42
-bit 12_47
bit 12_50
bit 12_58
bit 12_63
@@ -601,83 +598,80 @@
bit 12_72
bit 12_73
bit 12_74
-bit 12_82
+bit 12_76
+bit 12_79
bit 12_87
bit 12_90
bit 12_95
bit 12_98
+bit 12_102
bit 12_103
+bit 12_106
+bit 12_111
bit 12_113
-bit 12_114
bit 12_119
bit 12_121
bit 12_122
+bit 12_124
+bit 12_127
bit 12_128
bit 12_129
bit 12_130
bit 12_132
bit 12_135
-bit 12_136
+bit 12_137
bit 12_138
+bit 12_140
+bit 12_143
bit 12_145
bit 12_146
bit 12_148
-bit 12_150
+bit 12_151
bit 12_154
bit 12_162
bit 12_164
bit 12_167
-bit 12_169
bit 12_170
bit 12_174
-bit 12_176
-bit 12_178
-bit 12_179
bit 12_180
bit 12_183
bit 12_186
+bit 12_190
bit 12_191
bit 12_194
bit 12_199
bit 12_201
bit 12_202
+bit 12_205
bit 12_207
bit 12_210
-bit 12_211
bit 12_215
bit 12_217
-bit 12_218
+bit 12_223
bit 12_225
bit 12_226
-bit 12_231
+bit 12_228
bit 12_232
+bit 12_233
bit 12_234
-bit 12_237
bit 12_242
-bit 12_248
+bit 12_244
bit 12_249
bit 12_250
bit 12_252
-bit 12_253
-bit 12_255
bit 12_256
bit 12_258
-bit 12_262
+bit 12_263
bit 12_264
bit 12_266
-bit 12_271
+bit 12_272
bit 12_274
-bit 12_276
+bit 12_280
bit 12_282
bit 12_287
-bit 12_288
bit 12_290
-bit 12_292
-bit 12_295
bit 12_297
bit 12_298
-bit 12_299
-bit 12_302
bit 12_303
bit 12_306
bit 12_311
@@ -685,209 +679,217 @@
bit 12_314
bit 12_319
bit 13_01
-bit 13_02
+bit 13_07
+bit 13_08
bit 13_09
+bit 13_10
+bit 13_11
bit 13_14
-bit 13_24
-bit 13_31
-bit 13_36
+bit 13_15
+bit 13_25
+bit 13_26
bit 13_39
bit 13_41
-bit 13_42
bit 13_50
-bit 13_52
+bit 13_51
bit 13_55
-bit 13_62
+bit 13_57
+bit 13_58
bit 13_63
+bit 13_65
bit 13_66
bit 13_71
+bit 13_72
bit 13_73
bit 13_76
bit 13_87
bit 13_89
+bit 13_90
+bit 13_92
+bit 13_95
bit 13_97
bit 13_98
bit 13_103
bit 13_105
-bit 13_111
bit 13_113
bit 13_119
+bit 13_124
bit 13_129
bit 13_130
+bit 13_132
bit 13_135
bit 13_137
+bit 13_140
bit 13_143
bit 13_145
bit 13_146
-bit 13_157
+bit 13_151
+bit 13_152
+bit 13_153
+bit 13_155
bit 13_159
bit 13_161
-bit 13_162
-bit 13_164
bit 13_167
+bit 13_169
bit 13_170
bit 13_174
-bit 13_175
+bit 13_176
bit 13_177
+bit 13_178
+bit 13_180
bit 13_183
bit 13_185
bit 13_186
-bit 13_190
+bit 13_188
bit 13_191
-bit 13_192
bit 13_193
bit 13_194
+bit 13_198
bit 13_199
+bit 13_202
+bit 13_204
bit 13_207
-bit 13_208
-bit 13_211
+bit 13_209
bit 13_215
bit 13_216
bit 13_217
+bit 13_219
bit 13_223
bit 13_225
bit 13_226
bit 13_231
bit 13_233
+bit 13_235
bit 13_237
bit 13_239
bit 13_241
+bit 13_249
bit 13_257
-bit 13_258
bit 13_263
+bit 13_264
bit 13_265
+bit 13_266
+bit 13_268
+bit 13_270
bit 13_271
bit 13_273
-bit 13_274
-bit 13_276
+bit 13_281
+bit 13_283
bit 13_287
-bit 13_289
-bit 13_291
bit 13_297
bit 13_303
-bit 13_305
-bit 13_308
+bit 13_306
bit 13_311
+bit 13_312
bit 13_313
bit 13_314
bit 13_318
bit 13_319
-bit 14_02
bit 14_08
bit 14_10
bit 14_18
+bit 14_24
bit 14_34
+bit 14_40
bit 14_42
-bit 14_50
bit 14_58
bit 14_60
bit 14_66
+bit 14_72
bit 14_74
+bit 14_76
bit 14_82
-bit 14_84
-bit 14_90
bit 14_98
bit 14_100
+bit 14_114
+bit 14_122
bit 14_130
bit 14_132
-bit 14_140
+bit 14_138
bit 14_148
bit 14_154
bit 14_162
+bit 14_166
bit 14_170
-bit 14_176
bit 14_178
bit 14_180
bit 14_186
-bit 14_190
bit 14_194
-bit 14_196
-bit 14_208
-bit 14_216
bit 14_218
bit 14_226
bit 14_232
+bit 14_242
bit 14_250
bit 14_252
bit 14_258
+bit 14_264
bit 14_266
bit 14_268
bit 14_274
-bit 14_276
-bit 14_282
+bit 14_280
bit 14_284
bit 14_290
+bit 14_298
bit 14_306
-bit 14_312
bit 14_314
bit 14_316
+bit 15_01
bit 15_07
bit 15_09
bit 15_15
+bit 15_17
bit 15_25
+bit 15_31
bit 15_39
bit 15_41
+bit 15_47
bit 15_49
-bit 15_55
bit 15_57
bit 15_63
bit 15_65
bit 15_71
-bit 15_73
+bit 15_75
bit 15_81
bit 15_87
bit 15_103
-bit 15_113
+bit 15_111
bit 15_119
bit 15_121
-bit 15_127
bit 15_129
-bit 15_135
bit 15_137
bit 15_151
-bit 15_153
-bit 15_161
bit 15_167
bit 15_169
bit 15_177
bit 15_183
bit 15_185
bit 15_191
-bit 15_193
bit 15_199
bit 15_201
-bit 15_207
bit 15_209
-bit 15_217
-bit 15_219
+bit 15_215
bit 15_223
bit 15_225
-bit 15_231
bit 15_233
-bit 15_239
-bit 15_245
+bit 15_241
bit 15_249
bit 15_257
bit 15_263
bit 15_265
bit 15_273
-bit 15_275
bit 15_281
+bit 15_287
bit 15_295
bit 15_297
-bit 15_299
-bit 15_309
-bit 15_311
+bit 15_303
bit 15_313
bit 15_319
bit 16_00
bit 16_07
bit 16_95
bit 16_96
-bit 16_103
bit 16_135
bit 16_144
-bit 16_151
bit 16_156
bit 16_157
bit 16_162
@@ -896,15 +898,15 @@
bit 16_180
bit 16_181
bit 16_183
-bit 16_199
bit 16_207
+bit 16_223
bit 16_228
bit 16_229
bit 16_231
bit 16_234
bit 16_235
-bit 16_240
bit 16_247
+bit 16_248
bit 16_250
bit 16_256
bit 16_257
@@ -914,17 +916,20 @@
bit 16_263
bit 16_264
bit 16_266
-bit 16_267
+bit 16_271
bit 16_272
bit 16_279
bit 16_280
bit 16_288
bit 17_00
bit 17_07
+bit 17_96
+bit 17_103
+bit 17_104
+bit 17_144
bit 17_151
bit 17_156
bit 17_157
-bit 17_159
bit 17_160
bit 17_162
bit 17_163
@@ -936,26 +941,30 @@
bit 17_229
bit 17_231
bit 17_234
-bit 17_235
-bit 17_247
+bit 17_240
+bit 17_248
bit 17_250
bit 17_251
+bit 17_256
bit 17_257
bit 17_258
bit 17_259
+bit 17_262
bit 17_263
bit 17_264
bit 17_266
+bit 17_267
+bit 17_272
bit 17_296
-bit 17_303
-bit 17_312
bit 18_01
-bit 18_25
+bit 18_06
+bit 18_17
bit 18_97
-bit 18_102
-bit 18_105
+bit 18_145
bit 18_150
bit 18_156
+bit 18_157
+bit 18_158
bit 18_161
bit 18_162
bit 18_163
@@ -964,10 +973,10 @@
bit 18_180
bit 18_181
bit 18_182
-bit 18_206
-bit 18_209
+bit 18_193
bit 18_228
bit 18_229
+bit 18_234
bit 18_235
bit 18_241
bit 18_246
@@ -979,24 +988,24 @@
bit 18_259
bit 18_262
bit 18_263
+bit 18_265
bit 18_266
-bit 18_267
-bit 18_270
bit 18_273
bit 18_278
bit 18_289
+bit 18_294
+bit 18_297
bit 19_01
bit 19_06
bit 19_09
bit 19_17
-bit 19_97
+bit 19_25
+bit 19_94
bit 19_102
-bit 19_134
bit 19_145
bit 19_150
bit 19_156
bit 19_157
-bit 19_158
bit 19_161
bit 19_162
bit 19_163
@@ -1006,8 +1015,7 @@
bit 19_181
bit 19_182
bit 19_185
-bit 19_198
-bit 19_206
+bit 19_209
bit 19_222
bit 19_228
bit 19_229
@@ -1027,31 +1035,34 @@
bit 19_263
bit 19_265
bit 19_266
+bit 19_267
bit 19_273
bit 19_278
+bit 19_281
bit 19_289
bit 20_00
bit 20_96
+bit 20_103
+bit 20_144
bit 20_156
bit 20_160
-bit 20_163
-bit 20_228
+bit 20_162
+bit 20_183
+bit 20_184
bit 20_234
bit 20_256
-bit 20_257
bit 20_262
bit 20_266
-bit 20_267
-bit 20_288
+bit 20_272
bit 20_293
bit 21_07
+bit 21_96
bit 21_103
bit 21_157
bit 21_160
bit 21_163
+bit 21_181
bit 21_183
-bit 21_199
-bit 21_229
bit 21_235
bit 21_242
bit 21_244
@@ -1059,14 +1070,17 @@
bit 21_256
bit 21_257
bit 21_267
+bit 21_279
bit 21_292
bit 22_00
bit 22_07
bit 22_08
bit 22_16
+bit 22_24
bit 22_95
bit 22_96
bit 22_103
+bit 22_104
bit 22_144
bit 22_151
bit 22_156
@@ -1079,7 +1093,8 @@
bit 22_180
bit 22_181
bit 22_183
-bit 22_207
+bit 22_184
+bit 22_192
bit 22_228
bit 22_229
bit 22_231
@@ -1087,6 +1102,7 @@
bit 22_235
bit 22_240
bit 22_247
+bit 22_248
bit 22_250
bit 22_251
bit 22_256
@@ -1102,52 +1118,58 @@
bit 22_279
bit 22_280
bit 22_288
+bit 22_296
bit 23_00
bit 23_07
+bit 23_95
bit 23_96
bit 23_103
bit 23_144
bit 23_151
bit 23_156
bit 23_157
+bit 23_159
bit 23_160
-bit 23_162
bit 23_163
bit 23_168
+bit 23_176
bit 23_180
bit 23_181
bit 23_183
bit 23_184
-bit 23_199
+bit 23_207
bit 23_223
bit 23_228
bit 23_229
-bit 23_231
bit 23_234
bit 23_235
bit 23_240
bit 23_247
+bit 23_248
bit 23_250
bit 23_251
bit 23_256
+bit 23_257
bit 23_258
bit 23_259
bit 23_262
bit 23_263
-bit 23_264
bit 23_266
bit 23_267
+bit 23_271
bit 23_272
bit 23_279
bit 23_288
-bit 23_303
+bit 23_295
bit 24_00
bit 24_07
bit 24_08
bit 24_16
+bit 24_24
bit 24_95
bit 24_96
bit 24_103
+bit 24_104
bit 24_135
bit 24_144
bit 24_151
@@ -1163,7 +1185,7 @@
bit 24_181
bit 24_183
bit 24_184
-bit 24_199
+bit 24_192
bit 24_207
bit 24_208
bit 24_223
@@ -1192,7 +1214,8 @@
bit 24_280
bit 24_288
bit 24_293
-bit 24_303
+bit 24_295
+bit 24_296
bit 25_00
bit 25_07
bit 25_08
@@ -1202,6 +1225,7 @@
bit 25_96
bit 25_103
bit 25_104
+bit 25_135
bit 25_144
bit 25_151
bit 25_156
@@ -1216,7 +1240,7 @@
bit 25_181
bit 25_183
bit 25_184
-bit 25_199
+bit 25_192
bit 25_207
bit 25_223
bit 25_228
@@ -1240,14 +1264,14 @@
bit 25_264
bit 25_266
bit 25_267
+bit 25_271
bit 25_272
bit 25_279
bit 25_280
bit 25_288
bit 25_292
+bit 25_295
bit 25_296
-bit 25_303
-bit 25_312
bit 26_01
bit 26_02
bit 26_03
diff --git a/kintex7/mask_dsp_r.db b/kintex7/mask_dsp_r.db
index b291547..c6b32e4 100644
--- a/kintex7/mask_dsp_r.db
+++ b/kintex7/mask_dsp_r.db
@@ -1,6 +1,3 @@
-bit 00_07
-bit 00_09
-bit 00_11
bit 00_42
bit 00_78
bit 00_81
@@ -20,13 +17,12 @@
bit 00_214
bit 00_217
bit 00_234
+bit 00_257
+bit 00_259
bit 00_266
bit 00_267
bit 00_273
bit 00_295
-bit 01_09
-bit 01_10
-bit 01_14
bit 01_32
bit 01_37
bit 01_38
@@ -71,47 +67,55 @@
bit 02_46
bit 02_47
bit 02_54
+bit 02_55
bit 02_62
bit 02_63
bit 02_70
bit 02_71
bit 02_78
+bit 02_79
bit 02_86
bit 02_87
+bit 02_89
bit 02_94
bit 02_95
bit 02_102
-bit 02_103
bit 02_110
bit 02_111
+bit 02_118
+bit 02_119
+bit 02_126
bit 02_134
bit 02_135
bit 02_142
bit 02_143
bit 02_150
bit 02_151
+bit 02_154
+bit 02_155
+bit 02_158
bit 02_159
bit 02_166
bit 02_167
+bit 02_169
bit 02_174
bit 02_175
-bit 02_182
+bit 02_183
bit 02_190
bit 02_191
bit 02_198
bit 02_199
+bit 02_205
bit 02_206
-bit 02_210
+bit 02_207
bit 02_214
bit 02_222
-bit 02_223
-bit 02_227
+bit 02_229
bit 02_230
bit 02_231
bit 02_234
bit 02_238
bit 02_239
-bit 02_242
bit 02_246
bit 02_247
bit 02_253
@@ -121,56 +125,50 @@
bit 02_262
bit 02_263
bit 02_266
+bit 02_267
bit 02_269
bit 02_270
bit 02_271
-bit 02_278
-bit 02_279
bit 02_286
bit 02_287
bit 02_294
bit 02_295
-bit 02_297
bit 02_302
-bit 02_307
bit 02_310
bit 02_311
bit 02_318
+bit 02_319
bit 03_02
+bit 03_05
bit 03_06
bit 03_14
bit 03_22
-bit 03_25
-bit 03_70
-bit 03_86
+bit 03_40
+bit 03_44
+bit 03_45
+bit 03_56
+bit 03_60
+bit 03_61
+bit 03_88
bit 03_94
-bit 03_102
bit 03_104
-bit 03_110
bit 03_120
-bit 03_126
+bit 03_136
bit 03_158
-bit 03_166
-bit 03_168
-bit 03_182
-bit 03_189
-bit 03_190
+bit 03_173
+bit 03_184
+bit 03_198
bit 03_200
bit 03_205
-bit 03_206
-bit 03_213
-bit 03_214
-bit 03_216
-bit 03_221
bit 03_228
bit 03_229
bit 03_230
bit 03_234
+bit 03_238
bit 03_242
bit 03_246
bit 03_253
bit 03_254
-bit 03_258
bit 03_260
bit 03_261
bit 03_262
@@ -178,379 +176,398 @@
bit 03_268
bit 03_269
bit 03_270
-bit 03_286
-bit 03_290
+bit 03_280
bit 03_294
-bit 03_297
bit 04_04
+bit 04_09
bit 04_12
-bit 04_68
-bit 04_100
+bit 04_41
+bit 04_60
+bit 04_76
+bit 04_79
+bit 04_89
bit 04_105
bit 04_108
+bit 04_119
bit 04_121
-bit 04_124
-bit 04_148
-bit 04_151
-bit 04_156
-bit 04_164
+bit 04_137
bit 04_169
-bit 04_188
+bit 04_185
+bit 04_196
bit 04_199
-bit 04_201
-bit 04_204
-bit 04_211
-bit 04_217
+bit 04_207
bit 04_229
-bit 04_244
-bit 04_247
+bit 04_233
+bit 04_236
+bit 04_252
bit 04_260
bit 04_261
bit 04_268
bit 04_269
-bit 04_284
-bit 04_292
+bit 04_281
bit 04_313
bit 05_02
-bit 05_06
+bit 05_04
bit 05_43
+bit 05_59
+bit 05_91
+bit 05_94
+bit 05_123
+bit 05_130
bit 05_139
-bit 05_140
-bit 05_143
+bit 05_150
bit 05_158
-bit 05_166
+bit 05_170
+bit 05_182
bit 05_187
-bit 05_216
+bit 05_200
+bit 05_203
+bit 05_204
bit 05_219
-bit 05_226
bit 05_230
-bit 05_245
-bit 05_254
-bit 05_258
+bit 05_242
+bit 05_251
+bit 05_255
bit 05_263
bit 05_270
-bit 05_271
+bit 05_283
bit 05_290
-bit 05_294
-bit 05_299
-bit 05_306
bit 05_315
-bit 06_01
bit 06_03
-bit 06_24
-bit 06_33
-bit 06_35
-bit 06_39
+bit 06_08
+bit 06_11
+bit 06_37
bit 06_40
-bit 06_43
-bit 06_51
-bit 06_69
-bit 06_73
+bit 06_44
+bit 06_59
+bit 06_61
+bit 06_67
bit 06_75
bit 06_77
+bit 06_78
bit 06_85
bit 06_99
bit 06_101
+bit 06_107
bit 06_120
-bit 06_123
bit 06_125
-bit 06_131
bit 06_133
bit 06_136
-bit 06_147
-bit 06_149
+bit 06_145
bit 06_155
+bit 06_161
bit 06_163
bit 06_165
+bit 06_167
bit 06_171
-bit 06_177
+bit 06_172
bit 06_179
bit 06_181
bit 06_184
-bit 06_187
-bit 06_188
-bit 06_199
-bit 06_204
-bit 06_209
-bit 06_212
+bit 06_197
+bit 06_200
+bit 06_203
+bit 06_205
bit 06_216
-bit 06_219
-bit 06_220
-bit 06_227
-bit 06_228
-bit 06_229
+bit 06_221
+bit 06_225
+bit 06_232
bit 06_243
-bit 06_245
+bit 06_248
bit 06_249
-bit 06_251
bit 06_253
bit 06_259
-bit 06_261
+bit 06_265
bit 06_267
bit 06_268
bit 06_269
-bit 06_275
bit 06_277
-bit 06_279
bit 06_283
bit 06_285
-bit 06_289
bit 06_291
bit 06_293
-bit 06_296
bit 06_312
-bit 06_315
-bit 06_317
bit 07_00
+bit 07_03
bit 07_07
bit 07_08
bit 07_15
-bit 07_23
bit 07_24
bit 07_26
+bit 07_31
bit 07_32
-bit 07_38
bit 07_39
bit 07_40
bit 07_42
+bit 07_46
bit 07_47
bit 07_48
bit 07_55
bit 07_56
+bit 07_62
+bit 07_63
bit 07_64
bit 07_71
bit 07_72
bit 07_79
bit 07_80
-bit 07_87
bit 07_88
+bit 07_90
+bit 07_95
+bit 07_96
bit 07_103
bit 07_104
-bit 07_106
bit 07_111
bit 07_112
-bit 07_118
bit 07_120
+bit 07_127
bit 07_128
+bit 07_131
bit 07_135
bit 07_136
bit 07_143
+bit 07_144
bit 07_151
bit 07_152
bit 07_154
-bit 07_156
bit 07_158
+bit 07_159
bit 07_160
-bit 07_166
+bit 07_167
bit 07_168
-bit 07_174
-bit 07_175
+bit 07_171
bit 07_176
-bit 07_178
bit 07_184
bit 07_190
+bit 07_191
+bit 07_192
bit 07_198
bit 07_199
bit 07_200
-bit 07_206
bit 07_207
bit 07_208
bit 07_214
bit 07_215
bit 07_216
+bit 07_222
+bit 07_223
bit 07_224
bit 07_230
-bit 07_231
-bit 07_232
bit 07_236
bit 07_239
+bit 07_240
+bit 07_247
bit 07_248
-bit 07_256
+bit 07_254
bit 07_262
bit 07_263
bit 07_264
+bit 07_270
bit 07_271
bit 07_272
-bit 07_279
+bit 07_278
bit 07_280
+bit 07_282
bit 07_287
bit 07_291
-bit 07_294
bit 07_295
bit 07_296
+bit 07_302
bit 07_303
-bit 07_307
bit 07_311
bit 07_312
+bit 07_318
bit 07_319
bit 08_01
bit 08_06
bit 08_08
bit 08_09
+bit 08_11
bit 08_14
+bit 08_15
bit 08_16
bit 08_22
+bit 08_23
+bit 08_24
bit 08_25
bit 08_30
bit 08_31
-bit 08_37
+bit 08_36
bit 08_38
-bit 08_39
+bit 08_40
bit 08_46
+bit 08_48
bit 08_54
+bit 08_55
bit 08_62
-bit 08_63
bit 08_70
-bit 08_71
-bit 08_72
bit 08_73
-bit 08_78
+bit 08_81
bit 08_85
bit 08_86
bit 08_87
-bit 08_88
bit 08_94
-bit 08_95
+bit 08_96
+bit 08_100
bit 08_102
+bit 08_103
+bit 08_104
bit 08_105
bit 08_112
-bit 08_116
+bit 08_113
bit 08_118
bit 08_119
-bit 08_121
+bit 08_120
+bit 08_125
bit 08_126
+bit 08_128
bit 08_129
bit 08_134
-bit 08_137
-bit 08_148
+bit 08_142
+bit 08_144
+bit 08_145
bit 08_150
-bit 08_153
+bit 08_151
+bit 08_152
bit 08_160
bit 08_161
+bit 08_164
bit 08_166
bit 08_167
-bit 08_168
bit 08_174
+bit 08_176
bit 08_177
+bit 08_180
bit 08_182
bit 08_183
bit 08_190
bit 08_191
bit 08_193
-bit 08_196
bit 08_198
bit 08_199
-bit 08_201
-bit 08_205
bit 08_206
bit 08_207
bit 08_208
-bit 08_209
bit 08_214
bit 08_215
bit 08_216
bit 08_217
bit 08_222
bit 08_223
-bit 08_224
bit 08_225
bit 08_230
bit 08_231
-bit 08_236
+bit 08_232
bit 08_238
bit 08_241
-bit 08_254
+bit 08_248
+bit 08_249
bit 08_256
bit 08_262
bit 08_263
+bit 08_264
bit 08_265
bit 08_270
bit 08_271
+bit 08_272
bit 08_273
-bit 08_278
+bit 08_276
+bit 08_280
bit 08_286
bit 08_287
-bit 08_293
bit 08_294
-bit 08_296
+bit 08_295
bit 08_297
bit 08_302
bit 08_303
+bit 08_304
bit 08_310
bit 08_311
-bit 08_312
+bit 08_313
bit 08_318
bit 08_319
bit 09_02
+bit 09_03
bit 09_04
-bit 09_08
bit 09_09
bit 09_10
bit 09_18
-bit 09_19
bit 09_24
-bit 09_25
-bit 09_31
+bit 09_26
bit 09_35
+bit 09_36
bit 09_40
bit 09_42
bit 09_43
bit 09_50
bit 09_51
-bit 09_52
bit 09_58
+bit 09_59
bit 09_66
bit 09_67
bit 09_72
bit 09_73
bit 09_74
+bit 09_75
bit 09_82
bit 09_83
+bit 09_88
+bit 09_89
bit 09_90
+bit 09_91
+bit 09_96
+bit 09_98
bit 09_99
-bit 09_100
-bit 09_109
-bit 09_112
+bit 09_101
+bit 09_106
bit 09_114
+bit 09_115
bit 09_122
+bit 09_123
bit 09_128
-bit 09_130
bit 09_131
bit 09_132
bit 09_138
bit 09_139
bit 09_147
bit 09_148
-bit 09_153
bit 09_154
bit 09_155
-bit 09_159
bit 09_162
bit 09_163
-bit 09_176
+bit 09_167
+bit 09_169
+bit 09_170
+bit 09_175
+bit 09_177
bit 09_178
bit 09_179
bit 09_180
bit 09_181
bit 09_186
bit 09_187
-bit 09_188
-bit 09_192
-bit 09_194
+bit 09_190
+bit 09_191
bit 09_195
+bit 09_200
+bit 09_201
bit 09_202
+bit 09_204
bit 09_208
bit 09_210
bit 09_211
+bit 09_216
bit 09_218
+bit 09_219
bit 09_227
bit 09_232
bit 09_233
bit 09_234
-bit 09_241
+bit 09_235
bit 09_242
bit 09_243
-bit 09_249
+bit 09_250
+bit 09_251
bit 09_258
bit 09_259
bit 09_265
@@ -558,83 +575,80 @@
bit 09_267
bit 09_268
bit 09_269
-bit 09_270
bit 09_274
bit 09_275
+bit 09_280
bit 09_281
bit 09_282
+bit 09_283
bit 09_284
bit 09_285
-bit 09_288
bit 09_290
bit 09_291
bit 09_292
+bit 09_294
bit 09_298
-bit 09_300
-bit 09_304
bit 09_306
+bit 09_307
+bit 09_312
bit 09_314
bit 10_06
bit 10_09
+bit 10_10
bit 10_11
-bit 10_25
+bit 10_14
+bit 10_51
+bit 10_60
bit 10_65
-bit 10_72
+bit 10_73
+bit 10_74
bit 10_76
-bit 10_92
+bit 10_97
bit 10_98
bit 10_100
-bit 10_121
+bit 10_112
bit 10_129
bit 10_130
+bit 10_138
bit 10_140
-bit 10_146
-bit 10_148
-bit 10_151
-bit 10_158
+bit 10_143
+bit 10_160
bit 10_161
-bit 10_167
+bit 10_162
+bit 10_166
+bit 10_169
bit 10_170
bit 10_174
-bit 10_177
bit 10_178
bit 10_180
-bit 10_182
-bit 10_185
+bit 10_183
bit 10_186
-bit 10_187
bit 10_191
-bit 10_192
-bit 10_193
-bit 10_207
-bit 10_209
+bit 10_194
+bit 10_204
bit 10_217
bit 10_223
-bit 10_225
bit 10_226
bit 10_231
-bit 10_233
-bit 10_239
+bit 10_232
bit 10_242
bit 10_249
-bit 10_252
-bit 10_257
-bit 10_258
-bit 10_260
bit 10_263
bit 10_264
+bit 10_265
+bit 10_266
+bit 10_268
bit 10_270
+bit 10_273
bit 10_276
-bit 10_284
+bit 10_282
bit 10_290
-bit 10_291
-bit 10_292
-bit 10_294
bit 10_297
-bit 10_314
-bit 10_318
-bit 11_01
+bit 10_304
+bit 10_307
+bit 10_316
bit 11_02
+bit 11_07
bit 11_09
bit 11_10
bit 11_18
@@ -642,34 +656,37 @@
bit 11_25
bit 11_26
bit 11_31
+bit 11_33
bit 11_34
bit 11_39
bit 11_41
bit 11_42
-bit 11_47
+bit 11_49
bit 11_50
+bit 11_51
+bit 11_56
bit 11_58
bit 11_63
-bit 11_65
bit 11_66
bit 11_71
bit 11_73
bit 11_74
+bit 11_75
bit 11_79
-bit 11_82
+bit 11_81
bit 11_87
bit 11_89
bit 11_90
bit 11_95
bit 11_97
bit 11_98
-bit 11_100
-bit 11_103
bit 11_105
+bit 11_107
+bit 11_111
bit 11_113
bit 11_114
bit 11_119
-bit 11_121
+bit 11_122
bit 11_127
bit 11_129
bit 11_130
@@ -677,85 +694,97 @@
bit 11_137
bit 11_138
bit 11_145
+bit 11_146
+bit 11_151
bit 11_153
bit 11_154
-bit 11_155
-bit 11_159
+bit 11_160
+bit 11_161
bit 11_162
+bit 11_164
bit 11_167
bit 11_170
+bit 11_175
bit 11_177
bit 11_178
+bit 11_180
bit 11_183
bit 11_185
bit 11_186
+bit 11_187
+bit 11_192
bit 11_193
bit 11_194
bit 11_199
-bit 11_201
+bit 11_200
bit 11_202
bit 11_207
bit 11_209
-bit 11_210
bit 11_215
bit 11_217
bit 11_218
+bit 11_219
bit 11_223
-bit 11_224
bit 11_225
bit 11_226
-bit 11_231
+bit 11_233
+bit 11_234
bit 11_237
bit 11_239
+bit 11_241
+bit 11_242
+bit 11_247
bit 11_249
+bit 11_250
bit 11_255
+bit 11_257
bit 11_258
bit 11_263
bit 11_264
bit 11_265
bit 11_266
-bit 11_267
bit 11_268
bit 11_271
bit 11_273
bit 11_274
-bit 11_275
bit 11_281
bit 11_282
bit 11_287
bit 11_289
bit 11_290
bit 11_295
+bit 11_297
+bit 11_298
bit 11_303
bit 11_306
bit 11_311
bit 11_313
bit 11_314
bit 11_319
-bit 12_00
bit 12_01
bit 12_02
bit 12_04
bit 12_06
+bit 12_07
bit 12_08
+bit 12_09
bit 12_10
bit 12_15
bit 12_18
bit 12_23
bit 12_25
+bit 12_26
bit 12_31
-bit 12_32
-bit 12_33
bit 12_34
-bit 12_37
+bit 12_36
bit 12_39
bit 12_41
bit 12_42
-bit 12_47
+bit 12_49
bit 12_50
-bit 12_52
-bit 12_55
+bit 12_51
bit 12_58
+bit 12_60
bit 12_63
bit 12_65
bit 12_66
@@ -764,240 +793,265 @@
bit 12_73
bit 12_74
bit 12_76
+bit 12_79
bit 12_82
+bit 12_84
bit 12_87
+bit 12_88
bit 12_89
bit 12_90
-bit 12_92
bit 12_95
+bit 12_97
bit 12_98
bit 12_100
bit 12_103
bit 12_105
-bit 12_108
+bit 12_106
+bit 12_111
+bit 12_112
bit 12_113
bit 12_114
bit 12_119
+bit 12_121
bit 12_122
bit 12_124
+bit 12_125
+bit 12_127
bit 12_129
bit 12_130
bit 12_132
bit 12_135
+bit 12_137
bit 12_138
bit 12_140
+bit 12_144
+bit 12_145
bit 12_146
bit 12_148
-bit 12_149
bit 12_154
-bit 12_158
-bit 12_159
+bit 12_160
bit 12_161
bit 12_162
-bit 12_164
+bit 12_166
bit 12_167
+bit 12_168
+bit 12_169
bit 12_170
+bit 12_175
bit 12_176
+bit 12_177
bit 12_178
-bit 12_179
bit 12_180
-bit 12_182
bit 12_183
-bit 12_185
bit 12_186
+bit 12_187
+bit 12_190
bit 12_191
-bit 12_192
bit 12_193
bit 12_194
-bit 12_198
bit 12_199
bit 12_201
bit 12_202
-bit 12_205
+bit 12_204
bit 12_207
bit 12_209
bit 12_210
bit 12_215
bit 12_217
bit 12_218
+bit 12_223
bit 12_225
bit 12_226
bit 12_232
bit 12_234
bit 12_239
-bit 12_240
+bit 12_241
bit 12_242
-bit 12_244
bit 12_248
bit 12_249
bit 12_250
-bit 12_252
bit 12_255
-bit 12_257
bit 12_258
-bit 12_260
bit 12_263
bit 12_264
+bit 12_265
bit 12_266
bit 12_268
bit 12_271
bit 12_274
bit 12_276
-bit 12_278
bit 12_280
bit 12_282
bit 12_284
bit 12_287
-bit 12_288
bit 12_290
-bit 12_291
bit 12_292
-bit 12_293
-bit 12_294
bit 12_295
bit 12_297
bit 12_298
-bit 12_300
bit 12_303
bit 12_306
+bit 12_307
bit 12_311
bit 12_313
bit 12_314
+bit 12_316
bit 12_319
bit 13_01
+bit 13_02
bit 13_07
bit 13_09
bit 13_10
+bit 13_11
+bit 13_14
bit 13_15
+bit 13_23
bit 13_25
-bit 13_30
-bit 13_38
+bit 13_26
+bit 13_31
+bit 13_34
+bit 13_36
+bit 13_37
bit 13_39
-bit 13_40
bit 13_41
bit 13_42
+bit 13_47
+bit 13_49
bit 13_50
-bit 13_63
-bit 13_65
+bit 13_51
+bit 13_55
+bit 13_56
+bit 13_58
bit 13_66
bit 13_71
bit 13_72
bit 13_73
bit 13_74
+bit 13_75
bit 13_76
-bit 13_79
+bit 13_81
bit 13_85
bit 13_87
bit 13_89
-bit 13_95
+bit 13_90
+bit 13_91
+bit 13_96
bit 13_97
bit 13_98
-bit 13_100
+bit 13_101
bit 13_103
bit 13_105
-bit 13_112
+bit 13_107
bit 13_113
-bit 13_117
bit 13_119
-bit 13_121
+bit 13_122
bit 13_127
bit 13_128
bit 13_129
bit 13_130
-bit 13_132
bit 13_135
bit 13_137
bit 13_138
+bit 13_143
bit 13_145
bit 13_146
-bit 13_148
+bit 13_151
bit 13_153
-bit 13_154
bit 13_155
-bit 13_157
-bit 13_158
bit 13_159
bit 13_161
bit 13_162
bit 13_164
+bit 13_165
+bit 13_166
bit 13_167
+bit 13_170
bit 13_174
bit 13_175
bit 13_177
-bit 13_178
+bit 13_180
+bit 13_181
bit 13_183
bit 13_185
bit 13_186
-bit 13_188
+bit 13_190
bit 13_191
+bit 13_192
bit 13_193
bit 13_194
+bit 13_196
bit 13_199
-bit 13_201
+bit 13_200
bit 13_202
+bit 13_204
bit 13_207
bit 13_208
bit 13_209
-bit 13_210
bit 13_215
+bit 13_216
bit 13_217
-bit 13_218
+bit 13_220
bit 13_223
+bit 13_224
bit 13_225
bit 13_226
bit 13_231
bit 13_232
+bit 13_233
bit 13_237
bit 13_239
bit 13_241
-bit 13_248
+bit 13_247
bit 13_249
+bit 13_250
bit 13_255
bit 13_257
bit 13_258
bit 13_263
bit 13_265
-bit 13_267
-bit 13_268
+bit 13_266
bit 13_270
bit 13_271
bit 13_273
-bit 13_274
-bit 13_275
bit 13_276
+bit 13_277
bit 13_279
+bit 13_280
bit 13_281
bit 13_282
bit 13_284
bit 13_287
-bit 13_288
bit 13_289
bit 13_290
+bit 13_292
+bit 13_294
bit 13_295
bit 13_297
+bit 13_298
bit 13_303
+bit 13_304
bit 13_306
bit 13_311
+bit 13_312
bit 13_313
bit 13_314
-bit 13_318
bit 13_319
bit 14_02
-bit 14_08
bit 14_10
bit 14_18
bit 14_24
-bit 14_26
bit 14_34
+bit 14_40
bit 14_42
bit 14_50
bit 14_58
+bit 14_60
bit 14_66
-bit 14_68
bit 14_72
bit 14_74
+bit 14_76
bit 14_82
-bit 14_84
+bit 14_88
bit 14_90
bit 14_98
bit 14_100
@@ -1007,38 +1061,37 @@
bit 14_130
bit 14_132
bit 14_138
-bit 14_146
-bit 14_152
+bit 14_148
bit 14_154
+bit 14_160
bit 14_162
+bit 14_166
bit 14_170
-bit 14_176
+bit 14_174
bit 14_178
bit 14_180
bit 14_186
-bit 14_192
bit 14_194
-bit 14_224
+bit 14_202
+bit 14_210
+bit 14_218
bit 14_226
-bit 14_228
bit 14_232
+bit 14_234
bit 14_242
bit 14_252
bit 14_258
bit 14_264
bit 14_266
bit 14_268
-bit 14_270
bit 14_274
-bit 14_276
+bit 14_280
bit 14_282
bit 14_284
bit 14_290
-bit 14_292
-bit 14_304
+bit 14_298
bit 14_306
bit 14_314
-bit 14_316
bit 15_01
bit 15_07
bit 15_09
@@ -1049,27 +1102,32 @@
bit 15_25
bit 15_27
bit 15_31
+bit 15_33
bit 15_39
bit 15_41
bit 15_43
-bit 15_47
bit 15_49
+bit 15_51
+bit 15_55
bit 15_57
bit 15_63
bit 15_65
bit 15_71
bit 15_73
-bit 15_79
bit 15_81
bit 15_87
-bit 15_89
+bit 15_95
+bit 15_97
bit 15_103
-bit 15_107
+bit 15_111
+bit 15_113
bit 15_119
bit 15_121
bit 15_129
bit 15_135
bit 15_137
+bit 15_143
+bit 15_145
bit 15_151
bit 15_153
bit 15_159
@@ -1079,22 +1137,18 @@
bit 15_177
bit 15_183
bit 15_185
-bit 15_187
bit 15_191
bit 15_193
-bit 15_197
bit 15_199
bit 15_201
bit 15_207
bit 15_209
bit 15_215
bit 15_217
+bit 15_219
bit 15_223
-bit 15_225
bit 15_231
bit 15_233
-bit 15_237
-bit 15_239
bit 15_249
bit 15_257
bit 15_263
@@ -1102,16 +1156,17 @@
bit 15_271
bit 15_273
bit 15_281
+bit 15_283
bit 15_287
bit 15_295
bit 15_297
bit 15_303
+bit 15_305
bit 15_311
-bit 15_313
bit 15_319
bit 16_00
bit 16_07
-bit 16_95
+bit 16_24
bit 16_96
bit 16_103
bit 16_135
@@ -1119,6 +1174,7 @@
bit 16_151
bit 16_156
bit 16_157
+bit 16_159
bit 16_160
bit 16_162
bit 16_163
@@ -1126,9 +1182,8 @@
bit 16_180
bit 16_181
bit 16_183
+bit 16_184
bit 16_199
-bit 16_207
-bit 16_223
bit 16_228
bit 16_229
bit 16_231
@@ -1137,7 +1192,6 @@
bit 16_240
bit 16_247
bit 16_250
-bit 16_251
bit 16_256
bit 16_257
bit 16_258
@@ -1152,14 +1206,11 @@
bit 16_279
bit 16_280
bit 16_288
-bit 16_295
bit 17_00
bit 17_07
-bit 17_24
bit 17_96
bit 17_103
bit 17_104
-bit 17_135
bit 17_144
bit 17_151
bit 17_156
@@ -1171,12 +1222,13 @@
bit 17_180
bit 17_181
bit 17_183
+bit 17_199
bit 17_228
bit 17_229
+bit 17_231
bit 17_234
bit 17_235
bit 17_240
-bit 17_247
bit 17_248
bit 17_250
bit 17_251
@@ -1189,26 +1241,22 @@
bit 17_264
bit 17_266
bit 17_267
-bit 17_271
-bit 17_272
bit 17_279
-bit 17_280
bit 17_288
bit 17_296
-bit 17_303
-bit 17_312
bit 18_01
bit 18_06
-bit 18_17
-bit 18_25
bit 18_97
bit 18_102
bit 18_105
-bit 18_145
+bit 18_134
bit 18_150
bit 18_156
bit 18_157
+bit 18_161
bit 18_162
+bit 18_163
+bit 18_166
bit 18_169
bit 18_177
bit 18_180
@@ -1216,7 +1264,7 @@
bit 18_182
bit 18_193
bit 18_198
-bit 18_209
+bit 18_206
bit 18_222
bit 18_228
bit 18_229
@@ -1227,8 +1275,6 @@
bit 18_246
bit 18_249
bit 18_250
-bit 18_251
-bit 18_254
bit 18_256
bit 18_257
bit 18_258
@@ -1243,7 +1289,6 @@
bit 18_278
bit 18_281
bit 18_289
-bit 18_313
bit 19_01
bit 19_06
bit 19_09
@@ -1251,12 +1296,9 @@
bit 19_94
bit 19_97
bit 19_102
-bit 19_105
-bit 19_113
bit 19_134
bit 19_145
bit 19_150
-bit 19_153
bit 19_156
bit 19_157
bit 19_158
@@ -1265,10 +1307,14 @@
bit 19_163
bit 19_169
bit 19_177
+bit 19_180
bit 19_181
bit 19_182
+bit 19_185
bit 19_206
+bit 19_209
bit 19_222
+bit 19_228
bit 19_229
bit 19_230
bit 19_234
@@ -1287,42 +1333,42 @@
bit 19_265
bit 19_266
bit 19_267
+bit 19_270
bit 19_273
bit 19_278
bit 19_281
bit 19_289
-bit 19_297
bit 20_00
-bit 20_07
bit 20_96
bit 20_103
-bit 20_144
bit 20_156
bit 20_160
bit 20_162
bit 20_163
-bit 20_183
+bit 20_176
+bit 20_180
bit 20_228
bit 20_234
+bit 20_240
bit 20_256
bit 20_257
+bit 20_259
bit 20_262
-bit 20_263
bit 20_266
bit 20_267
bit 20_272
-bit 20_288
bit 20_293
bit 21_07
bit 21_96
bit 21_103
bit 21_157
bit 21_160
-bit 21_162
bit 21_163
+bit 21_181
bit 21_183
bit 21_199
bit 21_229
+bit 21_231
bit 21_235
bit 21_242
bit 21_244
@@ -1330,22 +1376,17 @@
bit 21_256
bit 21_257
bit 21_258
-bit 21_262
-bit 21_264
+bit 21_259
bit 21_266
bit 21_267
-bit 21_279
bit 21_292
bit 22_00
bit 22_07
bit 22_08
bit 22_16
-bit 22_95
bit 22_96
bit 22_103
bit 22_104
-bit 22_112
-bit 22_135
bit 22_144
bit 22_151
bit 22_156
@@ -1358,8 +1399,11 @@
bit 22_180
bit 22_181
bit 22_183
+bit 22_184
bit 22_192
+bit 22_199
bit 22_207
+bit 22_208
bit 22_228
bit 22_229
bit 22_231
@@ -1367,7 +1411,6 @@
bit 22_235
bit 22_240
bit 22_247
-bit 22_248
bit 22_250
bit 22_251
bit 22_256
@@ -1379,29 +1422,32 @@
bit 22_264
bit 22_266
bit 22_267
+bit 22_271
bit 22_272
bit 22_279
bit 22_280
bit 22_288
bit 23_00
bit 23_07
-bit 23_08
-bit 23_24
bit 23_96
bit 23_103
-bit 23_104
+bit 23_135
bit 23_144
bit 23_151
bit 23_156
bit 23_157
+bit 23_160
bit 23_162
bit 23_163
+bit 23_167
bit 23_168
bit 23_176
bit 23_180
bit 23_181
bit 23_183
+bit 23_184
bit 23_199
+bit 23_207
bit 23_223
bit 23_228
bit 23_229
@@ -1419,6 +1465,7 @@
bit 23_259
bit 23_262
bit 23_263
+bit 23_264
bit 23_266
bit 23_267
bit 23_271
@@ -1426,9 +1473,6 @@
bit 23_279
bit 23_280
bit 23_288
-bit 23_295
-bit 23_296
-bit 23_303
bit 24_00
bit 24_07
bit 24_08
@@ -1438,7 +1482,6 @@
bit 24_96
bit 24_103
bit 24_104
-bit 24_112
bit 24_135
bit 24_144
bit 24_151
@@ -1448,11 +1491,13 @@
bit 24_160
bit 24_162
bit 24_163
+bit 24_167
bit 24_168
bit 24_176
bit 24_180
bit 24_181
bit 24_183
+bit 24_184
bit 24_192
bit 24_199
bit 24_207
@@ -1483,36 +1528,34 @@
bit 24_280
bit 24_288
bit 24_293
-bit 24_295
-bit 24_296
-bit 24_303
bit 25_00
bit 25_07
bit 25_08
bit 25_16
-bit 25_24
bit 25_95
bit 25_96
bit 25_103
bit 25_104
-bit 25_112
bit 25_135
bit 25_144
bit 25_151
-bit 25_152
bit 25_156
bit 25_157
+bit 25_159
bit 25_160
bit 25_162
bit 25_163
+bit 25_167
bit 25_168
bit 25_176
bit 25_180
bit 25_181
bit 25_183
+bit 25_184
bit 25_192
bit 25_199
bit 25_207
+bit 25_208
bit 25_223
bit 25_228
bit 25_229
@@ -1526,7 +1569,6 @@
bit 25_248
bit 25_250
bit 25_251
-bit 25_255
bit 25_256
bit 25_257
bit 25_258
@@ -1542,10 +1584,7 @@
bit 25_280
bit 25_288
bit 25_292
-bit 25_295
bit 25_296
-bit 25_303
-bit 25_312
bit 26_01
bit 26_02
bit 26_03
diff --git a/kintex7/segbits_int_l.origin_info.db b/kintex7/segbits_int_l.origin_info.db
index d95920e..ee662b7 100644
--- a/kintex7/segbits_int_l.origin_info.db
+++ b/kintex7/segbits_int_l.origin_info.db
@@ -301,7 +301,7 @@
INT_L.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
INT_L.FAN_ALT0.LOGIC_OUTS_L12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
-INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
+INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
INT_L.FAN_ALT0.SR1END_N3_3 origin:050-pip-seed !23_00 19_01 22_00 24_00 25_00
INT_L.FAN_ALT0.SS2END_N0_3 origin:050-pip-seed !22_00 !23_00 !24_00 17_00 25_00
INT_L.FAN_ALT0.SW2END_N0_3 origin:050-pip-seed !22_00 !23_00 !25_00 17_00 24_00
@@ -393,10 +393,10 @@
INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
-INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
+INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
-INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
+INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:056-pip-rem !22_08 !23_08 !25_08 21_08 24_08
INT_L.FAN_ALT4.SR1BEG_S0 origin:050-pip-seed !23_08 19_09 22_08 24_08 25_08
INT_L.FAN_ALT4.EE2END0 origin:050-pip-seed !22_08 !23_08 !24_08 16_08 25_08
INT_L.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08
@@ -1937,7 +1937,7 @@
INT_L.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
INT_L.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
INT_L.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_L.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
+INT_L.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
INT_L.EL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_20 14_21
INT_L.EL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_21 14_21
INT_L.EL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_21 13_21
@@ -2491,7 +2491,7 @@
INT_L.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
INT_L.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
INT_L.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
-INT_L.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
+INT_L.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
INT_L.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
INT_L.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
INT_L.NR1BEG0.LOGIC_OUTS_L0 origin:050-pip-seed 11_07 14_07
@@ -3302,7 +3302,7 @@
INT_L.SW6BEG1.LOGIC_OUTS_L23 origin:050-pip-seed 04_30 06_28
INT_L.SW6BEG1.LV_L9 origin:056-pip-rem 04_30 05_28
INT_L.SW6BEG1.EE2END1 origin:050-pip-seed 03_28 04_29
-INT_L.SW6BEG1.EE4END1 origin:050-pip-seed 04_29 05_28
+INT_L.SW6BEG1.EE4END1 origin:056-pip-rem 04_29 05_28
INT_L.SW6BEG1.LH6 origin:056-pip-rem 05_28 07_29
INT_L.SW6BEG1.NW2END2 origin:050-pip-seed 02_29 05_31
INT_L.SW6BEG1.NW6END2 origin:050-pip-seed 05_31 06_28
@@ -3323,7 +3323,7 @@
INT_L.SW6BEG2.LVB_L0 origin:056-pip-rem 04_46 05_44
INT_L.SW6BEG2.LVB_L12 origin:056-pip-rem 05_44 07_45
INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
+INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_L.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
INT_L.SW6BEG2.NW6END3 origin:050-pip-seed 05_47 06_44
INT_L.SW6BEG2.SE2END2 origin:050-pip-seed 02_45 04_45
@@ -3345,7 +3345,7 @@
INT_L.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60
INT_L.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63
INT_L.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
-INT_L.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
+INT_L.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
INT_L.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
INT_L.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61
INT_L.SW6BEG3.SE6END3 origin:050-pip-seed 04_61 06_60
@@ -3623,7 +3623,7 @@
INT_L.WW4BEG3.LV_L18 origin:056-pip-rem 05_48 07_49
INT_L.WW4BEG3.LH0 origin:056-pip-rem 04_50 05_48
INT_L.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51
-INT_L.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51
+INT_L.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51
INT_L.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51
INT_L.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48
INT_L.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49
diff --git a/kintex7/segbits_int_r.origin_info.db b/kintex7/segbits_int_r.origin_info.db
index 08afa8e..9f3d3c2 100644
--- a/kintex7/segbits_int_r.origin_info.db
+++ b/kintex7/segbits_int_r.origin_info.db
@@ -237,7 +237,7 @@
INT_R.FAN_ALT0.FAN_BOUNCE6 origin:050-pip-seed !23_00 20_00 22_00 24_00 25_00
INT_R.FAN_ALT0.LOGIC_OUTS0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
INT_R.FAN_ALT0.LOGIC_OUTS12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
-INT_R.FAN_ALT0.LOGIC_OUTS22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
+INT_R.FAN_ALT0.LOGIC_OUTS22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
INT_R.FAN_ALT0.SR1END_N3_3 origin:050-pip-seed !23_00 19_01 22_00 24_00 25_00
INT_R.FAN_ALT0.SS2END_N0_3 origin:050-pip-seed !22_00 !23_00 !24_00 17_00 25_00
INT_R.FAN_ALT0.SW2END_N0_3 origin:050-pip-seed !22_00 !23_00 !25_00 17_00 24_00
@@ -329,7 +329,7 @@
INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
-INT_R.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
+INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
@@ -685,7 +685,7 @@
INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
-INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
+INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
INT_R.EE4BEG2.LOGIC_OUTS2 origin:050-pip-seed 02_41 04_42
INT_R.EE4BEG2.LOGIC_OUTS6 origin:050-pip-seed 02_41 07_41
INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
@@ -3321,7 +3321,7 @@
INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
diff --git a/kintex7/xc7k70tfbg484-1/package_pins.csv b/kintex7/xc7k70tfbg484-1/package_pins.csv
new file mode 100644
index 0000000..73f4284
--- /dev/null
+++ b/kintex7/xc7k70tfbg484-1/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A3,115,OPAD_X0Y6,GTX_CHANNEL_3_X99Y150,MGTXTXN3_115
+A4,115,OPAD_X0Y7,GTX_CHANNEL_3_X99Y150,MGTXTXP3_115
+A8,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A9,16,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_16
+A10,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+A11,16,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_16
+A13,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_AD9P_15
+A14,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_AD9N_15
+A15,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD11N_15
+A16,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD3N_15
+A18,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD4N_15
+A19,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
+A20,15,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A17_15
+A21,15,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A16_15
+AA1,34,IOB_X1Y56,RIOB18_X43Y55,IO_L22P_T3_34
+AA3,34,IOB_X1Y54,RIOB18_X43Y53,IO_L23P_T3_34
+AA4,34,IOB_X1Y52,RIOB18_X43Y51,IO_L24P_T3_34
+AA5,33,IOB_X1Y48,RIOB18_X43Y47,IO_L1P_T0_33
+AA6,33,IOB_X1Y44,RIOB18_X43Y43,IO_L3P_T0_DQS_33
+AA8,33,IOB_X1Y39,RIOB18_X43Y39,IO_L5N_T0_33
+AA9,33,IOB_X1Y40,RIOB18_X43Y39,IO_L5P_T0_33
+AA10,33,IOB_X1Y42,RIOB18_X43Y41,IO_L4P_T0_33
+AA11,33,IOB_X1Y10,RIOB18_X43Y9,IO_L20P_T3_33
+AA13,33,IOB_X1Y7,RIOB18_X43Y7,IO_L21N_T3_DQS_33
+AA14,13,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_13
+AA15,13,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_13
+AA16,13,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_13
+AA18,13,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_13
+AA19,13,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_13
+AA20,13,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_13
+AA21,13,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_13
+AB1,34,IOB_X1Y55,RIOB18_X43Y55,IO_L22N_T3_34
+AB2,34,IOB_X1Y53,RIOB18_X43Y53,IO_L23N_T3_34
+AB3,34,IOB_X1Y51,RIOB18_X43Y51,IO_L24N_T3_34
+AB5,33,IOB_X1Y47,RIOB18_X43Y47,IO_L1N_T0_33
+AB6,33,IOB_X1Y43,RIOB18_X43Y43,IO_L3N_T0_DQS_33
+AB7,33,IOB_X1Y45,RIOB18_X43Y45,IO_L2N_T0_33
+AB8,33,IOB_X1Y46,RIOB18_X43Y45,IO_L2P_T0_33
+AB10,33,IOB_X1Y41,RIOB18_X43Y41,IO_L4N_T0_33
+AB11,33,IOB_X1Y9,RIOB18_X43Y9,IO_L20N_T3_33
+AB12,33,IOB_X1Y5,RIOB18_X43Y5,IO_L22N_T3_33
+AB13,33,IOB_X1Y6,RIOB18_X43Y5,IO_L22P_T3_33
+AB15,13,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_13
+AB16,13,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_13
+AB17,13,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_13
+AB18,13,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_13
+AB20,13,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_13
+AB21,13,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_13
+AB22,13,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_13
+B1,115,OPAD_X0Y4,GTX_CHANNEL_2_X99Y139,MGTXTXN2_115
+B2,115,OPAD_X0Y5,GTX_CHANNEL_2_X99Y139,MGTXTXP2_115
+B5,115,IPAD_X0Y24,GTX_CHANNEL_3_X99Y150,MGTXRXN3_115
+B6,115,IPAD_X0Y25,GTX_CHANNEL_3_X99Y150,MGTXRXP3_115
+B8,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
+B10,16,IOB_X0Y159,LIOB33_X0Y159,IO_L20N_T3_16
+B11,16,IOB_X0Y160,LIOB33_X0Y159,IO_L20P_T3_16
+B12,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+B13,15,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_AD2N_15
+B15,15,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_AD11P_15
+B16,15,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_AD3P_15
+B17,15,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_AD4P_15
+B18,15,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A20_15
+B20,15,IOB_X0Y102,LIOB33_X0Y101,IO_L24P_T3_RS1_15
+B21,15,IOB_X0Y101,LIOB33_X0Y101,IO_L24N_T3_RS0_15
+B22,15,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_A18_15
+C3,115,IPAD_X0Y18,GTX_CHANNEL_2_X99Y139,MGTXRXN2_115
+C4,115,IPAD_X0Y19,GTX_CHANNEL_2_X99Y139,MGTXRXP2_115
+C8,16,IOB_X0Y156,LIOB33_X0Y155,IO_L22P_T3_16
+C9,16,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_VREF_16
+C10,16,IOB_X0Y185,LIOB33_X0Y185,IO_L7N_T1_16
+C12,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+C13,15,IOB_X0Y140,LIOB33_X0Y139,IO_L5P_T0_AD2P_15
+C14,15,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_AD10P_15
+C15,15,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_AD10N_15
+C17,15,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_AD5P_15
+C18,15,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_AD5N_15
+C19,15,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_A22_15
+C20,15,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_A21_VREF_15
+C22,15,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_15
+D1,115,OPAD_X0Y2,GTX_CHANNEL_1_X99Y121,MGTXTXN1_115
+D2,115,OPAD_X0Y3,GTX_CHANNEL_1_X99Y121,MGTXTXP1_115
+D5,115,IPAD_X0Y9,GTX_COMMON_X99Y127,MGTREFCLK0N_115
+D6,115,IPAD_X0Y8,GTX_COMMON_X99Y127,MGTREFCLK0P_115
+D9,16,IOB_X0Y162,LIOB33_X0Y161,IO_L19P_T3_16
+D10,16,IOB_X0Y186,LIOB33_X0Y185,IO_L7P_T1_16
+D11,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
+D12,15,IOB_X0Y149,LIOB33_SING_X0Y149,IO_0_15
+D14,15,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_15
+D15,15,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_AD12P_15
+D16,15,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_AD12N_15
+D17,15,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_15
+D19,15,IOB_X0Y114,LIOB33_X0Y113,IO_L18P_T2_A24_15
+D20,15,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_A23_15
+D21,15,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_FOE_B_15
+D22,15,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_FWE_B_15
+E3,115,IPAD_X0Y6,GTX_CHANNEL_1_X99Y121,MGTXRXN1_115
+E4,115,IPAD_X0Y7,GTX_CHANNEL_1_X99Y121,MGTXRXP1_115
+E8,16,IOB_X0Y152,LIOB33_X0Y151,IO_24_T3_16
+E9,16,IOB_X0Y169,LIOB33_X0Y169,IO_L15N_T2_DQS_16
+E11,16,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_16
+E12,16,IOB_X0Y179,LIOB33_X0Y179,IO_L10N_T1_16
+E13,16,IOB_X0Y180,LIOB33_X0Y179,IO_L10P_T1_16
+E14,15,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_15
+E16,15,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_15
+E17,15,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_15
+E18,15,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_15
+E19,15,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A25_15
+E21,14,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_D09_14
+E22,14,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_D10_14
+F1,115,OPAD_X0Y0,GTX_CHANNEL_0_X99Y110,MGTXTXN0_115
+F2,115,OPAD_X0Y1,GTX_CHANNEL_0_X99Y110,MGTXTXP0_115
+F5,115,IPAD_X0Y11,GTX_COMMON_X99Y127,MGTREFCLK1N_115
+F6,115,IPAD_X0Y10,GTX_COMMON_X99Y127,MGTREFCLK1P_115
+F8,16,IOB_X0Y165,LIOB33_X0Y165,IO_L17N_T2_16
+F9,16,IOB_X0Y170,LIOB33_X0Y169,IO_L15P_T2_DQS_16
+F10,16,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_16
+F11,16,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_16
+F13,16,IOB_X0Y183,LIOB33_X0Y183,IO_L8N_T1_16
+F14,16,IOB_X0Y187,LIOB33_X0Y187,IO_6_T0_VREF_16
+F15,15,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_AD1P_15
+F16,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+F18,15,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A26_15
+F19,14,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_D03_14
+F20,14,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_D05_14
+F21,14,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_D13_14
+G3,115,IPAD_X0Y0,GTX_CHANNEL_0_X99Y110,MGTXRXN0_115
+G4,115,IPAD_X0Y1,GTX_CHANNEL_0_X99Y110,MGTXRXP0_115
+G8,16,IOB_X0Y166,LIOB33_X0Y165,IO_L17P_T2_16
+G10,16,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_16
+G11,16,IOB_X0Y174,LIOB33_X0Y173,IO_L13P_T2_MRCC_16
+G12,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16
+G13,16,IOB_X0Y184,LIOB33_X0Y183,IO_L8P_T1_16
+G15,15,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_AD0P_15
+G16,15,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_AD0N_15
+G17,15,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_ADV_B_15
+G18,14,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_D02_14
+G20,14,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_D04_14
+G21,14,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_14
+G22,14,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_D12_14
+H8,16,IOB_X0Y167,LIOB33_X0Y167,IO_L16N_T2_16
+H9,16,IOB_X0Y168,LIOB33_X0Y167,IO_L16P_T2_16
+H10,16,IOB_X0Y164,LIOB33_X0Y163,IO_18_T2_16
+H12,16,IOB_X0Y172,LIOB33_X0Y171,IO_L14P_T2_SRCC_16
+H13,16,IOB_X0Y181,LIOB33_X0Y181,IO_L9N_T1_DQS_16
+H14,16,IOB_X0Y182,LIOB33_X0Y181,IO_L9P_T1_DQS_16
+H15,15,IOB_X0Y100,LIOB33_SING_X0Y100,IO_25_15
+H17,15,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_15
+H18,14,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_D00_MOSI_14
+H19,14,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_D01_DIN_14
+H20,14,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_14
+H22,14,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_D11_14
+J16,15,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_A28_15
+J17,15,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A27_15
+J19,14,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_EMCCLK_14
+J20,14,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_14
+J21,14,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_D14_14
+J22,14,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_D15_14
+K1,34,IOB_X1Y96,RIOB18_X43Y95,IO_L2P_T0_34
+K2,34,IOB_X1Y91,RIOB18_X43Y91,IO_L4N_T0_34
+K3,34,IOB_X1Y92,RIOB18_X43Y91,IO_L4P_T0_34
+K4,34,IOB_X1Y99,RIOB18_SING_X43Y99,IO_0_VRN_34
+K16,14,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_14
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diff --git a/kintex7/xc7k70tfbg484-1/part.json b/kintex7/xc7k70tfbg484-1/part.json
new file mode 100644
index 0000000..4dc0b1c
--- /dev/null
+++ b/kintex7/xc7k70tfbg484-1/part.json
@@ -0,0 +1,602 @@
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+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56914067,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182"
+ }
+}
diff --git a/kintex7/xc7k70tfbg484-1/part.yaml b/kintex7/xc7k70tfbg484-1/part.yaml
new file mode 100644
index 0000000..0293099
--- /dev/null
+++ b/kintex7/xc7k70tfbg484-1/part.yaml
@@ -0,0 +1,387 @@
+!<xilinx/xc7series/part>
+idcode: 0x3647093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/kintex7/xc7k70tfbg484-2/package_pins.csv b/kintex7/xc7k70tfbg484-2/package_pins.csv
new file mode 100644
index 0000000..73f4284
--- /dev/null
+++ b/kintex7/xc7k70tfbg484-2/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A3,115,OPAD_X0Y6,GTX_CHANNEL_3_X99Y150,MGTXTXN3_115
+A4,115,OPAD_X0Y7,GTX_CHANNEL_3_X99Y150,MGTXTXP3_115
+A8,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A9,16,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_16
+A10,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+A11,16,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_16
+A13,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_AD9P_15
+A14,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_AD9N_15
+A15,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD11N_15
+A16,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD3N_15
+A18,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD4N_15
+A19,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
+A20,15,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A17_15
+A21,15,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A16_15
+AA1,34,IOB_X1Y56,RIOB18_X43Y55,IO_L22P_T3_34
+AA3,34,IOB_X1Y54,RIOB18_X43Y53,IO_L23P_T3_34
+AA4,34,IOB_X1Y52,RIOB18_X43Y51,IO_L24P_T3_34
+AA5,33,IOB_X1Y48,RIOB18_X43Y47,IO_L1P_T0_33
+AA6,33,IOB_X1Y44,RIOB18_X43Y43,IO_L3P_T0_DQS_33
+AA8,33,IOB_X1Y39,RIOB18_X43Y39,IO_L5N_T0_33
+AA9,33,IOB_X1Y40,RIOB18_X43Y39,IO_L5P_T0_33
+AA10,33,IOB_X1Y42,RIOB18_X43Y41,IO_L4P_T0_33
+AA11,33,IOB_X1Y10,RIOB18_X43Y9,IO_L20P_T3_33
+AA13,33,IOB_X1Y7,RIOB18_X43Y7,IO_L21N_T3_DQS_33
+AA14,13,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_13
+AA15,13,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_13
+AA16,13,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_13
+AA18,13,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_13
+AA19,13,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_13
+AA20,13,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_13
+AA21,13,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_13
+AB1,34,IOB_X1Y55,RIOB18_X43Y55,IO_L22N_T3_34
+AB2,34,IOB_X1Y53,RIOB18_X43Y53,IO_L23N_T3_34
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+Y19,13,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_13
+Y21,13,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_13
+Y22,13,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_13
diff --git a/kintex7/xc7k70tfbg484-2/part.json b/kintex7/xc7k70tfbg484-2/part.json
new file mode 100644
index 0000000..4dc0b1c
--- /dev/null
+++ b/kintex7/xc7k70tfbg484-2/part.json
@@ -0,0 +1,602 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
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+ },
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+ },
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+ },
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+ }
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+ "CLB_IO_CLK": {
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+ }
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+ },
+ "1": {
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+ },
+ "2": {
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+ }
+ }
+ },
+ "CLB_IO_CLK": {
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+ },
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+ },
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+ "frame_count": 32
+ }
+ }
+ }
+ }
+ },
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+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
+ "4": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "28": {
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+ },
+ "29": {
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+ },
+ "30": {
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+ },
+ "31": {
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+ },
+ "32": {
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+ },
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+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56914067,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182"
+ }
+}
diff --git a/kintex7/xc7k70tfbg484-2/part.yaml b/kintex7/xc7k70tfbg484-2/part.yaml
new file mode 100644
index 0000000..0293099
--- /dev/null
+++ b/kintex7/xc7k70tfbg484-2/part.yaml
@@ -0,0 +1,387 @@
+!<xilinx/xc7series/part>
+idcode: 0x3647093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
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+ 29: !<xilinx/xc7series/configuration_column>
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+ 32: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
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+ 4: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
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+ 10: !<xilinx/xc7series/configuration_column>
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+ 11: !<xilinx/xc7series/configuration_column>
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+ 12: !<xilinx/xc7series/configuration_column>
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+ 13: !<xilinx/xc7series/configuration_column>
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+ 14: !<xilinx/xc7series/configuration_column>
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+ 15: !<xilinx/xc7series/configuration_column>
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+ 16: !<xilinx/xc7series/configuration_column>
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+ 17: !<xilinx/xc7series/configuration_column>
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+ 18: !<xilinx/xc7series/configuration_column>
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+ 19: !<xilinx/xc7series/configuration_column>
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+ 20: !<xilinx/xc7series/configuration_column>
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+ 21: !<xilinx/xc7series/configuration_column>
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+ 22: !<xilinx/xc7series/configuration_column>
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+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
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+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
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+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
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+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/kintex7/xc7k70tfbg484-2L/package_pins.csv b/kintex7/xc7k70tfbg484-2L/package_pins.csv
new file mode 100644
index 0000000..73f4284
--- /dev/null
+++ b/kintex7/xc7k70tfbg484-2L/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A3,115,OPAD_X0Y6,GTX_CHANNEL_3_X99Y150,MGTXTXN3_115
+A4,115,OPAD_X0Y7,GTX_CHANNEL_3_X99Y150,MGTXTXP3_115
+A8,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A9,16,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_16
+A10,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+A11,16,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_16
+A13,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_AD9P_15
+A14,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_AD9N_15
+A15,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD11N_15
+A16,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD3N_15
+A18,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD4N_15
+A19,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
+A20,15,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A17_15
+A21,15,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A16_15
+AA1,34,IOB_X1Y56,RIOB18_X43Y55,IO_L22P_T3_34
+AA3,34,IOB_X1Y54,RIOB18_X43Y53,IO_L23P_T3_34
+AA4,34,IOB_X1Y52,RIOB18_X43Y51,IO_L24P_T3_34
+AA5,33,IOB_X1Y48,RIOB18_X43Y47,IO_L1P_T0_33
+AA6,33,IOB_X1Y44,RIOB18_X43Y43,IO_L3P_T0_DQS_33
+AA8,33,IOB_X1Y39,RIOB18_X43Y39,IO_L5N_T0_33
+AA9,33,IOB_X1Y40,RIOB18_X43Y39,IO_L5P_T0_33
+AA10,33,IOB_X1Y42,RIOB18_X43Y41,IO_L4P_T0_33
+AA11,33,IOB_X1Y10,RIOB18_X43Y9,IO_L20P_T3_33
+AA13,33,IOB_X1Y7,RIOB18_X43Y7,IO_L21N_T3_DQS_33
+AA14,13,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_13
+AA15,13,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_13
+AA16,13,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_13
+AA18,13,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_13
+AA19,13,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_13
+AA20,13,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_13
+AA21,13,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_13
+AB1,34,IOB_X1Y55,RIOB18_X43Y55,IO_L22N_T3_34
+AB2,34,IOB_X1Y53,RIOB18_X43Y53,IO_L23N_T3_34
+AB3,34,IOB_X1Y51,RIOB18_X43Y51,IO_L24N_T3_34
+AB5,33,IOB_X1Y47,RIOB18_X43Y47,IO_L1N_T0_33
+AB6,33,IOB_X1Y43,RIOB18_X43Y43,IO_L3N_T0_DQS_33
+AB7,33,IOB_X1Y45,RIOB18_X43Y45,IO_L2N_T0_33
+AB8,33,IOB_X1Y46,RIOB18_X43Y45,IO_L2P_T0_33
+AB10,33,IOB_X1Y41,RIOB18_X43Y41,IO_L4N_T0_33
+AB11,33,IOB_X1Y9,RIOB18_X43Y9,IO_L20N_T3_33
+AB12,33,IOB_X1Y5,RIOB18_X43Y5,IO_L22N_T3_33
+AB13,33,IOB_X1Y6,RIOB18_X43Y5,IO_L22P_T3_33
+AB15,13,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_13
+AB16,13,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_13
+AB17,13,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_13
+AB18,13,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_13
+AB20,13,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_13
+AB21,13,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_13
+AB22,13,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_13
+B1,115,OPAD_X0Y4,GTX_CHANNEL_2_X99Y139,MGTXTXN2_115
+B2,115,OPAD_X0Y5,GTX_CHANNEL_2_X99Y139,MGTXTXP2_115
+B5,115,IPAD_X0Y24,GTX_CHANNEL_3_X99Y150,MGTXRXN3_115
+B6,115,IPAD_X0Y25,GTX_CHANNEL_3_X99Y150,MGTXRXP3_115
+B8,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
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+B12,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+B13,15,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_AD2N_15
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+B17,15,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_AD4P_15
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+D1,115,OPAD_X0Y2,GTX_CHANNEL_1_X99Y121,MGTXTXN1_115
+D2,115,OPAD_X0Y3,GTX_CHANNEL_1_X99Y121,MGTXTXP1_115
+D5,115,IPAD_X0Y9,GTX_COMMON_X99Y127,MGTREFCLK0N_115
+D6,115,IPAD_X0Y8,GTX_COMMON_X99Y127,MGTREFCLK0P_115
+D9,16,IOB_X0Y162,LIOB33_X0Y161,IO_L19P_T3_16
+D10,16,IOB_X0Y186,LIOB33_X0Y185,IO_L7P_T1_16
+D11,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
+D12,15,IOB_X0Y149,LIOB33_SING_X0Y149,IO_0_15
+D14,15,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_15
+D15,15,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_AD12P_15
+D16,15,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_AD12N_15
+D17,15,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_15
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+D20,15,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_A23_15
+D21,15,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_FOE_B_15
+D22,15,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_FWE_B_15
+E3,115,IPAD_X0Y6,GTX_CHANNEL_1_X99Y121,MGTXRXN1_115
+E4,115,IPAD_X0Y7,GTX_CHANNEL_1_X99Y121,MGTXRXP1_115
+E8,16,IOB_X0Y152,LIOB33_X0Y151,IO_24_T3_16
+E9,16,IOB_X0Y169,LIOB33_X0Y169,IO_L15N_T2_DQS_16
+E11,16,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_16
+E12,16,IOB_X0Y179,LIOB33_X0Y179,IO_L10N_T1_16
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+E14,15,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_15
+E16,15,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_15
+E17,15,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_15
+E18,15,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_15
+E19,15,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A25_15
+E21,14,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_D09_14
+E22,14,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_D10_14
+F1,115,OPAD_X0Y0,GTX_CHANNEL_0_X99Y110,MGTXTXN0_115
+F2,115,OPAD_X0Y1,GTX_CHANNEL_0_X99Y110,MGTXTXP0_115
+F5,115,IPAD_X0Y11,GTX_COMMON_X99Y127,MGTREFCLK1N_115
+F6,115,IPAD_X0Y10,GTX_COMMON_X99Y127,MGTREFCLK1P_115
+F8,16,IOB_X0Y165,LIOB33_X0Y165,IO_L17N_T2_16
+F9,16,IOB_X0Y170,LIOB33_X0Y169,IO_L15P_T2_DQS_16
+F10,16,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_16
+F11,16,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_16
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diff --git a/kintex7/xc7k70tfbg484-2L/part.json b/kintex7/xc7k70tfbg484-2L/part.json
new file mode 100644
index 0000000..4dc0b1c
--- /dev/null
+++ b/kintex7/xc7k70tfbg484-2L/part.json
@@ -0,0 +1,602 @@
+{
+ "global_clock_regions": {
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+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56914067,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182"
+ }
+}
diff --git a/kintex7/xc7k70tfbg484-2L/part.yaml b/kintex7/xc7k70tfbg484-2L/part.yaml
new file mode 100644
index 0000000..0293099
--- /dev/null
+++ b/kintex7/xc7k70tfbg484-2L/part.yaml
@@ -0,0 +1,387 @@
+!<xilinx/xc7series/part>
+idcode: 0x3647093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/kintex7/xc7k70tfbg484-3/package_pins.csv b/kintex7/xc7k70tfbg484-3/package_pins.csv
new file mode 100644
index 0000000..73f4284
--- /dev/null
+++ b/kintex7/xc7k70tfbg484-3/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A3,115,OPAD_X0Y6,GTX_CHANNEL_3_X99Y150,MGTXTXN3_115
+A4,115,OPAD_X0Y7,GTX_CHANNEL_3_X99Y150,MGTXTXP3_115
+A8,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A9,16,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_16
+A10,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+A11,16,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_16
+A13,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_AD9P_15
+A14,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_AD9N_15
+A15,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD11N_15
+A16,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD3N_15
+A18,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD4N_15
+A19,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
+A20,15,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A17_15
+A21,15,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A16_15
+AA1,34,IOB_X1Y56,RIOB18_X43Y55,IO_L22P_T3_34
+AA3,34,IOB_X1Y54,RIOB18_X43Y53,IO_L23P_T3_34
+AA4,34,IOB_X1Y52,RIOB18_X43Y51,IO_L24P_T3_34
+AA5,33,IOB_X1Y48,RIOB18_X43Y47,IO_L1P_T0_33
+AA6,33,IOB_X1Y44,RIOB18_X43Y43,IO_L3P_T0_DQS_33
+AA8,33,IOB_X1Y39,RIOB18_X43Y39,IO_L5N_T0_33
+AA9,33,IOB_X1Y40,RIOB18_X43Y39,IO_L5P_T0_33
+AA10,33,IOB_X1Y42,RIOB18_X43Y41,IO_L4P_T0_33
+AA11,33,IOB_X1Y10,RIOB18_X43Y9,IO_L20P_T3_33
+AA13,33,IOB_X1Y7,RIOB18_X43Y7,IO_L21N_T3_DQS_33
+AA14,13,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_13
+AA15,13,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_13
+AA16,13,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_13
+AA18,13,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_13
+AA19,13,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_13
+AA20,13,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_13
+AA21,13,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_13
+AB1,34,IOB_X1Y55,RIOB18_X43Y55,IO_L22N_T3_34
+AB2,34,IOB_X1Y53,RIOB18_X43Y53,IO_L23N_T3_34
+AB3,34,IOB_X1Y51,RIOB18_X43Y51,IO_L24N_T3_34
+AB5,33,IOB_X1Y47,RIOB18_X43Y47,IO_L1N_T0_33
+AB6,33,IOB_X1Y43,RIOB18_X43Y43,IO_L3N_T0_DQS_33
+AB7,33,IOB_X1Y45,RIOB18_X43Y45,IO_L2N_T0_33
+AB8,33,IOB_X1Y46,RIOB18_X43Y45,IO_L2P_T0_33
+AB10,33,IOB_X1Y41,RIOB18_X43Y41,IO_L4N_T0_33
+AB11,33,IOB_X1Y9,RIOB18_X43Y9,IO_L20N_T3_33
+AB12,33,IOB_X1Y5,RIOB18_X43Y5,IO_L22N_T3_33
+AB13,33,IOB_X1Y6,RIOB18_X43Y5,IO_L22P_T3_33
+AB15,13,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_13
+AB16,13,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_13
+AB17,13,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_13
+AB18,13,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_13
+AB20,13,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_13
+AB21,13,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_13
+AB22,13,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_13
+B1,115,OPAD_X0Y4,GTX_CHANNEL_2_X99Y139,MGTXTXN2_115
+B2,115,OPAD_X0Y5,GTX_CHANNEL_2_X99Y139,MGTXTXP2_115
+B5,115,IPAD_X0Y24,GTX_CHANNEL_3_X99Y150,MGTXRXN3_115
+B6,115,IPAD_X0Y25,GTX_CHANNEL_3_X99Y150,MGTXRXP3_115
+B8,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
+B10,16,IOB_X0Y159,LIOB33_X0Y159,IO_L20N_T3_16
+B11,16,IOB_X0Y160,LIOB33_X0Y159,IO_L20P_T3_16
+B12,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+B13,15,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_AD2N_15
+B15,15,IOB_X0Y132,LIOB33_X0Y131,IO_L9P_T1_DQS_AD11P_15
+B16,15,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_AD3P_15
+B17,15,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_AD4P_15
+B18,15,IOB_X0Y110,LIOB33_X0Y109,IO_L20P_T3_A20_15
+B20,15,IOB_X0Y102,LIOB33_X0Y101,IO_L24P_T3_RS1_15
+B21,15,IOB_X0Y101,LIOB33_X0Y101,IO_L24N_T3_RS0_15
+B22,15,IOB_X0Y107,LIOB33_X0Y107,IO_L21N_T3_DQS_A18_15
+C3,115,IPAD_X0Y18,GTX_CHANNEL_2_X99Y139,MGTXRXN2_115
+C4,115,IPAD_X0Y19,GTX_CHANNEL_2_X99Y139,MGTXRXP2_115
+C8,16,IOB_X0Y156,LIOB33_X0Y155,IO_L22P_T3_16
+C9,16,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_VREF_16
+C10,16,IOB_X0Y185,LIOB33_X0Y185,IO_L7N_T1_16
+C12,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+C13,15,IOB_X0Y140,LIOB33_X0Y139,IO_L5P_T0_AD2P_15
+C14,15,IOB_X0Y136,LIOB33_X0Y135,IO_L7P_T1_AD10P_15
+C15,15,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_AD10N_15
+C17,15,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_AD5P_15
+C18,15,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_AD5N_15
+C19,15,IOB_X0Y112,LIOB33_X0Y111,IO_L19P_T3_A22_15
+C20,15,IOB_X0Y111,LIOB33_X0Y111,IO_L19N_T3_A21_VREF_15
+C22,15,IOB_X0Y108,LIOB33_X0Y107,IO_L21P_T3_DQS_15
+D1,115,OPAD_X0Y2,GTX_CHANNEL_1_X99Y121,MGTXTXN1_115
+D2,115,OPAD_X0Y3,GTX_CHANNEL_1_X99Y121,MGTXTXP1_115
+D5,115,IPAD_X0Y9,GTX_COMMON_X99Y127,MGTREFCLK0N_115
+D6,115,IPAD_X0Y8,GTX_COMMON_X99Y127,MGTREFCLK0P_115
+D9,16,IOB_X0Y162,LIOB33_X0Y161,IO_L19P_T3_16
+D10,16,IOB_X0Y186,LIOB33_X0Y185,IO_L7P_T1_16
+D11,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
+D12,15,IOB_X0Y149,LIOB33_SING_X0Y149,IO_0_15
+D14,15,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_15
+D15,15,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_AD12P_15
+D16,15,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_AD12N_15
+D17,15,IOB_X0Y121,LIOB33_X0Y121,IO_L14N_T2_SRCC_15
+D19,15,IOB_X0Y114,LIOB33_X0Y113,IO_L18P_T2_A24_15
+D20,15,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_A23_15
+D21,15,IOB_X0Y104,LIOB33_X0Y103,IO_L23P_T3_FOE_B_15
+D22,15,IOB_X0Y103,LIOB33_X0Y103,IO_L23N_T3_FWE_B_15
+E3,115,IPAD_X0Y6,GTX_CHANNEL_1_X99Y121,MGTXRXN1_115
+E4,115,IPAD_X0Y7,GTX_CHANNEL_1_X99Y121,MGTXRXP1_115
+E8,16,IOB_X0Y152,LIOB33_X0Y151,IO_24_T3_16
+E9,16,IOB_X0Y169,LIOB33_X0Y169,IO_L15N_T2_DQS_16
+E11,16,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_16
+E12,16,IOB_X0Y179,LIOB33_X0Y179,IO_L10N_T1_16
+E13,16,IOB_X0Y180,LIOB33_X0Y179,IO_L10P_T1_16
+E14,15,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_15
+E16,15,IOB_X0Y122,LIOB33_X0Y121,IO_L14P_T2_SRCC_15
+E17,15,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_15
+E18,15,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_15
+E19,15,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A25_15
+E21,14,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_D09_14
+E22,14,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_D10_14
+F1,115,OPAD_X0Y0,GTX_CHANNEL_0_X99Y110,MGTXTXN0_115
+F2,115,OPAD_X0Y1,GTX_CHANNEL_0_X99Y110,MGTXTXP0_115
+F5,115,IPAD_X0Y11,GTX_COMMON_X99Y127,MGTREFCLK1N_115
+F6,115,IPAD_X0Y10,GTX_COMMON_X99Y127,MGTREFCLK1P_115
+F8,16,IOB_X0Y165,LIOB33_X0Y165,IO_L17N_T2_16
+F9,16,IOB_X0Y170,LIOB33_X0Y169,IO_L15P_T2_DQS_16
+F10,16,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_16
+F11,16,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_16
+F13,16,IOB_X0Y183,LIOB33_X0Y183,IO_L8N_T1_16
+F14,16,IOB_X0Y187,LIOB33_X0Y187,IO_6_T0_VREF_16
+F15,15,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_AD1P_15
+F16,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+F18,15,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A26_15
+F19,14,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_D03_14
+F20,14,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_D05_14
+F21,14,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_D13_14
+G3,115,IPAD_X0Y0,GTX_CHANNEL_0_X99Y110,MGTXRXN0_115
+G4,115,IPAD_X0Y1,GTX_CHANNEL_0_X99Y110,MGTXRXP0_115
+G8,16,IOB_X0Y166,LIOB33_X0Y165,IO_L17P_T2_16
+G10,16,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_16
+G11,16,IOB_X0Y174,LIOB33_X0Y173,IO_L13P_T2_MRCC_16
+G12,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16
+G13,16,IOB_X0Y184,LIOB33_X0Y183,IO_L8P_T1_16
+G15,15,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_AD0P_15
+G16,15,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_AD0N_15
+G17,15,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_ADV_B_15
+G18,14,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_D02_14
+G20,14,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_D04_14
+G21,14,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_14
+G22,14,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_D12_14
+H8,16,IOB_X0Y167,LIOB33_X0Y167,IO_L16N_T2_16
+H9,16,IOB_X0Y168,LIOB33_X0Y167,IO_L16P_T2_16
+H10,16,IOB_X0Y164,LIOB33_X0Y163,IO_18_T2_16
+H12,16,IOB_X0Y172,LIOB33_X0Y171,IO_L14P_T2_SRCC_16
+H13,16,IOB_X0Y181,LIOB33_X0Y181,IO_L9N_T1_DQS_16
+H14,16,IOB_X0Y182,LIOB33_X0Y181,IO_L9P_T1_DQS_16
+H15,15,IOB_X0Y100,LIOB33_SING_X0Y100,IO_25_15
+H17,15,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_15
+H18,14,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_D00_MOSI_14
+H19,14,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_D01_DIN_14
+H20,14,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_14
+H22,14,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_D11_14
+J16,15,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_A28_15
+J17,15,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A27_15
+J19,14,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_EMCCLK_14
+J20,14,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_14
+J21,14,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_D14_14
+J22,14,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_D15_14
+K1,34,IOB_X1Y96,RIOB18_X43Y95,IO_L2P_T0_34
+K2,34,IOB_X1Y91,RIOB18_X43Y91,IO_L4N_T0_34
+K3,34,IOB_X1Y92,RIOB18_X43Y91,IO_L4P_T0_34
+K4,34,IOB_X1Y99,RIOB18_SING_X43Y99,IO_0_VRN_34
+K16,14,IOB_X0Y99,LIOB33_SING_X0Y99,IO_0_14
+K17,14,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_D08_VREF_14
+K18,14,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_PUDC_B_14
+K19,14,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_D07_14
+K21,14,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_CSI_B_14
+K22,14,IOB_X0Y67,LIOB33_X0Y67,IO_L16N_T2_A15_D31_14
+L1,34,IOB_X1Y95,RIOB18_X43Y95,IO_L2N_T0_34
+L3,34,IOB_X1Y98,RIOB18_X43Y97,IO_L1P_T0_34
+L4,34,IOB_X1Y87,RIOB18_X43Y87,IO_L6N_T0_VREF_34
+L5,34,IOB_X1Y88,RIOB18_X43Y87,IO_L6P_T0_34
+L12,0,IPAD_X0Y66,MONITOR_BOT_FUJI2_X61Y131,VP_0
+L16,14,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_FCS_B_14
+L18,14,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_D06_14
+L19,14,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_14
+L20,14,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_14
+L21,14,IOB_X0Y63,LIOB33_X0Y63,IO_L18N_T2_A11_D27_14
+M1,34,IOB_X1Y93,RIOB18_X43Y93,IO_L3N_T0_DQS_34
+M2,34,IOB_X1Y94,RIOB18_X43Y93,IO_L3P_T0_DQS_34
+M3,34,IOB_X1Y97,RIOB18_X43Y97,IO_L1N_T0_34
+M5,34,IOB_X1Y82,RIOB18_X43Y81,IO_L9P_T1_DQS_34
+M11,0,IPAD_X0Y67,MONITOR_BOT_FUJI2_X61Y131,VN_0
+M16,14,IOB_X0Y50,LIOB33_SING_X0Y50,IO_25_14
+M17,14,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_14
+M18,14,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_14
+M20,14,IOB_X0Y64,LIOB33_X0Y63,IO_L18P_T2_A12_D28_14
+M21,14,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A13_D29_14
+M22,14,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_DOUT_CSO_B_14
+N2,34,IOB_X1Y89,RIOB18_X43Y89,IO_L5N_T0_34
+N3,34,IOB_X1Y90,RIOB18_X43Y89,IO_L5P_T0_34
+N4,34,IOB_X1Y81,RIOB18_X43Y81,IO_L9N_T1_DQS_34
+N5,34,IOB_X1Y64,RIOB18_X43Y63,IO_L18P_T2_34
+N17,14,IOB_X0Y53,LIOB33_X0Y53,IO_L23N_T3_A02_D18_14
+N18,14,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_14
+N19,14,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_14
+N20,14,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A14_D30_14
+N22,14,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_RDWR_B_14
+P1,34,IOB_X1Y84,RIOB18_X43Y83,IO_L8P_T1_34
+P2,34,IOB_X1Y86,RIOB18_X43Y85,IO_L7P_T1_34
+P4,34,IOB_X1Y78,RIOB18_X43Y77,IO_L11P_T1_SRCC_34
+P5,34,IOB_X1Y63,RIOB18_X43Y63,IO_L18N_T2_34
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diff --git a/kintex7/xc7k70tfbg484-3/part.json b/kintex7/xc7k70tfbg484-3/part.json
new file mode 100644
index 0000000..4dc0b1c
--- /dev/null
+++ b/kintex7/xc7k70tfbg484-3/part.json
@@ -0,0 +1,602 @@
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+}
diff --git a/kintex7/xc7k70tfbg484-3/part.yaml b/kintex7/xc7k70tfbg484-3/part.yaml
new file mode 100644
index 0000000..0293099
--- /dev/null
+++ b/kintex7/xc7k70tfbg484-3/part.yaml
@@ -0,0 +1,387 @@
+!<xilinx/xc7series/part>
+idcode: 0x3647093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/kintex7/xc7k70tfbg676-1/package_pins.csv b/kintex7/xc7k70tfbg676-1/package_pins.csv
new file mode 100644
index 0000000..d3e1d54
--- /dev/null
+++ b/kintex7/xc7k70tfbg676-1/package_pins.csv
@@ -0,0 +1,343 @@
+pin,bank,site,tile,pin_function
+A3,116,OPAD_X0Y14,GTX_CHANNEL_3_X99Y202,MGTXTXN3_116
+A4,116,OPAD_X0Y15,GTX_CHANNEL_3_X99Y202,MGTXTXP3_116
+A8,16,IOB_X0Y181,LIOB33_X0Y181,IO_L9N_T1_DQS_16
+A9,16,IOB_X0Y182,LIOB33_X0Y181,IO_L9P_T1_DQS_16
+A10,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
+A12,16,IOB_X0Y151,LIOB33_X0Y151,IO_L24N_T3_16
+A13,16,IOB_X0Y152,LIOB33_X0Y151,IO_L24P_T3_16
+A14,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A15,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+A17,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+A18,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+A19,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+A20,14,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_D12_14
+A22,14,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_D03_14
+A23,14,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_D04_14
+A24,14,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_D05_14
+A25,14,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_D01_DIN_14
+AA2,34,IOB_X1Y75,RIOB18_X43Y75,IO_L12N_T1_MRCC_34
+AA3,34,IOB_X1Y76,RIOB18_X43Y75,IO_L12P_T1_MRCC_34
+AA4,34,IOB_X1Y74,RIOB18_X43Y73,IO_L13P_T2_MRCC_34
+AA5,34,IOB_X1Y70,RIOB18_X43Y69,IO_L15P_T2_DQS_34
+AA7,33,IOB_X1Y33,RIOB18_X43Y33,IO_L8N_T1_33
+AA8,33,IOB_X1Y34,RIOB18_X43Y33,IO_L8P_T1_33
+AA9,33,IOB_X1Y28,RIOB18_X43Y27,IO_L11P_T1_SRCC_33
+AA10,33,IOB_X1Y22,RIOB18_X43Y21,IO_L14P_T2_SRCC_33
+AA12,33,IOB_X1Y17,RIOB18_X43Y17,IO_L16N_T2_33
+AA13,33,IOB_X1Y18,RIOB18_X43Y17,IO_L16P_T2_33
+AB1,34,IOB_X1Y82,RIOB18_X43Y81,IO_L9P_T1_DQS_34
+AB2,34,IOB_X1Y78,RIOB18_X43Y77,IO_L11P_T1_SRCC_34
+AB4,34,IOB_X1Y73,RIOB18_X43Y73,IO_L13N_T2_MRCC_34
+AB5,34,IOB_X1Y69,RIOB18_X43Y69,IO_L15N_T2_DQS_34
+AB6,34,IOB_X1Y68,RIOB18_X43Y67,IO_L16P_T2_34
+AB7,33,IOB_X1Y30,RIOB18_X43Y29,IO_L10P_T1_33
+AB9,33,IOB_X1Y27,RIOB18_X43Y27,IO_L11N_T1_SRCC_33
+AB10,33,IOB_X1Y21,RIOB18_X43Y21,IO_L14N_T2_SRCC_33
+AB11,33,IOB_X1Y24,RIOB18_X43Y23,IO_L13P_T2_MRCC_33
+AB12,33,IOB_X1Y20,RIOB18_X43Y19,IO_L15P_T2_DQS_33
+AC1,34,IOB_X1Y81,RIOB18_X43Y81,IO_L9N_T1_DQS_34
+AC2,34,IOB_X1Y77,RIOB18_X43Y77,IO_L11N_T1_SRCC_34
+AC3,34,IOB_X1Y71,RIOB18_X43Y71,IO_L14N_T2_SRCC_34
+AC4,34,IOB_X1Y72,RIOB18_X43Y71,IO_L14P_T2_SRCC_34
+AC6,34,IOB_X1Y67,RIOB18_X43Y67,IO_L16N_T2_34
+AC7,33,IOB_X1Y29,RIOB18_X43Y29,IO_L10N_T1_33
+AC8,33,IOB_X1Y32,RIOB18_X43Y31,IO_L9P_T1_DQS_33
+AC9,33,IOB_X1Y26,RIOB18_X43Y25,IO_L12P_T1_MRCC_33
+AC11,33,IOB_X1Y23,RIOB18_X43Y23,IO_L13N_T2_MRCC_33
+AC12,33,IOB_X1Y19,RIOB18_X43Y19,IO_L15N_T2_DQS_33
+AC13,33,IOB_X1Y16,RIOB18_X43Y15,IO_L17P_T2_33
+AD1,34,IOB_X1Y60,RIOB18_X43Y59,IO_L20P_T3_34
+AD3,34,IOB_X1Y61,RIOB18_X43Y61,IO_L19N_T3_VREF_34
+AD4,34,IOB_X1Y62,RIOB18_X43Y61,IO_L19P_T3_34
+AD5,34,IOB_X1Y63,RIOB18_X43Y63,IO_L18N_T2_34
+AD6,34,IOB_X1Y64,RIOB18_X43Y63,IO_L18P_T2_34
+AD8,33,IOB_X1Y31,RIOB18_X43Y31,IO_L9N_T1_DQS_33
+AD9,33,IOB_X1Y25,RIOB18_X43Y25,IO_L12N_T1_MRCC_33
+AD10,33,IOB_X1Y10,RIOB18_X43Y9,IO_L20P_T3_33
+AD11,33,IOB_X1Y12,RIOB18_X43Y11,IO_L19P_T3_33
+AD13,33,IOB_X1Y15,RIOB18_X43Y15,IO_L17N_T2_33
+AE1,34,IOB_X1Y59,RIOB18_X43Y59,IO_L20N_T3_34
+AE2,34,IOB_X1Y55,RIOB18_X43Y55,IO_L22N_T3_34
+AE3,34,IOB_X1Y56,RIOB18_X43Y55,IO_L22P_T3_34
+AE5,34,IOB_X1Y53,RIOB18_X43Y53,IO_L23N_T3_34
+AE6,34,IOB_X1Y54,RIOB18_X43Y53,IO_L23P_T3_34
+AE7,33,IOB_X1Y36,RIOB18_X43Y35,IO_L7P_T1_33
+AE8,33,IOB_X1Y6,RIOB18_X43Y5,IO_L22P_T3_33
+AE10,33,IOB_X1Y9,RIOB18_X43Y9,IO_L20N_T3_33
+AE11,33,IOB_X1Y11,RIOB18_X43Y11,IO_L19N_T3_VREF_33
+AE12,33,IOB_X1Y8,RIOB18_X43Y7,IO_L21P_T3_DQS_33
+AE13,33,IOB_X1Y4,RIOB18_X43Y3,IO_L23P_T3_33
+AF2,34,IOB_X1Y51,RIOB18_X43Y51,IO_L24N_T3_34
+AF3,34,IOB_X1Y52,RIOB18_X43Y51,IO_L24P_T3_34
+AF4,34,IOB_X1Y57,RIOB18_X43Y57,IO_L21N_T3_DQS_34
+AF5,34,IOB_X1Y58,RIOB18_X43Y57,IO_L21P_T3_DQS_34
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+Y6,34,IOB_X1Y66,RIOB18_X43Y65,IO_L17P_T2_34
+Y7,33,IOB_X1Y41,RIOB18_X43Y41,IO_L4N_T0_33
+Y8,33,IOB_X1Y42,RIOB18_X43Y41,IO_L4P_T0_33
+Y10,33,IOB_X1Y39,RIOB18_X43Y39,IO_L5N_T0_33
+Y11,33,IOB_X1Y40,RIOB18_X43Y39,IO_L5P_T0_33
+Y12,33,IOB_X1Y13,RIOB18_X43Y13,IO_L18N_T2_33
+Y13,33,IOB_X1Y14,RIOB18_X43Y13,IO_L18P_T2_33
diff --git a/kintex7/xc7k70tfbg676-1/part.json b/kintex7/xc7k70tfbg676-1/part.json
new file mode 100644
index 0000000..4dc0b1c
--- /dev/null
+++ b/kintex7/xc7k70tfbg676-1/part.json
@@ -0,0 +1,602 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ }
+ }
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+ },
+ "1": {
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+ },
+ "2": {
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+ },
+ "3": {
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+ }
+ }
+ },
+ "CLB_IO_CLK": {
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+ "0": {
+ "frame_count": 42
+ },
+ "1": {
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+ },
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+ },
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+ }
+ }
+ }
+ }
+ }
+ }
+ },
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+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
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+ },
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+ },
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+ },
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+ "frame_count": 32
+ }
+ }
+ }
+ }
+ },
+ "1": {
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+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
+ "4": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ "frame_count": 30
+ },
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+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
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+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
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+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56914067,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182"
+ }
+}
diff --git a/kintex7/xc7k70tfbg676-1/part.yaml b/kintex7/xc7k70tfbg676-1/part.yaml
new file mode 100644
index 0000000..0293099
--- /dev/null
+++ b/kintex7/xc7k70tfbg676-1/part.yaml
@@ -0,0 +1,387 @@
+!<xilinx/xc7series/part>
+idcode: 0x3647093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
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+ 23: !<xilinx/xc7series/configuration_column>
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+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
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+ 29: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 32: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
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+ 10: !<xilinx/xc7series/configuration_column>
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+ 11: !<xilinx/xc7series/configuration_column>
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+ 12: !<xilinx/xc7series/configuration_column>
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+ 13: !<xilinx/xc7series/configuration_column>
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+ 14: !<xilinx/xc7series/configuration_column>
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+ 15: !<xilinx/xc7series/configuration_column>
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+ 16: !<xilinx/xc7series/configuration_column>
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+ 17: !<xilinx/xc7series/configuration_column>
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+ 18: !<xilinx/xc7series/configuration_column>
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+ 19: !<xilinx/xc7series/configuration_column>
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+ 20: !<xilinx/xc7series/configuration_column>
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+ 21: !<xilinx/xc7series/configuration_column>
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+ 22: !<xilinx/xc7series/configuration_column>
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+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
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+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
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+ 29: !<xilinx/xc7series/configuration_column>
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+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
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+ 34: !<xilinx/xc7series/configuration_column>
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+ 35: !<xilinx/xc7series/configuration_column>
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+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/kintex7/xc7k70tfbg676-2L/package_pins.csv b/kintex7/xc7k70tfbg676-2L/package_pins.csv
new file mode 100644
index 0000000..d3e1d54
--- /dev/null
+++ b/kintex7/xc7k70tfbg676-2L/package_pins.csv
@@ -0,0 +1,343 @@
+pin,bank,site,tile,pin_function
+A3,116,OPAD_X0Y14,GTX_CHANNEL_3_X99Y202,MGTXTXN3_116
+A4,116,OPAD_X0Y15,GTX_CHANNEL_3_X99Y202,MGTXTXP3_116
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+A10,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
+A12,16,IOB_X0Y151,LIOB33_X0Y151,IO_L24N_T3_16
+A13,16,IOB_X0Y152,LIOB33_X0Y151,IO_L24P_T3_16
+A14,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A15,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+A17,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+A18,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+A19,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
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+A22,14,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_D03_14
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+A25,14,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_D01_DIN_14
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+AA3,34,IOB_X1Y76,RIOB18_X43Y75,IO_L12P_T1_MRCC_34
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+AA7,33,IOB_X1Y33,RIOB18_X43Y33,IO_L8N_T1_33
+AA8,33,IOB_X1Y34,RIOB18_X43Y33,IO_L8P_T1_33
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+AA12,33,IOB_X1Y17,RIOB18_X43Y17,IO_L16N_T2_33
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+AB7,33,IOB_X1Y30,RIOB18_X43Y29,IO_L10P_T1_33
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+AB11,33,IOB_X1Y24,RIOB18_X43Y23,IO_L13P_T2_MRCC_33
+AB12,33,IOB_X1Y20,RIOB18_X43Y19,IO_L15P_T2_DQS_33
+AC1,34,IOB_X1Y81,RIOB18_X43Y81,IO_L9N_T1_DQS_34
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+C23,14,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_FCS_B_14
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+C26,14,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_D07_14
+D1,116,OPAD_X0Y10,GTX_CHANNEL_1_X99Y173,MGTXTXN1_116
+D2,116,OPAD_X0Y11,GTX_CHANNEL_1_X99Y173,MGTXTXP1_116
+D5,116,IPAD_X0Y39,GTX_COMMON_X99Y179,MGTREFCLK0N_116
+D6,116,IPAD_X0Y38,GTX_COMMON_X99Y179,MGTREFCLK0P_116
+D8,16,IOB_X0Y183,LIOB33_X0Y183,IO_L8N_T1_16
+D9,16,IOB_X0Y184,LIOB33_X0Y183,IO_L8P_T1_16
+D10,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
+D11,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16
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+Y12,33,IOB_X1Y13,RIOB18_X43Y13,IO_L18N_T2_33
+Y13,33,IOB_X1Y14,RIOB18_X43Y13,IO_L18P_T2_33
diff --git a/kintex7/xc7k70tfbg676-2L/part.json b/kintex7/xc7k70tfbg676-2L/part.json
new file mode 100644
index 0000000..4dc0b1c
--- /dev/null
+++ b/kintex7/xc7k70tfbg676-2L/part.json
@@ -0,0 +1,602 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
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+ },
+ "31": {
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+ },
+ "32": {
+ "frame_count": 36
+ },
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+ },
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+ "frame_count": 36
+ },
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+ },
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+ },
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+ "frame_count": 28
+ },
+ "38": {
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+ },
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+ "frame_count": 36
+ },
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+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
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+ },
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+ },
+ "9": {
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+ },
+ "10": {
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+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
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+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56914067,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182"
+ }
+}
diff --git a/kintex7/xc7k70tfbg676-2L/part.yaml b/kintex7/xc7k70tfbg676-2L/part.yaml
new file mode 100644
index 0000000..0293099
--- /dev/null
+++ b/kintex7/xc7k70tfbg676-2L/part.yaml
@@ -0,0 +1,387 @@
+!<xilinx/xc7series/part>
+idcode: 0x3647093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/kintex7/xc7k70tfbg676-3/package_pins.csv b/kintex7/xc7k70tfbg676-3/package_pins.csv
new file mode 100644
index 0000000..d3e1d54
--- /dev/null
+++ b/kintex7/xc7k70tfbg676-3/package_pins.csv
@@ -0,0 +1,343 @@
+pin,bank,site,tile,pin_function
+A3,116,OPAD_X0Y14,GTX_CHANNEL_3_X99Y202,MGTXTXN3_116
+A4,116,OPAD_X0Y15,GTX_CHANNEL_3_X99Y202,MGTXTXP3_116
+A8,16,IOB_X0Y181,LIOB33_X0Y181,IO_L9N_T1_DQS_16
+A9,16,IOB_X0Y182,LIOB33_X0Y181,IO_L9P_T1_DQS_16
+A10,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
+A12,16,IOB_X0Y151,LIOB33_X0Y151,IO_L24N_T3_16
+A13,16,IOB_X0Y152,LIOB33_X0Y151,IO_L24P_T3_16
+A14,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A15,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+A17,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+A18,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+A19,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+A20,14,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_D12_14
+A22,14,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_D03_14
+A23,14,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_D04_14
+A24,14,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_D05_14
+A25,14,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_D01_DIN_14
+AA2,34,IOB_X1Y75,RIOB18_X43Y75,IO_L12N_T1_MRCC_34
+AA3,34,IOB_X1Y76,RIOB18_X43Y75,IO_L12P_T1_MRCC_34
+AA4,34,IOB_X1Y74,RIOB18_X43Y73,IO_L13P_T2_MRCC_34
+AA5,34,IOB_X1Y70,RIOB18_X43Y69,IO_L15P_T2_DQS_34
+AA7,33,IOB_X1Y33,RIOB18_X43Y33,IO_L8N_T1_33
+AA8,33,IOB_X1Y34,RIOB18_X43Y33,IO_L8P_T1_33
+AA9,33,IOB_X1Y28,RIOB18_X43Y27,IO_L11P_T1_SRCC_33
+AA10,33,IOB_X1Y22,RIOB18_X43Y21,IO_L14P_T2_SRCC_33
+AA12,33,IOB_X1Y17,RIOB18_X43Y17,IO_L16N_T2_33
+AA13,33,IOB_X1Y18,RIOB18_X43Y17,IO_L16P_T2_33
+AB1,34,IOB_X1Y82,RIOB18_X43Y81,IO_L9P_T1_DQS_34
+AB2,34,IOB_X1Y78,RIOB18_X43Y77,IO_L11P_T1_SRCC_34
+AB4,34,IOB_X1Y73,RIOB18_X43Y73,IO_L13N_T2_MRCC_34
+AB5,34,IOB_X1Y69,RIOB18_X43Y69,IO_L15N_T2_DQS_34
+AB6,34,IOB_X1Y68,RIOB18_X43Y67,IO_L16P_T2_34
+AB7,33,IOB_X1Y30,RIOB18_X43Y29,IO_L10P_T1_33
+AB9,33,IOB_X1Y27,RIOB18_X43Y27,IO_L11N_T1_SRCC_33
+AB10,33,IOB_X1Y21,RIOB18_X43Y21,IO_L14N_T2_SRCC_33
+AB11,33,IOB_X1Y24,RIOB18_X43Y23,IO_L13P_T2_MRCC_33
+AB12,33,IOB_X1Y20,RIOB18_X43Y19,IO_L15P_T2_DQS_33
+AC1,34,IOB_X1Y81,RIOB18_X43Y81,IO_L9N_T1_DQS_34
+AC2,34,IOB_X1Y77,RIOB18_X43Y77,IO_L11N_T1_SRCC_34
+AC3,34,IOB_X1Y71,RIOB18_X43Y71,IO_L14N_T2_SRCC_34
+AC4,34,IOB_X1Y72,RIOB18_X43Y71,IO_L14P_T2_SRCC_34
+AC6,34,IOB_X1Y67,RIOB18_X43Y67,IO_L16N_T2_34
+AC7,33,IOB_X1Y29,RIOB18_X43Y29,IO_L10N_T1_33
+AC8,33,IOB_X1Y32,RIOB18_X43Y31,IO_L9P_T1_DQS_33
+AC9,33,IOB_X1Y26,RIOB18_X43Y25,IO_L12P_T1_MRCC_33
+AC11,33,IOB_X1Y23,RIOB18_X43Y23,IO_L13N_T2_MRCC_33
+AC12,33,IOB_X1Y19,RIOB18_X43Y19,IO_L15N_T2_DQS_33
+AC13,33,IOB_X1Y16,RIOB18_X43Y15,IO_L17P_T2_33
+AD1,34,IOB_X1Y60,RIOB18_X43Y59,IO_L20P_T3_34
+AD3,34,IOB_X1Y61,RIOB18_X43Y61,IO_L19N_T3_VREF_34
+AD4,34,IOB_X1Y62,RIOB18_X43Y61,IO_L19P_T3_34
+AD5,34,IOB_X1Y63,RIOB18_X43Y63,IO_L18N_T2_34
+AD6,34,IOB_X1Y64,RIOB18_X43Y63,IO_L18P_T2_34
+AD8,33,IOB_X1Y31,RIOB18_X43Y31,IO_L9N_T1_DQS_33
+AD9,33,IOB_X1Y25,RIOB18_X43Y25,IO_L12N_T1_MRCC_33
+AD10,33,IOB_X1Y10,RIOB18_X43Y9,IO_L20P_T3_33
+AD11,33,IOB_X1Y12,RIOB18_X43Y11,IO_L19P_T3_33
+AD13,33,IOB_X1Y15,RIOB18_X43Y15,IO_L17N_T2_33
+AE1,34,IOB_X1Y59,RIOB18_X43Y59,IO_L20N_T3_34
+AE2,34,IOB_X1Y55,RIOB18_X43Y55,IO_L22N_T3_34
+AE3,34,IOB_X1Y56,RIOB18_X43Y55,IO_L22P_T3_34
+AE5,34,IOB_X1Y53,RIOB18_X43Y53,IO_L23N_T3_34
+AE6,34,IOB_X1Y54,RIOB18_X43Y53,IO_L23P_T3_34
+AE7,33,IOB_X1Y36,RIOB18_X43Y35,IO_L7P_T1_33
+AE8,33,IOB_X1Y6,RIOB18_X43Y5,IO_L22P_T3_33
+AE10,33,IOB_X1Y9,RIOB18_X43Y9,IO_L20N_T3_33
+AE11,33,IOB_X1Y11,RIOB18_X43Y11,IO_L19N_T3_VREF_33
+AE12,33,IOB_X1Y8,RIOB18_X43Y7,IO_L21P_T3_DQS_33
+AE13,33,IOB_X1Y4,RIOB18_X43Y3,IO_L23P_T3_33
+AF2,34,IOB_X1Y51,RIOB18_X43Y51,IO_L24N_T3_34
+AF3,34,IOB_X1Y52,RIOB18_X43Y51,IO_L24P_T3_34
+AF4,34,IOB_X1Y57,RIOB18_X43Y57,IO_L21N_T3_DQS_34
+AF5,34,IOB_X1Y58,RIOB18_X43Y57,IO_L21P_T3_DQS_34
+AF7,33,IOB_X1Y35,RIOB18_X43Y35,IO_L7N_T1_33
+AF8,33,IOB_X1Y5,RIOB18_X43Y5,IO_L22N_T3_33
+AF9,33,IOB_X1Y1,RIOB18_X43Y1,IO_L24N_T3_33
+AF10,33,IOB_X1Y2,RIOB18_X43Y1,IO_L24P_T3_33
+AF12,33,IOB_X1Y7,RIOB18_X43Y7,IO_L21N_T3_DQS_33
+AF13,33,IOB_X1Y3,RIOB18_X43Y3,IO_L23N_T3_33
+B1,116,OPAD_X0Y12,GTX_CHANNEL_2_X99Y191,MGTXTXN2_116
+B2,116,OPAD_X0Y13,GTX_CHANNEL_2_X99Y191,MGTXTXP2_116
+B5,116,IPAD_X0Y54,GTX_CHANNEL_3_X99Y202,MGTXRXN3_116
+B6,116,IPAD_X0Y55,GTX_CHANNEL_3_X99Y202,MGTXRXP3_116
+B9,16,IOB_X0Y179,LIOB33_X0Y179,IO_L10N_T1_16
+B10,16,IOB_X0Y156,LIOB33_X0Y155,IO_L22P_T3_16
+B11,16,IOB_X0Y159,LIOB33_X0Y159,IO_L20N_T3_16
+B12,16,IOB_X0Y160,LIOB33_X0Y159,IO_L20P_T3_16
+B14,16,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_16
+B15,16,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_16
+B16,15,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_AD0N_15
+B17,15,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_AD1P_15
+B19,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_AD9N_15
+B20,14,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_D11_14
+B21,14,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_D15_14
+B22,14,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_D02_14
+B24,14,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_D00_MOSI_14
+B25,14,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_PUDC_B_14
+B26,14,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_EMCCLK_14
+C3,116,IPAD_X0Y48,GTX_CHANNEL_2_X99Y191,MGTXRXN2_116
+C4,116,IPAD_X0Y49,GTX_CHANNEL_2_X99Y191,MGTXRXP2_116
+C9,16,IOB_X0Y180,LIOB33_X0Y179,IO_L10P_T1_16
+C11,16,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_16
+C12,16,IOB_X0Y174,LIOB33_X0Y173,IO_L13P_T2_MRCC_16
+C13,16,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_VREF_16
+C14,16,IOB_X0Y162,LIOB33_X0Y161,IO_L19P_T3_16
+C16,15,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_AD0P_15
+C17,15,IOB_X0Y140,LIOB33_X0Y139,IO_L5P_T0_AD2P_15
+C18,15,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_AD2N_15
+C19,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_AD9P_15
+C21,14,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_D14_14
+C22,14,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_D10_14
+C23,14,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_FCS_B_14
+C24,14,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_D08_VREF_14
+C26,14,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_D07_14
+D1,116,OPAD_X0Y10,GTX_CHANNEL_1_X99Y173,MGTXTXN1_116
+D2,116,OPAD_X0Y11,GTX_CHANNEL_1_X99Y173,MGTXTXP1_116
+D5,116,IPAD_X0Y39,GTX_COMMON_X99Y179,MGTREFCLK0N_116
+D6,116,IPAD_X0Y38,GTX_COMMON_X99Y179,MGTREFCLK0P_116
+D8,16,IOB_X0Y183,LIOB33_X0Y183,IO_L8N_T1_16
+D9,16,IOB_X0Y184,LIOB33_X0Y183,IO_L8P_T1_16
+D10,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
+D11,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16
+D13,16,IOB_X0Y165,LIOB33_X0Y165,IO_L17N_T2_16
+D14,16,IOB_X0Y166,LIOB33_X0Y165,IO_L17P_T2_16
+D15,15,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_15
+D16,15,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_15
+D18,15,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_15
+D19,15,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_15
+D20,15,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_ADV_B_15
+D21,14,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_D09_14
+D23,14,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_14
+D24,14,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_14
+D25,14,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_DOUT_CSO_B_14
+D26,14,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_D06_14
+E3,116,IPAD_X0Y36,GTX_CHANNEL_1_X99Y173,MGTXRXN1_116
+E4,116,IPAD_X0Y37,GTX_CHANNEL_1_X99Y173,MGTXRXP1_116
+E10,16,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_16
+E11,16,IOB_X0Y172,LIOB33_X0Y171,IO_L14P_T2_SRCC_16
+E12,16,IOB_X0Y163,LIOB33_X0Y163,IO_L18N_T2_16
+E13,16,IOB_X0Y164,LIOB33_X0Y163,IO_L18P_T2_16
+E15,15,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_AD4P_15
+E16,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD4N_15
+E17,15,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_AD5N_15
+E18,15,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_15
+E20,15,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A25_15
+E21,14,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_14
+E22,14,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_D13_14
+E23,14,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_14
+E25,14,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_RDWR_B_14
+E26,14,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A13_D29_14
+F1,116,OPAD_X0Y8,GTX_CHANNEL_0_X99Y162,MGTXTXN0_116
+F2,116,OPAD_X0Y9,GTX_CHANNEL_0_X99Y162,MGTXTXP0_116
+F5,116,IPAD_X0Y41,GTX_COMMON_X99Y179,MGTREFCLK1N_116
+F6,116,IPAD_X0Y40,GTX_COMMON_X99Y179,MGTREFCLK1P_116
+F8,16,IOB_X0Y185,LIOB33_X0Y185,IO_L7N_T1_16
+F9,16,IOB_X0Y186,LIOB33_X0Y185,IO_L7P_T1_16
+F10,16,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_16
+F12,16,IOB_X0Y167,LIOB33_X0Y167,IO_L16N_T2_16
+F13,16,IOB_X0Y169,LIOB33_X0Y169,IO_L15N_T2_DQS_16
+F14,16,IOB_X0Y170,LIOB33_X0Y169,IO_L15P_T2_DQS_16
+F15,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD3N_15
+F17,15,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_AD5P_15
+F18,15,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_AD12N_15
+F19,15,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A26_15
+F20,15,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A27_15
+F22,14,IOB_X0Y76,LIOB33_X0Y75,IO_L12P_T1_MRCC_14
+F23,14,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_14
+F24,14,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_14
+F25,14,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A14_D30_14
+G3,116,IPAD_X0Y30,GTX_CHANNEL_0_X99Y162,MGTXRXN0_116
+G4,116,IPAD_X0Y31,GTX_CHANNEL_0_X99Y162,MGTXRXP0_116
+G9,16,IOB_X0Y195,LIOB33_X0Y195,IO_L2N_T0_16
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diff --git a/kintex7/xc7k70tfbg676-3/part.json b/kintex7/xc7k70tfbg676-3/part.json
new file mode 100644
index 0000000..4dc0b1c
--- /dev/null
+++ b/kintex7/xc7k70tfbg676-3/part.json
@@ -0,0 +1,602 @@
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+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56914067,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182"
+ }
+}
diff --git a/kintex7/xc7k70tfbg676-3/part.yaml b/kintex7/xc7k70tfbg676-3/part.yaml
new file mode 100644
index 0000000..0293099
--- /dev/null
+++ b/kintex7/xc7k70tfbg676-3/part.yaml
@@ -0,0 +1,387 @@
+!<xilinx/xc7series/part>
+idcode: 0x3647093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/kintex7/xc7k70tfbv484-1/package_pins.csv b/kintex7/xc7k70tfbv484-1/package_pins.csv
new file mode 100644
index 0000000..73f4284
--- /dev/null
+++ b/kintex7/xc7k70tfbv484-1/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A3,115,OPAD_X0Y6,GTX_CHANNEL_3_X99Y150,MGTXTXN3_115
+A4,115,OPAD_X0Y7,GTX_CHANNEL_3_X99Y150,MGTXTXP3_115
+A8,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A9,16,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_16
+A10,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+A11,16,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_16
+A13,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_AD9P_15
+A14,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_AD9N_15
+A15,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD11N_15
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diff --git a/kintex7/xc7k70tfbv484-1/part.json b/kintex7/xc7k70tfbv484-1/part.json
new file mode 100644
index 0000000..4dc0b1c
--- /dev/null
+++ b/kintex7/xc7k70tfbv484-1/part.json
@@ -0,0 +1,602 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
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+ }
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+ },
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+ }
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+ },
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+ "frame_count": 32
+ }
+ }
+ }
+ }
+ },
+ "1": {
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+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
+ "4": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "25": {
+ "frame_count": 30
+ },
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+ },
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+ },
+ "28": {
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+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56914067,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182"
+ }
+}
diff --git a/kintex7/xc7k70tfbv484-1/part.yaml b/kintex7/xc7k70tfbv484-1/part.yaml
new file mode 100644
index 0000000..0293099
--- /dev/null
+++ b/kintex7/xc7k70tfbv484-1/part.yaml
@@ -0,0 +1,387 @@
+!<xilinx/xc7series/part>
+idcode: 0x3647093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
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+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
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+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
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+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
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+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/kintex7/xc7k70tfbv484-2/package_pins.csv b/kintex7/xc7k70tfbv484-2/package_pins.csv
new file mode 100644
index 0000000..73f4284
--- /dev/null
+++ b/kintex7/xc7k70tfbv484-2/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
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+A4,115,OPAD_X0Y7,GTX_CHANNEL_3_X99Y150,MGTXTXP3_115
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+AA4,34,IOB_X1Y52,RIOB18_X43Y51,IO_L24P_T3_34
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+AB7,33,IOB_X1Y45,RIOB18_X43Y45,IO_L2N_T0_33
+AB8,33,IOB_X1Y46,RIOB18_X43Y45,IO_L2P_T0_33
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+B6,115,IPAD_X0Y25,GTX_CHANNEL_3_X99Y150,MGTXRXP3_115
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+D5,115,IPAD_X0Y9,GTX_COMMON_X99Y127,MGTREFCLK0N_115
+D6,115,IPAD_X0Y8,GTX_COMMON_X99Y127,MGTREFCLK0P_115
+D9,16,IOB_X0Y162,LIOB33_X0Y161,IO_L19P_T3_16
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diff --git a/kintex7/xc7k70tfbv484-2/part.json b/kintex7/xc7k70tfbv484-2/part.json
new file mode 100644
index 0000000..4dc0b1c
--- /dev/null
+++ b/kintex7/xc7k70tfbv484-2/part.json
@@ -0,0 +1,602 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
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+ },
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+ },
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+ },
+ "11": {
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+ },
+ "12": {
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+ },
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+ "frame_count": 36
+ },
+ "14": {
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+ },
+ "15": {
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+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
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+ },
+ "18": {
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+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
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+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
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+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56914067,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182"
+ }
+}
diff --git a/kintex7/xc7k70tfbv484-2/part.yaml b/kintex7/xc7k70tfbv484-2/part.yaml
new file mode 100644
index 0000000..0293099
--- /dev/null
+++ b/kintex7/xc7k70tfbv484-2/part.yaml
@@ -0,0 +1,387 @@
+!<xilinx/xc7series/part>
+idcode: 0x3647093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
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+ 7: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/kintex7/xc7k70tfbv484-2L/package_pins.csv b/kintex7/xc7k70tfbv484-2L/package_pins.csv
new file mode 100644
index 0000000..73f4284
--- /dev/null
+++ b/kintex7/xc7k70tfbv484-2L/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A3,115,OPAD_X0Y6,GTX_CHANNEL_3_X99Y150,MGTXTXN3_115
+A4,115,OPAD_X0Y7,GTX_CHANNEL_3_X99Y150,MGTXTXP3_115
+A8,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A9,16,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_16
+A10,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+A11,16,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_16
+A13,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_AD9P_15
+A14,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_AD9N_15
+A15,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD11N_15
+A16,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD3N_15
+A18,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD4N_15
+A19,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
+A20,15,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A17_15
+A21,15,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A16_15
+AA1,34,IOB_X1Y56,RIOB18_X43Y55,IO_L22P_T3_34
+AA3,34,IOB_X1Y54,RIOB18_X43Y53,IO_L23P_T3_34
+AA4,34,IOB_X1Y52,RIOB18_X43Y51,IO_L24P_T3_34
+AA5,33,IOB_X1Y48,RIOB18_X43Y47,IO_L1P_T0_33
+AA6,33,IOB_X1Y44,RIOB18_X43Y43,IO_L3P_T0_DQS_33
+AA8,33,IOB_X1Y39,RIOB18_X43Y39,IO_L5N_T0_33
+AA9,33,IOB_X1Y40,RIOB18_X43Y39,IO_L5P_T0_33
+AA10,33,IOB_X1Y42,RIOB18_X43Y41,IO_L4P_T0_33
+AA11,33,IOB_X1Y10,RIOB18_X43Y9,IO_L20P_T3_33
+AA13,33,IOB_X1Y7,RIOB18_X43Y7,IO_L21N_T3_DQS_33
+AA14,13,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_13
+AA15,13,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_13
+AA16,13,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_13
+AA18,13,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_13
+AA19,13,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_13
+AA20,13,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_13
+AA21,13,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_13
+AB1,34,IOB_X1Y55,RIOB18_X43Y55,IO_L22N_T3_34
+AB2,34,IOB_X1Y53,RIOB18_X43Y53,IO_L23N_T3_34
+AB3,34,IOB_X1Y51,RIOB18_X43Y51,IO_L24N_T3_34
+AB5,33,IOB_X1Y47,RIOB18_X43Y47,IO_L1N_T0_33
+AB6,33,IOB_X1Y43,RIOB18_X43Y43,IO_L3N_T0_DQS_33
+AB7,33,IOB_X1Y45,RIOB18_X43Y45,IO_L2N_T0_33
+AB8,33,IOB_X1Y46,RIOB18_X43Y45,IO_L2P_T0_33
+AB10,33,IOB_X1Y41,RIOB18_X43Y41,IO_L4N_T0_33
+AB11,33,IOB_X1Y9,RIOB18_X43Y9,IO_L20N_T3_33
+AB12,33,IOB_X1Y5,RIOB18_X43Y5,IO_L22N_T3_33
+AB13,33,IOB_X1Y6,RIOB18_X43Y5,IO_L22P_T3_33
+AB15,13,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_13
+AB16,13,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_13
+AB17,13,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_13
+AB18,13,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_13
+AB20,13,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_13
+AB21,13,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_13
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+B6,115,IPAD_X0Y25,GTX_CHANNEL_3_X99Y150,MGTXRXP3_115
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+D6,115,IPAD_X0Y8,GTX_COMMON_X99Y127,MGTREFCLK0P_115
+D9,16,IOB_X0Y162,LIOB33_X0Y161,IO_L19P_T3_16
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+D12,15,IOB_X0Y149,LIOB33_SING_X0Y149,IO_0_15
+D14,15,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_15
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+E11,16,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_16
+E12,16,IOB_X0Y179,LIOB33_X0Y179,IO_L10N_T1_16
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+E17,15,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_15
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+E19,15,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A25_15
+E21,14,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_D09_14
+E22,14,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_D10_14
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+F5,115,IPAD_X0Y11,GTX_COMMON_X99Y127,MGTREFCLK1N_115
+F6,115,IPAD_X0Y10,GTX_COMMON_X99Y127,MGTREFCLK1P_115
+F8,16,IOB_X0Y165,LIOB33_X0Y165,IO_L17N_T2_16
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+F10,16,IOB_X0Y177,LIOB33_X0Y177,IO_L11N_T1_SRCC_16
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diff --git a/kintex7/xc7k70tfbv484-2L/part.json b/kintex7/xc7k70tfbv484-2L/part.json
new file mode 100644
index 0000000..4dc0b1c
--- /dev/null
+++ b/kintex7/xc7k70tfbv484-2L/part.json
@@ -0,0 +1,602 @@
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+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56914067,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182"
+ }
+}
diff --git a/kintex7/xc7k70tfbv484-2L/part.yaml b/kintex7/xc7k70tfbv484-2L/part.yaml
new file mode 100644
index 0000000..0293099
--- /dev/null
+++ b/kintex7/xc7k70tfbv484-2L/part.yaml
@@ -0,0 +1,387 @@
+!<xilinx/xc7series/part>
+idcode: 0x3647093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/kintex7/xc7k70tfbv484-3/package_pins.csv b/kintex7/xc7k70tfbv484-3/package_pins.csv
new file mode 100644
index 0000000..73f4284
--- /dev/null
+++ b/kintex7/xc7k70tfbv484-3/package_pins.csv
@@ -0,0 +1,308 @@
+pin,bank,site,tile,pin_function
+A3,115,OPAD_X0Y6,GTX_CHANNEL_3_X99Y150,MGTXTXN3_115
+A4,115,OPAD_X0Y7,GTX_CHANNEL_3_X99Y150,MGTXTXP3_115
+A8,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A9,16,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_16
+A10,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+A11,16,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_16
+A13,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_AD9P_15
+A14,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_AD9N_15
+A15,15,IOB_X0Y131,LIOB33_X0Y131,IO_L9N_T1_DQS_AD11N_15
+A16,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD3N_15
+A18,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD4N_15
+A19,15,IOB_X0Y109,LIOB33_X0Y109,IO_L20N_T3_A19_15
+A20,15,IOB_X0Y106,LIOB33_X0Y105,IO_L22P_T3_A17_15
+A21,15,IOB_X0Y105,LIOB33_X0Y105,IO_L22N_T3_A16_15
+AA1,34,IOB_X1Y56,RIOB18_X43Y55,IO_L22P_T3_34
+AA3,34,IOB_X1Y54,RIOB18_X43Y53,IO_L23P_T3_34
+AA4,34,IOB_X1Y52,RIOB18_X43Y51,IO_L24P_T3_34
+AA5,33,IOB_X1Y48,RIOB18_X43Y47,IO_L1P_T0_33
+AA6,33,IOB_X1Y44,RIOB18_X43Y43,IO_L3P_T0_DQS_33
+AA8,33,IOB_X1Y39,RIOB18_X43Y39,IO_L5N_T0_33
+AA9,33,IOB_X1Y40,RIOB18_X43Y39,IO_L5P_T0_33
+AA10,33,IOB_X1Y42,RIOB18_X43Y41,IO_L4P_T0_33
+AA11,33,IOB_X1Y10,RIOB18_X43Y9,IO_L20P_T3_33
+AA13,33,IOB_X1Y7,RIOB18_X43Y7,IO_L21N_T3_DQS_33
+AA14,13,IOB_X0Y14,LIOB33_X0Y13,IO_L18P_T2_13
+AA15,13,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_13
+AA16,13,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_13
+AA18,13,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_13
+AA19,13,IOB_X0Y30,LIOB33_X0Y29,IO_L10P_T1_13
+AA20,13,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_13
+AA21,13,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_13
+AB1,34,IOB_X1Y55,RIOB18_X43Y55,IO_L22N_T3_34
+AB2,34,IOB_X1Y53,RIOB18_X43Y53,IO_L23N_T3_34
+AB3,34,IOB_X1Y51,RIOB18_X43Y51,IO_L24N_T3_34
+AB5,33,IOB_X1Y47,RIOB18_X43Y47,IO_L1N_T0_33
+AB6,33,IOB_X1Y43,RIOB18_X43Y43,IO_L3N_T0_DQS_33
+AB7,33,IOB_X1Y45,RIOB18_X43Y45,IO_L2N_T0_33
+AB8,33,IOB_X1Y46,RIOB18_X43Y45,IO_L2P_T0_33
+AB10,33,IOB_X1Y41,RIOB18_X43Y41,IO_L4N_T0_33
+AB11,33,IOB_X1Y9,RIOB18_X43Y9,IO_L20N_T3_33
+AB12,33,IOB_X1Y5,RIOB18_X43Y5,IO_L22N_T3_33
+AB13,33,IOB_X1Y6,RIOB18_X43Y5,IO_L22P_T3_33
+AB15,13,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_13
+AB16,13,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_13
+AB17,13,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_13
+AB18,13,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_13
+AB20,13,IOB_X0Y29,LIOB33_X0Y29,IO_L10N_T1_13
+AB21,13,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_13
+AB22,13,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_13
+B1,115,OPAD_X0Y4,GTX_CHANNEL_2_X99Y139,MGTXTXN2_115
+B2,115,OPAD_X0Y5,GTX_CHANNEL_2_X99Y139,MGTXTXP2_115
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+Y4,34,IOB_X1Y61,RIOB18_X43Y61,IO_L19N_T3_VREF_34
+Y6,33,IOB_X1Y35,RIOB18_X43Y35,IO_L7N_T1_33
+Y7,33,IOB_X1Y25,RIOB18_X43Y25,IO_L12N_T1_MRCC_33
+Y8,33,IOB_X1Y26,RIOB18_X43Y25,IO_L12P_T1_MRCC_33
+Y9,33,IOB_X1Y23,RIOB18_X43Y23,IO_L13N_T2_MRCC_33
+Y11,33,IOB_X1Y37,RIOB18_X43Y37,IO_L6N_T0_VREF_33
+Y12,33,IOB_X1Y11,RIOB18_X43Y11,IO_L19N_T3_VREF_33
+Y13,33,IOB_X1Y8,RIOB18_X43Y7,IO_L21P_T3_DQS_33
+Y14,13,IOB_X0Y5,LIOB33_X0Y5,IO_L22N_T3_13
+Y16,13,IOB_X0Y7,LIOB33_X0Y7,IO_L21N_T3_DQS_13
+Y17,13,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_13
+Y18,13,IOB_X0Y24,LIOB33_X0Y23,IO_L13P_T2_MRCC_13
+Y19,13,IOB_X0Y23,LIOB33_X0Y23,IO_L13N_T2_MRCC_13
+Y21,13,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_13
+Y22,13,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_13
diff --git a/kintex7/xc7k70tfbv484-3/part.json b/kintex7/xc7k70tfbv484-3/part.json
new file mode 100644
index 0000000..4dc0b1c
--- /dev/null
+++ b/kintex7/xc7k70tfbv484-3/part.json
@@ -0,0 +1,602 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
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+ },
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+ },
+ "8": {
+ "frame_count": 36
+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ }
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+ },
+ "1": {
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+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
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+ }
+ }
+ },
+ "CLB_IO_CLK": {
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+ "0": {
+ "frame_count": 42
+ },
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+ "frame_count": 30
+ },
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+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
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+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
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+ "0": {
+ "frame_count": 42
+ },
+ "1": {
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+ },
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+ },
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+ },
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+ "frame_count": 32
+ }
+ }
+ }
+ }
+ },
+ "1": {
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+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
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+ },
+ "30": {
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+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56914067,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182"
+ }
+}
diff --git a/kintex7/xc7k70tfbv484-3/part.yaml b/kintex7/xc7k70tfbv484-3/part.yaml
new file mode 100644
index 0000000..0293099
--- /dev/null
+++ b/kintex7/xc7k70tfbv484-3/part.yaml
@@ -0,0 +1,387 @@
+!<xilinx/xc7series/part>
+idcode: 0x3647093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
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+ 7: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
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+ 37: !<xilinx/xc7series/configuration_column>
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+ 38: !<xilinx/xc7series/configuration_column>
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+ 39: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
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+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
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+ 6: !<xilinx/xc7series/configuration_column>
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+ 7: !<xilinx/xc7series/configuration_column>
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+ 8: !<xilinx/xc7series/configuration_column>
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+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
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+ 12: !<xilinx/xc7series/configuration_column>
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+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/kintex7/xc7k70tfbv676-1/package_pins.csv b/kintex7/xc7k70tfbv676-1/package_pins.csv
new file mode 100644
index 0000000..d3e1d54
--- /dev/null
+++ b/kintex7/xc7k70tfbv676-1/package_pins.csv
@@ -0,0 +1,343 @@
+pin,bank,site,tile,pin_function
+A3,116,OPAD_X0Y14,GTX_CHANNEL_3_X99Y202,MGTXTXN3_116
+A4,116,OPAD_X0Y15,GTX_CHANNEL_3_X99Y202,MGTXTXP3_116
+A8,16,IOB_X0Y181,LIOB33_X0Y181,IO_L9N_T1_DQS_16
+A9,16,IOB_X0Y182,LIOB33_X0Y181,IO_L9P_T1_DQS_16
+A10,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
+A12,16,IOB_X0Y151,LIOB33_X0Y151,IO_L24N_T3_16
+A13,16,IOB_X0Y152,LIOB33_X0Y151,IO_L24P_T3_16
+A14,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A15,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+A17,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+A18,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+A19,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+A20,14,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_D12_14
+A22,14,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_D03_14
+A23,14,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_D04_14
+A24,14,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_D05_14
+A25,14,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_D01_DIN_14
+AA2,34,IOB_X1Y75,RIOB18_X43Y75,IO_L12N_T1_MRCC_34
+AA3,34,IOB_X1Y76,RIOB18_X43Y75,IO_L12P_T1_MRCC_34
+AA4,34,IOB_X1Y74,RIOB18_X43Y73,IO_L13P_T2_MRCC_34
+AA5,34,IOB_X1Y70,RIOB18_X43Y69,IO_L15P_T2_DQS_34
+AA7,33,IOB_X1Y33,RIOB18_X43Y33,IO_L8N_T1_33
+AA8,33,IOB_X1Y34,RIOB18_X43Y33,IO_L8P_T1_33
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+AA12,33,IOB_X1Y17,RIOB18_X43Y17,IO_L16N_T2_33
+AA13,33,IOB_X1Y18,RIOB18_X43Y17,IO_L16P_T2_33
+AB1,34,IOB_X1Y82,RIOB18_X43Y81,IO_L9P_T1_DQS_34
+AB2,34,IOB_X1Y78,RIOB18_X43Y77,IO_L11P_T1_SRCC_34
+AB4,34,IOB_X1Y73,RIOB18_X43Y73,IO_L13N_T2_MRCC_34
+AB5,34,IOB_X1Y69,RIOB18_X43Y69,IO_L15N_T2_DQS_34
+AB6,34,IOB_X1Y68,RIOB18_X43Y67,IO_L16P_T2_34
+AB7,33,IOB_X1Y30,RIOB18_X43Y29,IO_L10P_T1_33
+AB9,33,IOB_X1Y27,RIOB18_X43Y27,IO_L11N_T1_SRCC_33
+AB10,33,IOB_X1Y21,RIOB18_X43Y21,IO_L14N_T2_SRCC_33
+AB11,33,IOB_X1Y24,RIOB18_X43Y23,IO_L13P_T2_MRCC_33
+AB12,33,IOB_X1Y20,RIOB18_X43Y19,IO_L15P_T2_DQS_33
+AC1,34,IOB_X1Y81,RIOB18_X43Y81,IO_L9N_T1_DQS_34
+AC2,34,IOB_X1Y77,RIOB18_X43Y77,IO_L11N_T1_SRCC_34
+AC3,34,IOB_X1Y71,RIOB18_X43Y71,IO_L14N_T2_SRCC_34
+AC4,34,IOB_X1Y72,RIOB18_X43Y71,IO_L14P_T2_SRCC_34
+AC6,34,IOB_X1Y67,RIOB18_X43Y67,IO_L16N_T2_34
+AC7,33,IOB_X1Y29,RIOB18_X43Y29,IO_L10N_T1_33
+AC8,33,IOB_X1Y32,RIOB18_X43Y31,IO_L9P_T1_DQS_33
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+AC12,33,IOB_X1Y19,RIOB18_X43Y19,IO_L15N_T2_DQS_33
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+AD1,34,IOB_X1Y60,RIOB18_X43Y59,IO_L20P_T3_34
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+C21,14,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_D14_14
+C22,14,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_D10_14
+C23,14,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_FCS_B_14
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+C26,14,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_D07_14
+D1,116,OPAD_X0Y10,GTX_CHANNEL_1_X99Y173,MGTXTXN1_116
+D2,116,OPAD_X0Y11,GTX_CHANNEL_1_X99Y173,MGTXTXP1_116
+D5,116,IPAD_X0Y39,GTX_COMMON_X99Y179,MGTREFCLK0N_116
+D6,116,IPAD_X0Y38,GTX_COMMON_X99Y179,MGTREFCLK0P_116
+D8,16,IOB_X0Y183,LIOB33_X0Y183,IO_L8N_T1_16
+D9,16,IOB_X0Y184,LIOB33_X0Y183,IO_L8P_T1_16
+D10,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
+D11,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16
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+D14,16,IOB_X0Y166,LIOB33_X0Y165,IO_L17P_T2_16
+D15,15,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_15
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+D18,15,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_15
+D19,15,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_15
+D20,15,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_ADV_B_15
+D21,14,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_D09_14
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+D26,14,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_D06_14
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diff --git a/kintex7/xc7k70tfbv676-1/part.json b/kintex7/xc7k70tfbv676-1/part.json
new file mode 100644
index 0000000..4dc0b1c
--- /dev/null
+++ b/kintex7/xc7k70tfbv676-1/part.json
@@ -0,0 +1,602 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
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+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
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+ },
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+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
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+ },
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+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
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+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
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+ },
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+ },
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+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
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+ },
+ "26": {
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+ },
+ "27": {
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+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 28
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 36
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 30
+ },
+ "43": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
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+ },
+ "7": {
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+ },
+ "8": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "15": {
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+ },
+ "16": {
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+ },
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+ },
+ "18": {
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+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
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+ },
+ "21": {
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+ },
+ "22": {
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+ },
+ "23": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
+ "35": {
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+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
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+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56914067,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182"
+ }
+}
diff --git a/kintex7/xc7k70tfbv676-1/part.yaml b/kintex7/xc7k70tfbv676-1/part.yaml
new file mode 100644
index 0000000..0293099
--- /dev/null
+++ b/kintex7/xc7k70tfbv676-1/part.yaml
@@ -0,0 +1,387 @@
+!<xilinx/xc7series/part>
+idcode: 0x3647093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/kintex7/xc7k70tfbv676-2/package_pins.csv b/kintex7/xc7k70tfbv676-2/package_pins.csv
new file mode 100644
index 0000000..d3e1d54
--- /dev/null
+++ b/kintex7/xc7k70tfbv676-2/package_pins.csv
@@ -0,0 +1,343 @@
+pin,bank,site,tile,pin_function
+A3,116,OPAD_X0Y14,GTX_CHANNEL_3_X99Y202,MGTXTXN3_116
+A4,116,OPAD_X0Y15,GTX_CHANNEL_3_X99Y202,MGTXTXP3_116
+A8,16,IOB_X0Y181,LIOB33_X0Y181,IO_L9N_T1_DQS_16
+A9,16,IOB_X0Y182,LIOB33_X0Y181,IO_L9P_T1_DQS_16
+A10,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
+A12,16,IOB_X0Y151,LIOB33_X0Y151,IO_L24N_T3_16
+A13,16,IOB_X0Y152,LIOB33_X0Y151,IO_L24P_T3_16
+A14,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A15,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+A17,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+A18,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+A19,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+A20,14,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_D12_14
+A22,14,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_D03_14
+A23,14,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_D04_14
+A24,14,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_D05_14
+A25,14,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_D01_DIN_14
+AA2,34,IOB_X1Y75,RIOB18_X43Y75,IO_L12N_T1_MRCC_34
+AA3,34,IOB_X1Y76,RIOB18_X43Y75,IO_L12P_T1_MRCC_34
+AA4,34,IOB_X1Y74,RIOB18_X43Y73,IO_L13P_T2_MRCC_34
+AA5,34,IOB_X1Y70,RIOB18_X43Y69,IO_L15P_T2_DQS_34
+AA7,33,IOB_X1Y33,RIOB18_X43Y33,IO_L8N_T1_33
+AA8,33,IOB_X1Y34,RIOB18_X43Y33,IO_L8P_T1_33
+AA9,33,IOB_X1Y28,RIOB18_X43Y27,IO_L11P_T1_SRCC_33
+AA10,33,IOB_X1Y22,RIOB18_X43Y21,IO_L14P_T2_SRCC_33
+AA12,33,IOB_X1Y17,RIOB18_X43Y17,IO_L16N_T2_33
+AA13,33,IOB_X1Y18,RIOB18_X43Y17,IO_L16P_T2_33
+AB1,34,IOB_X1Y82,RIOB18_X43Y81,IO_L9P_T1_DQS_34
+AB2,34,IOB_X1Y78,RIOB18_X43Y77,IO_L11P_T1_SRCC_34
+AB4,34,IOB_X1Y73,RIOB18_X43Y73,IO_L13N_T2_MRCC_34
+AB5,34,IOB_X1Y69,RIOB18_X43Y69,IO_L15N_T2_DQS_34
+AB6,34,IOB_X1Y68,RIOB18_X43Y67,IO_L16P_T2_34
+AB7,33,IOB_X1Y30,RIOB18_X43Y29,IO_L10P_T1_33
+AB9,33,IOB_X1Y27,RIOB18_X43Y27,IO_L11N_T1_SRCC_33
+AB10,33,IOB_X1Y21,RIOB18_X43Y21,IO_L14N_T2_SRCC_33
+AB11,33,IOB_X1Y24,RIOB18_X43Y23,IO_L13P_T2_MRCC_33
+AB12,33,IOB_X1Y20,RIOB18_X43Y19,IO_L15P_T2_DQS_33
+AC1,34,IOB_X1Y81,RIOB18_X43Y81,IO_L9N_T1_DQS_34
+AC2,34,IOB_X1Y77,RIOB18_X43Y77,IO_L11N_T1_SRCC_34
+AC3,34,IOB_X1Y71,RIOB18_X43Y71,IO_L14N_T2_SRCC_34
+AC4,34,IOB_X1Y72,RIOB18_X43Y71,IO_L14P_T2_SRCC_34
+AC6,34,IOB_X1Y67,RIOB18_X43Y67,IO_L16N_T2_34
+AC7,33,IOB_X1Y29,RIOB18_X43Y29,IO_L10N_T1_33
+AC8,33,IOB_X1Y32,RIOB18_X43Y31,IO_L9P_T1_DQS_33
+AC9,33,IOB_X1Y26,RIOB18_X43Y25,IO_L12P_T1_MRCC_33
+AC11,33,IOB_X1Y23,RIOB18_X43Y23,IO_L13N_T2_MRCC_33
+AC12,33,IOB_X1Y19,RIOB18_X43Y19,IO_L15N_T2_DQS_33
+AC13,33,IOB_X1Y16,RIOB18_X43Y15,IO_L17P_T2_33
+AD1,34,IOB_X1Y60,RIOB18_X43Y59,IO_L20P_T3_34
+AD3,34,IOB_X1Y61,RIOB18_X43Y61,IO_L19N_T3_VREF_34
+AD4,34,IOB_X1Y62,RIOB18_X43Y61,IO_L19P_T3_34
+AD5,34,IOB_X1Y63,RIOB18_X43Y63,IO_L18N_T2_34
+AD6,34,IOB_X1Y64,RIOB18_X43Y63,IO_L18P_T2_34
+AD8,33,IOB_X1Y31,RIOB18_X43Y31,IO_L9N_T1_DQS_33
+AD9,33,IOB_X1Y25,RIOB18_X43Y25,IO_L12N_T1_MRCC_33
+AD10,33,IOB_X1Y10,RIOB18_X43Y9,IO_L20P_T3_33
+AD11,33,IOB_X1Y12,RIOB18_X43Y11,IO_L19P_T3_33
+AD13,33,IOB_X1Y15,RIOB18_X43Y15,IO_L17N_T2_33
+AE1,34,IOB_X1Y59,RIOB18_X43Y59,IO_L20N_T3_34
+AE2,34,IOB_X1Y55,RIOB18_X43Y55,IO_L22N_T3_34
+AE3,34,IOB_X1Y56,RIOB18_X43Y55,IO_L22P_T3_34
+AE5,34,IOB_X1Y53,RIOB18_X43Y53,IO_L23N_T3_34
+AE6,34,IOB_X1Y54,RIOB18_X43Y53,IO_L23P_T3_34
+AE7,33,IOB_X1Y36,RIOB18_X43Y35,IO_L7P_T1_33
+AE8,33,IOB_X1Y6,RIOB18_X43Y5,IO_L22P_T3_33
+AE10,33,IOB_X1Y9,RIOB18_X43Y9,IO_L20N_T3_33
+AE11,33,IOB_X1Y11,RIOB18_X43Y11,IO_L19N_T3_VREF_33
+AE12,33,IOB_X1Y8,RIOB18_X43Y7,IO_L21P_T3_DQS_33
+AE13,33,IOB_X1Y4,RIOB18_X43Y3,IO_L23P_T3_33
+AF2,34,IOB_X1Y51,RIOB18_X43Y51,IO_L24N_T3_34
+AF3,34,IOB_X1Y52,RIOB18_X43Y51,IO_L24P_T3_34
+AF4,34,IOB_X1Y57,RIOB18_X43Y57,IO_L21N_T3_DQS_34
+AF5,34,IOB_X1Y58,RIOB18_X43Y57,IO_L21P_T3_DQS_34
+AF7,33,IOB_X1Y35,RIOB18_X43Y35,IO_L7N_T1_33
+AF8,33,IOB_X1Y5,RIOB18_X43Y5,IO_L22N_T3_33
+AF9,33,IOB_X1Y1,RIOB18_X43Y1,IO_L24N_T3_33
+AF10,33,IOB_X1Y2,RIOB18_X43Y1,IO_L24P_T3_33
+AF12,33,IOB_X1Y7,RIOB18_X43Y7,IO_L21N_T3_DQS_33
+AF13,33,IOB_X1Y3,RIOB18_X43Y3,IO_L23N_T3_33
+B1,116,OPAD_X0Y12,GTX_CHANNEL_2_X99Y191,MGTXTXN2_116
+B2,116,OPAD_X0Y13,GTX_CHANNEL_2_X99Y191,MGTXTXP2_116
+B5,116,IPAD_X0Y54,GTX_CHANNEL_3_X99Y202,MGTXRXN3_116
+B6,116,IPAD_X0Y55,GTX_CHANNEL_3_X99Y202,MGTXRXP3_116
+B9,16,IOB_X0Y179,LIOB33_X0Y179,IO_L10N_T1_16
+B10,16,IOB_X0Y156,LIOB33_X0Y155,IO_L22P_T3_16
+B11,16,IOB_X0Y159,LIOB33_X0Y159,IO_L20N_T3_16
+B12,16,IOB_X0Y160,LIOB33_X0Y159,IO_L20P_T3_16
+B14,16,IOB_X0Y158,LIOB33_X0Y157,IO_L21P_T3_DQS_16
+B15,16,IOB_X0Y154,LIOB33_X0Y153,IO_L23P_T3_16
+B16,15,IOB_X0Y147,LIOB33_X0Y147,IO_L1N_T0_AD0N_15
+B17,15,IOB_X0Y144,LIOB33_X0Y143,IO_L3P_T0_DQS_AD1P_15
+B19,15,IOB_X0Y141,LIOB33_X0Y141,IO_L4N_T0_AD9N_15
+B20,14,IOB_X0Y84,LIOB33_X0Y83,IO_L8P_T1_D11_14
+B21,14,IOB_X0Y79,LIOB33_X0Y79,IO_L10N_T1_D15_14
+B22,14,IOB_X0Y96,LIOB33_X0Y95,IO_L2P_T0_D02_14
+B24,14,IOB_X0Y98,LIOB33_X0Y97,IO_L1P_T0_D00_MOSI_14
+B25,14,IOB_X0Y94,LIOB33_X0Y93,IO_L3P_T0_DQS_PUDC_B_14
+B26,14,IOB_X0Y93,LIOB33_X0Y93,IO_L3N_T0_DQS_EMCCLK_14
+C3,116,IPAD_X0Y48,GTX_CHANNEL_2_X99Y191,MGTXRXN2_116
+C4,116,IPAD_X0Y49,GTX_CHANNEL_2_X99Y191,MGTXRXP2_116
+C9,16,IOB_X0Y180,LIOB33_X0Y179,IO_L10P_T1_16
+C11,16,IOB_X0Y173,LIOB33_X0Y173,IO_L13N_T2_MRCC_16
+C12,16,IOB_X0Y174,LIOB33_X0Y173,IO_L13P_T2_MRCC_16
+C13,16,IOB_X0Y161,LIOB33_X0Y161,IO_L19N_T3_VREF_16
+C14,16,IOB_X0Y162,LIOB33_X0Y161,IO_L19P_T3_16
+C16,15,IOB_X0Y148,LIOB33_X0Y147,IO_L1P_T0_AD0P_15
+C17,15,IOB_X0Y140,LIOB33_X0Y139,IO_L5P_T0_AD2P_15
+C18,15,IOB_X0Y139,LIOB33_X0Y139,IO_L5N_T0_AD2N_15
+C19,15,IOB_X0Y142,LIOB33_X0Y141,IO_L4P_T0_AD9P_15
+C21,14,IOB_X0Y80,LIOB33_X0Y79,IO_L10P_T1_D14_14
+C22,14,IOB_X0Y85,LIOB33_X0Y85,IO_L7N_T1_D10_14
+C23,14,IOB_X0Y88,LIOB33_X0Y87,IO_L6P_T0_FCS_B_14
+C24,14,IOB_X0Y87,LIOB33_X0Y87,IO_L6N_T0_D08_VREF_14
+C26,14,IOB_X0Y89,LIOB33_X0Y89,IO_L5N_T0_D07_14
+D1,116,OPAD_X0Y10,GTX_CHANNEL_1_X99Y173,MGTXTXN1_116
+D2,116,OPAD_X0Y11,GTX_CHANNEL_1_X99Y173,MGTXTXP1_116
+D5,116,IPAD_X0Y39,GTX_COMMON_X99Y179,MGTREFCLK0N_116
+D6,116,IPAD_X0Y38,GTX_COMMON_X99Y179,MGTREFCLK0P_116
+D8,16,IOB_X0Y183,LIOB33_X0Y183,IO_L8N_T1_16
+D9,16,IOB_X0Y184,LIOB33_X0Y183,IO_L8P_T1_16
+D10,16,IOB_X0Y175,LIOB33_X0Y175,IO_L12N_T1_MRCC_16
+D11,16,IOB_X0Y171,LIOB33_X0Y171,IO_L14N_T2_SRCC_16
+D13,16,IOB_X0Y165,LIOB33_X0Y165,IO_L17N_T2_16
+D14,16,IOB_X0Y166,LIOB33_X0Y165,IO_L17P_T2_16
+D15,15,IOB_X0Y138,LIOB33_X0Y137,IO_L6P_T0_15
+D16,15,IOB_X0Y137,LIOB33_X0Y137,IO_L6N_T0_VREF_15
+D18,15,IOB_X0Y123,LIOB33_X0Y123,IO_L13N_T2_MRCC_15
+D19,15,IOB_X0Y120,LIOB33_X0Y119,IO_L15P_T2_DQS_15
+D20,15,IOB_X0Y119,LIOB33_X0Y119,IO_L15N_T2_DQS_ADV_B_15
+D21,14,IOB_X0Y86,LIOB33_X0Y85,IO_L7P_T1_D09_14
+D23,14,IOB_X0Y78,LIOB33_X0Y77,IO_L11P_T1_SRCC_14
+D24,14,IOB_X0Y77,LIOB33_X0Y77,IO_L11N_T1_SRCC_14
+D25,14,IOB_X0Y69,LIOB33_X0Y69,IO_L15N_T2_DQS_DOUT_CSO_B_14
+D26,14,IOB_X0Y90,LIOB33_X0Y89,IO_L5P_T0_D06_14
+E3,116,IPAD_X0Y36,GTX_CHANNEL_1_X99Y173,MGTXRXN1_116
+E4,116,IPAD_X0Y37,GTX_CHANNEL_1_X99Y173,MGTXRXP1_116
+E10,16,IOB_X0Y176,LIOB33_X0Y175,IO_L12P_T1_MRCC_16
+E11,16,IOB_X0Y172,LIOB33_X0Y171,IO_L14P_T2_SRCC_16
+E12,16,IOB_X0Y163,LIOB33_X0Y163,IO_L18N_T2_16
+E13,16,IOB_X0Y164,LIOB33_X0Y163,IO_L18P_T2_16
+E15,15,IOB_X0Y130,LIOB33_X0Y129,IO_L10P_T1_AD4P_15
+E16,15,IOB_X0Y129,LIOB33_X0Y129,IO_L10N_T1_AD4N_15
+E17,15,IOB_X0Y125,LIOB33_X0Y125,IO_L12N_T1_MRCC_AD5N_15
+E18,15,IOB_X0Y124,LIOB33_X0Y123,IO_L13P_T2_MRCC_15
+E20,15,IOB_X0Y115,LIOB33_X0Y115,IO_L17N_T2_A25_15
+E21,14,IOB_X0Y82,LIOB33_X0Y81,IO_L9P_T1_DQS_14
+E22,14,IOB_X0Y81,LIOB33_X0Y81,IO_L9N_T1_DQS_D13_14
+E23,14,IOB_X0Y75,LIOB33_X0Y75,IO_L12N_T1_MRCC_14
+E25,14,IOB_X0Y70,LIOB33_X0Y69,IO_L15P_T2_DQS_RDWR_B_14
+E26,14,IOB_X0Y65,LIOB33_X0Y65,IO_L17N_T2_A13_D29_14
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+F5,116,IPAD_X0Y41,GTX_COMMON_X99Y179,MGTREFCLK1N_116
+F6,116,IPAD_X0Y40,GTX_COMMON_X99Y179,MGTREFCLK1P_116
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+F9,16,IOB_X0Y186,LIOB33_X0Y185,IO_L7P_T1_16
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+F13,16,IOB_X0Y169,LIOB33_X0Y169,IO_L15N_T2_DQS_16
+F14,16,IOB_X0Y170,LIOB33_X0Y169,IO_L15P_T2_DQS_16
+F15,15,IOB_X0Y133,LIOB33_X0Y133,IO_L8N_T1_AD3N_15
+F17,15,IOB_X0Y126,LIOB33_X0Y125,IO_L12P_T1_MRCC_AD5P_15
+F18,15,IOB_X0Y127,LIOB33_X0Y127,IO_L11N_T1_SRCC_AD12N_15
+F19,15,IOB_X0Y116,LIOB33_X0Y115,IO_L17P_T2_A26_15
+F20,15,IOB_X0Y117,LIOB33_X0Y117,IO_L16N_T2_A27_15
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+F23,14,IOB_X0Y73,LIOB33_X0Y73,IO_L13N_T2_MRCC_14
+F24,14,IOB_X0Y71,LIOB33_X0Y71,IO_L14N_T2_SRCC_14
+F25,14,IOB_X0Y66,LIOB33_X0Y65,IO_L17P_T2_A14_D30_14
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+G4,116,IPAD_X0Y31,GTX_CHANNEL_0_X99Y162,MGTXRXP0_116
+G9,16,IOB_X0Y195,LIOB33_X0Y195,IO_L2N_T0_16
+G10,16,IOB_X0Y196,LIOB33_X0Y195,IO_L2P_T0_16
+G11,16,IOB_X0Y178,LIOB33_X0Y177,IO_L11P_T1_SRCC_16
+G12,16,IOB_X0Y168,LIOB33_X0Y167,IO_L16P_T2_16
+G14,16,IOB_X0Y189,LIOB33_X0Y189,IO_L5N_T0_16
+G15,15,IOB_X0Y134,LIOB33_X0Y133,IO_L8P_T1_AD3P_15
+G16,15,IOB_X0Y135,LIOB33_X0Y135,IO_L7N_T1_AD10N_15
+G17,15,IOB_X0Y128,LIOB33_X0Y127,IO_L11P_T1_SRCC_AD12P_15
+G19,15,IOB_X0Y118,LIOB33_X0Y117,IO_L16P_T2_A28_15
+G20,15,IOB_X0Y113,LIOB33_X0Y113,IO_L18N_T2_A23_15
+G21,14,IOB_X0Y61,LIOB33_X0Y61,IO_L19N_T3_A09_D25_VREF_14
+G22,14,IOB_X0Y74,LIOB33_X0Y73,IO_L13P_T2_MRCC_14
+G24,14,IOB_X0Y72,LIOB33_X0Y71,IO_L14P_T2_SRCC_14
+G25,14,IOB_X0Y68,LIOB33_X0Y67,IO_L16P_T2_CSI_B_14
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diff --git a/kintex7/xc7k70tfbv676-2/part.json b/kintex7/xc7k70tfbv676-2/part.json
new file mode 100644
index 0000000..4dc0b1c
--- /dev/null
+++ b/kintex7/xc7k70tfbv676-2/part.json
@@ -0,0 +1,602 @@
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+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ },
+ "1": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 36
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 30
+ },
+ "25": {
+ "frame_count": 30
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56914067,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182"
+ }
+}
diff --git a/kintex7/xc7k70tfbv676-2/part.yaml b/kintex7/xc7k70tfbv676-2/part.yaml
new file mode 100644
index 0000000..0293099
--- /dev/null
+++ b/kintex7/xc7k70tfbv676-2/part.yaml
@@ -0,0 +1,387 @@
+!<xilinx/xc7series/part>
+idcode: 0x3647093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/kintex7/xc7k70tfbv676-2L/package_pins.csv b/kintex7/xc7k70tfbv676-2L/package_pins.csv
new file mode 100644
index 0000000..d3e1d54
--- /dev/null
+++ b/kintex7/xc7k70tfbv676-2L/package_pins.csv
@@ -0,0 +1,343 @@
+pin,bank,site,tile,pin_function
+A3,116,OPAD_X0Y14,GTX_CHANNEL_3_X99Y202,MGTXTXN3_116
+A4,116,OPAD_X0Y15,GTX_CHANNEL_3_X99Y202,MGTXTXP3_116
+A8,16,IOB_X0Y181,LIOB33_X0Y181,IO_L9N_T1_DQS_16
+A9,16,IOB_X0Y182,LIOB33_X0Y181,IO_L9P_T1_DQS_16
+A10,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
+A12,16,IOB_X0Y151,LIOB33_X0Y151,IO_L24N_T3_16
+A13,16,IOB_X0Y152,LIOB33_X0Y151,IO_L24P_T3_16
+A14,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A15,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+A17,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+A18,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
+A19,15,IOB_X0Y145,LIOB33_X0Y145,IO_L2N_T0_AD8N_15
+A20,14,IOB_X0Y83,LIOB33_X0Y83,IO_L8N_T1_D12_14
+A22,14,IOB_X0Y95,LIOB33_X0Y95,IO_L2N_T0_D03_14
+A23,14,IOB_X0Y92,LIOB33_X0Y91,IO_L4P_T0_D04_14
+A24,14,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_D05_14
+A25,14,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_D01_DIN_14
+AA2,34,IOB_X1Y75,RIOB18_X43Y75,IO_L12N_T1_MRCC_34
+AA3,34,IOB_X1Y76,RIOB18_X43Y75,IO_L12P_T1_MRCC_34
+AA4,34,IOB_X1Y74,RIOB18_X43Y73,IO_L13P_T2_MRCC_34
+AA5,34,IOB_X1Y70,RIOB18_X43Y69,IO_L15P_T2_DQS_34
+AA7,33,IOB_X1Y33,RIOB18_X43Y33,IO_L8N_T1_33
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diff --git a/kintex7/xc7k70tfbv676-2L/part.json b/kintex7/xc7k70tfbv676-2L/part.json
new file mode 100644
index 0000000..4dc0b1c
--- /dev/null
+++ b/kintex7/xc7k70tfbv676-2L/part.json
@@ -0,0 +1,602 @@
+{
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+ }
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+ },
+ "idcode": 56914067,
+ "iobanks": {
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+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182"
+ }
+}
diff --git a/kintex7/xc7k70tfbv676-2L/part.yaml b/kintex7/xc7k70tfbv676-2L/part.yaml
new file mode 100644
index 0000000..0293099
--- /dev/null
+++ b/kintex7/xc7k70tfbv676-2L/part.yaml
@@ -0,0 +1,387 @@
+!<xilinx/xc7series/part>
+idcode: 0x3647093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
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+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
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+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
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+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
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+ 1: !<xilinx/xc7series/configuration_column>
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+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
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+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
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+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/kintex7/xc7k70tfbv676-3/package_pins.csv b/kintex7/xc7k70tfbv676-3/package_pins.csv
new file mode 100644
index 0000000..d3e1d54
--- /dev/null
+++ b/kintex7/xc7k70tfbv676-3/package_pins.csv
@@ -0,0 +1,343 @@
+pin,bank,site,tile,pin_function
+A3,116,OPAD_X0Y14,GTX_CHANNEL_3_X99Y202,MGTXTXN3_116
+A4,116,OPAD_X0Y15,GTX_CHANNEL_3_X99Y202,MGTXTXP3_116
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+A10,16,IOB_X0Y155,LIOB33_X0Y155,IO_L22N_T3_16
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+A13,16,IOB_X0Y152,LIOB33_X0Y151,IO_L24P_T3_16
+A14,16,IOB_X0Y157,LIOB33_X0Y157,IO_L21N_T3_DQS_16
+A15,16,IOB_X0Y153,LIOB33_X0Y153,IO_L23N_T3_16
+A17,15,IOB_X0Y143,LIOB33_X0Y143,IO_L3N_T0_DQS_AD1N_15
+A18,15,IOB_X0Y146,LIOB33_X0Y145,IO_L2P_T0_AD8P_15
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+A24,14,IOB_X0Y91,LIOB33_X0Y91,IO_L4N_T0_D05_14
+A25,14,IOB_X0Y97,LIOB33_X0Y97,IO_L1N_T0_D01_DIN_14
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+Y3,34,IOB_X1Y86,RIOB18_X43Y85,IO_L7P_T1_34
+Y5,34,IOB_X1Y65,RIOB18_X43Y65,IO_L17N_T2_34
+Y6,34,IOB_X1Y66,RIOB18_X43Y65,IO_L17P_T2_34
+Y7,33,IOB_X1Y41,RIOB18_X43Y41,IO_L4N_T0_33
+Y8,33,IOB_X1Y42,RIOB18_X43Y41,IO_L4P_T0_33
+Y10,33,IOB_X1Y39,RIOB18_X43Y39,IO_L5N_T0_33
+Y11,33,IOB_X1Y40,RIOB18_X43Y39,IO_L5P_T0_33
+Y12,33,IOB_X1Y13,RIOB18_X43Y13,IO_L18N_T2_33
+Y13,33,IOB_X1Y14,RIOB18_X43Y13,IO_L18P_T2_33
diff --git a/kintex7/xc7k70tfbv676-3/part.json b/kintex7/xc7k70tfbv676-3/part.json
new file mode 100644
index 0000000..4dc0b1c
--- /dev/null
+++ b/kintex7/xc7k70tfbv676-3/part.json
@@ -0,0 +1,602 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
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+ },
+ "5": {
+ "frame_count": 36
+ },
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+ },
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+ },
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+ },
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+ }
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+ },
+ "1": {
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+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
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+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
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+ },
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+ },
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+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
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+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
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+ "0": {
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+ },
+ "1": {
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+ },
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+ },
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+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ },
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+ "configuration_buses": {
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+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
+ "4": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ "frame_count": 30
+ },
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+ },
+ "27": {
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+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 28
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 28
+ },
+ "34": {
+ "frame_count": 36
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 32
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 56914067,
+ "iobanks": {
+ "0": "X1Y130",
+ "13": "X1Y26",
+ "14": "X1Y78",
+ "15": "X1Y130",
+ "16": "X1Y182"
+ }
+}
diff --git a/kintex7/xc7k70tfbv676-3/part.yaml b/kintex7/xc7k70tfbv676-3/part.yaml
new file mode 100644
index 0000000..0293099
--- /dev/null
+++ b/kintex7/xc7k70tfbv676-3/part.yaml
@@ -0,0 +1,387 @@
+!<xilinx/xc7series/part>
+idcode: 0x3647093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 32
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/zynq7/mapping/devices.yaml b/zynq7/mapping/devices.yaml
index f780df4..e252aec 100644
--- a/zynq7/mapping/devices.yaml
+++ b/zynq7/mapping/devices.yaml
@@ -1,5 +1,5 @@
# device to fabric mapping
-"xc7z020s":
- fabric: "xc7z020s"
-"xc7z010s":
- fabric: "xc7z010s"
+"xc7z020":
+ fabric: "xc7z020"
+"xc7z010":
+ fabric: "xc7z010"
diff --git a/zynq7/mapping/parts.yaml b/zynq7/mapping/parts.yaml
index 538f8e0..a47e274 100644
--- a/zynq7/mapping/parts.yaml
+++ b/zynq7/mapping/parts.yaml
@@ -1,13 +1,48 @@
-# part number to device, package and speed grade mapping
-"xc7z020clg484-1":
- device: "xc7z020s"
- package: "clg481"
- speedgrade: "1"
-"xc7z020clg400-1":
- device: "xc7z020s"
- package: "clg400"
- speedgrade: "1"
-"xc7z010clg400-1":
- device: "xc7z010s"
- package: "clg400"
- speedgrade: "1"
+xc7z010clg225-1:
+ device: xc7z010
+ package: clg225
+ speedgrade: '1'
+xc7z010clg225-2:
+ device: xc7z010
+ package: clg225
+ speedgrade: '2'
+xc7z010clg225-3:
+ device: xc7z010
+ package: clg225
+ speedgrade: '3'
+xc7z010clg400-1:
+ device: xc7z010
+ package: clg400
+ speedgrade: '1'
+xc7z010clg400-2:
+ device: xc7z010
+ package: clg400
+ speedgrade: '2'
+xc7z010clg400-3:
+ device: xc7z010
+ package: clg400
+ speedgrade: '3'
+xc7z020clg400-1:
+ device: xc7z020
+ package: clg400
+ speedgrade: '1'
+xc7z020clg400-2:
+ device: xc7z020
+ package: clg400
+ speedgrade: '2'
+xc7z020clg400-3:
+ device: xc7z020
+ package: clg400
+ speedgrade: '3'
+xc7z020clg484-1:
+ device: xc7z020
+ package: clg484
+ speedgrade: '1'
+xc7z020clg484-2:
+ device: xc7z020
+ package: clg484
+ speedgrade: '2'
+xc7z020clg484-3:
+ device: xc7z020
+ package: clg484
+ speedgrade: '3'
diff --git a/zynq7/mask_bram_l.db b/zynq7/mask_bram_l.db
index 945e1ef..b85f315 100644
--- a/zynq7/mask_bram_l.db
+++ b/zynq7/mask_bram_l.db
@@ -1,69 +1,24 @@
-bit 00_11
-bit 00_22
bit 00_25
bit 00_26
bit 00_27
-bit 00_29
bit 00_30
-bit 00_33
-bit 00_34
-bit 00_37
-bit 00_38
-bit 00_39
-bit 00_41
bit 00_42
-bit 00_75
-bit 00_78
-bit 00_81
-bit 00_83
-bit 00_86
bit 00_89
bit 00_90
bit 00_91
-bit 00_93
bit 00_94
-bit 00_97
-bit 00_98
-bit 00_99
-bit 00_101
-bit 00_102
-bit 00_103
-bit 00_105
bit 00_106
bit 00_139
bit 00_145
-bit 00_203
-bit 00_214
bit 00_217
bit 00_218
bit 00_219
-bit 00_221
bit 00_222
-bit 00_225
-bit 00_226
-bit 00_227
-bit 00_229
-bit 00_230
-bit 00_231
-bit 00_233
bit 00_234
-bit 00_266
-bit 00_267
-bit 00_270
-bit 00_273
-bit 00_275
-bit 00_278
bit 00_281
bit 00_282
bit 00_283
-bit 00_285
bit 00_286
-bit 00_289
-bit 00_290
-bit 00_291
-bit 00_293
-bit 00_295
-bit 00_297
bit 00_298
bit 01_09
bit 01_10
@@ -77,14 +32,12 @@
bit 01_32
bit 01_33
bit 01_34
-bit 01_36
bit 01_37
bit 01_38
bit 01_40
bit 01_41
bit 01_73
bit 01_74
-bit 01_77
bit 01_78
bit 01_84
bit 01_85
@@ -93,6 +46,7 @@
bit 01_90
bit 01_93
bit 01_96
+bit 01_97
bit 01_98
bit 01_100
bit 01_101
@@ -111,7 +65,6 @@
bit 01_218
bit 01_221
bit 01_224
-bit 01_225
bit 01_226
bit 01_228
bit 01_229
@@ -122,6 +75,7 @@
bit 01_266
bit 01_269
bit 01_270
+bit 01_276
bit 01_277
bit 01_280
bit 01_281
@@ -135,35 +89,30 @@
bit 01_294
bit 01_296
bit 01_297
-bit 02_46
+bit 02_37
bit 02_54
-bit 02_101
+bit 02_86
+bit 02_109
bit 02_110
-bit 02_174
-bit 02_238
bit 02_251
bit 02_253
-bit 02_278
bit 02_302
-bit 03_21
+bit 02_303
bit 03_54
-bit 03_97
-bit 03_101
+bit 03_110
bit 03_198
bit 03_214
bit 03_230
+bit 03_244
bit 03_250
bit 03_252
-bit 04_108
bit 04_111
-bit 04_156
+bit 04_246
bit 04_254
-bit 04_279
-bit 04_280
-bit 04_283
-bit 05_20
-bit 05_23
-bit 05_96
+bit 05_39
+bit 05_86
+bit 05_110
+bit 05_111
bit 05_198
bit 05_214
bit 05_230
@@ -171,10 +120,11 @@
bit 06_03
bit 06_05
bit 06_11
-bit 06_17
+bit 06_15
bit 06_19
-bit 06_20
+bit 06_21
bit 06_27
+bit 06_29
bit 06_33
bit 06_35
bit 06_37
@@ -185,34 +135,32 @@
bit 06_65
bit 06_67
bit 06_69
-bit 06_77
+bit 06_73
+bit 06_81
bit 06_83
bit 06_85
-bit 06_89
-bit 06_93
bit 06_99
bit 06_101
+bit 06_107
bit 06_115
bit 06_117
bit 06_125
bit 06_133
+bit 06_137
bit 06_147
bit 06_149
+bit 06_157
bit 06_163
-bit 06_171
-bit 06_179
-bit 06_181
-bit 06_187
bit 06_211
-bit 06_217
+bit 06_213
bit 06_219
bit 06_227
bit 06_243
bit 06_259
-bit 06_261
+bit 06_265
bit 06_275
+bit 06_277
bit 06_283
-bit 06_285
bit 06_291
bit 06_293
bit 06_299
@@ -227,40 +175,36 @@
bit 07_12
bit 07_14
bit 07_16
+bit 07_18
bit 07_22
-bit 07_24
bit 07_26
bit 07_28
bit 07_30
bit 07_32
bit 07_34
-bit 07_36
bit 07_38
bit 07_42
bit 07_46
-bit 07_47
bit 07_48
bit 07_52
bit 07_54
+bit 07_56
bit 07_58
bit 07_62
bit 07_64
-bit 07_66
bit 07_70
bit 07_72
bit 07_74
-bit 07_76
bit 07_78
bit 07_80
bit 07_82
+bit 07_84
bit 07_86
+bit 07_87
bit 07_88
bit 07_94
bit 07_96
bit 07_102
-bit 07_104
-bit 07_110
-bit 07_111
bit 07_112
bit 07_118
bit 07_120
@@ -273,30 +217,28 @@
bit 07_144
bit 07_150
bit 07_158
-bit 07_159
bit 07_160
bit 07_164
bit 07_166
bit 07_168
bit 07_174
-bit 07_175
bit 07_176
+bit 07_178
+bit 07_180
bit 07_182
bit 07_184
-bit 07_186
bit 07_190
bit 07_192
bit 07_200
bit 07_202
bit 07_206
bit 07_208
-bit 07_216
bit 07_218
bit 07_222
+bit 07_224
bit 07_230
bit 07_234
bit 07_238
-bit 07_239
bit 07_244
bit 07_246
bit 07_250
@@ -312,20 +254,20 @@
bit 07_288
bit 07_294
bit 07_298
-bit 07_303
-bit 07_304
bit 07_314
bit 07_318
bit 08_00
-bit 08_04
-bit 08_05
+bit 08_03
bit 08_06
bit 08_07
bit 08_08
+bit 08_10
bit 08_11
bit 08_12
+bit 08_15
bit 08_16
bit 08_17
+bit 08_18
bit 08_19
bit 08_20
bit 08_21
@@ -333,7 +275,6 @@
bit 08_23
bit 08_25
bit 08_26
-bit 08_27
bit 08_28
bit 08_29
bit 08_32
@@ -342,7 +283,6 @@
bit 08_37
bit 08_38
bit 08_39
-bit 08_42
bit 08_45
bit 08_48
bit 08_49
@@ -352,34 +292,37 @@
bit 08_53
bit 08_54
bit 08_55
+bit 08_56
+bit 08_58
bit 08_60
bit 08_61
bit 08_62
bit 08_64
bit 08_65
-bit 08_66
bit 08_67
+bit 08_69
bit 08_70
bit 08_71
-bit 08_77
+bit 08_73
+bit 08_75
bit 08_78
bit 08_79
bit 08_80
bit 08_81
-bit 08_84
+bit 08_82
+bit 08_83
bit 08_85
bit 08_86
bit 08_87
bit 08_90
+bit 08_93
bit 08_94
bit 08_96
bit 08_97
-bit 08_99
bit 08_100
bit 08_101
bit 08_102
bit 08_103
-bit 08_105
bit 08_106
bit 08_110
bit 08_112
@@ -388,51 +331,45 @@
bit 08_117
bit 08_118
bit 08_119
-bit 08_121
-bit 08_125
bit 08_126
bit 08_127
bit 08_128
bit 08_129
-bit 08_131
-bit 08_132
bit 08_133
bit 08_134
bit 08_135
bit 08_136
bit 08_137
-bit 08_138
bit 08_142
bit 08_143
bit 08_144
bit 08_145
+bit 08_148
bit 08_150
bit 08_151
bit 08_152
bit 08_158
+bit 08_159
bit 08_160
bit 08_161
bit 08_165
bit 08_166
bit 08_167
bit 08_168
-bit 08_174
+bit 08_175
bit 08_176
bit 08_177
-bit 08_180
bit 08_182
bit 08_184
bit 08_190
bit 08_191
bit 08_192
bit 08_193
-bit 08_197
bit 08_200
bit 08_206
bit 08_207
bit 08_213
bit 08_216
-bit 08_217
bit 08_222
bit 08_223
bit 08_224
@@ -448,84 +385,92 @@
bit 08_255
bit 08_264
bit 08_265
-bit 08_267
bit 08_270
bit 08_271
-bit 08_272
bit 08_276
bit 08_280
bit 08_282
+bit 08_283
bit 08_286
bit 08_288
bit 08_292
bit 08_293
bit 08_294
-bit 08_295
bit 08_296
+bit 08_298
bit 08_304
bit 08_307
bit 08_308
bit 08_309
bit 08_311
bit 08_312
+bit 08_314
+bit 08_315
bit 09_00
bit 09_02
bit 09_03
bit 09_04
+bit 09_05
bit 09_06
bit 09_08
bit 09_10
bit 09_11
bit 09_14
bit 09_16
-bit 09_17
bit 09_18
bit 09_19
+bit 09_21
+bit 09_23
+bit 09_30
bit 09_32
+bit 09_33
bit 09_34
bit 09_35
bit 09_36
bit 09_37
bit 09_39
bit 09_40
-bit 09_42
bit 09_48
bit 09_49
bit 09_50
bit 09_51
-bit 09_53
bit 09_56
bit 09_59
bit 09_61
+bit 09_62
bit 09_65
bit 09_66
bit 09_67
bit 09_68
-bit 09_71
bit 09_72
bit 09_76
+bit 09_77
bit 09_78
bit 09_80
+bit 09_81
bit 09_82
bit 09_83
-bit 09_92
+bit 09_84
+bit 09_93
+bit 09_94
+bit 09_95
bit 09_96
bit 09_98
bit 09_99
-bit 09_104
-bit 09_107
-bit 09_109
+bit 09_103
+bit 09_106
bit 09_112
+bit 09_113
bit 09_114
bit 09_115
bit 09_120
bit 09_121
-bit 09_124
-bit 09_125
bit 09_130
-bit 09_140
+bit 09_133
bit 09_141
bit 09_148
+bit 09_156
+bit 09_157
bit 09_160
bit 09_176
bit 09_182
@@ -534,22 +479,21 @@
bit 09_188
bit 09_203
bit 09_223
-bit 09_237
+bit 09_224
bit 09_248
bit 09_250
bit 09_252
bit 09_260
-bit 09_264
-bit 09_265
+bit 09_261
bit 09_269
bit 09_272
bit 09_274
-bit 09_285
+bit 09_278
bit 09_290
bit 09_296
-bit 09_304
bit 09_306
bit 09_307
+bit 09_312
bit 10_01
bit 10_02
bit 10_03
@@ -558,87 +502,87 @@
bit 10_07
bit 10_11
bit 10_13
+bit 10_15
bit 10_16
bit 10_17
bit 10_18
-bit 10_19
-bit 10_20
bit 10_23
-bit 10_29
bit 10_32
bit 10_33
bit 10_34
-bit 10_35
+bit 10_36
+bit 10_37
bit 10_39
bit 10_42
+bit 10_45
+bit 10_46
bit 10_48
bit 10_49
bit 10_50
bit 10_52
bit 10_53
+bit 10_54
bit 10_55
bit 10_59
-bit 10_60
bit 10_64
bit 10_65
bit 10_66
+bit 10_67
bit 10_68
bit 10_69
-bit 10_73
+bit 10_74
bit 10_75
-bit 10_76
+bit 10_77
bit 10_79
+bit 10_80
bit 10_81
bit 10_82
-bit 10_88
+bit 10_84
bit 10_96
bit 10_97
bit 10_98
bit 10_112
bit 10_113
bit 10_114
-bit 10_123
bit 10_124
bit 10_127
bit 10_128
bit 10_129
bit 10_130
-bit 10_131
-bit 10_132
+bit 10_134
bit 10_145
-bit 10_146
bit 10_148
-bit 10_156
+bit 10_151
bit 10_161
+bit 10_162
+bit 10_163
+bit 10_165
bit 10_177
bit 10_179
bit 10_181
bit 10_185
-bit 10_191
+bit 10_187
bit 10_193
bit 10_194
-bit 10_196
+bit 10_208
bit 10_210
bit 10_226
bit 10_233
bit 10_242
bit 10_245
-bit 10_251
bit 10_255
-bit 10_257
bit 10_258
-bit 10_267
+bit 10_260
bit 10_268
bit 10_272
bit 10_274
bit 10_288
bit 10_290
-bit 10_292
bit 10_305
bit 10_306
-bit 10_315
bit 11_00
bit 11_01
+bit 11_02
bit 11_03
bit 11_04
bit 11_06
@@ -646,28 +590,25 @@
bit 11_08
bit 11_10
bit 11_11
+bit 11_12
bit 11_14
bit 11_15
-bit 11_16
bit 11_17
bit 11_18
bit 11_21
bit 11_23
bit 11_27
bit 11_29
-bit 11_31
bit 11_32
bit 11_33
bit 11_34
+bit 11_37
bit 11_39
-bit 11_41
-bit 11_43
-bit 11_45
-bit 11_47
bit 11_48
bit 11_49
bit 11_50
bit 11_52
+bit 11_53
bit 11_55
bit 11_61
bit 11_63
@@ -676,57 +617,56 @@
bit 11_66
bit 11_68
bit 11_71
+bit 11_72
bit 11_74
bit 11_75
bit 11_76
-bit 11_77
bit 11_78
bit 11_79
bit 11_80
bit 11_81
bit 11_82
bit 11_87
-bit 11_91
bit 11_93
bit 11_95
bit 11_96
bit 11_97
bit 11_98
-bit 11_101
bit 11_103
bit 11_111
bit 11_112
bit 11_113
bit 11_119
-bit 11_122
-bit 11_125
+bit 11_121
bit 11_127
bit 11_129
bit 11_135
-bit 11_139
bit 11_143
bit 11_145
-bit 11_148
+bit 11_146
bit 11_151
-bit 11_153
+bit 11_156
bit 11_159
bit 11_161
bit 11_162
+bit 11_163
bit 11_167
bit 11_169
+bit 11_173
bit 11_175
bit 11_177
bit 11_182
+bit 11_184
bit 11_186
bit 11_187
-bit 11_188
bit 11_191
bit 11_193
bit 11_199
+bit 11_206
bit 11_207
+bit 11_209
bit 11_215
bit 11_223
-bit 11_226
bit 11_229
bit 11_239
bit 11_248
@@ -739,57 +679,51 @@
bit 11_272
bit 11_273
bit 11_274
-bit 11_276
+bit 11_277
bit 11_279
-bit 11_282
-bit 11_283
bit 11_285
bit 11_287
+bit 11_293
bit 11_295
bit 11_299
bit 11_303
-bit 11_305
bit 11_311
-bit 11_315
bit 12_02
bit 12_04
+bit 12_06
bit 12_09
bit 12_10
bit 12_16
bit 12_18
-bit 12_19
+bit 12_20
+bit 12_22
bit 12_26
-bit 12_27
+bit 12_28
+bit 12_30
bit 12_32
bit 12_34
bit 12_36
-bit 12_37
-bit 12_38
bit 12_40
bit 12_42
bit 12_48
bit 12_50
bit 12_52
bit 12_60
-bit 12_62
bit 12_64
bit 12_66
bit 12_68
-bit 12_70
+bit 12_72
bit 12_76
bit 12_80
bit 12_82
bit 12_84
-bit 12_88
bit 12_92
-bit 12_93
+bit 12_94
bit 12_96
bit 12_98
bit 12_100
-bit 12_104
-bit 12_105
+bit 12_102
bit 12_106
-bit 12_108
bit 12_112
bit 12_114
bit 12_116
@@ -798,30 +732,28 @@
bit 12_128
bit 12_130
bit 12_132
-bit 12_140
-bit 12_145
+bit 12_136
+bit 12_143
bit 12_146
bit 12_148
+bit 12_149
+bit 12_156
bit 12_160
bit 12_162
-bit 12_170
bit 12_176
-bit 12_178
-bit 12_186
bit 12_193
bit 12_194
-bit 12_196
bit 12_202
bit 12_207
+bit 12_208
bit 12_210
-bit 12_216
+bit 12_212
bit 12_218
+bit 12_224
bit 12_226
-bit 12_236
bit 12_239
bit 12_242
bit 12_255
-bit 12_257
bit 12_258
bit 12_260
bit 12_264
@@ -830,26 +762,24 @@
bit 12_271
bit 12_272
bit 12_274
+bit 12_276
bit 12_277
bit 12_281
bit 12_282
-bit 12_284
bit 12_287
bit 12_288
bit 12_290
bit 12_292
-bit 12_295
bit 12_296
bit 12_297
bit 12_298
-bit 12_304
bit 12_306
bit 12_308
+bit 12_312
bit 12_313
bit 12_314
bit 13_01
bit 13_03
-bit 13_05
bit 13_07
bit 13_09
bit 13_11
@@ -867,34 +797,32 @@
bit 13_37
bit 13_38
bit 13_39
-bit 13_41
-bit 13_43
bit 13_45
-bit 13_47
+bit 13_46
bit 13_49
bit 13_51
bit 13_53
bit 13_55
+bit 13_57
+bit 13_59
bit 13_61
bit 13_63
bit 13_65
+bit 13_69
bit 13_71
bit 13_75
-bit 13_77
bit 13_79
bit 13_81
+bit 13_83
bit 13_85
bit 13_87
bit 13_89
bit 13_91
-bit 13_92
bit 13_93
bit 13_95
bit 13_97
-bit 13_99
bit 13_101
bit 13_103
-bit 13_105
bit 13_107
bit 13_111
bit 13_113
@@ -907,25 +835,25 @@
bit 13_133
bit 13_135
bit 13_137
-bit 13_139
bit 13_143
bit 13_145
-bit 13_146
bit 13_151
bit 13_153
-bit 13_156
bit 13_159
bit 13_161
+bit 13_163
bit 13_165
bit 13_167
bit 13_169
bit 13_175
bit 13_177
+bit 13_179
bit 13_183
bit 13_187
bit 13_191
bit 13_193
bit 13_201
+bit 13_206
bit 13_207
bit 13_209
bit 13_213
@@ -939,6 +867,7 @@
bit 13_239
bit 13_241
bit 13_247
+bit 13_249
bit 13_255
bit 13_257
bit 13_263
@@ -948,10 +877,11 @@
bit 13_271
bit 13_272
bit 13_273
-bit 13_276
+bit 13_277
bit 13_279
bit 13_281
bit 13_283
+bit 13_285
bit 13_287
bit 13_289
bit 13_293
@@ -970,96 +900,96 @@
bit 14_03
bit 14_04
bit 14_05
+bit 14_07
bit 14_10
bit 14_11
bit 14_13
+bit 14_14
bit 14_15
bit 14_16
bit 14_18
-bit 14_20
bit 14_32
bit 14_34
bit 14_36
bit 14_48
bit 14_50
bit 14_52
+bit 14_54
bit 14_56
bit 14_58
+bit 14_62
bit 14_64
bit 14_66
bit 14_67
bit 14_68
bit 14_69
bit 14_73
+bit 14_74
bit 14_75
+bit 14_76
bit 14_77
bit 14_79
bit 14_80
bit 14_82
+bit 14_84
+bit 14_94
bit 14_96
bit 14_98
bit 14_112
bit 14_114
bit 14_120
-bit 14_122
bit 14_124
bit 14_130
bit 14_132
+bit 14_134
bit 14_140
bit 14_146
bit 14_148
bit 14_156
bit 14_162
bit 14_176
-bit 14_180
+bit 14_179
bit 14_181
bit 14_185
bit 14_187
-bit 14_191
bit 14_222
-bit 14_226
bit 14_245
bit 14_251
bit 14_255
bit 14_258
-bit 14_260
-bit 14_264
-bit 14_268
bit 14_274
-bit 14_282
-bit 14_284
-bit 14_288
+bit 14_278
bit 14_290
bit 14_306
bit 15_00
bit 15_01
+bit 15_02
bit 15_03
bit 15_04
-bit 15_05
bit 15_06
bit 15_07
bit 15_08
bit 15_10
bit 15_11
+bit 15_12
bit 15_14
bit 15_15
bit 15_17
-bit 15_21
+bit 15_19
bit 15_23
bit 15_27
bit 15_29
bit 15_31
bit 15_33
-bit 15_35
bit 15_37
bit 15_39
bit 15_43
bit 15_45
bit 15_47
bit 15_49
-bit 15_51
bit 15_53
bit 15_55
+bit 15_57
bit 15_59
bit 15_61
bit 15_63
@@ -1069,6 +999,7 @@
bit 15_68
bit 15_71
bit 15_72
+bit 15_73
bit 15_74
bit 15_75
bit 15_76
@@ -1076,24 +1007,17 @@
bit 15_79
bit 15_81
bit 15_83
-bit 15_85
bit 15_87
bit 15_93
bit 15_95
bit 15_97
-bit 15_99
bit 15_103
-bit 15_111
bit 15_113
bit 15_117
bit 15_119
bit 15_121
-bit 15_123
-bit 15_125
bit 15_127
bit 15_129
-bit 15_131
-bit 15_133
bit 15_135
bit 15_137
bit 15_143
@@ -1102,13 +1026,14 @@
bit 15_153
bit 15_159
bit 15_161
+bit 15_163
bit 15_165
bit 15_167
bit 15_169
+bit 15_173
bit 15_175
bit 15_177
bit 15_179
-bit 15_181
bit 15_182
bit 15_183
bit 15_184
@@ -1117,14 +1042,15 @@
bit 15_188
bit 15_191
bit 15_193
-bit 15_197
bit 15_199
bit 15_201
bit 15_203
bit 15_207
+bit 15_209
bit 15_217
bit 15_219
bit 15_223
+bit 15_225
bit 15_229
bit 15_231
bit 15_233
@@ -1137,22 +1063,19 @@
bit 15_251
bit 15_252
bit 15_255
-bit 15_263
bit 15_267
bit 15_271
-bit 15_273
bit 15_281
bit 15_283
-bit 15_285
bit 15_287
bit 15_289
+bit 15_293
bit 15_295
bit 15_297
bit 15_299
bit 15_305
bit 15_309
bit 15_315
-bit 15_319
bit 16_23
bit 16_40
bit 16_48
@@ -1196,7 +1119,6 @@
bit 16_115
bit 16_116
bit 16_117
-bit 16_119
bit 16_120
bit 16_122
bit 16_123
@@ -1269,7 +1191,6 @@
bit 16_211
bit 16_212
bit 16_213
-bit 16_215
bit 16_216
bit 16_218
bit 16_219
@@ -1291,25 +1212,23 @@
bit 16_244
bit 16_245
bit 16_248
-bit 16_271
bit 16_279
bit 16_296
-bit 16_304
+bit 17_15
bit 17_23
bit 17_40
-bit 17_48
bit 17_55
bit 17_66
bit 17_67
bit 17_68
bit 17_69
bit 17_71
-bit 17_80
bit 17_82
bit 17_83
bit 17_84
bit 17_85
bit 17_87
+bit 17_96
bit 17_104
bit 17_112
bit 17_119
@@ -1340,13 +1259,16 @@
bit 17_175
bit 17_184
bit 17_232
+bit 17_240
+bit 17_271
bit 17_279
bit 17_296
bit 17_304
+bit 18_14
bit 18_22
+bit 18_33
bit 18_38
bit 18_41
-bit 18_49
bit 18_54
bit 18_62
bit 18_66
@@ -1369,7 +1291,6 @@
bit 18_92
bit 18_93
bit 18_94
-bit 18_97
bit 18_98
bit 18_99
bit 18_100
@@ -1465,7 +1386,6 @@
bit 18_228
bit 18_229
bit 18_230
-bit 18_233
bit 18_234
bit 18_235
bit 18_236
@@ -1475,12 +1395,14 @@
bit 18_243
bit 18_244
bit 18_245
+bit 18_270
+bit 18_278
bit 18_294
bit 18_297
bit 19_22
-bit 19_33
bit 19_41
bit 19_49
+bit 19_54
bit 19_62
bit 19_66
bit 19_67
@@ -1496,6 +1418,7 @@
bit 19_83
bit 19_84
bit 19_85
+bit 19_86
bit 19_90
bit 19_91
bit 19_92
@@ -1521,7 +1444,6 @@
bit 19_123
bit 19_124
bit 19_125
-bit 19_129
bit 19_130
bit 19_131
bit 19_132
@@ -1570,6 +1492,7 @@
bit 19_183
bit 19_185
bit 19_190
+bit 19_193
bit 19_194
bit 19_195
bit 19_196
@@ -1579,6 +1502,7 @@
bit 19_203
bit 19_204
bit 19_205
+bit 19_206
bit 19_210
bit 19_211
bit 19_212
@@ -1729,10 +1653,8 @@
bit 21_243
bit 21_245
bit 22_23
-bit 22_32
bit 22_40
bit 22_47
-bit 22_48
bit 22_55
bit 22_63
bit 22_66
@@ -1853,13 +1775,16 @@
bit 22_235
bit 22_236
bit 22_237
+bit 22_240
bit 22_242
bit 22_243
bit 22_244
bit 22_245
bit 22_248
bit 22_271
+bit 22_279
bit 22_296
+bit 23_15
bit 23_23
bit 23_39
bit 23_40
@@ -1879,7 +1804,6 @@
bit 23_96
bit 23_104
bit 23_112
-bit 23_119
bit 23_127
bit 23_135
bit 23_143
@@ -1897,6 +1821,7 @@
bit 23_158
bit 23_159
bit 23_161
+bit 23_167
bit 23_168
bit 23_169
bit 23_170
@@ -1906,12 +1831,14 @@
bit 23_174
bit 23_175
bit 23_184
-bit 23_215
+bit 23_192
bit 23_232
bit 23_240
+bit 23_271
bit 23_279
bit 23_295
bit 23_304
+bit 24_15
bit 24_23
bit 24_32
bit 24_39
@@ -1958,7 +1885,6 @@
bit 24_115
bit 24_116
bit 24_117
-bit 24_119
bit 24_120
bit 24_122
bit 24_123
@@ -2018,6 +1944,7 @@
bit 24_184
bit 24_189
bit 24_191
+bit 24_192
bit 24_194
bit 24_195
bit 24_196
@@ -2062,8 +1989,8 @@
bit 24_295
bit 24_296
bit 24_304
+bit 25_15
bit 25_23
-bit 25_32
bit 25_39
bit 25_40
bit 25_48
@@ -2124,6 +2051,8 @@
bit 25_182
bit 25_184
bit 25_188
+bit 25_192
+bit 25_207
bit 25_215
bit 25_232
bit 25_240
diff --git a/zynq7/mask_bram_r.db b/zynq7/mask_bram_r.db
index 945e1ef..b85f315 100644
--- a/zynq7/mask_bram_r.db
+++ b/zynq7/mask_bram_r.db
@@ -1,69 +1,24 @@
-bit 00_11
-bit 00_22
bit 00_25
bit 00_26
bit 00_27
-bit 00_29
bit 00_30
-bit 00_33
-bit 00_34
-bit 00_37
-bit 00_38
-bit 00_39
-bit 00_41
bit 00_42
-bit 00_75
-bit 00_78
-bit 00_81
-bit 00_83
-bit 00_86
bit 00_89
bit 00_90
bit 00_91
-bit 00_93
bit 00_94
-bit 00_97
-bit 00_98
-bit 00_99
-bit 00_101
-bit 00_102
-bit 00_103
-bit 00_105
bit 00_106
bit 00_139
bit 00_145
-bit 00_203
-bit 00_214
bit 00_217
bit 00_218
bit 00_219
-bit 00_221
bit 00_222
-bit 00_225
-bit 00_226
-bit 00_227
-bit 00_229
-bit 00_230
-bit 00_231
-bit 00_233
bit 00_234
-bit 00_266
-bit 00_267
-bit 00_270
-bit 00_273
-bit 00_275
-bit 00_278
bit 00_281
bit 00_282
bit 00_283
-bit 00_285
bit 00_286
-bit 00_289
-bit 00_290
-bit 00_291
-bit 00_293
-bit 00_295
-bit 00_297
bit 00_298
bit 01_09
bit 01_10
@@ -77,14 +32,12 @@
bit 01_32
bit 01_33
bit 01_34
-bit 01_36
bit 01_37
bit 01_38
bit 01_40
bit 01_41
bit 01_73
bit 01_74
-bit 01_77
bit 01_78
bit 01_84
bit 01_85
@@ -93,6 +46,7 @@
bit 01_90
bit 01_93
bit 01_96
+bit 01_97
bit 01_98
bit 01_100
bit 01_101
@@ -111,7 +65,6 @@
bit 01_218
bit 01_221
bit 01_224
-bit 01_225
bit 01_226
bit 01_228
bit 01_229
@@ -122,6 +75,7 @@
bit 01_266
bit 01_269
bit 01_270
+bit 01_276
bit 01_277
bit 01_280
bit 01_281
@@ -135,35 +89,30 @@
bit 01_294
bit 01_296
bit 01_297
-bit 02_46
+bit 02_37
bit 02_54
-bit 02_101
+bit 02_86
+bit 02_109
bit 02_110
-bit 02_174
-bit 02_238
bit 02_251
bit 02_253
-bit 02_278
bit 02_302
-bit 03_21
+bit 02_303
bit 03_54
-bit 03_97
-bit 03_101
+bit 03_110
bit 03_198
bit 03_214
bit 03_230
+bit 03_244
bit 03_250
bit 03_252
-bit 04_108
bit 04_111
-bit 04_156
+bit 04_246
bit 04_254
-bit 04_279
-bit 04_280
-bit 04_283
-bit 05_20
-bit 05_23
-bit 05_96
+bit 05_39
+bit 05_86
+bit 05_110
+bit 05_111
bit 05_198
bit 05_214
bit 05_230
@@ -171,10 +120,11 @@
bit 06_03
bit 06_05
bit 06_11
-bit 06_17
+bit 06_15
bit 06_19
-bit 06_20
+bit 06_21
bit 06_27
+bit 06_29
bit 06_33
bit 06_35
bit 06_37
@@ -185,34 +135,32 @@
bit 06_65
bit 06_67
bit 06_69
-bit 06_77
+bit 06_73
+bit 06_81
bit 06_83
bit 06_85
-bit 06_89
-bit 06_93
bit 06_99
bit 06_101
+bit 06_107
bit 06_115
bit 06_117
bit 06_125
bit 06_133
+bit 06_137
bit 06_147
bit 06_149
+bit 06_157
bit 06_163
-bit 06_171
-bit 06_179
-bit 06_181
-bit 06_187
bit 06_211
-bit 06_217
+bit 06_213
bit 06_219
bit 06_227
bit 06_243
bit 06_259
-bit 06_261
+bit 06_265
bit 06_275
+bit 06_277
bit 06_283
-bit 06_285
bit 06_291
bit 06_293
bit 06_299
@@ -227,40 +175,36 @@
bit 07_12
bit 07_14
bit 07_16
+bit 07_18
bit 07_22
-bit 07_24
bit 07_26
bit 07_28
bit 07_30
bit 07_32
bit 07_34
-bit 07_36
bit 07_38
bit 07_42
bit 07_46
-bit 07_47
bit 07_48
bit 07_52
bit 07_54
+bit 07_56
bit 07_58
bit 07_62
bit 07_64
-bit 07_66
bit 07_70
bit 07_72
bit 07_74
-bit 07_76
bit 07_78
bit 07_80
bit 07_82
+bit 07_84
bit 07_86
+bit 07_87
bit 07_88
bit 07_94
bit 07_96
bit 07_102
-bit 07_104
-bit 07_110
-bit 07_111
bit 07_112
bit 07_118
bit 07_120
@@ -273,30 +217,28 @@
bit 07_144
bit 07_150
bit 07_158
-bit 07_159
bit 07_160
bit 07_164
bit 07_166
bit 07_168
bit 07_174
-bit 07_175
bit 07_176
+bit 07_178
+bit 07_180
bit 07_182
bit 07_184
-bit 07_186
bit 07_190
bit 07_192
bit 07_200
bit 07_202
bit 07_206
bit 07_208
-bit 07_216
bit 07_218
bit 07_222
+bit 07_224
bit 07_230
bit 07_234
bit 07_238
-bit 07_239
bit 07_244
bit 07_246
bit 07_250
@@ -312,20 +254,20 @@
bit 07_288
bit 07_294
bit 07_298
-bit 07_303
-bit 07_304
bit 07_314
bit 07_318
bit 08_00
-bit 08_04
-bit 08_05
+bit 08_03
bit 08_06
bit 08_07
bit 08_08
+bit 08_10
bit 08_11
bit 08_12
+bit 08_15
bit 08_16
bit 08_17
+bit 08_18
bit 08_19
bit 08_20
bit 08_21
@@ -333,7 +275,6 @@
bit 08_23
bit 08_25
bit 08_26
-bit 08_27
bit 08_28
bit 08_29
bit 08_32
@@ -342,7 +283,6 @@
bit 08_37
bit 08_38
bit 08_39
-bit 08_42
bit 08_45
bit 08_48
bit 08_49
@@ -352,34 +292,37 @@
bit 08_53
bit 08_54
bit 08_55
+bit 08_56
+bit 08_58
bit 08_60
bit 08_61
bit 08_62
bit 08_64
bit 08_65
-bit 08_66
bit 08_67
+bit 08_69
bit 08_70
bit 08_71
-bit 08_77
+bit 08_73
+bit 08_75
bit 08_78
bit 08_79
bit 08_80
bit 08_81
-bit 08_84
+bit 08_82
+bit 08_83
bit 08_85
bit 08_86
bit 08_87
bit 08_90
+bit 08_93
bit 08_94
bit 08_96
bit 08_97
-bit 08_99
bit 08_100
bit 08_101
bit 08_102
bit 08_103
-bit 08_105
bit 08_106
bit 08_110
bit 08_112
@@ -388,51 +331,45 @@
bit 08_117
bit 08_118
bit 08_119
-bit 08_121
-bit 08_125
bit 08_126
bit 08_127
bit 08_128
bit 08_129
-bit 08_131
-bit 08_132
bit 08_133
bit 08_134
bit 08_135
bit 08_136
bit 08_137
-bit 08_138
bit 08_142
bit 08_143
bit 08_144
bit 08_145
+bit 08_148
bit 08_150
bit 08_151
bit 08_152
bit 08_158
+bit 08_159
bit 08_160
bit 08_161
bit 08_165
bit 08_166
bit 08_167
bit 08_168
-bit 08_174
+bit 08_175
bit 08_176
bit 08_177
-bit 08_180
bit 08_182
bit 08_184
bit 08_190
bit 08_191
bit 08_192
bit 08_193
-bit 08_197
bit 08_200
bit 08_206
bit 08_207
bit 08_213
bit 08_216
-bit 08_217
bit 08_222
bit 08_223
bit 08_224
@@ -448,84 +385,92 @@
bit 08_255
bit 08_264
bit 08_265
-bit 08_267
bit 08_270
bit 08_271
-bit 08_272
bit 08_276
bit 08_280
bit 08_282
+bit 08_283
bit 08_286
bit 08_288
bit 08_292
bit 08_293
bit 08_294
-bit 08_295
bit 08_296
+bit 08_298
bit 08_304
bit 08_307
bit 08_308
bit 08_309
bit 08_311
bit 08_312
+bit 08_314
+bit 08_315
bit 09_00
bit 09_02
bit 09_03
bit 09_04
+bit 09_05
bit 09_06
bit 09_08
bit 09_10
bit 09_11
bit 09_14
bit 09_16
-bit 09_17
bit 09_18
bit 09_19
+bit 09_21
+bit 09_23
+bit 09_30
bit 09_32
+bit 09_33
bit 09_34
bit 09_35
bit 09_36
bit 09_37
bit 09_39
bit 09_40
-bit 09_42
bit 09_48
bit 09_49
bit 09_50
bit 09_51
-bit 09_53
bit 09_56
bit 09_59
bit 09_61
+bit 09_62
bit 09_65
bit 09_66
bit 09_67
bit 09_68
-bit 09_71
bit 09_72
bit 09_76
+bit 09_77
bit 09_78
bit 09_80
+bit 09_81
bit 09_82
bit 09_83
-bit 09_92
+bit 09_84
+bit 09_93
+bit 09_94
+bit 09_95
bit 09_96
bit 09_98
bit 09_99
-bit 09_104
-bit 09_107
-bit 09_109
+bit 09_103
+bit 09_106
bit 09_112
+bit 09_113
bit 09_114
bit 09_115
bit 09_120
bit 09_121
-bit 09_124
-bit 09_125
bit 09_130
-bit 09_140
+bit 09_133
bit 09_141
bit 09_148
+bit 09_156
+bit 09_157
bit 09_160
bit 09_176
bit 09_182
@@ -534,22 +479,21 @@
bit 09_188
bit 09_203
bit 09_223
-bit 09_237
+bit 09_224
bit 09_248
bit 09_250
bit 09_252
bit 09_260
-bit 09_264
-bit 09_265
+bit 09_261
bit 09_269
bit 09_272
bit 09_274
-bit 09_285
+bit 09_278
bit 09_290
bit 09_296
-bit 09_304
bit 09_306
bit 09_307
+bit 09_312
bit 10_01
bit 10_02
bit 10_03
@@ -558,87 +502,87 @@
bit 10_07
bit 10_11
bit 10_13
+bit 10_15
bit 10_16
bit 10_17
bit 10_18
-bit 10_19
-bit 10_20
bit 10_23
-bit 10_29
bit 10_32
bit 10_33
bit 10_34
-bit 10_35
+bit 10_36
+bit 10_37
bit 10_39
bit 10_42
+bit 10_45
+bit 10_46
bit 10_48
bit 10_49
bit 10_50
bit 10_52
bit 10_53
+bit 10_54
bit 10_55
bit 10_59
-bit 10_60
bit 10_64
bit 10_65
bit 10_66
+bit 10_67
bit 10_68
bit 10_69
-bit 10_73
+bit 10_74
bit 10_75
-bit 10_76
+bit 10_77
bit 10_79
+bit 10_80
bit 10_81
bit 10_82
-bit 10_88
+bit 10_84
bit 10_96
bit 10_97
bit 10_98
bit 10_112
bit 10_113
bit 10_114
-bit 10_123
bit 10_124
bit 10_127
bit 10_128
bit 10_129
bit 10_130
-bit 10_131
-bit 10_132
+bit 10_134
bit 10_145
-bit 10_146
bit 10_148
-bit 10_156
+bit 10_151
bit 10_161
+bit 10_162
+bit 10_163
+bit 10_165
bit 10_177
bit 10_179
bit 10_181
bit 10_185
-bit 10_191
+bit 10_187
bit 10_193
bit 10_194
-bit 10_196
+bit 10_208
bit 10_210
bit 10_226
bit 10_233
bit 10_242
bit 10_245
-bit 10_251
bit 10_255
-bit 10_257
bit 10_258
-bit 10_267
+bit 10_260
bit 10_268
bit 10_272
bit 10_274
bit 10_288
bit 10_290
-bit 10_292
bit 10_305
bit 10_306
-bit 10_315
bit 11_00
bit 11_01
+bit 11_02
bit 11_03
bit 11_04
bit 11_06
@@ -646,28 +590,25 @@
bit 11_08
bit 11_10
bit 11_11
+bit 11_12
bit 11_14
bit 11_15
-bit 11_16
bit 11_17
bit 11_18
bit 11_21
bit 11_23
bit 11_27
bit 11_29
-bit 11_31
bit 11_32
bit 11_33
bit 11_34
+bit 11_37
bit 11_39
-bit 11_41
-bit 11_43
-bit 11_45
-bit 11_47
bit 11_48
bit 11_49
bit 11_50
bit 11_52
+bit 11_53
bit 11_55
bit 11_61
bit 11_63
@@ -676,57 +617,56 @@
bit 11_66
bit 11_68
bit 11_71
+bit 11_72
bit 11_74
bit 11_75
bit 11_76
-bit 11_77
bit 11_78
bit 11_79
bit 11_80
bit 11_81
bit 11_82
bit 11_87
-bit 11_91
bit 11_93
bit 11_95
bit 11_96
bit 11_97
bit 11_98
-bit 11_101
bit 11_103
bit 11_111
bit 11_112
bit 11_113
bit 11_119
-bit 11_122
-bit 11_125
+bit 11_121
bit 11_127
bit 11_129
bit 11_135
-bit 11_139
bit 11_143
bit 11_145
-bit 11_148
+bit 11_146
bit 11_151
-bit 11_153
+bit 11_156
bit 11_159
bit 11_161
bit 11_162
+bit 11_163
bit 11_167
bit 11_169
+bit 11_173
bit 11_175
bit 11_177
bit 11_182
+bit 11_184
bit 11_186
bit 11_187
-bit 11_188
bit 11_191
bit 11_193
bit 11_199
+bit 11_206
bit 11_207
+bit 11_209
bit 11_215
bit 11_223
-bit 11_226
bit 11_229
bit 11_239
bit 11_248
@@ -739,57 +679,51 @@
bit 11_272
bit 11_273
bit 11_274
-bit 11_276
+bit 11_277
bit 11_279
-bit 11_282
-bit 11_283
bit 11_285
bit 11_287
+bit 11_293
bit 11_295
bit 11_299
bit 11_303
-bit 11_305
bit 11_311
-bit 11_315
bit 12_02
bit 12_04
+bit 12_06
bit 12_09
bit 12_10
bit 12_16
bit 12_18
-bit 12_19
+bit 12_20
+bit 12_22
bit 12_26
-bit 12_27
+bit 12_28
+bit 12_30
bit 12_32
bit 12_34
bit 12_36
-bit 12_37
-bit 12_38
bit 12_40
bit 12_42
bit 12_48
bit 12_50
bit 12_52
bit 12_60
-bit 12_62
bit 12_64
bit 12_66
bit 12_68
-bit 12_70
+bit 12_72
bit 12_76
bit 12_80
bit 12_82
bit 12_84
-bit 12_88
bit 12_92
-bit 12_93
+bit 12_94
bit 12_96
bit 12_98
bit 12_100
-bit 12_104
-bit 12_105
+bit 12_102
bit 12_106
-bit 12_108
bit 12_112
bit 12_114
bit 12_116
@@ -798,30 +732,28 @@
bit 12_128
bit 12_130
bit 12_132
-bit 12_140
-bit 12_145
+bit 12_136
+bit 12_143
bit 12_146
bit 12_148
+bit 12_149
+bit 12_156
bit 12_160
bit 12_162
-bit 12_170
bit 12_176
-bit 12_178
-bit 12_186
bit 12_193
bit 12_194
-bit 12_196
bit 12_202
bit 12_207
+bit 12_208
bit 12_210
-bit 12_216
+bit 12_212
bit 12_218
+bit 12_224
bit 12_226
-bit 12_236
bit 12_239
bit 12_242
bit 12_255
-bit 12_257
bit 12_258
bit 12_260
bit 12_264
@@ -830,26 +762,24 @@
bit 12_271
bit 12_272
bit 12_274
+bit 12_276
bit 12_277
bit 12_281
bit 12_282
-bit 12_284
bit 12_287
bit 12_288
bit 12_290
bit 12_292
-bit 12_295
bit 12_296
bit 12_297
bit 12_298
-bit 12_304
bit 12_306
bit 12_308
+bit 12_312
bit 12_313
bit 12_314
bit 13_01
bit 13_03
-bit 13_05
bit 13_07
bit 13_09
bit 13_11
@@ -867,34 +797,32 @@
bit 13_37
bit 13_38
bit 13_39
-bit 13_41
-bit 13_43
bit 13_45
-bit 13_47
+bit 13_46
bit 13_49
bit 13_51
bit 13_53
bit 13_55
+bit 13_57
+bit 13_59
bit 13_61
bit 13_63
bit 13_65
+bit 13_69
bit 13_71
bit 13_75
-bit 13_77
bit 13_79
bit 13_81
+bit 13_83
bit 13_85
bit 13_87
bit 13_89
bit 13_91
-bit 13_92
bit 13_93
bit 13_95
bit 13_97
-bit 13_99
bit 13_101
bit 13_103
-bit 13_105
bit 13_107
bit 13_111
bit 13_113
@@ -907,25 +835,25 @@
bit 13_133
bit 13_135
bit 13_137
-bit 13_139
bit 13_143
bit 13_145
-bit 13_146
bit 13_151
bit 13_153
-bit 13_156
bit 13_159
bit 13_161
+bit 13_163
bit 13_165
bit 13_167
bit 13_169
bit 13_175
bit 13_177
+bit 13_179
bit 13_183
bit 13_187
bit 13_191
bit 13_193
bit 13_201
+bit 13_206
bit 13_207
bit 13_209
bit 13_213
@@ -939,6 +867,7 @@
bit 13_239
bit 13_241
bit 13_247
+bit 13_249
bit 13_255
bit 13_257
bit 13_263
@@ -948,10 +877,11 @@
bit 13_271
bit 13_272
bit 13_273
-bit 13_276
+bit 13_277
bit 13_279
bit 13_281
bit 13_283
+bit 13_285
bit 13_287
bit 13_289
bit 13_293
@@ -970,96 +900,96 @@
bit 14_03
bit 14_04
bit 14_05
+bit 14_07
bit 14_10
bit 14_11
bit 14_13
+bit 14_14
bit 14_15
bit 14_16
bit 14_18
-bit 14_20
bit 14_32
bit 14_34
bit 14_36
bit 14_48
bit 14_50
bit 14_52
+bit 14_54
bit 14_56
bit 14_58
+bit 14_62
bit 14_64
bit 14_66
bit 14_67
bit 14_68
bit 14_69
bit 14_73
+bit 14_74
bit 14_75
+bit 14_76
bit 14_77
bit 14_79
bit 14_80
bit 14_82
+bit 14_84
+bit 14_94
bit 14_96
bit 14_98
bit 14_112
bit 14_114
bit 14_120
-bit 14_122
bit 14_124
bit 14_130
bit 14_132
+bit 14_134
bit 14_140
bit 14_146
bit 14_148
bit 14_156
bit 14_162
bit 14_176
-bit 14_180
+bit 14_179
bit 14_181
bit 14_185
bit 14_187
-bit 14_191
bit 14_222
-bit 14_226
bit 14_245
bit 14_251
bit 14_255
bit 14_258
-bit 14_260
-bit 14_264
-bit 14_268
bit 14_274
-bit 14_282
-bit 14_284
-bit 14_288
+bit 14_278
bit 14_290
bit 14_306
bit 15_00
bit 15_01
+bit 15_02
bit 15_03
bit 15_04
-bit 15_05
bit 15_06
bit 15_07
bit 15_08
bit 15_10
bit 15_11
+bit 15_12
bit 15_14
bit 15_15
bit 15_17
-bit 15_21
+bit 15_19
bit 15_23
bit 15_27
bit 15_29
bit 15_31
bit 15_33
-bit 15_35
bit 15_37
bit 15_39
bit 15_43
bit 15_45
bit 15_47
bit 15_49
-bit 15_51
bit 15_53
bit 15_55
+bit 15_57
bit 15_59
bit 15_61
bit 15_63
@@ -1069,6 +999,7 @@
bit 15_68
bit 15_71
bit 15_72
+bit 15_73
bit 15_74
bit 15_75
bit 15_76
@@ -1076,24 +1007,17 @@
bit 15_79
bit 15_81
bit 15_83
-bit 15_85
bit 15_87
bit 15_93
bit 15_95
bit 15_97
-bit 15_99
bit 15_103
-bit 15_111
bit 15_113
bit 15_117
bit 15_119
bit 15_121
-bit 15_123
-bit 15_125
bit 15_127
bit 15_129
-bit 15_131
-bit 15_133
bit 15_135
bit 15_137
bit 15_143
@@ -1102,13 +1026,14 @@
bit 15_153
bit 15_159
bit 15_161
+bit 15_163
bit 15_165
bit 15_167
bit 15_169
+bit 15_173
bit 15_175
bit 15_177
bit 15_179
-bit 15_181
bit 15_182
bit 15_183
bit 15_184
@@ -1117,14 +1042,15 @@
bit 15_188
bit 15_191
bit 15_193
-bit 15_197
bit 15_199
bit 15_201
bit 15_203
bit 15_207
+bit 15_209
bit 15_217
bit 15_219
bit 15_223
+bit 15_225
bit 15_229
bit 15_231
bit 15_233
@@ -1137,22 +1063,19 @@
bit 15_251
bit 15_252
bit 15_255
-bit 15_263
bit 15_267
bit 15_271
-bit 15_273
bit 15_281
bit 15_283
-bit 15_285
bit 15_287
bit 15_289
+bit 15_293
bit 15_295
bit 15_297
bit 15_299
bit 15_305
bit 15_309
bit 15_315
-bit 15_319
bit 16_23
bit 16_40
bit 16_48
@@ -1196,7 +1119,6 @@
bit 16_115
bit 16_116
bit 16_117
-bit 16_119
bit 16_120
bit 16_122
bit 16_123
@@ -1269,7 +1191,6 @@
bit 16_211
bit 16_212
bit 16_213
-bit 16_215
bit 16_216
bit 16_218
bit 16_219
@@ -1291,25 +1212,23 @@
bit 16_244
bit 16_245
bit 16_248
-bit 16_271
bit 16_279
bit 16_296
-bit 16_304
+bit 17_15
bit 17_23
bit 17_40
-bit 17_48
bit 17_55
bit 17_66
bit 17_67
bit 17_68
bit 17_69
bit 17_71
-bit 17_80
bit 17_82
bit 17_83
bit 17_84
bit 17_85
bit 17_87
+bit 17_96
bit 17_104
bit 17_112
bit 17_119
@@ -1340,13 +1259,16 @@
bit 17_175
bit 17_184
bit 17_232
+bit 17_240
+bit 17_271
bit 17_279
bit 17_296
bit 17_304
+bit 18_14
bit 18_22
+bit 18_33
bit 18_38
bit 18_41
-bit 18_49
bit 18_54
bit 18_62
bit 18_66
@@ -1369,7 +1291,6 @@
bit 18_92
bit 18_93
bit 18_94
-bit 18_97
bit 18_98
bit 18_99
bit 18_100
@@ -1465,7 +1386,6 @@
bit 18_228
bit 18_229
bit 18_230
-bit 18_233
bit 18_234
bit 18_235
bit 18_236
@@ -1475,12 +1395,14 @@
bit 18_243
bit 18_244
bit 18_245
+bit 18_270
+bit 18_278
bit 18_294
bit 18_297
bit 19_22
-bit 19_33
bit 19_41
bit 19_49
+bit 19_54
bit 19_62
bit 19_66
bit 19_67
@@ -1496,6 +1418,7 @@
bit 19_83
bit 19_84
bit 19_85
+bit 19_86
bit 19_90
bit 19_91
bit 19_92
@@ -1521,7 +1444,6 @@
bit 19_123
bit 19_124
bit 19_125
-bit 19_129
bit 19_130
bit 19_131
bit 19_132
@@ -1570,6 +1492,7 @@
bit 19_183
bit 19_185
bit 19_190
+bit 19_193
bit 19_194
bit 19_195
bit 19_196
@@ -1579,6 +1502,7 @@
bit 19_203
bit 19_204
bit 19_205
+bit 19_206
bit 19_210
bit 19_211
bit 19_212
@@ -1729,10 +1653,8 @@
bit 21_243
bit 21_245
bit 22_23
-bit 22_32
bit 22_40
bit 22_47
-bit 22_48
bit 22_55
bit 22_63
bit 22_66
@@ -1853,13 +1775,16 @@
bit 22_235
bit 22_236
bit 22_237
+bit 22_240
bit 22_242
bit 22_243
bit 22_244
bit 22_245
bit 22_248
bit 22_271
+bit 22_279
bit 22_296
+bit 23_15
bit 23_23
bit 23_39
bit 23_40
@@ -1879,7 +1804,6 @@
bit 23_96
bit 23_104
bit 23_112
-bit 23_119
bit 23_127
bit 23_135
bit 23_143
@@ -1897,6 +1821,7 @@
bit 23_158
bit 23_159
bit 23_161
+bit 23_167
bit 23_168
bit 23_169
bit 23_170
@@ -1906,12 +1831,14 @@
bit 23_174
bit 23_175
bit 23_184
-bit 23_215
+bit 23_192
bit 23_232
bit 23_240
+bit 23_271
bit 23_279
bit 23_295
bit 23_304
+bit 24_15
bit 24_23
bit 24_32
bit 24_39
@@ -1958,7 +1885,6 @@
bit 24_115
bit 24_116
bit 24_117
-bit 24_119
bit 24_120
bit 24_122
bit 24_123
@@ -2018,6 +1944,7 @@
bit 24_184
bit 24_189
bit 24_191
+bit 24_192
bit 24_194
bit 24_195
bit 24_196
@@ -2062,8 +1989,8 @@
bit 24_295
bit 24_296
bit 24_304
+bit 25_15
bit 25_23
-bit 25_32
bit 25_39
bit 25_40
bit 25_48
@@ -2124,6 +2051,8 @@
bit 25_182
bit 25_184
bit 25_188
+bit 25_192
+bit 25_207
bit 25_215
bit 25_232
bit 25_240
diff --git a/zynq7/mask_dsp_l.db b/zynq7/mask_dsp_l.db
index 4c75939..cabf394 100644
--- a/zynq7/mask_dsp_l.db
+++ b/zynq7/mask_dsp_l.db
@@ -1,4 +1,3 @@
-bit 00_11
bit 00_42
bit 00_78
bit 00_81
@@ -18,10 +17,10 @@
bit 00_214
bit 00_217
bit 00_234
+bit 00_266
bit 00_267
bit 00_273
bit 00_295
-bit 01_09
bit 01_10
bit 01_14
bit 01_32
@@ -54,16 +53,12 @@
bit 01_288
bit 01_293
bit 01_297
-bit 02_02
bit 02_03
bit 02_06
bit 02_07
bit 02_14
-bit 02_22
+bit 02_15
bit 02_30
-bit 02_31
-bit 02_38
-bit 02_39
bit 02_46
bit 02_47
bit 02_54
@@ -71,13 +66,15 @@
bit 02_63
bit 02_70
bit 02_71
+bit 02_74
bit 02_78
-bit 02_79
-bit 02_86
-bit 02_87
bit 02_94
bit 02_95
-bit 02_102
+bit 02_110
+bit 02_111
+bit 02_118
+bit 02_119
+bit 02_126
bit 02_134
bit 02_135
bit 02_142
@@ -85,312 +82,302 @@
bit 02_150
bit 02_151
bit 02_158
-bit 02_159
+bit 02_166
+bit 02_167
+bit 02_174
bit 02_182
bit 02_198
-bit 02_199
-bit 02_203
bit 02_205
bit 02_206
bit 02_207
-bit 02_214
+bit 02_222
bit 02_230
bit 02_231
bit 02_238
bit 02_239
-bit 02_243
+bit 02_242
bit 02_246
bit 02_247
-bit 02_253
bit 02_254
bit 02_255
bit 02_261
bit 02_262
bit 02_263
bit 02_266
-bit 02_267
bit 02_269
bit 02_270
bit 02_271
-bit 02_278
+bit 02_273
bit 02_286
bit 02_287
-bit 02_294
bit 02_302
bit 02_303
bit 02_310
bit 02_311
bit 02_318
bit 02_319
-bit 03_02
bit 03_06
+bit 03_13
bit 03_14
-bit 03_22
+bit 03_46
bit 03_64
-bit 03_70
bit 03_94
bit 03_96
-bit 03_110
+bit 03_97
bit 03_112
-bit 03_134
-bit 03_137
-bit 03_142
+bit 03_128
+bit 03_138
bit 03_144
-bit 03_156
-bit 03_158
+bit 03_145
bit 03_160
bit 03_166
+bit 03_176
bit 03_182
+bit 03_189
bit 03_190
+bit 03_198
bit 03_205
bit 03_206
bit 03_208
+bit 03_222
+bit 03_224
+bit 03_228
+bit 03_229
+bit 03_236
+bit 03_237
+bit 03_242
bit 03_246
bit 03_252
bit 03_253
bit 03_254
-bit 03_257
bit 03_260
bit 03_261
bit 03_262
-bit 03_268
+bit 03_266
bit 03_269
bit 03_270
bit 03_286
bit 03_288
+bit 03_289
+bit 03_304
+bit 03_318
+bit 04_04
bit 04_12
-bit 04_17
+bit 04_15
bit 04_33
-bit 04_60
-bit 04_108
-bit 04_113
-bit 04_140
+bit 04_44
+bit 04_79
+bit 04_129
bit 04_145
-bit 04_156
-bit 04_157
-bit 04_161
-bit 04_164
+bit 04_177
bit 04_180
bit 04_183
bit 04_188
+bit 04_193
bit 04_204
+bit 04_205
bit 04_209
-bit 04_225
+bit 04_229
bit 04_236
-bit 04_244
bit 04_252
+bit 04_257
+bit 04_260
bit 04_261
bit 04_268
bit 04_269
+bit 04_271
+bit 04_273
bit 04_284
bit 04_305
bit 05_02
-bit 05_34
+bit 05_03
+bit 05_14
+bit 05_26
bit 05_67
-bit 05_70
bit 05_99
bit 05_115
-bit 05_130
-bit 05_134
-bit 05_136
-bit 05_147
+bit 05_138
+bit 05_144
bit 05_150
bit 05_163
-bit 05_171
-bit 05_195
-bit 05_202
-bit 05_230
+bit 05_210
+bit 05_211
+bit 05_227
+bit 05_231
bit 05_242
bit 05_243
bit 05_246
-bit 05_256
-bit 05_262
-bit 05_266
-bit 05_271
-bit 05_290
+bit 05_254
+bit 05_270
+bit 05_282
+bit 05_286
+bit 05_288
bit 05_291
-bit 05_306
bit 05_307
-bit 06_01
+bit 05_318
+bit 06_00
+bit 06_07
bit 06_11
-bit 06_16
-bit 06_31
+bit 06_12
+bit 06_15
bit 06_32
-bit 06_37
bit 06_43
bit 06_59
bit 06_75
bit 06_77
bit 06_85
-bit 06_91
+bit 06_96
+bit 06_99
bit 06_101
-bit 06_107
bit 06_125
bit 06_133
-bit 06_139
-bit 06_144
-bit 06_145
bit 06_149
bit 06_163
-bit 06_165
-bit 06_168
bit 06_171
+bit 06_176
bit 06_177
bit 06_181
-bit 06_187
+bit 06_188
bit 06_192
-bit 06_203
-bit 06_207
+bit 06_204
+bit 06_205
bit 06_208
bit 06_224
-bit 06_227
bit 06_233
bit 06_240
-bit 06_245
+bit 06_243
+bit 06_249
bit 06_253
-bit 06_257
+bit 06_255
+bit 06_256
bit 06_259
bit 06_265
-bit 06_267
+bit 06_268
bit 06_269
+bit 06_272
bit 06_275
-bit 06_277
bit 06_283
-bit 06_285
bit 06_287
-bit 06_291
+bit 06_288
+bit 06_297
bit 06_299
-bit 06_301
bit 06_304
bit 06_315
bit 07_00
bit 07_06
bit 07_08
+bit 07_10
bit 07_15
-bit 07_23
bit 07_24
-bit 07_35
-bit 07_39
+bit 07_27
+bit 07_31
+bit 07_38
bit 07_40
+bit 07_47
bit 07_48
bit 07_55
bit 07_56
bit 07_64
bit 07_71
bit 07_72
-bit 07_74
+bit 07_75
bit 07_79
bit 07_80
-bit 07_87
-bit 07_88
-bit 07_102
-bit 07_103
-bit 07_106
+bit 07_95
+bit 07_111
bit 07_118
bit 07_120
+bit 07_127
bit 07_128
-bit 07_131
bit 07_135
bit 07_136
+bit 07_138
bit 07_143
-bit 07_151
+bit 07_150
bit 07_154
-bit 07_156
+bit 07_158
+bit 07_159
bit 07_160
bit 07_166
bit 07_168
-bit 07_176
+bit 07_175
bit 07_178
bit 07_184
+bit 07_186
+bit 07_192
bit 07_198
-bit 07_199
bit 07_200
bit 07_207
-bit 07_214
-bit 07_215
+bit 07_211
bit 07_216
+bit 07_223
bit 07_224
-bit 07_231
bit 07_232
bit 07_236
bit 07_238
bit 07_239
bit 07_240
+bit 07_243
bit 07_248
bit 07_256
bit 07_262
-bit 07_263
bit 07_264
-bit 07_266
-bit 07_267
bit 07_270
bit 07_271
-bit 07_274
-bit 07_279
bit 07_280
-bit 07_291
+bit 07_283
+bit 07_286
bit 07_294
-bit 07_295
bit 07_296
-bit 07_298
bit 07_303
-bit 07_304
-bit 07_307
-bit 07_310
bit 07_312
-bit 07_314
-bit 07_319
+bit 07_318
bit 08_01
-bit 08_06
bit 08_08
bit 08_09
-bit 08_10
+bit 08_11
bit 08_14
bit 08_15
-bit 08_17
-bit 08_22
-bit 08_23
bit 08_30
bit 08_38
+bit 08_39
+bit 08_46
bit 08_54
-bit 08_57
bit 08_62
+bit 08_63
+bit 08_65
bit 08_70
-bit 08_71
bit 08_72
bit 08_73
+bit 08_75
bit 08_86
bit 08_87
+bit 08_89
bit 08_94
-bit 08_96
+bit 08_95
+bit 08_97
+bit 08_100
bit 08_102
-bit 08_113
+bit 08_105
bit 08_118
bit 08_119
bit 08_126
bit 08_129
bit 08_134
+bit 08_135
bit 08_142
bit 08_144
-bit 08_145
bit 08_150
-bit 08_160
-bit 08_161
+bit 08_164
bit 08_166
-bit 08_167
-bit 08_168
-bit 08_175
bit 08_176
-bit 08_177
+bit 08_182
bit 08_183
-bit 08_184
bit 08_190
bit 08_191
-bit 08_192
bit 08_193
bit 08_198
bit 08_199
-bit 08_201
bit 08_205
bit 08_206
bit 08_207
@@ -398,61 +385,60 @@
bit 08_209
bit 08_214
bit 08_215
-bit 08_216
-bit 08_217
bit 08_222
bit 08_223
+bit 08_225
bit 08_230
bit 08_231
+bit 08_232
bit 08_233
bit 08_238
bit 08_241
-bit 08_248
+bit 08_246
bit 08_249
bit 08_256
bit 08_262
bit 08_263
-bit 08_265
+bit 08_264
bit 08_270
bit 08_271
-bit 08_272
bit 08_273
+bit 08_275
+bit 08_279
bit 08_281
bit 08_286
-bit 08_289
bit 08_294
bit 08_296
bit 08_297
bit 08_302
bit 08_310
bit 08_311
+bit 08_312
+bit 08_313
bit 08_318
-bit 08_319
bit 09_02
bit 09_03
bit 09_04
+bit 09_05
+bit 09_07
+bit 09_09
bit 09_10
-bit 09_18
-bit 09_35
+bit 09_24
bit 09_36
+bit 09_42
bit 09_43
bit 09_50
bit 09_51
-bit 09_56
bit 09_58
-bit 09_66
-bit 09_67
bit 09_72
bit 09_73
bit 09_74
-bit 09_75
-bit 09_76
+bit 09_85
bit 09_88
-bit 09_90
bit 09_91
+bit 09_95
bit 09_99
-bit 09_106
-bit 09_114
+bit 09_107
bit 09_115
bit 09_122
bit 09_130
@@ -463,143 +449,124 @@
bit 09_139
bit 09_147
bit 09_148
+bit 09_152
bit 09_154
bit 09_155
-bit 09_160
+bit 09_161
bit 09_162
bit 09_163
bit 09_170
bit 09_176
-bit 09_177
-bit 09_178
bit 09_179
bit 09_180
+bit 09_181
bit 09_186
bit 09_187
bit 09_191
+bit 09_193
bit 09_195
bit 09_202
-bit 09_204
bit 09_208
bit 09_211
bit 09_218
bit 09_219
+bit 09_226
bit 09_227
bit 09_232
bit 09_233
-bit 09_235
bit 09_242
bit 09_243
-bit 09_251
+bit 09_250
bit 09_258
bit 09_259
bit 09_265
bit 09_266
-bit 09_267
-bit 09_268
bit 09_269
bit 09_274
bit 09_275
+bit 09_281
bit 09_282
-bit 09_283
-bit 09_285
-bit 09_290
bit 09_291
+bit 09_297
bit 09_298
bit 09_306
-bit 09_314
+bit 09_307
+bit 09_310
+bit 09_316
+bit 10_07
+bit 10_08
bit 10_09
+bit 10_10
bit 10_15
-bit 10_55
-bit 10_57
-bit 10_72
+bit 10_18
+bit 10_24
+bit 10_41
+bit 10_71
bit 10_73
bit 10_76
bit 10_90
-bit 10_98
-bit 10_103
-bit 10_106
-bit 10_119
bit 10_121
-bit 10_122
bit 10_130
bit 10_140
+bit 10_142
bit 10_143
-bit 10_151
+bit 10_146
bit 10_154
-bit 10_161
bit 10_162
bit 10_170
bit 10_174
bit 10_177
-bit 10_180
-bit 10_185
+bit 10_178
+bit 10_182
+bit 10_183
bit 10_186
-bit 10_194
-bit 10_202
-bit 10_206
-bit 10_220
+bit 10_200
+bit 10_226
bit 10_231
-bit 10_232
-bit 10_241
+bit 10_238
+bit 10_240
bit 10_249
-bit 10_250
bit 10_252
-bit 10_254
-bit 10_258
-bit 10_263
-bit 10_268
+bit 10_257
+bit 10_265
bit 10_270
bit 10_271
+bit 10_272
bit 10_274
-bit 10_275
bit 10_276
-bit 10_282
bit 10_286
-bit 10_290
-bit 10_291
-bit 10_298
-bit 10_303
-bit 10_312
-bit 10_318
+bit 10_307
+bit 10_313
bit 11_01
bit 11_02
+bit 11_08
bit 11_09
-bit 11_10
-bit 11_17
bit 11_18
bit 11_23
bit 11_25
bit 11_26
-bit 11_31
bit 11_34
-bit 11_39
bit 11_41
bit 11_42
bit 11_47
bit 11_50
bit 11_58
bit 11_63
-bit 11_65
bit 11_66
bit 11_71
bit 11_73
bit 11_74
-bit 11_76
-bit 11_81
bit 11_82
bit 11_87
-bit 11_89
bit 11_90
-bit 11_92
-bit 11_95
bit 11_97
bit 11_98
-bit 11_103
bit 11_105
+bit 11_106
bit 11_113
bit 11_114
bit 11_119
+bit 11_122
bit 11_127
bit 11_129
bit 11_130
@@ -607,22 +574,24 @@
bit 11_137
bit 11_138
bit 11_145
-bit 11_146
+bit 11_151
bit 11_153
bit 11_154
bit 11_161
+bit 11_162
bit 11_167
bit 11_170
bit 11_177
+bit 11_178
bit 11_180
bit 11_183
+bit 11_185
bit 11_186
-bit 11_191
bit 11_193
-bit 11_194
bit 11_199
bit 11_202
bit 11_207
+bit 11_208
bit 11_209
bit 11_215
bit 11_217
@@ -633,26 +602,24 @@
bit 11_231
bit 11_233
bit 11_234
-bit 11_237
+bit 11_235
bit 11_239
bit 11_245
+bit 11_249
bit 11_255
-bit 11_257
bit 11_258
-bit 11_259
bit 11_263
bit 11_264
bit 11_265
bit 11_266
-bit 11_270
bit 11_271
bit 11_273
bit 11_274
-bit 11_279
bit 11_282
bit 11_287
-bit 11_289
bit 11_290
+bit 11_292
+bit 11_297
bit 11_298
bit 11_303
bit 11_306
@@ -660,40 +627,37 @@
bit 11_313
bit 11_314
bit 11_319
-bit 12_00
bit 12_01
bit 12_02
bit 12_04
+bit 12_06
+bit 12_08
bit 12_09
bit 12_10
bit 12_15
-bit 12_17
-bit 12_18
bit 12_23
-bit 12_30
-bit 12_31
-bit 12_34
bit 12_36
bit 12_39
+bit 12_41
bit 12_42
bit 12_47
bit 12_50
+bit 12_55
bit 12_58
bit 12_63
-bit 12_65
-bit 12_66
bit 12_71
bit 12_72
bit 12_73
bit 12_74
bit 12_76
+bit 12_84
bit 12_87
bit 12_88
-bit 12_89
bit 12_90
-bit 12_95
+bit 12_94
bit 12_98
-bit 12_103
+bit 12_101
+bit 12_105
bit 12_106
bit 12_114
bit 12_119
@@ -707,104 +671,108 @@
bit 12_135
bit 12_137
bit 12_138
+bit 12_140
+bit 12_143
bit 12_146
bit 12_148
+bit 12_151
bit 12_154
bit 12_162
-bit 12_164
bit 12_167
-bit 12_169
bit 12_170
-bit 12_176
+bit 12_174
bit 12_178
bit 12_179
bit 12_180
+bit 12_182
bit 12_183
bit 12_186
+bit 12_190
bit 12_191
-bit 12_193
+bit 12_192
bit 12_194
bit 12_199
+bit 12_200
+bit 12_201
bit 12_202
bit 12_205
-bit 12_206
bit 12_207
bit 12_209
bit 12_210
bit 12_215
bit 12_217
bit 12_218
-bit 12_220
-bit 12_223
bit 12_225
bit 12_226
bit 12_231
bit 12_232
bit 12_233
-bit 12_234
bit 12_239
+bit 12_240
bit 12_241
bit 12_242
-bit 12_244
+bit 12_248
bit 12_249
bit 12_250
bit 12_252
bit 12_254
bit 12_255
-bit 12_256
-bit 12_257
bit 12_258
bit 12_263
-bit 12_264
-bit 12_265
bit 12_266
bit 12_271
+bit 12_272
bit 12_274
-bit 12_279
+bit 12_280
bit 12_282
bit 12_286
bit 12_287
bit 12_290
-bit 12_291
+bit 12_296
bit 12_297
bit 12_298
bit 12_303
-bit 12_305
bit 12_306
+bit 12_307
bit 12_311
-bit 12_312
bit 12_313
bit 12_314
+bit 12_316
bit 12_319
bit 13_01
bit 13_02
bit 13_07
+bit 13_08
bit 13_09
-bit 13_10
+bit 13_11
+bit 13_14
bit 13_15
-bit 13_17
+bit 13_18
bit 13_25
bit 13_26
bit 13_39
bit 13_41
bit 13_42
+bit 13_47
bit 13_50
bit 13_58
+bit 13_63
bit 13_65
-bit 13_66
bit 13_71
bit 13_72
bit 13_73
bit 13_74
+bit 13_75
bit 13_76
-bit 13_87
+bit 13_89
+bit 13_95
bit 13_97
bit 13_98
-bit 13_103
bit 13_105
bit 13_106
bit 13_113
bit 13_119
+bit 13_122
bit 13_127
bit 13_129
bit 13_130
@@ -812,20 +780,20 @@
bit 13_135
bit 13_137
bit 13_140
+bit 13_142
bit 13_143
-bit 13_144
bit 13_145
bit 13_146
-bit 13_148
+bit 13_151
+bit 13_152
bit 13_153
-bit 13_155
-bit 13_157
-bit 13_160
+bit 13_159
bit 13_161
+bit 13_165
bit 13_167
+bit 13_169
bit 13_170
bit 13_174
-bit 13_175
bit 13_177
bit 13_178
bit 13_183
@@ -834,10 +802,7 @@
bit 13_190
bit 13_191
bit 13_193
-bit 13_194
bit 13_199
-bit 13_201
-bit 13_202
bit 13_204
bit 13_207
bit 13_208
@@ -847,147 +812,143 @@
bit 13_218
bit 13_223
bit 13_225
+bit 13_226
bit 13_231
bit 13_232
bit 13_233
-bit 13_234
+bit 13_235
bit 13_237
bit 13_239
bit 13_241
+bit 13_242
+bit 13_247
+bit 13_248
bit 13_249
bit 13_257
bit 13_263
bit 13_265
+bit 13_266
bit 13_268
bit 13_270
bit 13_271
bit 13_273
bit 13_274
-bit 13_275
+bit 13_279
bit 13_281
-bit 13_282
-bit 13_284
bit 13_287
-bit 13_289
bit 13_290
bit 13_295
bit 13_297
-bit 13_303
+bit 13_298
bit 13_306
+bit 13_310
bit 13_311
bit 13_313
bit 13_314
-bit 13_318
bit 13_319
-bit 14_02
-bit 14_04
+bit 14_06
+bit 14_10
bit 14_18
+bit 14_24
bit 14_34
-bit 14_36
bit 14_42
-bit 14_56
+bit 14_50
bit 14_58
bit 14_66
-bit 14_72
bit 14_74
-bit 14_76
bit 14_82
bit 14_84
bit 14_90
-bit 14_92
bit 14_98
bit 14_100
-bit 14_106
bit 14_114
+bit 14_122
bit 14_130
bit 14_136
bit 14_138
bit 14_146
bit 14_148
bit 14_154
+bit 14_160
bit 14_162
bit 14_170
bit 14_176
+bit 14_178
bit 14_180
bit 14_186
-bit 14_190
-bit 14_194
+bit 14_202
+bit 14_204
bit 14_218
bit 14_226
bit 14_232
bit 14_234
+bit 14_238
bit 14_242
bit 14_252
bit 14_258
bit 14_264
bit 14_266
bit 14_268
-bit 14_270
bit 14_274
bit 14_276
bit 14_282
-bit 14_284
bit 14_286
bit 14_290
+bit 14_292
+bit 14_296
bit 14_298
-bit 14_300
+bit 14_306
bit 14_314
-bit 15_01
bit 15_07
bit 15_09
-bit 15_11
bit 15_15
-bit 15_23
bit 15_25
bit 15_31
+bit 15_39
bit 15_41
+bit 15_47
bit 15_49
-bit 15_55
bit 15_57
-bit 15_63
bit 15_65
bit 15_71
bit 15_73
-bit 15_75
bit 15_81
bit 15_87
-bit 15_89
+bit 15_95
bit 15_103
-bit 15_105
-bit 15_107
bit 15_119
bit 15_121
-bit 15_127
bit 15_129
+bit 15_135
bit 15_137
+bit 15_139
bit 15_143
bit 15_145
bit 15_151
-bit 15_161
+bit 15_155
bit 15_167
bit 15_169
bit 15_177
bit 15_183
bit 15_185
+bit 15_187
+bit 15_191
+bit 15_193
bit 15_199
bit 15_201
-bit 15_207
bit 15_209
bit 15_215
-bit 15_217
bit 15_223
bit 15_225
+bit 15_231
bit 15_233
-bit 15_237
bit 15_239
bit 15_241
bit 15_245
bit 15_249
bit 15_257
-bit 15_259
bit 15_263
bit 15_265
-bit 15_267
bit 15_271
bit 15_273
bit 15_275
@@ -995,10 +956,9 @@
bit 15_287
bit 15_295
bit 15_297
-bit 15_299
bit 15_303
bit 15_311
-bit 15_315
+bit 15_313
bit 15_319
bit 16_00
bit 16_07
@@ -1028,6 +988,7 @@
bit 16_240
bit 16_247
bit 16_250
+bit 16_251
bit 16_256
bit 16_257
bit 16_258
@@ -1037,12 +998,10 @@
bit 16_264
bit 16_266
bit 16_267
-bit 16_271
bit 16_272
bit 16_279
bit 16_280
bit 16_288
-bit 16_296
bit 17_00
bit 17_07
bit 17_96
@@ -1060,11 +1019,10 @@
bit 17_181
bit 17_183
bit 17_207
-bit 17_208
bit 17_228
bit 17_229
-bit 17_231
bit 17_234
+bit 17_240
bit 17_247
bit 17_248
bit 17_250
@@ -1080,34 +1038,31 @@
bit 17_267
bit 17_272
bit 17_279
-bit 17_280
bit 17_288
-bit 17_295
bit 17_296
+bit 17_312
bit 18_01
bit 18_06
-bit 18_25
+bit 18_17
bit 18_97
bit 18_102
-bit 18_105
bit 18_145
bit 18_150
bit 18_156
bit 18_157
-bit 18_161
bit 18_162
bit 18_163
bit 18_169
+bit 18_177
bit 18_180
bit 18_181
bit 18_182
-bit 18_185
bit 18_193
bit 18_198
-bit 18_206
bit 18_222
bit 18_228
bit 18_229
+bit 18_230
bit 18_234
bit 18_235
bit 18_238
@@ -1115,6 +1070,7 @@
bit 18_246
bit 18_249
bit 18_250
+bit 18_251
bit 18_256
bit 18_257
bit 18_258
@@ -1126,9 +1082,7 @@
bit 18_267
bit 18_273
bit 18_278
-bit 18_281
bit 18_289
-bit 18_297
bit 19_01
bit 19_06
bit 19_09
@@ -1136,7 +1090,6 @@
bit 19_94
bit 19_97
bit 19_102
-bit 19_134
bit 19_145
bit 19_150
bit 19_156
@@ -1146,11 +1099,11 @@
bit 19_163
bit 19_166
bit 19_169
-bit 19_177
bit 19_180
bit 19_181
bit 19_182
bit 19_185
+bit 19_193
bit 19_206
bit 19_222
bit 19_228
@@ -1172,26 +1125,29 @@
bit 19_265
bit 19_266
bit 19_267
+bit 19_270
bit 19_273
bit 19_278
bit 19_281
bit 19_289
-bit 19_297
bit 20_00
bit 20_96
bit 20_103
+bit 20_144
bit 20_156
-bit 20_160
-bit 20_163
bit 20_176
bit 20_180
+bit 20_181
bit 20_183
+bit 20_228
bit 20_234
bit 20_256
bit 20_257
+bit 20_259
bit 20_262
bit 20_266
bit 20_267
+bit 20_288
bit 20_293
bit 21_00
bit 21_07
@@ -1199,10 +1155,10 @@
bit 21_103
bit 21_157
bit 21_160
-bit 21_162
bit 21_163
-bit 21_180
+bit 21_223
bit 21_229
+bit 21_231
bit 21_235
bit 21_242
bit 21_244
@@ -1211,17 +1167,14 @@
bit 21_257
bit 21_266
bit 21_267
-bit 21_279
bit 21_292
bit 22_00
bit 22_07
bit 22_08
bit 22_16
-bit 22_95
bit 22_96
bit 22_103
bit 22_104
-bit 22_135
bit 22_144
bit 22_151
bit 22_156
@@ -1239,7 +1192,6 @@
bit 22_192
bit 22_228
bit 22_229
-bit 22_231
bit 22_234
bit 22_235
bit 22_240
@@ -1260,19 +1212,15 @@
bit 22_279
bit 22_280
bit 22_288
-bit 22_296
bit 23_00
bit 23_07
-bit 23_24
bit 23_95
bit 23_96
bit 23_103
-bit 23_135
bit 23_144
bit 23_151
bit 23_156
bit 23_157
-bit 23_160
bit 23_162
bit 23_163
bit 23_168
@@ -1281,7 +1229,6 @@
bit 23_181
bit 23_183
bit 23_199
-bit 23_207
bit 23_223
bit 23_228
bit 23_229
@@ -1296,25 +1243,19 @@
bit 23_251
bit 23_256
bit 23_257
-bit 23_258
bit 23_259
bit 23_262
bit 23_263
bit 23_264
bit 23_266
bit 23_267
-bit 23_271
bit 23_272
bit 23_279
-bit 23_280
bit 23_288
-bit 23_295
-bit 23_296
bit 24_00
bit 24_07
bit 24_08
bit 24_16
-bit 24_24
bit 24_95
bit 24_96
bit 24_103
@@ -1336,7 +1277,6 @@
bit 24_184
bit 24_192
bit 24_199
-bit 24_207
bit 24_223
bit 24_228
bit 24_229
@@ -1358,24 +1298,19 @@
bit 24_264
bit 24_266
bit 24_267
-bit 24_271
bit 24_272
bit 24_279
bit 24_280
bit 24_288
bit 24_293
-bit 24_295
-bit 24_296
bit 25_00
bit 25_07
bit 25_08
bit 25_16
-bit 25_24
bit 25_95
bit 25_96
bit 25_103
bit 25_104
-bit 25_135
bit 25_144
bit 25_151
bit 25_156
@@ -1393,7 +1328,6 @@
bit 25_192
bit 25_199
bit 25_207
-bit 25_208
bit 25_223
bit 25_228
bit 25_229
@@ -1423,8 +1357,8 @@
bit 25_280
bit 25_288
bit 25_292
-bit 25_295
bit 25_296
+bit 25_312
bit 26_01
bit 26_02
bit 26_03
diff --git a/zynq7/mask_dsp_r.db b/zynq7/mask_dsp_r.db
index f4abe54..4118c68 100644
--- a/zynq7/mask_dsp_r.db
+++ b/zynq7/mask_dsp_r.db
@@ -15,13 +15,13 @@
bit 00_167
bit 00_170
bit 00_185
-bit 00_186
bit 00_187
bit 00_209
bit 00_214
bit 00_217
bit 00_234
-bit 00_266
+bit 00_249
+bit 00_251
bit 00_267
bit 00_273
bit 00_295
@@ -45,7 +45,6 @@
bit 01_165
bit 01_166
bit 01_169
-bit 01_186
bit 01_205
bit 01_213
bit 01_216
@@ -61,39 +60,37 @@
bit 01_297
bit 02_06
bit 02_07
-bit 02_10
-bit 02_11
+bit 02_14
+bit 02_15
bit 02_22
+bit 02_23
bit 02_30
-bit 02_31
bit 02_38
bit 02_39
-bit 02_42
+bit 02_41
bit 02_46
bit 02_47
bit 02_50
-bit 02_51
bit 02_54
-bit 02_55
bit 02_62
bit 02_63
bit 02_70
bit 02_71
-bit 02_74
bit 02_78
bit 02_79
bit 02_86
-bit 02_87
+bit 02_89
bit 02_94
bit 02_95
bit 02_102
+bit 02_103
bit 02_110
-bit 02_118
-bit 02_119
+bit 02_111
bit 02_126
bit 02_127
bit 02_134
bit 02_135
+bit 02_141
bit 02_142
bit 02_143
bit 02_150
@@ -101,35 +98,41 @@
bit 02_158
bit 02_159
bit 02_166
-bit 02_167
-bit 02_174
+bit 02_171
+bit 02_182
bit 02_190
bit 02_191
+bit 02_193
bit 02_198
-bit 02_202
bit 02_206
bit 02_207
bit 02_210
bit 02_214
bit 02_215
-bit 02_218
bit 02_222
+bit 02_223
+bit 02_229
bit 02_230
bit 02_231
bit 02_238
bit 02_239
+bit 02_242
+bit 02_243
bit 02_246
bit 02_247
bit 02_253
bit 02_254
bit 02_255
-bit 02_259
+bit 02_258
bit 02_261
bit 02_262
bit 02_263
+bit 02_266
+bit 02_267
bit 02_269
bit 02_270
bit 02_271
+bit 02_278
bit 02_286
bit 02_287
bit 02_294
@@ -140,154 +143,163 @@
bit 02_311
bit 02_318
bit 02_319
-bit 03_02
+bit 03_01
+bit 03_04
bit 03_06
-bit 03_08
+bit 03_14
bit 03_16
-bit 03_24
-bit 03_25
+bit 03_20
+bit 03_21
+bit 03_30
+bit 03_37
bit 03_40
+bit 03_69
+bit 03_80
bit 03_81
+bit 03_86
bit 03_88
bit 03_94
-bit 03_96
bit 03_104
-bit 03_110
bit 03_120
-bit 03_126
bit 03_134
-bit 03_136
-bit 03_144
-bit 03_156
-bit 03_157
+bit 03_141
+bit 03_150
bit 03_158
bit 03_166
-bit 03_176
-bit 03_189
-bit 03_200
+bit 03_168
+bit 03_174
+bit 03_182
+bit 03_197
bit 03_204
bit 03_205
-bit 03_206
-bit 03_217
+bit 03_213
bit 03_222
bit 03_228
bit 03_229
bit 03_230
bit 03_232
-bit 03_234
bit 03_238
bit 03_242
bit 03_246
bit 03_252
bit 03_253
bit 03_254
-bit 03_260
+bit 03_258
bit 03_261
bit 03_262
+bit 03_266
bit 03_268
+bit 03_269
bit 03_270
bit 03_272
bit 03_273
bit 03_286
-bit 03_309
-bit 03_312
+bit 03_289
bit 04_04
+bit 04_12
bit 04_15
bit 04_17
-bit 04_23
+bit 04_33
+bit 04_41
bit 04_51
+bit 04_71
+bit 04_73
bit 04_84
bit 04_87
bit 04_89
-bit 04_97
bit 04_100
-bit 04_103
bit 04_105
-bit 04_108
bit 04_121
bit 04_124
bit 04_132
bit 04_137
-bit 04_145
+bit 04_140
+bit 04_143
bit 04_148
bit 04_151
bit 04_156
bit 04_164
-bit 04_177
-bit 04_187
-bit 04_201
+bit 04_167
+bit 04_169
+bit 04_180
+bit 04_183
+bit 04_193
+bit 04_200
bit 04_203
-bit 04_205
-bit 04_215
+bit 04_209
+bit 04_212
+bit 04_216
bit 04_219
bit 04_229
-bit 04_232
bit 04_233
-bit 04_236
-bit 04_244
+bit 04_247
bit 04_252
bit 04_257
bit 04_260
bit 04_261
bit 04_268
bit 04_269
-bit 04_273
-bit 04_284
+bit 04_279
+bit 04_292
bit 04_295
-bit 04_300
-bit 04_303
-bit 04_305
-bit 05_02
+bit 04_308
+bit 04_313
+bit 04_319
+bit 05_00
+bit 05_07
bit 05_11
bit 05_14
-bit 05_27
+bit 05_22
+bit 05_23
+bit 05_30
bit 05_34
bit 05_43
-bit 05_50
-bit 05_71
bit 05_80
+bit 05_83
bit 05_91
bit 05_94
+bit 05_107
bit 05_123
-bit 05_139
+bit 05_142
bit 05_146
-bit 05_147
bit 05_158
-bit 05_186
+bit 05_170
+bit 05_174
bit 05_187
-bit 05_190
bit 05_196
-bit 05_199
-bit 05_203
-bit 05_216
-bit 05_230
-bit 05_234
-bit 05_235
-bit 05_238
-bit 05_242
-bit 05_251
-bit 05_252
+bit 05_208
+bit 05_212
+bit 05_219
bit 05_254
bit 05_255
-bit 05_258
-bit 05_262
-bit 05_270
+bit 05_263
+bit 05_266
bit 05_272
+bit 05_275
+bit 05_288
bit 05_290
-bit 05_304
+bit 05_302
bit 05_315
bit 06_03
-bit 06_09
+bit 06_05
+bit 06_07
+bit 06_08
bit 06_11
bit 06_15
-bit 06_33
+bit 06_19
+bit 06_21
+bit 06_32
bit 06_35
-bit 06_37
-bit 06_51
+bit 06_36
+bit 06_43
+bit 06_59
bit 06_61
bit 06_68
-bit 06_75
+bit 06_69
+bit 06_72
bit 06_77
+bit 06_81
+bit 06_85
bit 06_93
bit 06_97
bit 06_99
@@ -295,73 +307,71 @@
bit 06_104
bit 06_115
bit 06_120
+bit 06_123
bit 06_125
bit 06_129
bit 06_131
bit 06_133
-bit 06_144
-bit 06_145
+bit 06_136
+bit 06_141
bit 06_149
-bit 06_153
bit 06_155
+bit 06_157
+bit 06_161
bit 06_163
-bit 06_167
-bit 06_169
+bit 06_171
bit 06_177
+bit 06_179
bit 06_181
bit 06_184
bit 06_187
-bit 06_188
bit 06_189
-bit 06_191
bit 06_193
-bit 06_196
bit 06_197
-bit 06_200
-bit 06_201
+bit 06_199
bit 06_203
bit 06_204
-bit 06_205
-bit 06_225
+bit 06_208
+bit 06_209
+bit 06_216
+bit 06_217
+bit 06_221
bit 06_227
-bit 06_232
+bit 06_237
bit 06_243
-bit 06_248
-bit 06_249
bit 06_253
bit 06_256
bit 06_259
bit 06_265
bit 06_267
+bit 06_268
bit 06_269
-bit 06_275
-bit 06_283
+bit 06_273
bit 06_285
-bit 06_287
bit 06_291
bit 06_293
+bit 06_299
bit 06_303
-bit 06_308
+bit 06_307
bit 06_312
bit 06_315
+bit 06_319
bit 07_00
-bit 07_07
bit 07_08
+bit 07_15
bit 07_24
-bit 07_30
+bit 07_31
bit 07_35
-bit 07_38
+bit 07_36
bit 07_39
bit 07_40
-bit 07_43
-bit 07_47
bit 07_48
bit 07_55
bit 07_56
+bit 07_63
bit 07_64
bit 07_71
bit 07_72
-bit 07_75
bit 07_79
bit 07_80
bit 07_87
@@ -369,26 +379,22 @@
bit 07_95
bit 07_103
bit 07_104
-bit 07_111
-bit 07_112
+bit 07_110
bit 07_118
bit 07_120
-bit 07_126
bit 07_127
bit 07_128
bit 07_135
bit 07_136
-bit 07_144
+bit 07_143
bit 07_147
bit 07_151
-bit 07_152
bit 07_154
bit 07_158
bit 07_159
bit 07_160
-bit 07_167
+bit 07_166
bit 07_168
-bit 07_175
bit 07_176
bit 07_178
bit 07_182
@@ -398,93 +404,87 @@
bit 07_198
bit 07_199
bit 07_200
-bit 07_203
bit 07_206
bit 07_207
bit 07_208
bit 07_211
+bit 07_215
bit 07_216
bit 07_222
-bit 07_223
bit 07_224
+bit 07_230
bit 07_231
bit 07_232
-bit 07_235
bit 07_236
bit 07_238
-bit 07_239
bit 07_240
-bit 07_244
bit 07_248
-bit 07_254
+bit 07_255
bit 07_256
bit 07_262
bit 07_264
bit 07_270
-bit 07_274
+bit 07_271
+bit 07_279
bit 07_280
bit 07_286
bit 07_287
bit 07_291
bit 07_295
bit 07_296
-bit 07_303
-bit 07_304
+bit 07_302
bit 07_311
bit 07_312
-bit 07_318
bit 07_319
bit 08_01
bit 08_06
bit 08_08
bit 08_09
bit 08_14
+bit 08_15
bit 08_16
bit 08_23
bit 08_30
-bit 08_37
+bit 08_31
bit 08_38
-bit 08_39
bit 08_40
bit 08_49
bit 08_54
+bit 08_55
+bit 08_57
bit 08_62
-bit 08_63
-bit 08_65
bit 08_70
bit 08_71
+bit 08_72
bit 08_73
bit 08_86
bit 08_94
-bit 08_96
-bit 08_97
+bit 08_100
+bit 08_101
bit 08_102
bit 08_103
bit 08_105
-bit 08_110
bit 08_112
bit 08_113
bit 08_118
bit 08_119
-bit 08_125
bit 08_126
-bit 08_128
bit 08_129
bit 08_134
bit 08_135
+bit 08_137
bit 08_142
+bit 08_144
bit 08_145
bit 08_150
-bit 08_155
-bit 08_159
+bit 08_153
bit 08_160
+bit 08_161
+bit 08_164
bit 08_166
bit 08_167
bit 08_168
-bit 08_174
-bit 08_175
bit 08_176
-bit 08_177
bit 08_180
bit 08_182
bit 08_183
@@ -494,6 +494,7 @@
bit 08_193
bit 08_198
bit 08_199
+bit 08_205
bit 08_206
bit 08_207
bit 08_208
@@ -501,35 +502,32 @@
bit 08_214
bit 08_215
bit 08_216
+bit 08_217
bit 08_222
bit 08_223
+bit 08_224
bit 08_225
bit 08_230
bit 08_231
bit 08_232
bit 08_233
-bit 08_236
-bit 08_237
bit 08_238
-bit 08_239
bit 08_240
bit 08_241
-bit 08_244
-bit 08_248
bit 08_249
-bit 08_253
bit 08_256
bit 08_262
bit 08_263
+bit 08_264
bit 08_265
bit 08_270
bit 08_271
bit 08_272
+bit 08_273
bit 08_278
-bit 08_279
+bit 08_281
bit 08_286
bit 08_287
-bit 08_293
bit 08_294
bit 08_295
bit 08_296
@@ -543,27 +541,25 @@
bit 09_02
bit 09_03
bit 09_04
-bit 09_05
+bit 09_06
bit 09_08
+bit 09_09
bit 09_10
bit 09_11
-bit 09_13
bit 09_18
bit 09_19
bit 09_24
bit 09_25
+bit 09_27
bit 09_35
-bit 09_36
bit 09_40
bit 09_42
bit 09_43
bit 09_50
bit 09_51
-bit 09_52
-bit 09_56
bit 09_58
-bit 09_59
-bit 09_67
+bit 09_72
+bit 09_73
bit 09_74
bit 09_75
bit 09_82
@@ -571,9 +567,8 @@
bit 09_91
bit 09_98
bit 09_99
-bit 09_104
bit 09_106
-bit 09_107
+bit 09_111
bit 09_115
bit 09_122
bit 09_123
@@ -582,16 +577,13 @@
bit 09_130
bit 09_131
bit 09_132
+bit 09_136
bit 09_138
bit 09_139
-bit 09_140
-bit 09_146
bit 09_147
bit 09_148
-bit 09_152
bit 09_154
bit 09_155
-bit 09_159
bit 09_160
bit 09_162
bit 09_163
@@ -599,11 +591,10 @@
bit 09_170
bit 09_171
bit 09_174
+bit 09_176
bit 09_177
-bit 09_178
bit 09_179
bit 09_180
-bit 09_181
bit 09_186
bit 09_187
bit 09_188
@@ -611,125 +602,111 @@
bit 09_192
bit 09_195
bit 09_202
-bit 09_209
+bit 09_203
bit 09_211
-bit 09_216
bit 09_218
bit 09_219
+bit 09_223
bit 09_227
bit 09_232
bit 09_233
bit 09_234
+bit 09_235
+bit 09_241
bit 09_242
-bit 09_243
-bit 09_244
bit 09_250
bit 09_251
bit 09_258
bit 09_259
-bit 09_264
bit 09_265
bit 09_266
bit 09_267
bit 09_268
bit 09_269
-bit 09_271
-bit 09_272
bit 09_274
bit 09_275
bit 09_276
bit 09_281
bit 09_282
-bit 09_284
+bit 09_283
bit 09_285
+bit 09_288
bit 09_290
bit 09_291
-bit 09_296
+bit 09_294
bit 09_298
bit 09_306
-bit 09_311
+bit 09_312
bit 09_314
-bit 10_00
-bit 10_02
+bit 10_06
bit 10_09
+bit 10_10
+bit 10_11
+bit 10_12
bit 10_14
bit 10_15
bit 10_18
+bit 10_24
bit 10_47
bit 10_51
-bit 10_60
-bit 10_73
-bit 10_74
+bit 10_70
bit 10_76
-bit 10_97
+bit 10_79
bit 10_98
-bit 10_99
-bit 10_100
-bit 10_121
-bit 10_128
bit 10_129
bit 10_130
-bit 10_132
+bit 10_135
bit 10_140
+bit 10_145
bit 10_146
bit 10_154
+bit 10_159
+bit 10_160
bit 10_161
bit 10_162
bit 10_170
-bit 10_171
bit 10_174
bit 10_175
-bit 10_176
bit 10_177
-bit 10_178
bit 10_180
+bit 10_182
bit 10_186
bit 10_188
-bit 10_191
-bit 10_192
-bit 10_200
-bit 10_204
+bit 10_193
bit 10_207
-bit 10_209
bit 10_223
-bit 10_225
+bit 10_224
bit 10_226
bit 10_232
-bit 10_238
+bit 10_234
bit 10_239
+bit 10_240
bit 10_242
-bit 10_244
-bit 10_249
bit 10_257
+bit 10_258
bit 10_263
bit 10_264
bit 10_265
+bit 10_266
bit 10_268
bit 10_270
bit 10_271
-bit 10_272
+bit 10_273
bit 10_274
-bit 10_276
-bit 10_290
-bit 10_292
bit 10_297
-bit 10_302
+bit 10_303
bit 10_306
-bit 10_313
bit 10_318
bit 10_319
-bit 11_01
bit 11_02
bit 11_07
bit 11_09
bit 11_10
-bit 11_11
+bit 11_15
bit 11_18
bit 11_23
-bit 11_25
bit 11_26
bit 11_31
-bit 11_33
bit 11_34
bit 11_36
bit 11_41
@@ -738,29 +715,27 @@
bit 11_49
bit 11_50
bit 11_51
-bit 11_55
-bit 11_57
+bit 11_56
bit 11_58
bit 11_63
-bit 11_64
bit 11_66
bit 11_71
bit 11_73
bit 11_74
-bit 11_76
-bit 11_81
+bit 11_82
bit 11_87
-bit 11_89
bit 11_90
+bit 11_95
bit 11_97
bit 11_98
-bit 11_103
bit 11_105
+bit 11_111
bit 11_113
bit 11_114
bit 11_119
bit 11_122
bit 11_127
+bit 11_128
bit 11_129
bit 11_130
bit 11_135
@@ -774,120 +749,107 @@
bit 11_154
bit 11_161
bit 11_162
-bit 11_164
bit 11_167
bit 11_169
bit 11_170
bit 11_177
-bit 11_178
bit 11_180
bit 11_183
bit 11_185
bit 11_186
-bit 11_188
-bit 11_191
bit 11_193
bit 11_194
bit 11_199
-bit 11_201
bit 11_202
bit 11_207
bit 11_208
bit 11_209
+bit 11_210
bit 11_215
bit 11_217
bit 11_218
+bit 11_219
+bit 11_220
bit 11_223
bit 11_225
bit 11_226
-bit 11_231
bit 11_233
-bit 11_234
-bit 11_236
-bit 11_237
bit 11_239
bit 11_241
bit 11_242
-bit 11_244
bit 11_249
-bit 11_250
bit 11_255
bit 11_258
+bit 11_259
bit 11_263
bit 11_264
bit 11_265
bit 11_266
bit 11_268
+bit 11_270
+bit 11_271
bit 11_273
bit 11_274
-bit 11_280
+bit 11_279
bit 11_281
bit 11_282
-bit 11_284
bit 11_287
bit 11_289
bit 11_290
+bit 11_295
bit 11_297
bit 11_303
bit 11_306
bit 11_311
-bit 11_312
bit 11_313
bit 11_314
bit 11_319
-bit 12_00
bit 12_01
bit 12_02
bit 12_04
+bit 12_06
bit 12_08
bit 12_09
bit 12_10
-bit 12_12
+bit 12_14
bit 12_15
bit 12_18
bit 12_23
bit 12_24
+bit 12_26
bit 12_31
-bit 12_32
bit 12_34
-bit 12_36
-bit 12_37
bit 12_39
bit 12_42
bit 12_47
-bit 12_49
bit 12_50
bit 12_51
-bit 12_52
bit 12_55
bit 12_57
bit 12_58
-bit 12_60
bit 12_63
-bit 12_65
-bit 12_66
bit 12_71
+bit 12_72
bit 12_73
bit 12_74
bit 12_76
-bit 12_81
+bit 12_79
+bit 12_80
bit 12_87
bit 12_89
bit 12_90
bit 12_95
bit 12_96
bit 12_98
-bit 12_100
+bit 12_101
bit 12_103
bit 12_105
bit 12_106
-bit 12_113
+bit 12_111
bit 12_114
bit 12_119
-bit 12_121
bit 12_122
bit 12_124
-bit 12_125
bit 12_127
bit 12_128
bit 12_129
@@ -902,17 +864,13 @@
bit 12_146
bit 12_148
bit 12_151
-bit 12_152
-bit 12_153
bit 12_154
+bit 12_160
bit 12_161
bit 12_162
bit 12_167
-bit 12_168
bit 12_170
-bit 12_171
bit 12_174
-bit 12_175
bit 12_176
bit 12_178
bit 12_179
@@ -920,98 +878,96 @@
bit 12_183
bit 12_186
bit 12_188
-bit 12_190
bit 12_191
-bit 12_192
bit 12_193
bit 12_194
bit 12_199
-bit 12_200
bit 12_201
bit 12_202
-bit 12_204
+bit 12_205
bit 12_207
-bit 12_208
bit 12_209
bit 12_210
bit 12_215
+bit 12_216
bit 12_217
bit 12_218
+bit 12_222
bit 12_223
-bit 12_225
+bit 12_224
bit 12_226
bit 12_231
bit 12_232
bit 12_233
+bit 12_234
bit 12_239
+bit 12_240
+bit 12_241
bit 12_242
-bit 12_244
-bit 12_248
bit 12_249
bit 12_250
bit 12_252
-bit 12_253
bit 12_255
bit 12_258
bit 12_263
bit 12_264
bit 12_266
-bit 12_272
+bit 12_268
+bit 12_271
bit 12_274
bit 12_276
bit 12_279
bit 12_280
bit 12_282
-bit 12_284
-bit 12_286
bit 12_287
+bit 12_288
bit 12_290
-bit 12_293
+bit 12_295
bit 12_297
bit 12_298
bit 12_302
bit 12_303
-bit 12_305
bit 12_306
bit 12_311
bit 12_313
bit 12_314
+bit 12_318
+bit 12_319
bit 13_01
bit 13_02
bit 13_07
+bit 13_08
bit 13_09
-bit 13_11
+bit 13_10
bit 13_14
-bit 13_17
+bit 13_15
bit 13_18
-bit 13_25
+bit 13_20
bit 13_26
-bit 13_31
-bit 13_34
-bit 13_36
+bit 13_37
bit 13_39
bit 13_41
bit 13_42
+bit 13_47
bit 13_49
bit 13_50
bit 13_51
+bit 13_55
+bit 13_56
bit 13_57
bit 13_58
bit 13_63
-bit 13_64
-bit 13_65
bit 13_71
+bit 13_72
bit 13_73
-bit 13_74
bit 13_76
-bit 13_81
-bit 13_87
-bit 13_89
+bit 13_82
bit 13_92
bit 13_97
bit 13_98
bit 13_103
bit 13_105
+bit 13_110
bit 13_111
bit 13_113
bit 13_114
@@ -1023,66 +979,56 @@
bit 13_130
bit 13_132
bit 13_135
+bit 13_136
bit 13_137
bit 13_138
-bit 13_140
bit 13_143
bit 13_145
bit 13_146
bit 13_151
bit 13_153
bit 13_155
-bit 13_158
+bit 13_156
bit 13_159
bit 13_160
bit 13_161
bit 13_162
-bit 13_164
bit 13_166
bit 13_167
bit 13_169
bit 13_170
bit 13_174
-bit 13_175
bit 13_177
-bit 13_178
bit 13_181
bit 13_183
bit 13_185
bit 13_186
+bit 13_188
bit 13_190
bit 13_191
bit 13_192
bit 13_193
bit 13_194
bit 13_196
+bit 13_198
bit 13_199
-bit 13_200
bit 13_202
-bit 13_204
bit 13_207
bit 13_208
bit 13_209
+bit 13_210
bit 13_215
-bit 13_216
bit 13_217
+bit 13_220
bit 13_223
-bit 13_224
bit 13_225
-bit 13_226
bit 13_231
-bit 13_232
bit 13_233
-bit 13_234
+bit 13_236
bit 13_237
-bit 13_238
bit 13_239
bit 13_241
-bit 13_242
-bit 13_244
-bit 13_245
bit 13_249
-bit 13_250
bit 13_257
bit 13_258
bit 13_263
@@ -1091,50 +1037,51 @@
bit 13_271
bit 13_272
bit 13_273
-bit 13_275
+bit 13_274
bit 13_279
-bit 13_280
+bit 13_281
bit 13_282
bit 13_284
bit 13_287
bit 13_289
bit 13_290
bit 13_292
+bit 13_294
bit 13_295
-bit 13_296
bit 13_297
+bit 13_298
bit 13_303
bit 13_306
-bit 13_310
bit 13_311
bit 13_312
bit 13_313
bit 13_314
bit 13_318
bit 13_319
-bit 14_02
+bit 14_04
bit 14_08
bit 14_10
+bit 14_12
bit 14_14
bit 14_18
bit 14_24
-bit 14_26
bit 14_34
bit 14_36
bit 14_40
bit 14_42
bit 14_50
-bit 14_56
bit 14_58
bit 14_60
bit 14_66
+bit 14_68
+bit 14_70
bit 14_74
-bit 14_76
bit 14_82
+bit 14_84
bit 14_90
bit 14_98
bit 14_100
-bit 14_104
+bit 14_106
bit 14_114
bit 14_122
bit 14_124
@@ -1142,27 +1089,25 @@
bit 14_130
bit 14_132
bit 14_138
-bit 14_144
+bit 14_140
+bit 14_146
bit 14_148
bit 14_154
bit 14_160
bit 14_162
-bit 14_166
bit 14_170
bit 14_176
bit 14_178
bit 14_180
+bit 14_182
bit 14_186
bit 14_188
-bit 14_190
-bit 14_192
bit 14_194
bit 14_202
+bit 14_210
bit 14_218
bit 14_226
bit 14_232
-bit 14_234
-bit 14_236
bit 14_242
bit 14_250
bit 14_252
@@ -1170,26 +1115,25 @@
bit 14_264
bit 14_266
bit 14_268
+bit 14_270
bit 14_274
-bit 14_276
-bit 14_280
bit 14_282
bit 14_284
+bit 14_288
bit 14_290
-bit 14_292
bit 14_306
+bit 14_312
bit 14_314
bit 15_01
bit 15_07
bit 15_09
+bit 15_11
bit 15_15
bit 15_17
bit 15_25
bit 15_31
-bit 15_33
bit 15_39
bit 15_41
-bit 15_47
bit 15_49
bit 15_55
bit 15_57
@@ -1199,11 +1143,7 @@
bit 15_73
bit 15_81
bit 15_87
-bit 15_97
-bit 15_99
bit 15_103
-bit 15_105
-bit 15_113
bit 15_119
bit 15_121
bit 15_127
@@ -1212,8 +1152,9 @@
bit 15_137
bit 15_145
bit 15_151
-bit 15_153
+bit 15_159
bit 15_161
+bit 15_165
bit 15_167
bit 15_169
bit 15_175
@@ -1224,24 +1165,22 @@
bit 15_193
bit 15_199
bit 15_201
-bit 15_207
bit 15_209
-bit 15_215
+bit 15_219
bit 15_223
bit 15_225
bit 15_231
bit 15_233
-bit 15_237
bit 15_239
bit 15_241
bit 15_249
bit 15_255
bit 15_257
+bit 15_259
bit 15_263
bit 15_265
bit 15_271
bit 15_273
-bit 15_279
bit 15_281
bit 15_287
bit 15_295
@@ -1263,14 +1202,13 @@
bit 16_160
bit 16_162
bit 16_163
+bit 16_167
bit 16_176
bit 16_180
bit 16_181
bit 16_183
bit 16_184
bit 16_199
-bit 16_207
-bit 16_223
bit 16_228
bit 16_229
bit 16_231
@@ -1289,7 +1227,6 @@
bit 16_264
bit 16_266
bit 16_267
-bit 16_271
bit 16_272
bit 16_279
bit 16_280
@@ -1297,7 +1234,9 @@
bit 16_312
bit 17_00
bit 17_07
+bit 17_08
bit 17_24
+bit 17_32
bit 17_96
bit 17_103
bit 17_104
@@ -1309,18 +1248,18 @@
bit 17_160
bit 17_162
bit 17_163
+bit 17_167
bit 17_168
bit 17_176
bit 17_180
bit 17_181
bit 17_183
+bit 17_199
bit 17_228
bit 17_229
bit 17_231
bit 17_234
bit 17_235
-bit 17_239
-bit 17_240
bit 17_247
bit 17_248
bit 17_250
@@ -1334,25 +1273,27 @@
bit 17_264
bit 17_266
bit 17_267
-bit 17_271
bit 17_272
bit 17_279
+bit 17_280
bit 17_288
bit 17_296
+bit 17_303
bit 17_312
bit 18_01
bit 18_06
-bit 18_25
+bit 18_17
bit 18_97
bit 18_102
+bit 18_105
bit 18_134
bit 18_145
bit 18_150
bit 18_156
bit 18_157
-bit 18_161
bit 18_162
bit 18_163
+bit 18_166
bit 18_169
bit 18_177
bit 18_180
@@ -1367,7 +1308,6 @@
bit 18_230
bit 18_234
bit 18_235
-bit 18_238
bit 18_241
bit 18_246
bit 18_249
@@ -1386,7 +1326,7 @@
bit 18_278
bit 18_281
bit 18_289
-bit 18_297
+bit 18_294
bit 19_01
bit 19_06
bit 19_09
@@ -1394,10 +1334,9 @@
bit 19_94
bit 19_97
bit 19_102
-bit 19_121
+bit 19_134
bit 19_145
bit 19_150
-bit 19_153
bit 19_156
bit 19_157
bit 19_161
@@ -1431,9 +1370,11 @@
bit 19_266
bit 19_267
bit 19_273
+bit 19_278
bit 19_281
bit 19_289
bit 20_00
+bit 20_07
bit 20_96
bit 20_103
bit 20_144
@@ -1441,14 +1382,16 @@
bit 20_160
bit 20_162
bit 20_163
+bit 20_176
bit 20_180
+bit 20_181
bit 20_183
bit 20_228
bit 20_234
bit 20_240
-bit 20_250
bit 20_256
bit 20_257
+bit 20_259
bit 20_262
bit 20_266
bit 20_267
@@ -1456,22 +1399,19 @@
bit 20_293
bit 21_00
bit 21_07
-bit 21_95
bit 21_96
bit 21_103
bit 21_157
bit 21_160
bit 21_163
-bit 21_229
-bit 21_231
+bit 21_181
+bit 21_223
bit 21_235
bit 21_242
bit 21_244
bit 21_247
-bit 21_251
bit 21_256
bit 21_257
-bit 21_258
bit 21_266
bit 21_267
bit 21_292
@@ -1491,6 +1431,7 @@
bit 22_160
bit 22_162
bit 22_163
+bit 22_167
bit 22_168
bit 22_176
bit 22_180
@@ -1498,8 +1439,8 @@
bit 22_183
bit 22_184
bit 22_192
+bit 22_199
bit 22_207
-bit 22_223
bit 22_228
bit 22_229
bit 22_231
@@ -1523,31 +1464,29 @@
bit 22_279
bit 22_280
bit 22_288
-bit 22_296
+bit 22_295
bit 22_312
bit 23_00
bit 23_07
-bit 23_24
+bit 23_08
bit 23_95
bit 23_96
bit 23_103
bit 23_104
-bit 23_120
bit 23_135
bit 23_144
bit 23_151
-bit 23_152
bit 23_156
bit 23_157
bit 23_160
bit 23_162
bit 23_163
+bit 23_167
bit 23_168
bit 23_176
bit 23_180
bit 23_181
bit 23_183
-bit 23_184
bit 23_199
bit 23_207
bit 23_223
@@ -1556,7 +1495,6 @@
bit 23_231
bit 23_234
bit 23_235
-bit 23_239
bit 23_240
bit 23_247
bit 23_248
@@ -1570,30 +1508,28 @@
bit 23_263
bit 23_266
bit 23_267
-bit 23_271
bit 23_272
bit 23_279
bit 23_280
bit 23_288
+bit 23_303
bit 24_00
bit 24_07
bit 24_08
bit 24_16
-bit 24_24
bit 24_95
bit 24_96
bit 24_103
bit 24_104
-bit 24_120
bit 24_135
bit 24_144
bit 24_151
-bit 24_152
bit 24_156
bit 24_157
bit 24_160
bit 24_162
bit 24_163
+bit 24_167
bit 24_168
bit 24_176
bit 24_180
@@ -1609,7 +1545,6 @@
bit 24_231
bit 24_234
bit 24_235
-bit 24_239
bit 24_240
bit 24_247
bit 24_248
@@ -1624,33 +1559,33 @@
bit 24_264
bit 24_266
bit 24_267
-bit 24_271
bit 24_272
bit 24_279
bit 24_280
bit 24_288
bit 24_293
-bit 24_296
+bit 24_295
+bit 24_303
bit 24_312
bit 25_00
bit 25_07
bit 25_08
bit 25_16
bit 25_24
+bit 25_32
bit 25_95
bit 25_96
bit 25_103
bit 25_104
-bit 25_120
bit 25_135
bit 25_144
bit 25_151
-bit 25_152
bit 25_156
bit 25_157
bit 25_160
bit 25_162
bit 25_163
+bit 25_167
bit 25_168
bit 25_176
bit 25_180
@@ -1666,7 +1601,6 @@
bit 25_231
bit 25_234
bit 25_235
-bit 25_239
bit 25_240
bit 25_242
bit 25_244
@@ -1683,13 +1617,14 @@
bit 25_264
bit 25_266
bit 25_267
-bit 25_271
bit 25_272
bit 25_279
bit 25_280
bit 25_288
bit 25_292
+bit 25_295
bit 25_296
+bit 25_303
bit 25_312
bit 26_01
bit 26_02
diff --git a/zynq7/segbits_int_l.origin_info.db b/zynq7/segbits_int_l.origin_info.db
index 22f30e5..c5b8c78 100644
--- a/zynq7/segbits_int_l.origin_info.db
+++ b/zynq7/segbits_int_l.origin_info.db
@@ -393,7 +393,7 @@
INT_L.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
INT_L.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
-INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
+INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
@@ -1917,7 +1917,7 @@
INT_L.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
INT_L.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
INT_L.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
-INT_L.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
+INT_L.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
INT_L.EE4BEG3.LOGIC_OUTS_L3 origin:050-pip-seed 02_57 07_57
INT_L.EE4BEG3.LOGIC_OUTS_L7 origin:050-pip-seed 02_57 04_58
INT_L.EE4BEG3.LOGIC_OUTS_L11 origin:050-pip-seed 03_56 04_58
@@ -2273,7 +2273,7 @@
INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
+INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17
INT_L.NL1BEG0.LOGIC_OUTS_L5 origin:050-pip-seed 11_17 14_17
INT_L.NL1BEG0.LOGIC_OUTS_L9 origin:050-pip-seed 10_17 13_17
@@ -2887,7 +2887,7 @@
INT_L.SE6BEG3.NE2END3 origin:050-pip-seed 03_58 04_56
INT_L.SE6BEG3.NE6END3 origin:050-pip-seed 04_56 04_59
INT_L.SE6BEG3.NN2END3 origin:050-pip-seed 02_59 04_56
-INT_L.SE6BEG3.NN6END3 origin:050-pip-seed 04_56 07_59
+INT_L.SE6BEG3.NN6END3 origin:056-pip-rem 04_56 07_59
INT_L.SE6BEG3.SE2END3 origin:050-pip-seed 02_58 03_58
INT_L.SE6BEG3.SE6END3 origin:050-pip-seed 02_58 07_59
INT_L.SE6BEG3.SS2END3 origin:050-pip-seed 02_59 05_58
@@ -3323,7 +3323,7 @@
INT_L.SW6BEG2.LVB_L0 origin:056-pip-rem 04_46 05_44
INT_L.SW6BEG2.LVB_L12 origin:056-pip-rem 05_44 07_45
INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
+INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
INT_L.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
INT_L.SW6BEG2.NW6END3 origin:050-pip-seed 05_47 06_44
INT_L.SW6BEG2.SE2END2 origin:050-pip-seed 02_45 04_45
@@ -3345,7 +3345,7 @@
INT_L.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60
INT_L.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63
INT_L.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
-INT_L.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
+INT_L.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
INT_L.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
INT_L.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61
INT_L.SW6BEG3.SE6END3 origin:050-pip-seed 04_61 06_60
@@ -3603,7 +3603,7 @@
INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32
INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33
INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
-INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
+INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
@@ -3623,7 +3623,7 @@
INT_L.WW4BEG3.LV_L18 origin:056-pip-rem 05_48 07_49
INT_L.WW4BEG3.LH0 origin:056-pip-rem 04_50 05_48
INT_L.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51
-INT_L.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51
+INT_L.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51
INT_L.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51
INT_L.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48
INT_L.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49
diff --git a/zynq7/segbits_int_r.origin_info.db b/zynq7/segbits_int_r.origin_info.db
index 9ea6b56..0de5787 100644
--- a/zynq7/segbits_int_r.origin_info.db
+++ b/zynq7/segbits_int_r.origin_info.db
@@ -329,7 +329,7 @@
INT_R.FAN_ALT4.BYP_BOUNCE_N3_3 origin:059-pip-byp-bounce !22_08 !23_08 !24_08 20_08 25_08
INT_R.FAN_ALT4.BYP_BOUNCE_N3_7 origin:059-pip-byp-bounce !22_08 !23_08 !25_08 20_08 24_08
INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
-INT_R.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08
+INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
@@ -2273,7 +2273,7 @@
INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
+INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17
INT_R.NL1BEG0.LOGIC_OUTS5 origin:050-pip-seed 11_17 14_17
INT_R.NL1BEG0.LOGIC_OUTS9 origin:050-pip-seed 10_17 13_17
@@ -3321,7 +3321,7 @@
INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
INT_R.SW6BEG2.LOGIC_OUTS20 origin:050-pip-seed 06_44 07_45
INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
INT_R.SW6BEG2.LVB0 origin:056-pip-rem 04_46 05_44
INT_R.SW6BEG2.LVB12 origin:056-pip-rem 05_44 07_45
INT_R.SW6BEG2.NW2END3 origin:050-pip-seed 02_45 05_47
@@ -3344,7 +3344,7 @@
INT_R.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60
INT_R.SW6BEG3.WW4END_S0_0 origin:050-pip-seed 05_60 05_63
INT_R.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61
-INT_R.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60
+INT_R.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60
INT_R.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60
INT_R.SW6BEG3.LV18 origin:056-pip-rem 05_60 07_61
INT_R.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61
@@ -3603,7 +3603,7 @@
INT_R.WW4BEG2.LVB0 origin:056-pip-rem 04_34 05_32
INT_R.WW4BEG2.LVB12 origin:056-pip-rem 05_32 07_33
INT_R.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
-INT_R.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
+INT_R.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
INT_R.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
INT_R.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
INT_R.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
@@ -3623,7 +3623,7 @@
INT_R.WW4BEG3.LH0 origin:056-pip-rem 04_50 05_48
INT_R.WW4BEG3.LV18 origin:056-pip-rem 05_48 07_49
INT_R.WW4BEG3.NE2END3 origin:050-pip-seed 02_49 05_51
-INT_R.WW4BEG3.NE6END3 origin:050-pip-seed 05_48 05_51
+INT_R.WW4BEG3.NE6END3 origin:056-pip-rem 05_48 05_51
INT_R.WW4BEG3.NN2END3 origin:050-pip-seed 03_48 05_51
INT_R.WW4BEG3.NN6END3 origin:050-pip-seed 05_51 06_48
INT_R.WW4BEG3.NW2END3 origin:050-pip-seed 02_49 03_49
diff --git a/zynq7/segbits_liob33.db b/zynq7/segbits_liob33.db
index e5c2ee6..91bdb8f 100644
--- a/zynq7/segbits_liob33.db
+++ b/zynq7/segbits_liob33.db
@@ -20,10 +20,10 @@
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127
LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_86 39_85 !39_87
-LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 !39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_106 !38_110 !39_105 !39_107 !39_109 !39_111
LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW 38_106 38_110 39_105 !39_107 39_109 !39_111
LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 39_95
+LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_64 !38_74 !38_76 !38_94 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 !39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127
@@ -32,6 +32,7 @@
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 39_127
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 39_119 !39_125 !39_127
+LIOB33.IOB_Y0.LVCMOS18.IN_ONLY !38_64 !38_74 !38_76 38_94 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 !39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 !39_119 !39_125 !39_127
LIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN 38_86 39_85 39_87
@@ -58,10 +59,10 @@
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 !38_00 38_02 !38_08 !38_10 38_14 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN !38_40 38_42 39_41
-LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_16 !38_18 !38_20 !38_22 !39_17 !39_21
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_16 38_18 !38_20 38_22 39_17 39_21
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 38_32
+LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63
LIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 !38_00 !38_02 38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 38_00 38_02 38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63
diff --git a/zynq7/segbits_liob33.origin_info.db b/zynq7/segbits_liob33.origin_info.db
index 5c43c07..31a8585 100644
--- a/zynq7/segbits_liob33.origin_info.db
+++ b/zynq7/segbits_liob33.origin_info.db
@@ -20,10 +20,10 @@
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_127 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_125 39_65
LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_75 !39_97 38_112 38_126 38_64 39_113 39_127 39_65
LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !39_87 38_86 39_85
-LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_64 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_65 !39_75 !39_97 38_118 39_113 39_119 39_125
LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_106 !38_110 !39_105 !39_107 !39_109 !39_111
LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !39_107 !39_111 38_106 38_110 39_105 39_109
LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 39_95
+LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_64 !38_74 !38_76 !38_94 !38_98 !39_101 !39_117 !39_127 !39_65 !39_75 !39_97 38_118 39_113 39_119 39_125
LIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_125 !39_127 !39_75 !39_97 38_112 38_64 39_113 39_119 39_65
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_75 !39_97 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65
LIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_75 !39_97 38_112 38_64 39_113 39_127 39_65
@@ -32,6 +32,7 @@
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_75 !39_97 38_112 38_126 38_64 39_113 39_119 39_125 39_65
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_112 38_126 38_64 39_113 39_125 39_127 39_65
LIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_125 !39_127 !39_75 !39_97 38_112 38_126 38_64 39_113 39_117 39_119 39_65
+LIOB33.IOB_Y0.LVCMOS18.IN_ONLY origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_64 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_65 !39_75 !39_97 38_118 38_94 39_113 39_119 39_125
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_127 !39_75 !39_97 38_112 38_64 39_113 39_65
LIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_127 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_65
LIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN origin:030-iob 38_86 39_85 39_87
@@ -58,10 +59,10 @@
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 38_02 38_14 38_62 39_01 39_09 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 38_00 38_14 38_62 39_01 39_15 39_63
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_42 39_41
-LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_16 !38_18 !38_20 !38_22 !39_17 !39_21
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !38_16 !38_20 38_18 38_22 39_17 39_21
LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 38_32
+LIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09
LIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 38_08 38_14 38_62 39_15 39_63
LIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 origin:030-iob !38_10 !39_09 38_00 38_02 38_08 38_14 38_62 39_01 39_15 39_63
LIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_01 !39_09 38_00 38_14 38_62 39_15 39_63
diff --git a/zynq7/segbits_riob33.db b/zynq7/segbits_riob33.db
index bf489d5..226c74d 100644
--- a/zynq7/segbits_riob33.db
+++ b/zynq7/segbits_riob33.db
@@ -20,10 +20,10 @@
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127
RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_86 39_85 !39_87
-RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_64 !38_74 !38_76 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 !39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_106 !38_110 !39_105 !39_107 !39_109 !39_111
RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW 38_106 38_110 39_105 !39_107 39_109 !39_111
RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 39_95
+RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_64 !38_74 !38_76 !38_94 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 !39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 39_127
@@ -32,6 +32,7 @@
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 39_125 39_127
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 39_119 !39_125 !39_127
+RIOB33.IOB_Y0.LVCMOS18.IN_ONLY !38_64 !38_74 !38_76 38_94 !38_98 !38_100 !38_102 !38_112 38_118 !38_126 !39_65 !39_75 !39_97 !39_101 39_113 !39_117 39_119 39_125 !39_127
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 !38_118 !38_126 39_65 !39_75 !39_97 !39_101 39_113 !39_117 !39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 38_64 !38_74 !38_76 !38_98 !38_100 !38_102 38_112 38_118 38_126 39_65 !39_75 !39_97 !39_101 39_113 39_117 !39_119 !39_125 !39_127
RIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN 38_86 39_85 39_87
@@ -58,10 +59,10 @@
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 !38_00 38_02 !38_08 !38_10 38_14 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN !38_40 38_42 39_41
-RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST !38_16 !38_18 !38_20 !38_22 !39_17 !39_21
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW !38_16 38_18 !38_20 38_22 39_17 39_21
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN 38_32
+RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY !38_00 38_02 38_08 !38_10 38_14 !38_62 !39_01 39_09 !39_15 !39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 !38_00 !38_02 38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 38_00 38_02 38_08 !38_10 38_14 38_62 39_01 !39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 38_00 !38_02 !38_08 !38_10 38_14 38_62 !39_01 !39_09 39_15 39_63
diff --git a/zynq7/segbits_riob33.origin_info.db b/zynq7/segbits_riob33.origin_info.db
index cee7b38..4d76d56 100644
--- a/zynq7/segbits_riob33.origin_info.db
+++ b/zynq7/segbits_riob33.origin_info.db
@@ -20,10 +20,10 @@
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_127 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_125 39_65
RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_75 !39_97 38_112 38_126 38_64 39_113 39_127 39_65
RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !39_87 38_86 39_85
-RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_64 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_65 !39_75 !39_97 38_118 39_113 39_119 39_125
RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_106 !38_110 !39_105 !39_107 !39_109 !39_111
RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !39_107 !39_111 38_106 38_110 39_105 39_109
RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 39_95
+RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_64 !38_74 !38_76 !38_94 !38_98 !39_101 !39_117 !39_127 !39_65 !39_75 !39_97 38_118 39_113 39_119 39_125
RIOB33.IOB_Y0.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_125 !39_127 !39_75 !39_97 38_112 38_64 39_113 39_119 39_65
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_75 !39_97 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65
RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_75 !39_97 38_112 38_64 39_113 39_127 39_65
@@ -32,6 +32,7 @@
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_75 !39_97 38_112 38_126 38_64 39_113 39_119 39_125 39_65
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_75 !39_97 38_112 38_126 38_64 39_113 39_125 39_127 39_65
RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_100 !38_102 !38_118 !38_74 !38_76 !38_98 !39_101 !39_125 !39_127 !39_75 !39_97 38_112 38_126 38_64 39_113 39_117 39_119 39_65
+RIOB33.IOB_Y0.LVCMOS18.IN_ONLY origin:030-iob !38_100 !38_102 !38_112 !38_126 !38_64 !38_74 !38_76 !38_98 !39_101 !39_117 !39_127 !39_65 !39_75 !39_97 38_118 38_94 39_113 39_119 39_125
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_100 !38_102 !38_118 !38_126 !38_74 !38_76 !38_98 !39_101 !39_117 !39_119 !39_125 !39_127 !39_75 !39_97 38_112 38_64 39_113 39_65
RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !38_100 !38_102 !38_74 !38_76 !38_98 !39_101 !39_119 !39_125 !39_127 !39_75 !39_97 38_112 38_118 38_126 38_64 39_113 39_117 39_65
RIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN origin:030-iob 38_86 39_85 39_87
@@ -58,10 +59,10 @@
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 38_02 38_14 38_62 39_01 39_09 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 38_00 38_14 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !38_40 38_42 39_41
-RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL.SLEW.FAST origin:030-iob !38_16 !38_18 !38_20 !38_22 !39_17 !39_21
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15.SLEW.SLOW origin:030-iob !38_16 !38_20 38_18 38_22 39_17 39_21
RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15.STEPDOWN origin:030-iob 38_32
+RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33.IN_ONLY origin:030-iob !38_00 !38_10 !38_62 !39_01 !39_15 !39_63 38_02 38_08 38_14 39_09
RIOB33.IOB_Y1.LVCMOS12_LVCMOS25.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 38_08 38_14 38_62 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 origin:030-iob !38_10 !39_09 38_00 38_02 38_08 38_14 38_62 39_01 39_15 39_63
RIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_01 !39_09 38_00 38_14 38_62 39_15 39_63
diff --git a/zynq7/xc7z010s/node_wires.json b/zynq7/xc7z010/node_wires.json
similarity index 100%
rename from zynq7/xc7z010s/node_wires.json
rename to zynq7/xc7z010/node_wires.json
diff --git a/zynq7/xc7z010s/tileconn.json b/zynq7/xc7z010/tileconn.json
similarity index 100%
rename from zynq7/xc7z010s/tileconn.json
rename to zynq7/xc7z010/tileconn.json
diff --git a/zynq7/xc7z010s/tilegrid.json b/zynq7/xc7z010/tilegrid.json
similarity index 100%
rename from zynq7/xc7z010s/tilegrid.json
rename to zynq7/xc7z010/tilegrid.json
diff --git a/zynq7/xc7z010clg225-1/package_pins.csv b/zynq7/xc7z010clg225-1/package_pins.csv
new file mode 100644
index 0000000..7745478
--- /dev/null
+++ b/zynq7/xc7z010clg225-1/package_pins.csv
@@ -0,0 +1,143 @@
+pin,bank,site,tile,pin_function
+A2,502,IOPAD_X1Y33,PSS2_X13Y53,PS_DDR_DQ1_502
+A3,502,IOPAD_X1Y39,PSS2_X13Y53,PS_DDR_DQ7_502
+A4,502,IOPAD_X1Y37,PSS2_X13Y53,PS_DDR_DQ5_502
+A5,500,IOPAD_X1Y78,PSS2_X13Y53,PS_MIO1_500
+A7,500,IOPAD_X1Y80,PSS2_X13Y53,PS_MIO3_500
+A8,500,IOPAD_X1Y79,PSS2_X13Y53,PS_MIO2_500
+A9,500,IOPAD_X1Y82,PSS2_X13Y53,PS_MIO5_500
+A10,500,IOPAD_X1Y83,PSS2_X13Y53,PS_MIO6_500
+A12,501,IOPAD_X1Y129,PSS2_X13Y53,PS_MIO52_501
+A13,501,IOPAD_X1Y115,PSS2_X13Y53,PS_MIO38_501
+A14,501,IOPAD_X1Y112,PSS2_X13Y53,PS_MIO35_501
+A15,501,IOPAD_X1Y105,PSS2_X13Y53,PS_MIO28_501
+B1,502,IOPAD_X1Y28,PSS2_X13Y53,PS_DDR_DM0_502
+B2,502,IOPAD_X1Y64,PSS2_X13Y53,PS_DDR_DQS_N0_502
+B4,502,IOPAD_X1Y36,PSS2_X13Y53,PS_DDR_DQ4_502
+B5,500,IOPAD_X1Y86,PSS2_X13Y53,PS_MIO9_500
+B6,500,IOPAD_X1Y85,PSS2_X13Y53,PS_MIO8_500
+B7,500,IOPAD_X1Y89,PSS2_X13Y53,PS_MIO12_500
+B9,500,IOPAD_X1Y91,PSS2_X13Y53,PS_MIO14_500
+B10,500,IOPAD_X1Y88,PSS2_X13Y53,PS_MIO11_500
+B11,501,IOPAD_X1Y134,PSS2_X13Y53,PS_SRST_B_501
+B12,501,IOPAD_X1Y125,PSS2_X13Y53,PS_MIO48_501
+B14,501,IOPAD_X1Y113,PSS2_X13Y53,PS_MIO36_501
+B15,501,IOPAD_X1Y107,PSS2_X13Y53,PS_MIO30_501
+C1,502,IOPAD_X1Y35,PSS2_X13Y53,PS_DDR_DQ3_502
+C2,502,IOPAD_X1Y68,PSS2_X13Y53,PS_DDR_DQS_P0_502
+C3,502,IOPAD_X1Y38,PSS2_X13Y53,PS_DDR_DQ6_502
+C4,502,IOPAD_X1Y34,PSS2_X13Y53,PS_DDR_DQ2_502
+C6,500,IOPAD_X1Y90,PSS2_X13Y53,PS_MIO13_500
+C7,500,IOPAD_X1Y26,PSS2_X13Y53,PS_CLK_500
+C8,500,IOPAD_X1Y81,PSS2_X13Y53,PS_MIO4_500
+C9,500,IOPAD_X1Y132,PSS2_X13Y53,PS_POR_B_500
+C11,501,IOPAD_X1Y110,PSS2_X13Y53,PS_MIO33_501
+C12,501,IOPAD_X1Y108,PSS2_X13Y53,PS_MIO31_501
+C13,501,IOPAD_X1Y130,PSS2_X13Y53,PS_MIO53_501
+C14,501,IOPAD_X1Y114,PSS2_X13Y53,PS_MIO37_501
+D1,502,IOPAD_X1Y41,PSS2_X13Y53,PS_DDR_DQ9_502
+D3,502,IOPAD_X1Y29,PSS2_X13Y53,PS_DDR_DM1_502
+D4,502,IOPAD_X1Y32,PSS2_X13Y53,PS_DDR_DQ0_502
+D6,500,IOPAD_X1Y87,PSS2_X13Y53,PS_MIO10_500
+D8,500,IOPAD_X1Y77,PSS2_X13Y53,PS_MIO0_500
+D9,500,IOPAD_X1Y84,PSS2_X13Y53,PS_MIO7_500
+D10,500,IOPAD_X1Y92,PSS2_X13Y53,PS_MIO15_500
+D11,501,IOPAD_X1Y106,PSS2_X13Y53,PS_MIO29_501
+D13,501,IOPAD_X1Y126,PSS2_X13Y53,PS_MIO49_501
+D14,501,IOPAD_X1Y116,PSS2_X13Y53,PS_MIO39_501
+D15,501,IOPAD_X1Y111,PSS2_X13Y53,PS_MIO34_501
+E1,502,IOPAD_X1Y40,PSS2_X13Y53,PS_DDR_DQ8_502
+E2,502,IOPAD_X1Y42,PSS2_X13Y53,PS_DDR_DQ10_502
+E3,502,IOPAD_X1Y43,PSS2_X13Y53,PS_DDR_DQ11_502
+E11,35,IOB_X0Y96,RIOB33_X31Y95,IO_L2P_T0_AD8P_35
+E12,35,IOB_X0Y95,RIOB33_X31Y95,IO_L2N_T0_AD8N_35
+E13,35,IOB_X0Y97,RIOB33_X31Y97,IO_L1N_T0_AD0N_35
+E15,501,IOPAD_X1Y109,PSS2_X13Y53,PS_MIO32_501
+F2,502,IOPAD_X1Y65,PSS2_X13Y53,PS_DDR_DQS_N1_502
+F3,502,IOPAD_X1Y44,PSS2_X13Y53,PS_DDR_DQ12_502
+F12,35,IOB_X0Y98,RIOB33_X31Y97,IO_L1P_T0_AD0P_35
+F13,35,IOB_X0Y94,RIOB33_X31Y93,IO_L3P_T0_DQS_AD1P_35
+F14,35,IOB_X0Y93,RIOB33_X31Y93,IO_L3N_T0_DQS_AD1N_35
+F15,35,IOB_X0Y89,RIOB33_X31Y89,IO_L5N_T0_AD9N_35
+G1,502,IOPAD_X1Y45,PSS2_X13Y53,PS_DDR_DQ13_502
+G2,502,IOPAD_X1Y69,PSS2_X13Y53,PS_DDR_DQS_P1_502
+G7,0,IPAD_X0Y0,MONITOR_BOT_PELE1_X67Y79,VP_0
+G11,34,IOB_X0Y48,RIOB33_X31Y47,IO_L1P_T0_34
+G12,34,IOB_X0Y46,RIOB33_X31Y45,IO_L2P_T0_34
+G14,34,IOB_X0Y44,RIOB33_X31Y43,IO_L3P_T0_DQS_PUDC_B_34
+G15,35,IOB_X0Y90,RIOB33_X31Y89,IO_L5P_T0_AD9P_35
+H1,502,IOPAD_X1Y46,PSS2_X13Y53,PS_DDR_DQ14_502
+H2,502,IOPAD_X1Y47,PSS2_X13Y53,PS_DDR_DQ15_502
+H3,502,IOPAD_X1Y3,PSS2_X13Y53,PS_DDR_VRP_502
+H8,0,IPAD_X0Y1,MONITOR_BOT_PELE1_X67Y79,VN_0
+H11,34,IOB_X0Y38,RIOB33_X31Y37,IO_L6P_T0_34
+H12,34,IOB_X0Y47,RIOB33_X31Y47,IO_L1N_T0_34
+H13,34,IOB_X0Y45,RIOB33_X31Y45,IO_L2N_T0_34
+H14,34,IOB_X0Y43,RIOB33_X31Y43,IO_L3N_T0_DQS_34
+J1,502,IOPAD_X1Y14,PSS2_X13Y53,PS_DDR_A10_502
+J3,502,IOPAD_X1Y2,PSS2_X13Y53,PS_DDR_VRN_502
+J11,34,IOB_X0Y37,RIOB33_X31Y37,IO_L6N_T0_VREF_34
+J13,34,IOB_X0Y40,RIOB33_X31Y39,IO_L5P_T0_34
+J14,34,IOB_X0Y39,RIOB33_X31Y39,IO_L5N_T0_34
+J15,34,IOB_X0Y42,RIOB33_X31Y41,IO_L4P_T0_34
+K1,502,IOPAD_X1Y17,PSS2_X13Y53,PS_DDR_A14_502
+K2,502,IOPAD_X1Y18,PSS2_X13Y53,PS_DDR_A13_502
+K3,502,IOPAD_X1Y131,PSS2_X13Y53,PS_DDR_ODT_502
+K11,34,IOB_X0Y28,RIOB33_X31Y27,IO_L11P_T1_SRCC_34
+K12,34,IOB_X0Y27,RIOB33_X31Y27,IO_L11N_T1_SRCC_34
+K13,34,IOB_X0Y30,RIOB33_X31Y29,IO_L10P_T1_34
+K15,34,IOB_X0Y41,RIOB33_X31Y41,IO_L4N_T0_34
+L2,502,IOPAD_X1Y15,PSS2_X13Y53,PS_DDR_A11_502
+L3,502,IOPAD_X1Y23,PSS2_X13Y53,PS_DDR_CKE_502
+L4,502,IOPAD_X1Y72,PSS2_X13Y53,PS_DDR_DRST_B_502
+L12,34,IOB_X0Y26,RIOB33_X31Y25,IO_L12P_T1_MRCC_34
+L13,34,IOB_X0Y29,RIOB33_X31Y29,IO_L10N_T1_34
+L14,34,IOB_X0Y32,RIOB33_X31Y31,IO_L9P_T1_DQS_34
+L15,34,IOB_X0Y34,RIOB33_X31Y33,IO_L8P_T1_34
+M1,502,IOPAD_X1Y6,PSS2_X13Y53,PS_DDR_A2_502
+M2,502,IOPAD_X1Y16,PSS2_X13Y53,PS_DDR_A12_502
+M4,502,IOPAD_X1Y7,PSS2_X13Y53,PS_DDR_A3_502
+M5,502,IOPAD_X1Y11,PSS2_X13Y53,PS_DDR_A7_502
+M6,502,IOPAD_X1Y19,PSS2_X13Y53,PS_DDR_BA0_502
+M9,34,IOB_X0Y12,RIOB33_X31Y11,IO_L19P_T3_34
+M10,34,IOB_X0Y8,RIOB33_X31Y7,IO_L21P_T3_DQS_34
+M11,34,IOB_X0Y7,RIOB33_X31Y7,IO_L21N_T3_DQS_34
+M12,34,IOB_X0Y25,RIOB33_X31Y25,IO_L12N_T1_MRCC_34
+M14,34,IOB_X0Y31,RIOB33_X31Y31,IO_L9N_T1_DQS_34
+M15,34,IOB_X0Y33,RIOB33_X31Y33,IO_L8N_T1_34
+N1,502,IOPAD_X1Y5,PSS2_X13Y53,PS_DDR_A1_502
+N2,502,IOPAD_X1Y24,PSS2_X13Y53,PS_DDR_CKN_502
+N3,502,IOPAD_X1Y25,PSS2_X13Y53,PS_DDR_CKP_502
+N4,502,IOPAD_X1Y13,PSS2_X13Y53,PS_DDR_A9_502
+N6,502,IOPAD_X1Y21,PSS2_X13Y53,PS_DDR_BA2_502
+N7,34,IOB_X0Y6,RIOB33_X31Y5,IO_L22P_T3_34
+N8,34,IOB_X0Y5,RIOB33_X31Y5,IO_L22N_T3_34
+N9,34,IOB_X0Y11,RIOB33_X31Y11,IO_L19N_T3_VREF_34
+N11,34,IOB_X0Y24,RIOB33_X31Y23,IO_L13P_T2_MRCC_34
+N12,34,IOB_X0Y23,RIOB33_X31Y23,IO_L13N_T2_MRCC_34
+N13,34,IOB_X0Y36,RIOB33_X31Y35,IO_L7P_T1_34
+N14,34,IOB_X0Y35,RIOB33_X31Y35,IO_L7N_T1_34
+P1,502,IOPAD_X1Y4,PSS2_X13Y53,PS_DDR_A0_502
+P3,502,IOPAD_X1Y8,PSS2_X13Y53,PS_DDR_A4_502
+P4,502,IOPAD_X1Y9,PSS2_X13Y53,PS_DDR_A5_502
+P5,502,IOPAD_X1Y10,PSS2_X13Y53,PS_DDR_A6_502
+P6,502,IOPAD_X1Y12,PSS2_X13Y53,PS_DDR_A8_502
+P8,34,IOB_X0Y4,RIOB33_X31Y3,IO_L23P_T3_34
+P9,34,IOB_X0Y3,RIOB33_X31Y3,IO_L23N_T3_34
+P10,34,IOB_X0Y2,RIOB33_X31Y1,IO_L24P_T3_34
+P11,34,IOB_X0Y18,RIOB33_X31Y17,IO_L16P_T2_34
+P13,34,IOB_X0Y14,RIOB33_X31Y13,IO_L18P_T2_34
+P14,34,IOB_X0Y13,RIOB33_X31Y13,IO_L18N_T2_34
+P15,34,IOB_X0Y20,RIOB33_X31Y19,IO_L15P_T2_DQS_34
+R1,502,IOPAD_X1Y20,PSS2_X13Y53,PS_DDR_BA1_502
+R2,502,IOPAD_X1Y27,PSS2_X13Y53,PS_DDR_CS_B_502
+R3,502,IOPAD_X1Y1,PSS2_X13Y53,PS_DDR_WE_B_502
+R5,502,IOPAD_X1Y22,PSS2_X13Y53,PS_DDR_CAS_B_502
+R6,502,IOPAD_X1Y133,PSS2_X13Y53,PS_DDR_RAS_B_502
+R7,34,IOB_X0Y10,RIOB33_X31Y9,IO_L20P_T3_34
+R8,34,IOB_X0Y9,RIOB33_X31Y9,IO_L20N_T3_34
+R10,34,IOB_X0Y1,RIOB33_X31Y1,IO_L24N_T3_34
+R11,34,IOB_X0Y17,RIOB33_X31Y17,IO_L16N_T2_34
+R12,34,IOB_X0Y16,RIOB33_X31Y15,IO_L17P_T2_34
+R13,34,IOB_X0Y15,RIOB33_X31Y15,IO_L17N_T2_34
+R15,34,IOB_X0Y19,RIOB33_X31Y19,IO_L15N_T2_DQS_34
diff --git a/zynq7/xc7z010clg225-1/part.json b/zynq7/xc7z010clg225-1/part.json
new file mode 100644
index 0000000..8fa289f
--- /dev/null
+++ b/zynq7/xc7z010clg225-1/part.json
@@ -0,0 +1,407 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ },
+ "4": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 28
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 28
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 30
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 30
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 28
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 36
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 28
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 36
+ },
+ "49": {
+ "frame_count": 28
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 36
+ },
+ "52": {
+ "frame_count": 36
+ },
+ "53": {
+ "frame_count": 36
+ },
+ "54": {
+ "frame_count": 30
+ },
+ "55": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ },
+ "4": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 28
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 28
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 30
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 30
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 28
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 36
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 28
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 36
+ },
+ "49": {
+ "frame_count": 28
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 36
+ },
+ "52": {
+ "frame_count": 36
+ },
+ "53": {
+ "frame_count": 36
+ },
+ "54": {
+ "frame_count": 30
+ },
+ "55": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 57811091,
+ "iobanks": {
+ "34": "X126Y26",
+ "35": "X126Y78"
+ }
+}
diff --git a/zynq7/xc7z010clg225-1/part.yaml b/zynq7/xc7z010clg225-1/part.yaml
new file mode 100644
index 0000000..d03d585
--- /dev/null
+++ b/zynq7/xc7z010clg225-1/part.yaml
@@ -0,0 +1,263 @@
+!<xilinx/xc7series/part>
+idcode: 0x3722093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/zynq7/xc7z010clg225-2/package_pins.csv b/zynq7/xc7z010clg225-2/package_pins.csv
new file mode 100644
index 0000000..7745478
--- /dev/null
+++ b/zynq7/xc7z010clg225-2/package_pins.csv
@@ -0,0 +1,143 @@
+pin,bank,site,tile,pin_function
+A2,502,IOPAD_X1Y33,PSS2_X13Y53,PS_DDR_DQ1_502
+A3,502,IOPAD_X1Y39,PSS2_X13Y53,PS_DDR_DQ7_502
+A4,502,IOPAD_X1Y37,PSS2_X13Y53,PS_DDR_DQ5_502
+A5,500,IOPAD_X1Y78,PSS2_X13Y53,PS_MIO1_500
+A7,500,IOPAD_X1Y80,PSS2_X13Y53,PS_MIO3_500
+A8,500,IOPAD_X1Y79,PSS2_X13Y53,PS_MIO2_500
+A9,500,IOPAD_X1Y82,PSS2_X13Y53,PS_MIO5_500
+A10,500,IOPAD_X1Y83,PSS2_X13Y53,PS_MIO6_500
+A12,501,IOPAD_X1Y129,PSS2_X13Y53,PS_MIO52_501
+A13,501,IOPAD_X1Y115,PSS2_X13Y53,PS_MIO38_501
+A14,501,IOPAD_X1Y112,PSS2_X13Y53,PS_MIO35_501
+A15,501,IOPAD_X1Y105,PSS2_X13Y53,PS_MIO28_501
+B1,502,IOPAD_X1Y28,PSS2_X13Y53,PS_DDR_DM0_502
+B2,502,IOPAD_X1Y64,PSS2_X13Y53,PS_DDR_DQS_N0_502
+B4,502,IOPAD_X1Y36,PSS2_X13Y53,PS_DDR_DQ4_502
+B5,500,IOPAD_X1Y86,PSS2_X13Y53,PS_MIO9_500
+B6,500,IOPAD_X1Y85,PSS2_X13Y53,PS_MIO8_500
+B7,500,IOPAD_X1Y89,PSS2_X13Y53,PS_MIO12_500
+B9,500,IOPAD_X1Y91,PSS2_X13Y53,PS_MIO14_500
+B10,500,IOPAD_X1Y88,PSS2_X13Y53,PS_MIO11_500
+B11,501,IOPAD_X1Y134,PSS2_X13Y53,PS_SRST_B_501
+B12,501,IOPAD_X1Y125,PSS2_X13Y53,PS_MIO48_501
+B14,501,IOPAD_X1Y113,PSS2_X13Y53,PS_MIO36_501
+B15,501,IOPAD_X1Y107,PSS2_X13Y53,PS_MIO30_501
+C1,502,IOPAD_X1Y35,PSS2_X13Y53,PS_DDR_DQ3_502
+C2,502,IOPAD_X1Y68,PSS2_X13Y53,PS_DDR_DQS_P0_502
+C3,502,IOPAD_X1Y38,PSS2_X13Y53,PS_DDR_DQ6_502
+C4,502,IOPAD_X1Y34,PSS2_X13Y53,PS_DDR_DQ2_502
+C6,500,IOPAD_X1Y90,PSS2_X13Y53,PS_MIO13_500
+C7,500,IOPAD_X1Y26,PSS2_X13Y53,PS_CLK_500
+C8,500,IOPAD_X1Y81,PSS2_X13Y53,PS_MIO4_500
+C9,500,IOPAD_X1Y132,PSS2_X13Y53,PS_POR_B_500
+C11,501,IOPAD_X1Y110,PSS2_X13Y53,PS_MIO33_501
+C12,501,IOPAD_X1Y108,PSS2_X13Y53,PS_MIO31_501
+C13,501,IOPAD_X1Y130,PSS2_X13Y53,PS_MIO53_501
+C14,501,IOPAD_X1Y114,PSS2_X13Y53,PS_MIO37_501
+D1,502,IOPAD_X1Y41,PSS2_X13Y53,PS_DDR_DQ9_502
+D3,502,IOPAD_X1Y29,PSS2_X13Y53,PS_DDR_DM1_502
+D4,502,IOPAD_X1Y32,PSS2_X13Y53,PS_DDR_DQ0_502
+D6,500,IOPAD_X1Y87,PSS2_X13Y53,PS_MIO10_500
+D8,500,IOPAD_X1Y77,PSS2_X13Y53,PS_MIO0_500
+D9,500,IOPAD_X1Y84,PSS2_X13Y53,PS_MIO7_500
+D10,500,IOPAD_X1Y92,PSS2_X13Y53,PS_MIO15_500
+D11,501,IOPAD_X1Y106,PSS2_X13Y53,PS_MIO29_501
+D13,501,IOPAD_X1Y126,PSS2_X13Y53,PS_MIO49_501
+D14,501,IOPAD_X1Y116,PSS2_X13Y53,PS_MIO39_501
+D15,501,IOPAD_X1Y111,PSS2_X13Y53,PS_MIO34_501
+E1,502,IOPAD_X1Y40,PSS2_X13Y53,PS_DDR_DQ8_502
+E2,502,IOPAD_X1Y42,PSS2_X13Y53,PS_DDR_DQ10_502
+E3,502,IOPAD_X1Y43,PSS2_X13Y53,PS_DDR_DQ11_502
+E11,35,IOB_X0Y96,RIOB33_X31Y95,IO_L2P_T0_AD8P_35
+E12,35,IOB_X0Y95,RIOB33_X31Y95,IO_L2N_T0_AD8N_35
+E13,35,IOB_X0Y97,RIOB33_X31Y97,IO_L1N_T0_AD0N_35
+E15,501,IOPAD_X1Y109,PSS2_X13Y53,PS_MIO32_501
+F2,502,IOPAD_X1Y65,PSS2_X13Y53,PS_DDR_DQS_N1_502
+F3,502,IOPAD_X1Y44,PSS2_X13Y53,PS_DDR_DQ12_502
+F12,35,IOB_X0Y98,RIOB33_X31Y97,IO_L1P_T0_AD0P_35
+F13,35,IOB_X0Y94,RIOB33_X31Y93,IO_L3P_T0_DQS_AD1P_35
+F14,35,IOB_X0Y93,RIOB33_X31Y93,IO_L3N_T0_DQS_AD1N_35
+F15,35,IOB_X0Y89,RIOB33_X31Y89,IO_L5N_T0_AD9N_35
+G1,502,IOPAD_X1Y45,PSS2_X13Y53,PS_DDR_DQ13_502
+G2,502,IOPAD_X1Y69,PSS2_X13Y53,PS_DDR_DQS_P1_502
+G7,0,IPAD_X0Y0,MONITOR_BOT_PELE1_X67Y79,VP_0
+G11,34,IOB_X0Y48,RIOB33_X31Y47,IO_L1P_T0_34
+G12,34,IOB_X0Y46,RIOB33_X31Y45,IO_L2P_T0_34
+G14,34,IOB_X0Y44,RIOB33_X31Y43,IO_L3P_T0_DQS_PUDC_B_34
+G15,35,IOB_X0Y90,RIOB33_X31Y89,IO_L5P_T0_AD9P_35
+H1,502,IOPAD_X1Y46,PSS2_X13Y53,PS_DDR_DQ14_502
+H2,502,IOPAD_X1Y47,PSS2_X13Y53,PS_DDR_DQ15_502
+H3,502,IOPAD_X1Y3,PSS2_X13Y53,PS_DDR_VRP_502
+H8,0,IPAD_X0Y1,MONITOR_BOT_PELE1_X67Y79,VN_0
+H11,34,IOB_X0Y38,RIOB33_X31Y37,IO_L6P_T0_34
+H12,34,IOB_X0Y47,RIOB33_X31Y47,IO_L1N_T0_34
+H13,34,IOB_X0Y45,RIOB33_X31Y45,IO_L2N_T0_34
+H14,34,IOB_X0Y43,RIOB33_X31Y43,IO_L3N_T0_DQS_34
+J1,502,IOPAD_X1Y14,PSS2_X13Y53,PS_DDR_A10_502
+J3,502,IOPAD_X1Y2,PSS2_X13Y53,PS_DDR_VRN_502
+J11,34,IOB_X0Y37,RIOB33_X31Y37,IO_L6N_T0_VREF_34
+J13,34,IOB_X0Y40,RIOB33_X31Y39,IO_L5P_T0_34
+J14,34,IOB_X0Y39,RIOB33_X31Y39,IO_L5N_T0_34
+J15,34,IOB_X0Y42,RIOB33_X31Y41,IO_L4P_T0_34
+K1,502,IOPAD_X1Y17,PSS2_X13Y53,PS_DDR_A14_502
+K2,502,IOPAD_X1Y18,PSS2_X13Y53,PS_DDR_A13_502
+K3,502,IOPAD_X1Y131,PSS2_X13Y53,PS_DDR_ODT_502
+K11,34,IOB_X0Y28,RIOB33_X31Y27,IO_L11P_T1_SRCC_34
+K12,34,IOB_X0Y27,RIOB33_X31Y27,IO_L11N_T1_SRCC_34
+K13,34,IOB_X0Y30,RIOB33_X31Y29,IO_L10P_T1_34
+K15,34,IOB_X0Y41,RIOB33_X31Y41,IO_L4N_T0_34
+L2,502,IOPAD_X1Y15,PSS2_X13Y53,PS_DDR_A11_502
+L3,502,IOPAD_X1Y23,PSS2_X13Y53,PS_DDR_CKE_502
+L4,502,IOPAD_X1Y72,PSS2_X13Y53,PS_DDR_DRST_B_502
+L12,34,IOB_X0Y26,RIOB33_X31Y25,IO_L12P_T1_MRCC_34
+L13,34,IOB_X0Y29,RIOB33_X31Y29,IO_L10N_T1_34
+L14,34,IOB_X0Y32,RIOB33_X31Y31,IO_L9P_T1_DQS_34
+L15,34,IOB_X0Y34,RIOB33_X31Y33,IO_L8P_T1_34
+M1,502,IOPAD_X1Y6,PSS2_X13Y53,PS_DDR_A2_502
+M2,502,IOPAD_X1Y16,PSS2_X13Y53,PS_DDR_A12_502
+M4,502,IOPAD_X1Y7,PSS2_X13Y53,PS_DDR_A3_502
+M5,502,IOPAD_X1Y11,PSS2_X13Y53,PS_DDR_A7_502
+M6,502,IOPAD_X1Y19,PSS2_X13Y53,PS_DDR_BA0_502
+M9,34,IOB_X0Y12,RIOB33_X31Y11,IO_L19P_T3_34
+M10,34,IOB_X0Y8,RIOB33_X31Y7,IO_L21P_T3_DQS_34
+M11,34,IOB_X0Y7,RIOB33_X31Y7,IO_L21N_T3_DQS_34
+M12,34,IOB_X0Y25,RIOB33_X31Y25,IO_L12N_T1_MRCC_34
+M14,34,IOB_X0Y31,RIOB33_X31Y31,IO_L9N_T1_DQS_34
+M15,34,IOB_X0Y33,RIOB33_X31Y33,IO_L8N_T1_34
+N1,502,IOPAD_X1Y5,PSS2_X13Y53,PS_DDR_A1_502
+N2,502,IOPAD_X1Y24,PSS2_X13Y53,PS_DDR_CKN_502
+N3,502,IOPAD_X1Y25,PSS2_X13Y53,PS_DDR_CKP_502
+N4,502,IOPAD_X1Y13,PSS2_X13Y53,PS_DDR_A9_502
+N6,502,IOPAD_X1Y21,PSS2_X13Y53,PS_DDR_BA2_502
+N7,34,IOB_X0Y6,RIOB33_X31Y5,IO_L22P_T3_34
+N8,34,IOB_X0Y5,RIOB33_X31Y5,IO_L22N_T3_34
+N9,34,IOB_X0Y11,RIOB33_X31Y11,IO_L19N_T3_VREF_34
+N11,34,IOB_X0Y24,RIOB33_X31Y23,IO_L13P_T2_MRCC_34
+N12,34,IOB_X0Y23,RIOB33_X31Y23,IO_L13N_T2_MRCC_34
+N13,34,IOB_X0Y36,RIOB33_X31Y35,IO_L7P_T1_34
+N14,34,IOB_X0Y35,RIOB33_X31Y35,IO_L7N_T1_34
+P1,502,IOPAD_X1Y4,PSS2_X13Y53,PS_DDR_A0_502
+P3,502,IOPAD_X1Y8,PSS2_X13Y53,PS_DDR_A4_502
+P4,502,IOPAD_X1Y9,PSS2_X13Y53,PS_DDR_A5_502
+P5,502,IOPAD_X1Y10,PSS2_X13Y53,PS_DDR_A6_502
+P6,502,IOPAD_X1Y12,PSS2_X13Y53,PS_DDR_A8_502
+P8,34,IOB_X0Y4,RIOB33_X31Y3,IO_L23P_T3_34
+P9,34,IOB_X0Y3,RIOB33_X31Y3,IO_L23N_T3_34
+P10,34,IOB_X0Y2,RIOB33_X31Y1,IO_L24P_T3_34
+P11,34,IOB_X0Y18,RIOB33_X31Y17,IO_L16P_T2_34
+P13,34,IOB_X0Y14,RIOB33_X31Y13,IO_L18P_T2_34
+P14,34,IOB_X0Y13,RIOB33_X31Y13,IO_L18N_T2_34
+P15,34,IOB_X0Y20,RIOB33_X31Y19,IO_L15P_T2_DQS_34
+R1,502,IOPAD_X1Y20,PSS2_X13Y53,PS_DDR_BA1_502
+R2,502,IOPAD_X1Y27,PSS2_X13Y53,PS_DDR_CS_B_502
+R3,502,IOPAD_X1Y1,PSS2_X13Y53,PS_DDR_WE_B_502
+R5,502,IOPAD_X1Y22,PSS2_X13Y53,PS_DDR_CAS_B_502
+R6,502,IOPAD_X1Y133,PSS2_X13Y53,PS_DDR_RAS_B_502
+R7,34,IOB_X0Y10,RIOB33_X31Y9,IO_L20P_T3_34
+R8,34,IOB_X0Y9,RIOB33_X31Y9,IO_L20N_T3_34
+R10,34,IOB_X0Y1,RIOB33_X31Y1,IO_L24N_T3_34
+R11,34,IOB_X0Y17,RIOB33_X31Y17,IO_L16N_T2_34
+R12,34,IOB_X0Y16,RIOB33_X31Y15,IO_L17P_T2_34
+R13,34,IOB_X0Y15,RIOB33_X31Y15,IO_L17N_T2_34
+R15,34,IOB_X0Y19,RIOB33_X31Y19,IO_L15N_T2_DQS_34
diff --git a/zynq7/xc7z010clg225-2/part.json b/zynq7/xc7z010clg225-2/part.json
new file mode 100644
index 0000000..8fa289f
--- /dev/null
+++ b/zynq7/xc7z010clg225-2/part.json
@@ -0,0 +1,407 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ },
+ "4": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 28
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 28
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 30
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 30
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 28
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 36
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 28
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 36
+ },
+ "49": {
+ "frame_count": 28
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 36
+ },
+ "52": {
+ "frame_count": 36
+ },
+ "53": {
+ "frame_count": 36
+ },
+ "54": {
+ "frame_count": 30
+ },
+ "55": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ },
+ "4": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 28
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 28
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 30
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 30
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 28
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 36
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 28
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 36
+ },
+ "49": {
+ "frame_count": 28
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 36
+ },
+ "52": {
+ "frame_count": 36
+ },
+ "53": {
+ "frame_count": 36
+ },
+ "54": {
+ "frame_count": 30
+ },
+ "55": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 57811091,
+ "iobanks": {
+ "34": "X126Y26",
+ "35": "X126Y78"
+ }
+}
diff --git a/zynq7/xc7z010clg225-2/part.yaml b/zynq7/xc7z010clg225-2/part.yaml
new file mode 100644
index 0000000..d03d585
--- /dev/null
+++ b/zynq7/xc7z010clg225-2/part.yaml
@@ -0,0 +1,263 @@
+!<xilinx/xc7series/part>
+idcode: 0x3722093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/zynq7/xc7z010clg225-3/package_pins.csv b/zynq7/xc7z010clg225-3/package_pins.csv
new file mode 100644
index 0000000..7745478
--- /dev/null
+++ b/zynq7/xc7z010clg225-3/package_pins.csv
@@ -0,0 +1,143 @@
+pin,bank,site,tile,pin_function
+A2,502,IOPAD_X1Y33,PSS2_X13Y53,PS_DDR_DQ1_502
+A3,502,IOPAD_X1Y39,PSS2_X13Y53,PS_DDR_DQ7_502
+A4,502,IOPAD_X1Y37,PSS2_X13Y53,PS_DDR_DQ5_502
+A5,500,IOPAD_X1Y78,PSS2_X13Y53,PS_MIO1_500
+A7,500,IOPAD_X1Y80,PSS2_X13Y53,PS_MIO3_500
+A8,500,IOPAD_X1Y79,PSS2_X13Y53,PS_MIO2_500
+A9,500,IOPAD_X1Y82,PSS2_X13Y53,PS_MIO5_500
+A10,500,IOPAD_X1Y83,PSS2_X13Y53,PS_MIO6_500
+A12,501,IOPAD_X1Y129,PSS2_X13Y53,PS_MIO52_501
+A13,501,IOPAD_X1Y115,PSS2_X13Y53,PS_MIO38_501
+A14,501,IOPAD_X1Y112,PSS2_X13Y53,PS_MIO35_501
+A15,501,IOPAD_X1Y105,PSS2_X13Y53,PS_MIO28_501
+B1,502,IOPAD_X1Y28,PSS2_X13Y53,PS_DDR_DM0_502
+B2,502,IOPAD_X1Y64,PSS2_X13Y53,PS_DDR_DQS_N0_502
+B4,502,IOPAD_X1Y36,PSS2_X13Y53,PS_DDR_DQ4_502
+B5,500,IOPAD_X1Y86,PSS2_X13Y53,PS_MIO9_500
+B6,500,IOPAD_X1Y85,PSS2_X13Y53,PS_MIO8_500
+B7,500,IOPAD_X1Y89,PSS2_X13Y53,PS_MIO12_500
+B9,500,IOPAD_X1Y91,PSS2_X13Y53,PS_MIO14_500
+B10,500,IOPAD_X1Y88,PSS2_X13Y53,PS_MIO11_500
+B11,501,IOPAD_X1Y134,PSS2_X13Y53,PS_SRST_B_501
+B12,501,IOPAD_X1Y125,PSS2_X13Y53,PS_MIO48_501
+B14,501,IOPAD_X1Y113,PSS2_X13Y53,PS_MIO36_501
+B15,501,IOPAD_X1Y107,PSS2_X13Y53,PS_MIO30_501
+C1,502,IOPAD_X1Y35,PSS2_X13Y53,PS_DDR_DQ3_502
+C2,502,IOPAD_X1Y68,PSS2_X13Y53,PS_DDR_DQS_P0_502
+C3,502,IOPAD_X1Y38,PSS2_X13Y53,PS_DDR_DQ6_502
+C4,502,IOPAD_X1Y34,PSS2_X13Y53,PS_DDR_DQ2_502
+C6,500,IOPAD_X1Y90,PSS2_X13Y53,PS_MIO13_500
+C7,500,IOPAD_X1Y26,PSS2_X13Y53,PS_CLK_500
+C8,500,IOPAD_X1Y81,PSS2_X13Y53,PS_MIO4_500
+C9,500,IOPAD_X1Y132,PSS2_X13Y53,PS_POR_B_500
+C11,501,IOPAD_X1Y110,PSS2_X13Y53,PS_MIO33_501
+C12,501,IOPAD_X1Y108,PSS2_X13Y53,PS_MIO31_501
+C13,501,IOPAD_X1Y130,PSS2_X13Y53,PS_MIO53_501
+C14,501,IOPAD_X1Y114,PSS2_X13Y53,PS_MIO37_501
+D1,502,IOPAD_X1Y41,PSS2_X13Y53,PS_DDR_DQ9_502
+D3,502,IOPAD_X1Y29,PSS2_X13Y53,PS_DDR_DM1_502
+D4,502,IOPAD_X1Y32,PSS2_X13Y53,PS_DDR_DQ0_502
+D6,500,IOPAD_X1Y87,PSS2_X13Y53,PS_MIO10_500
+D8,500,IOPAD_X1Y77,PSS2_X13Y53,PS_MIO0_500
+D9,500,IOPAD_X1Y84,PSS2_X13Y53,PS_MIO7_500
+D10,500,IOPAD_X1Y92,PSS2_X13Y53,PS_MIO15_500
+D11,501,IOPAD_X1Y106,PSS2_X13Y53,PS_MIO29_501
+D13,501,IOPAD_X1Y126,PSS2_X13Y53,PS_MIO49_501
+D14,501,IOPAD_X1Y116,PSS2_X13Y53,PS_MIO39_501
+D15,501,IOPAD_X1Y111,PSS2_X13Y53,PS_MIO34_501
+E1,502,IOPAD_X1Y40,PSS2_X13Y53,PS_DDR_DQ8_502
+E2,502,IOPAD_X1Y42,PSS2_X13Y53,PS_DDR_DQ10_502
+E3,502,IOPAD_X1Y43,PSS2_X13Y53,PS_DDR_DQ11_502
+E11,35,IOB_X0Y96,RIOB33_X31Y95,IO_L2P_T0_AD8P_35
+E12,35,IOB_X0Y95,RIOB33_X31Y95,IO_L2N_T0_AD8N_35
+E13,35,IOB_X0Y97,RIOB33_X31Y97,IO_L1N_T0_AD0N_35
+E15,501,IOPAD_X1Y109,PSS2_X13Y53,PS_MIO32_501
+F2,502,IOPAD_X1Y65,PSS2_X13Y53,PS_DDR_DQS_N1_502
+F3,502,IOPAD_X1Y44,PSS2_X13Y53,PS_DDR_DQ12_502
+F12,35,IOB_X0Y98,RIOB33_X31Y97,IO_L1P_T0_AD0P_35
+F13,35,IOB_X0Y94,RIOB33_X31Y93,IO_L3P_T0_DQS_AD1P_35
+F14,35,IOB_X0Y93,RIOB33_X31Y93,IO_L3N_T0_DQS_AD1N_35
+F15,35,IOB_X0Y89,RIOB33_X31Y89,IO_L5N_T0_AD9N_35
+G1,502,IOPAD_X1Y45,PSS2_X13Y53,PS_DDR_DQ13_502
+G2,502,IOPAD_X1Y69,PSS2_X13Y53,PS_DDR_DQS_P1_502
+G7,0,IPAD_X0Y0,MONITOR_BOT_PELE1_X67Y79,VP_0
+G11,34,IOB_X0Y48,RIOB33_X31Y47,IO_L1P_T0_34
+G12,34,IOB_X0Y46,RIOB33_X31Y45,IO_L2P_T0_34
+G14,34,IOB_X0Y44,RIOB33_X31Y43,IO_L3P_T0_DQS_PUDC_B_34
+G15,35,IOB_X0Y90,RIOB33_X31Y89,IO_L5P_T0_AD9P_35
+H1,502,IOPAD_X1Y46,PSS2_X13Y53,PS_DDR_DQ14_502
+H2,502,IOPAD_X1Y47,PSS2_X13Y53,PS_DDR_DQ15_502
+H3,502,IOPAD_X1Y3,PSS2_X13Y53,PS_DDR_VRP_502
+H8,0,IPAD_X0Y1,MONITOR_BOT_PELE1_X67Y79,VN_0
+H11,34,IOB_X0Y38,RIOB33_X31Y37,IO_L6P_T0_34
+H12,34,IOB_X0Y47,RIOB33_X31Y47,IO_L1N_T0_34
+H13,34,IOB_X0Y45,RIOB33_X31Y45,IO_L2N_T0_34
+H14,34,IOB_X0Y43,RIOB33_X31Y43,IO_L3N_T0_DQS_34
+J1,502,IOPAD_X1Y14,PSS2_X13Y53,PS_DDR_A10_502
+J3,502,IOPAD_X1Y2,PSS2_X13Y53,PS_DDR_VRN_502
+J11,34,IOB_X0Y37,RIOB33_X31Y37,IO_L6N_T0_VREF_34
+J13,34,IOB_X0Y40,RIOB33_X31Y39,IO_L5P_T0_34
+J14,34,IOB_X0Y39,RIOB33_X31Y39,IO_L5N_T0_34
+J15,34,IOB_X0Y42,RIOB33_X31Y41,IO_L4P_T0_34
+K1,502,IOPAD_X1Y17,PSS2_X13Y53,PS_DDR_A14_502
+K2,502,IOPAD_X1Y18,PSS2_X13Y53,PS_DDR_A13_502
+K3,502,IOPAD_X1Y131,PSS2_X13Y53,PS_DDR_ODT_502
+K11,34,IOB_X0Y28,RIOB33_X31Y27,IO_L11P_T1_SRCC_34
+K12,34,IOB_X0Y27,RIOB33_X31Y27,IO_L11N_T1_SRCC_34
+K13,34,IOB_X0Y30,RIOB33_X31Y29,IO_L10P_T1_34
+K15,34,IOB_X0Y41,RIOB33_X31Y41,IO_L4N_T0_34
+L2,502,IOPAD_X1Y15,PSS2_X13Y53,PS_DDR_A11_502
+L3,502,IOPAD_X1Y23,PSS2_X13Y53,PS_DDR_CKE_502
+L4,502,IOPAD_X1Y72,PSS2_X13Y53,PS_DDR_DRST_B_502
+L12,34,IOB_X0Y26,RIOB33_X31Y25,IO_L12P_T1_MRCC_34
+L13,34,IOB_X0Y29,RIOB33_X31Y29,IO_L10N_T1_34
+L14,34,IOB_X0Y32,RIOB33_X31Y31,IO_L9P_T1_DQS_34
+L15,34,IOB_X0Y34,RIOB33_X31Y33,IO_L8P_T1_34
+M1,502,IOPAD_X1Y6,PSS2_X13Y53,PS_DDR_A2_502
+M2,502,IOPAD_X1Y16,PSS2_X13Y53,PS_DDR_A12_502
+M4,502,IOPAD_X1Y7,PSS2_X13Y53,PS_DDR_A3_502
+M5,502,IOPAD_X1Y11,PSS2_X13Y53,PS_DDR_A7_502
+M6,502,IOPAD_X1Y19,PSS2_X13Y53,PS_DDR_BA0_502
+M9,34,IOB_X0Y12,RIOB33_X31Y11,IO_L19P_T3_34
+M10,34,IOB_X0Y8,RIOB33_X31Y7,IO_L21P_T3_DQS_34
+M11,34,IOB_X0Y7,RIOB33_X31Y7,IO_L21N_T3_DQS_34
+M12,34,IOB_X0Y25,RIOB33_X31Y25,IO_L12N_T1_MRCC_34
+M14,34,IOB_X0Y31,RIOB33_X31Y31,IO_L9N_T1_DQS_34
+M15,34,IOB_X0Y33,RIOB33_X31Y33,IO_L8N_T1_34
+N1,502,IOPAD_X1Y5,PSS2_X13Y53,PS_DDR_A1_502
+N2,502,IOPAD_X1Y24,PSS2_X13Y53,PS_DDR_CKN_502
+N3,502,IOPAD_X1Y25,PSS2_X13Y53,PS_DDR_CKP_502
+N4,502,IOPAD_X1Y13,PSS2_X13Y53,PS_DDR_A9_502
+N6,502,IOPAD_X1Y21,PSS2_X13Y53,PS_DDR_BA2_502
+N7,34,IOB_X0Y6,RIOB33_X31Y5,IO_L22P_T3_34
+N8,34,IOB_X0Y5,RIOB33_X31Y5,IO_L22N_T3_34
+N9,34,IOB_X0Y11,RIOB33_X31Y11,IO_L19N_T3_VREF_34
+N11,34,IOB_X0Y24,RIOB33_X31Y23,IO_L13P_T2_MRCC_34
+N12,34,IOB_X0Y23,RIOB33_X31Y23,IO_L13N_T2_MRCC_34
+N13,34,IOB_X0Y36,RIOB33_X31Y35,IO_L7P_T1_34
+N14,34,IOB_X0Y35,RIOB33_X31Y35,IO_L7N_T1_34
+P1,502,IOPAD_X1Y4,PSS2_X13Y53,PS_DDR_A0_502
+P3,502,IOPAD_X1Y8,PSS2_X13Y53,PS_DDR_A4_502
+P4,502,IOPAD_X1Y9,PSS2_X13Y53,PS_DDR_A5_502
+P5,502,IOPAD_X1Y10,PSS2_X13Y53,PS_DDR_A6_502
+P6,502,IOPAD_X1Y12,PSS2_X13Y53,PS_DDR_A8_502
+P8,34,IOB_X0Y4,RIOB33_X31Y3,IO_L23P_T3_34
+P9,34,IOB_X0Y3,RIOB33_X31Y3,IO_L23N_T3_34
+P10,34,IOB_X0Y2,RIOB33_X31Y1,IO_L24P_T3_34
+P11,34,IOB_X0Y18,RIOB33_X31Y17,IO_L16P_T2_34
+P13,34,IOB_X0Y14,RIOB33_X31Y13,IO_L18P_T2_34
+P14,34,IOB_X0Y13,RIOB33_X31Y13,IO_L18N_T2_34
+P15,34,IOB_X0Y20,RIOB33_X31Y19,IO_L15P_T2_DQS_34
+R1,502,IOPAD_X1Y20,PSS2_X13Y53,PS_DDR_BA1_502
+R2,502,IOPAD_X1Y27,PSS2_X13Y53,PS_DDR_CS_B_502
+R3,502,IOPAD_X1Y1,PSS2_X13Y53,PS_DDR_WE_B_502
+R5,502,IOPAD_X1Y22,PSS2_X13Y53,PS_DDR_CAS_B_502
+R6,502,IOPAD_X1Y133,PSS2_X13Y53,PS_DDR_RAS_B_502
+R7,34,IOB_X0Y10,RIOB33_X31Y9,IO_L20P_T3_34
+R8,34,IOB_X0Y9,RIOB33_X31Y9,IO_L20N_T3_34
+R10,34,IOB_X0Y1,RIOB33_X31Y1,IO_L24N_T3_34
+R11,34,IOB_X0Y17,RIOB33_X31Y17,IO_L16N_T2_34
+R12,34,IOB_X0Y16,RIOB33_X31Y15,IO_L17P_T2_34
+R13,34,IOB_X0Y15,RIOB33_X31Y15,IO_L17N_T2_34
+R15,34,IOB_X0Y19,RIOB33_X31Y19,IO_L15N_T2_DQS_34
diff --git a/zynq7/xc7z010clg225-3/part.json b/zynq7/xc7z010clg225-3/part.json
new file mode 100644
index 0000000..8fa289f
--- /dev/null
+++ b/zynq7/xc7z010clg225-3/part.json
@@ -0,0 +1,407 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ },
+ "4": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 28
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 28
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 30
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 30
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 28
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 36
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 28
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 36
+ },
+ "49": {
+ "frame_count": 28
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 36
+ },
+ "52": {
+ "frame_count": 36
+ },
+ "53": {
+ "frame_count": 36
+ },
+ "54": {
+ "frame_count": 30
+ },
+ "55": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ },
+ "4": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 28
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 28
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 30
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 30
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 28
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 36
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 28
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 36
+ },
+ "49": {
+ "frame_count": 28
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 36
+ },
+ "52": {
+ "frame_count": 36
+ },
+ "53": {
+ "frame_count": 36
+ },
+ "54": {
+ "frame_count": 30
+ },
+ "55": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 57811091,
+ "iobanks": {
+ "34": "X126Y26",
+ "35": "X126Y78"
+ }
+}
diff --git a/zynq7/xc7z010clg225-3/part.yaml b/zynq7/xc7z010clg225-3/part.yaml
new file mode 100644
index 0000000..d03d585
--- /dev/null
+++ b/zynq7/xc7z010clg225-3/part.yaml
@@ -0,0 +1,263 @@
+!<xilinx/xc7series/part>
+idcode: 0x3722093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/zynq7/xc7z010clg400-2/package_pins.csv b/zynq7/xc7z010clg400-2/package_pins.csv
new file mode 100644
index 0000000..b2220e7
--- /dev/null
+++ b/zynq7/xc7z010clg400-2/package_pins.csv
@@ -0,0 +1,233 @@
+pin,bank,site,tile,pin_function
+A1,502,IOPAD_X1Y28,PSS2_X13Y53,PS_DDR_DM0_502
+A2,502,IOPAD_X1Y34,PSS2_X13Y53,PS_DDR_DQ2_502
+A4,502,IOPAD_X1Y35,PSS2_X13Y53,PS_DDR_DQ3_502
+A5,500,IOPAD_X1Y83,PSS2_X13Y53,PS_MIO6_500
+A6,500,IOPAD_X1Y82,PSS2_X13Y53,PS_MIO5_500
+A7,500,IOPAD_X1Y78,PSS2_X13Y53,PS_MIO1_500
+A9,501,IOPAD_X1Y120,PSS2_X13Y53,PS_MIO43_501
+A10,501,IOPAD_X1Y114,PSS2_X13Y53,PS_MIO37_501
+A11,501,IOPAD_X1Y113,PSS2_X13Y53,PS_MIO36_501
+A12,501,IOPAD_X1Y111,PSS2_X13Y53,PS_MIO34_501
+A14,501,IOPAD_X1Y109,PSS2_X13Y53,PS_MIO32_501
+A15,501,IOPAD_X1Y103,PSS2_X13Y53,PS_MIO26_501
+A16,501,IOPAD_X1Y101,PSS2_X13Y53,PS_MIO24_501
+A17,501,IOPAD_X1Y97,PSS2_X13Y53,PS_MIO20_501
+A19,501,IOPAD_X1Y93,PSS2_X13Y53,PS_MIO16_501
+A20,35,IOB_X0Y95,RIOB33_X31Y95,IO_L2N_T0_AD8N_35
+B2,502,IOPAD_X1Y64,PSS2_X13Y53,PS_DDR_DQS_N0_502
+B3,502,IOPAD_X1Y33,PSS2_X13Y53,PS_DDR_DQ1_502
+B4,502,IOPAD_X1Y72,PSS2_X13Y53,PS_DDR_DRST_B_502
+B5,500,IOPAD_X1Y86,PSS2_X13Y53,PS_MIO9_500
+B7,500,IOPAD_X1Y81,PSS2_X13Y53,PS_MIO4_500
+B8,500,IOPAD_X1Y79,PSS2_X13Y53,PS_MIO2_500
+B9,501,IOPAD_X1Y128,PSS2_X13Y53,PS_MIO51_501
+B10,501,IOPAD_X1Y134,PSS2_X13Y53,PS_SRST_B_501
+B12,501,IOPAD_X1Y125,PSS2_X13Y53,PS_MIO48_501
+B13,501,IOPAD_X1Y127,PSS2_X13Y53,PS_MIO50_501
+B14,501,IOPAD_X1Y124,PSS2_X13Y53,PS_MIO47_501
+B15,501,IOPAD_X1Y122,PSS2_X13Y53,PS_MIO45_501
+B17,501,IOPAD_X1Y99,PSS2_X13Y53,PS_MIO22_501
+B18,501,IOPAD_X1Y95,PSS2_X13Y53,PS_MIO18_501
+B19,35,IOB_X0Y96,RIOB33_X31Y95,IO_L2P_T0_AD8P_35
+B20,35,IOB_X0Y97,RIOB33_X31Y97,IO_L1N_T0_AD0N_35
+C1,502,IOPAD_X1Y38,PSS2_X13Y53,PS_DDR_DQ6_502
+C2,502,IOPAD_X1Y68,PSS2_X13Y53,PS_DDR_DQS_P0_502
+C3,502,IOPAD_X1Y32,PSS2_X13Y53,PS_DDR_DQ0_502
+C5,500,IOPAD_X1Y91,PSS2_X13Y53,PS_MIO14_500
+C6,500,IOPAD_X1Y88,PSS2_X13Y53,PS_MIO11_500
+C7,500,IOPAD_X1Y132,PSS2_X13Y53,PS_POR_B_500
+C8,500,IOPAD_X1Y92,PSS2_X13Y53,PS_MIO15_500
+C10,501,IOPAD_X1Y129,PSS2_X13Y53,PS_MIO52_501
+C11,501,IOPAD_X1Y130,PSS2_X13Y53,PS_MIO53_501
+C12,501,IOPAD_X1Y126,PSS2_X13Y53,PS_MIO49_501
+C13,501,IOPAD_X1Y106,PSS2_X13Y53,PS_MIO29_501
+C15,501,IOPAD_X1Y107,PSS2_X13Y53,PS_MIO30_501
+C16,501,IOPAD_X1Y105,PSS2_X13Y53,PS_MIO28_501
+C17,501,IOPAD_X1Y118,PSS2_X13Y53,PS_MIO41_501
+C18,501,IOPAD_X1Y116,PSS2_X13Y53,PS_MIO39_501
+C20,35,IOB_X0Y98,RIOB33_X31Y97,IO_L1P_T0_AD0P_35
+D1,502,IOPAD_X1Y37,PSS2_X13Y53,PS_DDR_DQ5_502
+D3,502,IOPAD_X1Y36,PSS2_X13Y53,PS_DDR_DQ4_502
+D4,502,IOPAD_X1Y18,PSS2_X13Y53,PS_DDR_A13_502
+D5,500,IOPAD_X1Y85,PSS2_X13Y53,PS_MIO8_500
+D6,500,IOPAD_X1Y80,PSS2_X13Y53,PS_MIO3_500
+D8,500,IOPAD_X1Y84,PSS2_X13Y53,PS_MIO7_500
+D9,500,IOPAD_X1Y89,PSS2_X13Y53,PS_MIO12_500
+D10,501,IOPAD_X1Y96,PSS2_X13Y53,PS_MIO19_501
+D11,501,IOPAD_X1Y100,PSS2_X13Y53,PS_MIO23_501
+D13,501,IOPAD_X1Y104,PSS2_X13Y53,PS_MIO27_501
+D14,501,IOPAD_X1Y117,PSS2_X13Y53,PS_MIO40_501
+D15,501,IOPAD_X1Y110,PSS2_X13Y53,PS_MIO33_501
+D16,501,IOPAD_X1Y123,PSS2_X13Y53,PS_MIO46_501
+D18,35,IOB_X0Y93,RIOB33_X31Y93,IO_L3N_T0_DQS_AD1N_35
+D19,35,IOB_X0Y92,RIOB33_X31Y91,IO_L4P_T0_35
+D20,35,IOB_X0Y91,RIOB33_X31Y91,IO_L4N_T0_35
+E1,502,IOPAD_X1Y39,PSS2_X13Y53,PS_DDR_DQ7_502
+E2,502,IOPAD_X1Y40,PSS2_X13Y53,PS_DDR_DQ8_502
+E3,502,IOPAD_X1Y41,PSS2_X13Y53,PS_DDR_DQ9_502
+E4,502,IOPAD_X1Y16,PSS2_X13Y53,PS_DDR_A12_502
+E6,500,IOPAD_X1Y77,PSS2_X13Y53,PS_MIO0_500
+E7,500,IOPAD_X1Y26,PSS2_X13Y53,PS_CLK_500
+E8,500,IOPAD_X1Y90,PSS2_X13Y53,PS_MIO13_500
+E9,500,IOPAD_X1Y87,PSS2_X13Y53,PS_MIO10_500
+E12,501,IOPAD_X1Y119,PSS2_X13Y53,PS_MIO42_501
+E13,501,IOPAD_X1Y115,PSS2_X13Y53,PS_MIO38_501
+E14,501,IOPAD_X1Y94,PSS2_X13Y53,PS_MIO17_501
+E16,501,IOPAD_X1Y108,PSS2_X13Y53,PS_MIO31_501
+E17,35,IOB_X0Y94,RIOB33_X31Y93,IO_L3P_T0_DQS_AD1P_35
+E18,35,IOB_X0Y90,RIOB33_X31Y89,IO_L5P_T0_AD9P_35
+E19,35,IOB_X0Y89,RIOB33_X31Y89,IO_L5N_T0_AD9N_35
+F1,502,IOPAD_X1Y29,PSS2_X13Y53,PS_DDR_DM1_502
+F2,502,IOPAD_X1Y65,PSS2_X13Y53,PS_DDR_DQS_N1_502
+F4,502,IOPAD_X1Y17,PSS2_X13Y53,PS_DDR_A14_502
+F5,502,IOPAD_X1Y14,PSS2_X13Y53,PS_DDR_A10_502
+F12,501,IOPAD_X1Y112,PSS2_X13Y53,PS_MIO35_501
+F13,501,IOPAD_X1Y121,PSS2_X13Y53,PS_MIO44_501
+F14,501,IOPAD_X1Y98,PSS2_X13Y53,PS_MIO21_501
+F15,501,IOPAD_X1Y102,PSS2_X13Y53,PS_MIO25_501
+F16,35,IOB_X0Y88,RIOB33_X31Y87,IO_L6P_T0_35
+F17,35,IOB_X0Y87,RIOB33_X31Y87,IO_L6N_T0_VREF_35
+F19,35,IOB_X0Y70,RIOB33_X31Y69,IO_L15P_T2_DQS_AD12P_35
+F20,35,IOB_X0Y69,RIOB33_X31Y69,IO_L15N_T2_DQS_AD12N_35
+G2,502,IOPAD_X1Y69,PSS2_X13Y53,PS_DDR_DQS_P1_502
+G3,502,IOPAD_X1Y42,PSS2_X13Y53,PS_DDR_DQ10_502
+G4,502,IOPAD_X1Y15,PSS2_X13Y53,PS_DDR_A11_502
+G5,502,IOPAD_X1Y2,PSS2_X13Y53,PS_DDR_VRN_502
+G14,35,IOB_X0Y99,RIOB33_SING_X31Y99,IO_0_35
+G15,35,IOB_X0Y61,RIOB33_X31Y61,IO_L19N_T3_VREF_35
+G17,35,IOB_X0Y68,RIOB33_X31Y67,IO_L16P_T2_35
+G18,35,IOB_X0Y67,RIOB33_X31Y67,IO_L16N_T2_35
+G19,35,IOB_X0Y64,RIOB33_X31Y63,IO_L18P_T2_AD13P_35
+G20,35,IOB_X0Y63,RIOB33_X31Y63,IO_L18N_T2_AD13N_35
+H1,502,IOPAD_X1Y46,PSS2_X13Y53,PS_DDR_DQ14_502
+H2,502,IOPAD_X1Y45,PSS2_X13Y53,PS_DDR_DQ13_502
+H3,502,IOPAD_X1Y43,PSS2_X13Y53,PS_DDR_DQ11_502
+H5,502,IOPAD_X1Y3,PSS2_X13Y53,PS_DDR_VRP_502
+H15,35,IOB_X0Y62,RIOB33_X31Y61,IO_L19P_T3_35
+H16,35,IOB_X0Y74,RIOB33_X31Y73,IO_L13P_T2_MRCC_35
+H17,35,IOB_X0Y73,RIOB33_X31Y73,IO_L13N_T2_MRCC_35
+H18,35,IOB_X0Y71,RIOB33_X31Y71,IO_L14N_T2_AD4N_SRCC_35
+H20,35,IOB_X0Y65,RIOB33_X31Y65,IO_L17N_T2_AD5N_35
+J1,502,IOPAD_X1Y47,PSS2_X13Y53,PS_DDR_DQ15_502
+J3,502,IOPAD_X1Y44,PSS2_X13Y53,PS_DDR_DQ12_502
+J4,502,IOPAD_X1Y13,PSS2_X13Y53,PS_DDR_A9_502
+J5,502,IOPAD_X1Y21,PSS2_X13Y53,PS_DDR_BA2_502
+J14,35,IOB_X0Y59,RIOB33_X31Y59,IO_L20N_T3_AD6N_35
+J15,35,IOB_X0Y50,RIOB33_SING_X31Y50,IO_25_35
+J16,35,IOB_X0Y51,RIOB33_X31Y51,IO_L24N_T3_AD15N_35
+J18,35,IOB_X0Y72,RIOB33_X31Y71,IO_L14P_T2_AD4P_SRCC_35
+J19,35,IOB_X0Y79,RIOB33_X31Y79,IO_L10N_T1_AD11N_35
+J20,35,IOB_X0Y66,RIOB33_X31Y65,IO_L17P_T2_AD5P_35
+K1,502,IOPAD_X1Y12,PSS2_X13Y53,PS_DDR_A8_502
+K2,502,IOPAD_X1Y5,PSS2_X13Y53,PS_DDR_A1_502
+K3,502,IOPAD_X1Y7,PSS2_X13Y53,PS_DDR_A3_502
+K4,502,IOPAD_X1Y11,PSS2_X13Y53,PS_DDR_A7_502
+K9,0,IPAD_X0Y0,MONITOR_BOT_PELE1_X67Y79,VP_0
+K14,35,IOB_X0Y60,RIOB33_X31Y59,IO_L20P_T3_AD6P_35
+K16,35,IOB_X0Y52,RIOB33_X31Y51,IO_L24P_T3_AD15P_35
+K17,35,IOB_X0Y76,RIOB33_X31Y75,IO_L12P_T1_MRCC_35
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+N3,502,IOPAD_X1Y23,PSS2_X13Y53,PS_DDR_CKE_502
+N5,502,IOPAD_X1Y131,PSS2_X13Y53,PS_DDR_ODT_502
+N15,35,IOB_X0Y58,RIOB33_X31Y57,IO_L21P_T3_DQS_AD14P_35
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+N17,34,IOB_X0Y4,RIOB33_X31Y3,IO_L23P_T3_34
+N18,34,IOB_X0Y24,RIOB33_X31Y23,IO_L13P_T2_MRCC_34
+N20,34,IOB_X0Y22,RIOB33_X31Y21,IO_L14P_T2_SRCC_34
+P1,502,IOPAD_X1Y48,PSS2_X13Y53,PS_DDR_DQ16_502
+P3,502,IOPAD_X1Y49,PSS2_X13Y53,PS_DDR_DQ17_502
+P4,502,IOPAD_X1Y133,PSS2_X13Y53,PS_DDR_RAS_B_502
+P5,502,IOPAD_X1Y22,PSS2_X13Y53,PS_DDR_CAS_B_502
+P14,34,IOB_X0Y38,RIOB33_X31Y37,IO_L6P_T0_34
+P15,34,IOB_X0Y2,RIOB33_X31Y1,IO_L24P_T3_34
+P16,34,IOB_X0Y1,RIOB33_X31Y1,IO_L24N_T3_34
+P18,34,IOB_X0Y3,RIOB33_X31Y3,IO_L23N_T3_34
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+P20,34,IOB_X0Y21,RIOB33_X31Y21,IO_L14N_T2_SRCC_34
+R1,502,IOPAD_X1Y51,PSS2_X13Y53,PS_DDR_DQ19_502
+R2,502,IOPAD_X1Y70,PSS2_X13Y53,PS_DDR_DQS_P2_502
+R3,502,IOPAD_X1Y50,PSS2_X13Y53,PS_DDR_DQ18_502
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+R14,34,IOB_X0Y37,RIOB33_X31Y37,IO_L6N_T0_VREF_34
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+R17,34,IOB_X0Y11,RIOB33_X31Y11,IO_L19N_T3_VREF_34
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+T17,34,IOB_X0Y10,RIOB33_X31Y9,IO_L20P_T3_34
+T19,34,IOB_X0Y0,RIOB33_SING_X31Y0,IO_25_34
+T20,34,IOB_X0Y20,RIOB33_X31Y19,IO_L15P_T2_DQS_34
+U2,502,IOPAD_X1Y54,PSS2_X13Y53,PS_DDR_DQ22_502
+U3,502,IOPAD_X1Y55,PSS2_X13Y53,PS_DDR_DQ23_502
+U4,502,IOPAD_X1Y53,PSS2_X13Y53,PS_DDR_DQ21_502
+U12,34,IOB_X0Y45,RIOB33_X31Y45,IO_L2N_T0_34
+U13,34,IOB_X0Y44,RIOB33_X31Y43,IO_L3P_T0_DQS_PUDC_B_34
+U14,34,IOB_X0Y28,RIOB33_X31Y27,IO_L11P_T1_SRCC_34
+U15,34,IOB_X0Y27,RIOB33_X31Y27,IO_L11N_T1_SRCC_34
+U17,34,IOB_X0Y31,RIOB33_X31Y31,IO_L9N_T1_DQS_34
+U18,34,IOB_X0Y26,RIOB33_X31Y25,IO_L12P_T1_MRCC_34
+U19,34,IOB_X0Y25,RIOB33_X31Y25,IO_L12N_T1_MRCC_34
+U20,34,IOB_X0Y19,RIOB33_X31Y19,IO_L15N_T2_DQS_34
+V1,502,IOPAD_X1Y56,PSS2_X13Y53,PS_DDR_DQ24_502
+V2,502,IOPAD_X1Y62,PSS2_X13Y53,PS_DDR_DQ30_502
+V3,502,IOPAD_X1Y63,PSS2_X13Y53,PS_DDR_DQ31_502
+V12,34,IOB_X0Y42,RIOB33_X31Y41,IO_L4P_T0_34
+V13,34,IOB_X0Y43,RIOB33_X31Y43,IO_L3N_T0_DQS_34
+V15,34,IOB_X0Y30,RIOB33_X31Y29,IO_L10P_T1_34
+V16,34,IOB_X0Y14,RIOB33_X31Y13,IO_L18P_T2_34
+V17,34,IOB_X0Y8,RIOB33_X31Y7,IO_L21P_T3_DQS_34
+V18,34,IOB_X0Y7,RIOB33_X31Y7,IO_L21N_T3_DQS_34
+V20,34,IOB_X0Y18,RIOB33_X31Y17,IO_L16P_T2_34
+W1,502,IOPAD_X1Y58,PSS2_X13Y53,PS_DDR_DQ26_502
+W3,502,IOPAD_X1Y61,PSS2_X13Y53,PS_DDR_DQ29_502
+W4,502,IOPAD_X1Y67,PSS2_X13Y53,PS_DDR_DQS_N3_502
+W5,502,IOPAD_X1Y71,PSS2_X13Y53,PS_DDR_DQS_P3_502
+W13,34,IOB_X0Y41,RIOB33_X31Y41,IO_L4N_T0_34
+W14,34,IOB_X0Y34,RIOB33_X31Y33,IO_L8P_T1_34
+W15,34,IOB_X0Y29,RIOB33_X31Y29,IO_L10N_T1_34
+W16,34,IOB_X0Y13,RIOB33_X31Y13,IO_L18N_T2_34
+W18,34,IOB_X0Y6,RIOB33_X31Y5,IO_L22P_T3_34
+W19,34,IOB_X0Y5,RIOB33_X31Y5,IO_L22N_T3_34
+W20,34,IOB_X0Y17,RIOB33_X31Y17,IO_L16N_T2_34
+Y1,502,IOPAD_X1Y31,PSS2_X13Y53,PS_DDR_DM3_502
+Y2,502,IOPAD_X1Y60,PSS2_X13Y53,PS_DDR_DQ28_502
+Y3,502,IOPAD_X1Y57,PSS2_X13Y53,PS_DDR_DQ25_502
+Y4,502,IOPAD_X1Y59,PSS2_X13Y53,PS_DDR_DQ27_502
+Y14,34,IOB_X0Y33,RIOB33_X31Y33,IO_L8N_T1_34
+Y16,34,IOB_X0Y36,RIOB33_X31Y35,IO_L7P_T1_34
+Y17,34,IOB_X0Y35,RIOB33_X31Y35,IO_L7N_T1_34
+Y18,34,IOB_X0Y16,RIOB33_X31Y15,IO_L17P_T2_34
+Y19,34,IOB_X0Y15,RIOB33_X31Y15,IO_L17N_T2_34
diff --git a/zynq7/xc7z010clg400-2/part.json b/zynq7/xc7z010clg400-2/part.json
new file mode 100644
index 0000000..8fa289f
--- /dev/null
+++ b/zynq7/xc7z010clg400-2/part.json
@@ -0,0 +1,407 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ },
+ "4": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 28
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 28
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 30
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 30
+ },
+ "40": {
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+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 28
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 36
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 28
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 36
+ },
+ "49": {
+ "frame_count": 28
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 36
+ },
+ "52": {
+ "frame_count": 36
+ },
+ "53": {
+ "frame_count": 36
+ },
+ "54": {
+ "frame_count": 30
+ },
+ "55": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ },
+ "4": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 28
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 28
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 30
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 30
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 28
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 36
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 28
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 36
+ },
+ "49": {
+ "frame_count": 28
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 36
+ },
+ "52": {
+ "frame_count": 36
+ },
+ "53": {
+ "frame_count": 36
+ },
+ "54": {
+ "frame_count": 30
+ },
+ "55": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 57811091,
+ "iobanks": {
+ "34": "X126Y26",
+ "35": "X126Y78"
+ }
+}
diff --git a/zynq7/xc7z010clg400-2/part.yaml b/zynq7/xc7z010clg400-2/part.yaml
new file mode 100644
index 0000000..d03d585
--- /dev/null
+++ b/zynq7/xc7z010clg400-2/part.yaml
@@ -0,0 +1,263 @@
+!<xilinx/xc7series/part>
+idcode: 0x3722093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/zynq7/xc7z010clg400-3/package_pins.csv b/zynq7/xc7z010clg400-3/package_pins.csv
new file mode 100644
index 0000000..b2220e7
--- /dev/null
+++ b/zynq7/xc7z010clg400-3/package_pins.csv
@@ -0,0 +1,233 @@
+pin,bank,site,tile,pin_function
+A1,502,IOPAD_X1Y28,PSS2_X13Y53,PS_DDR_DM0_502
+A2,502,IOPAD_X1Y34,PSS2_X13Y53,PS_DDR_DQ2_502
+A4,502,IOPAD_X1Y35,PSS2_X13Y53,PS_DDR_DQ3_502
+A5,500,IOPAD_X1Y83,PSS2_X13Y53,PS_MIO6_500
+A6,500,IOPAD_X1Y82,PSS2_X13Y53,PS_MIO5_500
+A7,500,IOPAD_X1Y78,PSS2_X13Y53,PS_MIO1_500
+A9,501,IOPAD_X1Y120,PSS2_X13Y53,PS_MIO43_501
+A10,501,IOPAD_X1Y114,PSS2_X13Y53,PS_MIO37_501
+A11,501,IOPAD_X1Y113,PSS2_X13Y53,PS_MIO36_501
+A12,501,IOPAD_X1Y111,PSS2_X13Y53,PS_MIO34_501
+A14,501,IOPAD_X1Y109,PSS2_X13Y53,PS_MIO32_501
+A15,501,IOPAD_X1Y103,PSS2_X13Y53,PS_MIO26_501
+A16,501,IOPAD_X1Y101,PSS2_X13Y53,PS_MIO24_501
+A17,501,IOPAD_X1Y97,PSS2_X13Y53,PS_MIO20_501
+A19,501,IOPAD_X1Y93,PSS2_X13Y53,PS_MIO16_501
+A20,35,IOB_X0Y95,RIOB33_X31Y95,IO_L2N_T0_AD8N_35
+B2,502,IOPAD_X1Y64,PSS2_X13Y53,PS_DDR_DQS_N0_502
+B3,502,IOPAD_X1Y33,PSS2_X13Y53,PS_DDR_DQ1_502
+B4,502,IOPAD_X1Y72,PSS2_X13Y53,PS_DDR_DRST_B_502
+B5,500,IOPAD_X1Y86,PSS2_X13Y53,PS_MIO9_500
+B7,500,IOPAD_X1Y81,PSS2_X13Y53,PS_MIO4_500
+B8,500,IOPAD_X1Y79,PSS2_X13Y53,PS_MIO2_500
+B9,501,IOPAD_X1Y128,PSS2_X13Y53,PS_MIO51_501
+B10,501,IOPAD_X1Y134,PSS2_X13Y53,PS_SRST_B_501
+B12,501,IOPAD_X1Y125,PSS2_X13Y53,PS_MIO48_501
+B13,501,IOPAD_X1Y127,PSS2_X13Y53,PS_MIO50_501
+B14,501,IOPAD_X1Y124,PSS2_X13Y53,PS_MIO47_501
+B15,501,IOPAD_X1Y122,PSS2_X13Y53,PS_MIO45_501
+B17,501,IOPAD_X1Y99,PSS2_X13Y53,PS_MIO22_501
+B18,501,IOPAD_X1Y95,PSS2_X13Y53,PS_MIO18_501
+B19,35,IOB_X0Y96,RIOB33_X31Y95,IO_L2P_T0_AD8P_35
+B20,35,IOB_X0Y97,RIOB33_X31Y97,IO_L1N_T0_AD0N_35
+C1,502,IOPAD_X1Y38,PSS2_X13Y53,PS_DDR_DQ6_502
+C2,502,IOPAD_X1Y68,PSS2_X13Y53,PS_DDR_DQS_P0_502
+C3,502,IOPAD_X1Y32,PSS2_X13Y53,PS_DDR_DQ0_502
+C5,500,IOPAD_X1Y91,PSS2_X13Y53,PS_MIO14_500
+C6,500,IOPAD_X1Y88,PSS2_X13Y53,PS_MIO11_500
+C7,500,IOPAD_X1Y132,PSS2_X13Y53,PS_POR_B_500
+C8,500,IOPAD_X1Y92,PSS2_X13Y53,PS_MIO15_500
+C10,501,IOPAD_X1Y129,PSS2_X13Y53,PS_MIO52_501
+C11,501,IOPAD_X1Y130,PSS2_X13Y53,PS_MIO53_501
+C12,501,IOPAD_X1Y126,PSS2_X13Y53,PS_MIO49_501
+C13,501,IOPAD_X1Y106,PSS2_X13Y53,PS_MIO29_501
+C15,501,IOPAD_X1Y107,PSS2_X13Y53,PS_MIO30_501
+C16,501,IOPAD_X1Y105,PSS2_X13Y53,PS_MIO28_501
+C17,501,IOPAD_X1Y118,PSS2_X13Y53,PS_MIO41_501
+C18,501,IOPAD_X1Y116,PSS2_X13Y53,PS_MIO39_501
+C20,35,IOB_X0Y98,RIOB33_X31Y97,IO_L1P_T0_AD0P_35
+D1,502,IOPAD_X1Y37,PSS2_X13Y53,PS_DDR_DQ5_502
+D3,502,IOPAD_X1Y36,PSS2_X13Y53,PS_DDR_DQ4_502
+D4,502,IOPAD_X1Y18,PSS2_X13Y53,PS_DDR_A13_502
+D5,500,IOPAD_X1Y85,PSS2_X13Y53,PS_MIO8_500
+D6,500,IOPAD_X1Y80,PSS2_X13Y53,PS_MIO3_500
+D8,500,IOPAD_X1Y84,PSS2_X13Y53,PS_MIO7_500
+D9,500,IOPAD_X1Y89,PSS2_X13Y53,PS_MIO12_500
+D10,501,IOPAD_X1Y96,PSS2_X13Y53,PS_MIO19_501
+D11,501,IOPAD_X1Y100,PSS2_X13Y53,PS_MIO23_501
+D13,501,IOPAD_X1Y104,PSS2_X13Y53,PS_MIO27_501
+D14,501,IOPAD_X1Y117,PSS2_X13Y53,PS_MIO40_501
+D15,501,IOPAD_X1Y110,PSS2_X13Y53,PS_MIO33_501
+D16,501,IOPAD_X1Y123,PSS2_X13Y53,PS_MIO46_501
+D18,35,IOB_X0Y93,RIOB33_X31Y93,IO_L3N_T0_DQS_AD1N_35
+D19,35,IOB_X0Y92,RIOB33_X31Y91,IO_L4P_T0_35
+D20,35,IOB_X0Y91,RIOB33_X31Y91,IO_L4N_T0_35
+E1,502,IOPAD_X1Y39,PSS2_X13Y53,PS_DDR_DQ7_502
+E2,502,IOPAD_X1Y40,PSS2_X13Y53,PS_DDR_DQ8_502
+E3,502,IOPAD_X1Y41,PSS2_X13Y53,PS_DDR_DQ9_502
+E4,502,IOPAD_X1Y16,PSS2_X13Y53,PS_DDR_A12_502
+E6,500,IOPAD_X1Y77,PSS2_X13Y53,PS_MIO0_500
+E7,500,IOPAD_X1Y26,PSS2_X13Y53,PS_CLK_500
+E8,500,IOPAD_X1Y90,PSS2_X13Y53,PS_MIO13_500
+E9,500,IOPAD_X1Y87,PSS2_X13Y53,PS_MIO10_500
+E12,501,IOPAD_X1Y119,PSS2_X13Y53,PS_MIO42_501
+E13,501,IOPAD_X1Y115,PSS2_X13Y53,PS_MIO38_501
+E14,501,IOPAD_X1Y94,PSS2_X13Y53,PS_MIO17_501
+E16,501,IOPAD_X1Y108,PSS2_X13Y53,PS_MIO31_501
+E17,35,IOB_X0Y94,RIOB33_X31Y93,IO_L3P_T0_DQS_AD1P_35
+E18,35,IOB_X0Y90,RIOB33_X31Y89,IO_L5P_T0_AD9P_35
+E19,35,IOB_X0Y89,RIOB33_X31Y89,IO_L5N_T0_AD9N_35
+F1,502,IOPAD_X1Y29,PSS2_X13Y53,PS_DDR_DM1_502
+F2,502,IOPAD_X1Y65,PSS2_X13Y53,PS_DDR_DQS_N1_502
+F4,502,IOPAD_X1Y17,PSS2_X13Y53,PS_DDR_A14_502
+F5,502,IOPAD_X1Y14,PSS2_X13Y53,PS_DDR_A10_502
+F12,501,IOPAD_X1Y112,PSS2_X13Y53,PS_MIO35_501
+F13,501,IOPAD_X1Y121,PSS2_X13Y53,PS_MIO44_501
+F14,501,IOPAD_X1Y98,PSS2_X13Y53,PS_MIO21_501
+F15,501,IOPAD_X1Y102,PSS2_X13Y53,PS_MIO25_501
+F16,35,IOB_X0Y88,RIOB33_X31Y87,IO_L6P_T0_35
+F17,35,IOB_X0Y87,RIOB33_X31Y87,IO_L6N_T0_VREF_35
+F19,35,IOB_X0Y70,RIOB33_X31Y69,IO_L15P_T2_DQS_AD12P_35
+F20,35,IOB_X0Y69,RIOB33_X31Y69,IO_L15N_T2_DQS_AD12N_35
+G2,502,IOPAD_X1Y69,PSS2_X13Y53,PS_DDR_DQS_P1_502
+G3,502,IOPAD_X1Y42,PSS2_X13Y53,PS_DDR_DQ10_502
+G4,502,IOPAD_X1Y15,PSS2_X13Y53,PS_DDR_A11_502
+G5,502,IOPAD_X1Y2,PSS2_X13Y53,PS_DDR_VRN_502
+G14,35,IOB_X0Y99,RIOB33_SING_X31Y99,IO_0_35
+G15,35,IOB_X0Y61,RIOB33_X31Y61,IO_L19N_T3_VREF_35
+G17,35,IOB_X0Y68,RIOB33_X31Y67,IO_L16P_T2_35
+G18,35,IOB_X0Y67,RIOB33_X31Y67,IO_L16N_T2_35
+G19,35,IOB_X0Y64,RIOB33_X31Y63,IO_L18P_T2_AD13P_35
+G20,35,IOB_X0Y63,RIOB33_X31Y63,IO_L18N_T2_AD13N_35
+H1,502,IOPAD_X1Y46,PSS2_X13Y53,PS_DDR_DQ14_502
+H2,502,IOPAD_X1Y45,PSS2_X13Y53,PS_DDR_DQ13_502
+H3,502,IOPAD_X1Y43,PSS2_X13Y53,PS_DDR_DQ11_502
+H5,502,IOPAD_X1Y3,PSS2_X13Y53,PS_DDR_VRP_502
+H15,35,IOB_X0Y62,RIOB33_X31Y61,IO_L19P_T3_35
+H16,35,IOB_X0Y74,RIOB33_X31Y73,IO_L13P_T2_MRCC_35
+H17,35,IOB_X0Y73,RIOB33_X31Y73,IO_L13N_T2_MRCC_35
+H18,35,IOB_X0Y71,RIOB33_X31Y71,IO_L14N_T2_AD4N_SRCC_35
+H20,35,IOB_X0Y65,RIOB33_X31Y65,IO_L17N_T2_AD5N_35
+J1,502,IOPAD_X1Y47,PSS2_X13Y53,PS_DDR_DQ15_502
+J3,502,IOPAD_X1Y44,PSS2_X13Y53,PS_DDR_DQ12_502
+J4,502,IOPAD_X1Y13,PSS2_X13Y53,PS_DDR_A9_502
+J5,502,IOPAD_X1Y21,PSS2_X13Y53,PS_DDR_BA2_502
+J14,35,IOB_X0Y59,RIOB33_X31Y59,IO_L20N_T3_AD6N_35
+J15,35,IOB_X0Y50,RIOB33_SING_X31Y50,IO_25_35
+J16,35,IOB_X0Y51,RIOB33_X31Y51,IO_L24N_T3_AD15N_35
+J18,35,IOB_X0Y72,RIOB33_X31Y71,IO_L14P_T2_AD4P_SRCC_35
+J19,35,IOB_X0Y79,RIOB33_X31Y79,IO_L10N_T1_AD11N_35
+J20,35,IOB_X0Y66,RIOB33_X31Y65,IO_L17P_T2_AD5P_35
+K1,502,IOPAD_X1Y12,PSS2_X13Y53,PS_DDR_A8_502
+K2,502,IOPAD_X1Y5,PSS2_X13Y53,PS_DDR_A1_502
+K3,502,IOPAD_X1Y7,PSS2_X13Y53,PS_DDR_A3_502
+K4,502,IOPAD_X1Y11,PSS2_X13Y53,PS_DDR_A7_502
+K9,0,IPAD_X0Y0,MONITOR_BOT_PELE1_X67Y79,VP_0
+K14,35,IOB_X0Y60,RIOB33_X31Y59,IO_L20P_T3_AD6P_35
+K16,35,IOB_X0Y52,RIOB33_X31Y51,IO_L24P_T3_AD15P_35
+K17,35,IOB_X0Y76,RIOB33_X31Y75,IO_L12P_T1_MRCC_35
+K18,35,IOB_X0Y75,RIOB33_X31Y75,IO_L12N_T1_MRCC_35
+K19,35,IOB_X0Y80,RIOB33_X31Y79,IO_L10P_T1_AD11P_35
+L1,502,IOPAD_X1Y9,PSS2_X13Y53,PS_DDR_A5_502
+L2,502,IOPAD_X1Y25,PSS2_X13Y53,PS_DDR_CKP_502
+L4,502,IOPAD_X1Y10,PSS2_X13Y53,PS_DDR_A6_502
+L5,502,IOPAD_X1Y19,PSS2_X13Y53,PS_DDR_BA0_502
+L10,0,IPAD_X0Y1,MONITOR_BOT_PELE1_X67Y79,VN_0
+L14,35,IOB_X0Y56,RIOB33_X31Y55,IO_L22P_T3_AD7P_35
+L15,35,IOB_X0Y55,RIOB33_X31Y55,IO_L22N_T3_AD7N_35
+L16,35,IOB_X0Y78,RIOB33_X31Y77,IO_L11P_T1_SRCC_35
+L17,35,IOB_X0Y77,RIOB33_X31Y77,IO_L11N_T1_SRCC_35
+L19,35,IOB_X0Y82,RIOB33_X31Y81,IO_L9P_T1_DQS_AD3P_35
+L20,35,IOB_X0Y81,RIOB33_X31Y81,IO_L9N_T1_DQS_AD3N_35
+M2,502,IOPAD_X1Y24,PSS2_X13Y53,PS_DDR_CKN_502
+M3,502,IOPAD_X1Y6,PSS2_X13Y53,PS_DDR_A2_502
+M4,502,IOPAD_X1Y8,PSS2_X13Y53,PS_DDR_A4_502
+M5,502,IOPAD_X1Y1,PSS2_X13Y53,PS_DDR_WE_B_502
+M14,35,IOB_X0Y54,RIOB33_X31Y53,IO_L23P_T3_35
+M15,35,IOB_X0Y53,RIOB33_X31Y53,IO_L23N_T3_35
+M17,35,IOB_X0Y84,RIOB33_X31Y83,IO_L8P_T1_AD10P_35
+M18,35,IOB_X0Y83,RIOB33_X31Y83,IO_L8N_T1_AD10N_35
+M19,35,IOB_X0Y86,RIOB33_X31Y85,IO_L7P_T1_AD2P_35
+M20,35,IOB_X0Y85,RIOB33_X31Y85,IO_L7N_T1_AD2N_35
+N1,502,IOPAD_X1Y27,PSS2_X13Y53,PS_DDR_CS_B_502
+N2,502,IOPAD_X1Y4,PSS2_X13Y53,PS_DDR_A0_502
+N3,502,IOPAD_X1Y23,PSS2_X13Y53,PS_DDR_CKE_502
+N5,502,IOPAD_X1Y131,PSS2_X13Y53,PS_DDR_ODT_502
+N15,35,IOB_X0Y58,RIOB33_X31Y57,IO_L21P_T3_DQS_AD14P_35
+N16,35,IOB_X0Y57,RIOB33_X31Y57,IO_L21N_T3_DQS_AD14N_35
+N17,34,IOB_X0Y4,RIOB33_X31Y3,IO_L23P_T3_34
+N18,34,IOB_X0Y24,RIOB33_X31Y23,IO_L13P_T2_MRCC_34
+N20,34,IOB_X0Y22,RIOB33_X31Y21,IO_L14P_T2_SRCC_34
+P1,502,IOPAD_X1Y48,PSS2_X13Y53,PS_DDR_DQ16_502
+P3,502,IOPAD_X1Y49,PSS2_X13Y53,PS_DDR_DQ17_502
+P4,502,IOPAD_X1Y133,PSS2_X13Y53,PS_DDR_RAS_B_502
+P5,502,IOPAD_X1Y22,PSS2_X13Y53,PS_DDR_CAS_B_502
+P14,34,IOB_X0Y38,RIOB33_X31Y37,IO_L6P_T0_34
+P15,34,IOB_X0Y2,RIOB33_X31Y1,IO_L24P_T3_34
+P16,34,IOB_X0Y1,RIOB33_X31Y1,IO_L24N_T3_34
+P18,34,IOB_X0Y3,RIOB33_X31Y3,IO_L23N_T3_34
+P19,34,IOB_X0Y23,RIOB33_X31Y23,IO_L13N_T2_MRCC_34
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+U2,502,IOPAD_X1Y54,PSS2_X13Y53,PS_DDR_DQ22_502
+U3,502,IOPAD_X1Y55,PSS2_X13Y53,PS_DDR_DQ23_502
+U4,502,IOPAD_X1Y53,PSS2_X13Y53,PS_DDR_DQ21_502
+U12,34,IOB_X0Y45,RIOB33_X31Y45,IO_L2N_T0_34
+U13,34,IOB_X0Y44,RIOB33_X31Y43,IO_L3P_T0_DQS_PUDC_B_34
+U14,34,IOB_X0Y28,RIOB33_X31Y27,IO_L11P_T1_SRCC_34
+U15,34,IOB_X0Y27,RIOB33_X31Y27,IO_L11N_T1_SRCC_34
+U17,34,IOB_X0Y31,RIOB33_X31Y31,IO_L9N_T1_DQS_34
+U18,34,IOB_X0Y26,RIOB33_X31Y25,IO_L12P_T1_MRCC_34
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+U20,34,IOB_X0Y19,RIOB33_X31Y19,IO_L15N_T2_DQS_34
+V1,502,IOPAD_X1Y56,PSS2_X13Y53,PS_DDR_DQ24_502
+V2,502,IOPAD_X1Y62,PSS2_X13Y53,PS_DDR_DQ30_502
+V3,502,IOPAD_X1Y63,PSS2_X13Y53,PS_DDR_DQ31_502
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+V13,34,IOB_X0Y43,RIOB33_X31Y43,IO_L3N_T0_DQS_34
+V15,34,IOB_X0Y30,RIOB33_X31Y29,IO_L10P_T1_34
+V16,34,IOB_X0Y14,RIOB33_X31Y13,IO_L18P_T2_34
+V17,34,IOB_X0Y8,RIOB33_X31Y7,IO_L21P_T3_DQS_34
+V18,34,IOB_X0Y7,RIOB33_X31Y7,IO_L21N_T3_DQS_34
+V20,34,IOB_X0Y18,RIOB33_X31Y17,IO_L16P_T2_34
+W1,502,IOPAD_X1Y58,PSS2_X13Y53,PS_DDR_DQ26_502
+W3,502,IOPAD_X1Y61,PSS2_X13Y53,PS_DDR_DQ29_502
+W4,502,IOPAD_X1Y67,PSS2_X13Y53,PS_DDR_DQS_N3_502
+W5,502,IOPAD_X1Y71,PSS2_X13Y53,PS_DDR_DQS_P3_502
+W13,34,IOB_X0Y41,RIOB33_X31Y41,IO_L4N_T0_34
+W14,34,IOB_X0Y34,RIOB33_X31Y33,IO_L8P_T1_34
+W15,34,IOB_X0Y29,RIOB33_X31Y29,IO_L10N_T1_34
+W16,34,IOB_X0Y13,RIOB33_X31Y13,IO_L18N_T2_34
+W18,34,IOB_X0Y6,RIOB33_X31Y5,IO_L22P_T3_34
+W19,34,IOB_X0Y5,RIOB33_X31Y5,IO_L22N_T3_34
+W20,34,IOB_X0Y17,RIOB33_X31Y17,IO_L16N_T2_34
+Y1,502,IOPAD_X1Y31,PSS2_X13Y53,PS_DDR_DM3_502
+Y2,502,IOPAD_X1Y60,PSS2_X13Y53,PS_DDR_DQ28_502
+Y3,502,IOPAD_X1Y57,PSS2_X13Y53,PS_DDR_DQ25_502
+Y4,502,IOPAD_X1Y59,PSS2_X13Y53,PS_DDR_DQ27_502
+Y14,34,IOB_X0Y33,RIOB33_X31Y33,IO_L8N_T1_34
+Y16,34,IOB_X0Y36,RIOB33_X31Y35,IO_L7P_T1_34
+Y17,34,IOB_X0Y35,RIOB33_X31Y35,IO_L7N_T1_34
+Y18,34,IOB_X0Y16,RIOB33_X31Y15,IO_L17P_T2_34
+Y19,34,IOB_X0Y15,RIOB33_X31Y15,IO_L17N_T2_34
diff --git a/zynq7/xc7z010clg400-3/part.json b/zynq7/xc7z010clg400-3/part.json
new file mode 100644
index 0000000..8fa289f
--- /dev/null
+++ b/zynq7/xc7z010clg400-3/part.json
@@ -0,0 +1,407 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ },
+ "4": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
+ "frame_count": 36
+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 28
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 28
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 30
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 30
+ },
+ "40": {
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+ },
+ "41": {
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+ },
+ "42": {
+ "frame_count": 28
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 36
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 28
+ },
+ "47": {
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+ },
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+ },
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+ "frame_count": 28
+ },
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+ },
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+ "frame_count": 36
+ },
+ "52": {
+ "frame_count": 36
+ },
+ "53": {
+ "frame_count": 36
+ },
+ "54": {
+ "frame_count": 30
+ },
+ "55": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ },
+ "4": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
+ "frame_count": 36
+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
+ "frame_count": 28
+ },
+ "7": {
+ "frame_count": 36
+ },
+ "8": {
+ "frame_count": 36
+ },
+ "9": {
+ "frame_count": 28
+ },
+ "10": {
+ "frame_count": 36
+ },
+ "11": {
+ "frame_count": 36
+ },
+ "12": {
+ "frame_count": 36
+ },
+ "13": {
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+ },
+ "14": {
+ "frame_count": 28
+ },
+ "15": {
+ "frame_count": 36
+ },
+ "16": {
+ "frame_count": 36
+ },
+ "17": {
+ "frame_count": 28
+ },
+ "18": {
+ "frame_count": 36
+ },
+ "19": {
+ "frame_count": 36
+ },
+ "20": {
+ "frame_count": 36
+ },
+ "21": {
+ "frame_count": 36
+ },
+ "22": {
+ "frame_count": 28
+ },
+ "23": {
+ "frame_count": 36
+ },
+ "24": {
+ "frame_count": 36
+ },
+ "25": {
+ "frame_count": 28
+ },
+ "26": {
+ "frame_count": 36
+ },
+ "27": {
+ "frame_count": 36
+ },
+ "28": {
+ "frame_count": 36
+ },
+ "29": {
+ "frame_count": 36
+ },
+ "30": {
+ "frame_count": 36
+ },
+ "31": {
+ "frame_count": 36
+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
+ "frame_count": 36
+ },
+ "34": {
+ "frame_count": 30
+ },
+ "35": {
+ "frame_count": 36
+ },
+ "36": {
+ "frame_count": 36
+ },
+ "37": {
+ "frame_count": 36
+ },
+ "38": {
+ "frame_count": 36
+ },
+ "39": {
+ "frame_count": 30
+ },
+ "40": {
+ "frame_count": 36
+ },
+ "41": {
+ "frame_count": 36
+ },
+ "42": {
+ "frame_count": 28
+ },
+ "43": {
+ "frame_count": 36
+ },
+ "44": {
+ "frame_count": 36
+ },
+ "45": {
+ "frame_count": 36
+ },
+ "46": {
+ "frame_count": 28
+ },
+ "47": {
+ "frame_count": 36
+ },
+ "48": {
+ "frame_count": 36
+ },
+ "49": {
+ "frame_count": 28
+ },
+ "50": {
+ "frame_count": 36
+ },
+ "51": {
+ "frame_count": 36
+ },
+ "52": {
+ "frame_count": 36
+ },
+ "53": {
+ "frame_count": 36
+ },
+ "54": {
+ "frame_count": 30
+ },
+ "55": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 57811091,
+ "iobanks": {
+ "34": "X126Y26",
+ "35": "X126Y78"
+ }
+}
diff --git a/zynq7/xc7z010clg400-3/part.yaml b/zynq7/xc7z010clg400-3/part.yaml
new file mode 100644
index 0000000..d03d585
--- /dev/null
+++ b/zynq7/xc7z010clg400-3/part.yaml
@@ -0,0 +1,263 @@
+!<xilinx/xc7series/part>
+idcode: 0x3722093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/zynq7/xc7z020s/node_wires.json b/zynq7/xc7z020/node_wires.json
similarity index 100%
rename from zynq7/xc7z020s/node_wires.json
rename to zynq7/xc7z020/node_wires.json
diff --git a/zynq7/xc7z020s/tileconn.json b/zynq7/xc7z020/tileconn.json
similarity index 100%
rename from zynq7/xc7z020s/tileconn.json
rename to zynq7/xc7z020/tileconn.json
diff --git a/zynq7/xc7z020s/tilegrid.json b/zynq7/xc7z020/tilegrid.json
similarity index 100%
rename from zynq7/xc7z020s/tilegrid.json
rename to zynq7/xc7z020/tilegrid.json
diff --git a/zynq7/xc7z020clg400-2/package_pins.csv b/zynq7/xc7z020clg400-2/package_pins.csv
new file mode 100644
index 0000000..8c78375
--- /dev/null
+++ b/zynq7/xc7z020clg400-2/package_pins.csv
@@ -0,0 +1,258 @@
+pin,bank,site,tile,pin_function
+A1,502,IOPAD_X1Y28,PSS2_X32Y105,PS_DDR_DM0_502
+A2,502,IOPAD_X1Y34,PSS2_X32Y105,PS_DDR_DQ2_502
+A4,502,IOPAD_X1Y35,PSS2_X32Y105,PS_DDR_DQ3_502
+A5,500,IOPAD_X1Y83,PSS2_X32Y105,PS_MIO6_500
+A6,500,IOPAD_X1Y82,PSS2_X32Y105,PS_MIO5_500
+A7,500,IOPAD_X1Y78,PSS2_X32Y105,PS_MIO1_500
+A9,501,IOPAD_X1Y120,PSS2_X32Y105,PS_MIO43_501
+A10,501,IOPAD_X1Y114,PSS2_X32Y105,PS_MIO37_501
+A11,501,IOPAD_X1Y113,PSS2_X32Y105,PS_MIO36_501
+A12,501,IOPAD_X1Y111,PSS2_X32Y105,PS_MIO34_501
+A14,501,IOPAD_X1Y109,PSS2_X32Y105,PS_MIO32_501
+A15,501,IOPAD_X1Y103,PSS2_X32Y105,PS_MIO26_501
+A16,501,IOPAD_X1Y101,PSS2_X32Y105,PS_MIO24_501
+A17,501,IOPAD_X1Y97,PSS2_X32Y105,PS_MIO20_501
+A19,501,IOPAD_X1Y93,PSS2_X32Y105,PS_MIO16_501
+A20,35,IOB_X1Y145,RIOB33_X73Y145,IO_L2N_T0_AD8N_35
+B2,502,IOPAD_X1Y64,PSS2_X32Y105,PS_DDR_DQS_N0_502
+B3,502,IOPAD_X1Y33,PSS2_X32Y105,PS_DDR_DQ1_502
+B4,502,IOPAD_X1Y72,PSS2_X32Y105,PS_DDR_DRST_B_502
+B5,500,IOPAD_X1Y86,PSS2_X32Y105,PS_MIO9_500
+B7,500,IOPAD_X1Y81,PSS2_X32Y105,PS_MIO4_500
+B8,500,IOPAD_X1Y79,PSS2_X32Y105,PS_MIO2_500
+B9,501,IOPAD_X1Y128,PSS2_X32Y105,PS_MIO51_501
+B10,501,IOPAD_X1Y134,PSS2_X32Y105,PS_SRST_B_501
+B12,501,IOPAD_X1Y125,PSS2_X32Y105,PS_MIO48_501
+B13,501,IOPAD_X1Y127,PSS2_X32Y105,PS_MIO50_501
+B14,501,IOPAD_X1Y124,PSS2_X32Y105,PS_MIO47_501
+B15,501,IOPAD_X1Y122,PSS2_X32Y105,PS_MIO45_501
+B17,501,IOPAD_X1Y99,PSS2_X32Y105,PS_MIO22_501
+B18,501,IOPAD_X1Y95,PSS2_X32Y105,PS_MIO18_501
+B19,35,IOB_X1Y146,RIOB33_X73Y145,IO_L2P_T0_AD8P_35
+B20,35,IOB_X1Y147,RIOB33_X73Y147,IO_L1N_T0_AD0N_35
+C1,502,IOPAD_X1Y38,PSS2_X32Y105,PS_DDR_DQ6_502
+C2,502,IOPAD_X1Y68,PSS2_X32Y105,PS_DDR_DQS_P0_502
+C3,502,IOPAD_X1Y32,PSS2_X32Y105,PS_DDR_DQ0_502
+C5,500,IOPAD_X1Y91,PSS2_X32Y105,PS_MIO14_500
+C6,500,IOPAD_X1Y88,PSS2_X32Y105,PS_MIO11_500
+C7,500,IOPAD_X1Y132,PSS2_X32Y105,PS_POR_B_500
+C8,500,IOPAD_X1Y92,PSS2_X32Y105,PS_MIO15_500
+C10,501,IOPAD_X1Y129,PSS2_X32Y105,PS_MIO52_501
+C11,501,IOPAD_X1Y130,PSS2_X32Y105,PS_MIO53_501
+C12,501,IOPAD_X1Y126,PSS2_X32Y105,PS_MIO49_501
+C13,501,IOPAD_X1Y106,PSS2_X32Y105,PS_MIO29_501
+C15,501,IOPAD_X1Y107,PSS2_X32Y105,PS_MIO30_501
+C16,501,IOPAD_X1Y105,PSS2_X32Y105,PS_MIO28_501
+C17,501,IOPAD_X1Y118,PSS2_X32Y105,PS_MIO41_501
+C18,501,IOPAD_X1Y116,PSS2_X32Y105,PS_MIO39_501
+C20,35,IOB_X1Y148,RIOB33_X73Y147,IO_L1P_T0_AD0P_35
+D1,502,IOPAD_X1Y37,PSS2_X32Y105,PS_DDR_DQ5_502
+D3,502,IOPAD_X1Y36,PSS2_X32Y105,PS_DDR_DQ4_502
+D4,502,IOPAD_X1Y18,PSS2_X32Y105,PS_DDR_A13_502
+D5,500,IOPAD_X1Y85,PSS2_X32Y105,PS_MIO8_500
+D6,500,IOPAD_X1Y80,PSS2_X32Y105,PS_MIO3_500
+D8,500,IOPAD_X1Y84,PSS2_X32Y105,PS_MIO7_500
+D9,500,IOPAD_X1Y89,PSS2_X32Y105,PS_MIO12_500
+D10,501,IOPAD_X1Y96,PSS2_X32Y105,PS_MIO19_501
+D11,501,IOPAD_X1Y100,PSS2_X32Y105,PS_MIO23_501
+D13,501,IOPAD_X1Y104,PSS2_X32Y105,PS_MIO27_501
+D14,501,IOPAD_X1Y117,PSS2_X32Y105,PS_MIO40_501
+D15,501,IOPAD_X1Y110,PSS2_X32Y105,PS_MIO33_501
+D16,501,IOPAD_X1Y123,PSS2_X32Y105,PS_MIO46_501
+D18,35,IOB_X1Y143,RIOB33_X73Y143,IO_L3N_T0_DQS_AD1N_35
+D19,35,IOB_X1Y142,RIOB33_X73Y141,IO_L4P_T0_35
+D20,35,IOB_X1Y141,RIOB33_X73Y141,IO_L4N_T0_35
+E1,502,IOPAD_X1Y39,PSS2_X32Y105,PS_DDR_DQ7_502
+E2,502,IOPAD_X1Y40,PSS2_X32Y105,PS_DDR_DQ8_502
+E3,502,IOPAD_X1Y41,PSS2_X32Y105,PS_DDR_DQ9_502
+E4,502,IOPAD_X1Y16,PSS2_X32Y105,PS_DDR_A12_502
+E6,500,IOPAD_X1Y77,PSS2_X32Y105,PS_MIO0_500
+E7,500,IOPAD_X1Y26,PSS2_X32Y105,PS_CLK_500
+E8,500,IOPAD_X1Y90,PSS2_X32Y105,PS_MIO13_500
+E9,500,IOPAD_X1Y87,PSS2_X32Y105,PS_MIO10_500
+E12,501,IOPAD_X1Y119,PSS2_X32Y105,PS_MIO42_501
+E13,501,IOPAD_X1Y115,PSS2_X32Y105,PS_MIO38_501
+E14,501,IOPAD_X1Y94,PSS2_X32Y105,PS_MIO17_501
+E16,501,IOPAD_X1Y108,PSS2_X32Y105,PS_MIO31_501
+E17,35,IOB_X1Y144,RIOB33_X73Y143,IO_L3P_T0_DQS_AD1P_35
+E18,35,IOB_X1Y140,RIOB33_X73Y139,IO_L5P_T0_AD9P_35
+E19,35,IOB_X1Y139,RIOB33_X73Y139,IO_L5N_T0_AD9N_35
+F1,502,IOPAD_X1Y29,PSS2_X32Y105,PS_DDR_DM1_502
+F2,502,IOPAD_X1Y65,PSS2_X32Y105,PS_DDR_DQS_N1_502
+F4,502,IOPAD_X1Y17,PSS2_X32Y105,PS_DDR_A14_502
+F5,502,IOPAD_X1Y14,PSS2_X32Y105,PS_DDR_A10_502
+F12,501,IOPAD_X1Y112,PSS2_X32Y105,PS_MIO35_501
+F13,501,IOPAD_X1Y121,PSS2_X32Y105,PS_MIO44_501
+F14,501,IOPAD_X1Y98,PSS2_X32Y105,PS_MIO21_501
+F15,501,IOPAD_X1Y102,PSS2_X32Y105,PS_MIO25_501
+F16,35,IOB_X1Y138,RIOB33_X73Y137,IO_L6P_T0_35
+F17,35,IOB_X1Y137,RIOB33_X73Y137,IO_L6N_T0_VREF_35
+F19,35,IOB_X1Y120,RIOB33_X73Y119,IO_L15P_T2_DQS_AD12P_35
+F20,35,IOB_X1Y119,RIOB33_X73Y119,IO_L15N_T2_DQS_AD12N_35
+G2,502,IOPAD_X1Y69,PSS2_X32Y105,PS_DDR_DQS_P1_502
+G3,502,IOPAD_X1Y42,PSS2_X32Y105,PS_DDR_DQ10_502
+G4,502,IOPAD_X1Y15,PSS2_X32Y105,PS_DDR_A11_502
+G5,502,IOPAD_X1Y2,PSS2_X32Y105,PS_DDR_VRN_502
+G14,35,IOB_X1Y149,RIOB33_SING_X73Y149,IO_0_35
+G15,35,IOB_X1Y111,RIOB33_X73Y111,IO_L19N_T3_VREF_35
+G17,35,IOB_X1Y118,RIOB33_X73Y117,IO_L16P_T2_35
+G18,35,IOB_X1Y117,RIOB33_X73Y117,IO_L16N_T2_35
+G19,35,IOB_X1Y114,RIOB33_X73Y113,IO_L18P_T2_AD13P_35
+G20,35,IOB_X1Y113,RIOB33_X73Y113,IO_L18N_T2_AD13N_35
+H1,502,IOPAD_X1Y46,PSS2_X32Y105,PS_DDR_DQ14_502
+H2,502,IOPAD_X1Y45,PSS2_X32Y105,PS_DDR_DQ13_502
+H3,502,IOPAD_X1Y43,PSS2_X32Y105,PS_DDR_DQ11_502
+H5,502,IOPAD_X1Y3,PSS2_X32Y105,PS_DDR_VRP_502
+H15,35,IOB_X1Y112,RIOB33_X73Y111,IO_L19P_T3_35
+H16,35,IOB_X1Y124,RIOB33_X73Y123,IO_L13P_T2_MRCC_35
+H17,35,IOB_X1Y123,RIOB33_X73Y123,IO_L13N_T2_MRCC_35
+H18,35,IOB_X1Y121,RIOB33_X73Y121,IO_L14N_T2_AD4N_SRCC_35
+H20,35,IOB_X1Y115,RIOB33_X73Y115,IO_L17N_T2_AD5N_35
+J1,502,IOPAD_X1Y47,PSS2_X32Y105,PS_DDR_DQ15_502
+J3,502,IOPAD_X1Y44,PSS2_X32Y105,PS_DDR_DQ12_502
+J4,502,IOPAD_X1Y13,PSS2_X32Y105,PS_DDR_A9_502
+J5,502,IOPAD_X1Y21,PSS2_X32Y105,PS_DDR_BA2_502
+J14,35,IOB_X1Y109,RIOB33_X73Y109,IO_L20N_T3_AD6N_35
+J15,35,IOB_X1Y100,RIOB33_SING_X73Y100,IO_25_35
+J16,35,IOB_X1Y101,RIOB33_X73Y101,IO_L24N_T3_AD15N_35
+J18,35,IOB_X1Y122,RIOB33_X73Y121,IO_L14P_T2_AD4P_SRCC_35
+J19,35,IOB_X1Y129,RIOB33_X73Y129,IO_L10N_T1_AD11N_35
+J20,35,IOB_X1Y116,RIOB33_X73Y115,IO_L17P_T2_AD5P_35
+K1,502,IOPAD_X1Y12,PSS2_X32Y105,PS_DDR_A8_502
+K2,502,IOPAD_X1Y5,PSS2_X32Y105,PS_DDR_A1_502
+K3,502,IOPAD_X1Y7,PSS2_X32Y105,PS_DDR_A3_502
+K4,502,IOPAD_X1Y11,PSS2_X32Y105,PS_DDR_A7_502
+K9,0,IPAD_X0Y0,MONITOR_BOT_PELE1_X123Y131,VP_0
+K14,35,IOB_X1Y110,RIOB33_X73Y109,IO_L20P_T3_AD6P_35
+K16,35,IOB_X1Y102,RIOB33_X73Y101,IO_L24P_T3_AD15P_35
+K17,35,IOB_X1Y126,RIOB33_X73Y125,IO_L12P_T1_MRCC_35
+K18,35,IOB_X1Y125,RIOB33_X73Y125,IO_L12N_T1_MRCC_35
+K19,35,IOB_X1Y130,RIOB33_X73Y129,IO_L10P_T1_AD11P_35
+L1,502,IOPAD_X1Y9,PSS2_X32Y105,PS_DDR_A5_502
+L2,502,IOPAD_X1Y25,PSS2_X32Y105,PS_DDR_CKP_502
+L4,502,IOPAD_X1Y10,PSS2_X32Y105,PS_DDR_A6_502
+L5,502,IOPAD_X1Y19,PSS2_X32Y105,PS_DDR_BA0_502
+L10,0,IPAD_X0Y1,MONITOR_BOT_PELE1_X123Y131,VN_0
+L14,35,IOB_X1Y106,RIOB33_X73Y105,IO_L22P_T3_AD7P_35
+L15,35,IOB_X1Y105,RIOB33_X73Y105,IO_L22N_T3_AD7N_35
+L16,35,IOB_X1Y128,RIOB33_X73Y127,IO_L11P_T1_SRCC_35
+L17,35,IOB_X1Y127,RIOB33_X73Y127,IO_L11N_T1_SRCC_35
+L19,35,IOB_X1Y132,RIOB33_X73Y131,IO_L9P_T1_DQS_AD3P_35
+L20,35,IOB_X1Y131,RIOB33_X73Y131,IO_L9N_T1_DQS_AD3N_35
+M2,502,IOPAD_X1Y24,PSS2_X32Y105,PS_DDR_CKN_502
+M3,502,IOPAD_X1Y6,PSS2_X32Y105,PS_DDR_A2_502
+M4,502,IOPAD_X1Y8,PSS2_X32Y105,PS_DDR_A4_502
+M5,502,IOPAD_X1Y1,PSS2_X32Y105,PS_DDR_WE_B_502
+M14,35,IOB_X1Y104,RIOB33_X73Y103,IO_L23P_T3_35
+M15,35,IOB_X1Y103,RIOB33_X73Y103,IO_L23N_T3_35
+M17,35,IOB_X1Y134,RIOB33_X73Y133,IO_L8P_T1_AD10P_35
+M18,35,IOB_X1Y133,RIOB33_X73Y133,IO_L8N_T1_AD10N_35
+M19,35,IOB_X1Y136,RIOB33_X73Y135,IO_L7P_T1_AD2P_35
+M20,35,IOB_X1Y135,RIOB33_X73Y135,IO_L7N_T1_AD2N_35
+N1,502,IOPAD_X1Y27,PSS2_X32Y105,PS_DDR_CS_B_502
+N2,502,IOPAD_X1Y4,PSS2_X32Y105,PS_DDR_A0_502
+N3,502,IOPAD_X1Y23,PSS2_X32Y105,PS_DDR_CKE_502
+N5,502,IOPAD_X1Y131,PSS2_X32Y105,PS_DDR_ODT_502
+N15,35,IOB_X1Y108,RIOB33_X73Y107,IO_L21P_T3_DQS_AD14P_35
+N16,35,IOB_X1Y107,RIOB33_X73Y107,IO_L21N_T3_DQS_AD14N_35
+N17,34,IOB_X1Y54,RIOB33_X73Y53,IO_L23P_T3_34
+N18,34,IOB_X1Y74,RIOB33_X73Y73,IO_L13P_T2_MRCC_34
+N20,34,IOB_X1Y72,RIOB33_X73Y71,IO_L14P_T2_SRCC_34
+P1,502,IOPAD_X1Y48,PSS2_X32Y105,PS_DDR_DQ16_502
+P3,502,IOPAD_X1Y49,PSS2_X32Y105,PS_DDR_DQ17_502
+P4,502,IOPAD_X1Y133,PSS2_X32Y105,PS_DDR_RAS_B_502
+P5,502,IOPAD_X1Y22,PSS2_X32Y105,PS_DDR_CAS_B_502
+P14,34,IOB_X1Y88,RIOB33_X73Y87,IO_L6P_T0_34
+P15,34,IOB_X1Y52,RIOB33_X73Y51,IO_L24P_T3_34
+P16,34,IOB_X1Y51,RIOB33_X73Y51,IO_L24N_T3_34
+P18,34,IOB_X1Y53,RIOB33_X73Y53,IO_L23N_T3_34
+P19,34,IOB_X1Y73,RIOB33_X73Y73,IO_L13N_T2_MRCC_34
+P20,34,IOB_X1Y71,RIOB33_X73Y71,IO_L14N_T2_SRCC_34
+R1,502,IOPAD_X1Y51,PSS2_X32Y105,PS_DDR_DQ19_502
+R2,502,IOPAD_X1Y70,PSS2_X32Y105,PS_DDR_DQS_P2_502
+R3,502,IOPAD_X1Y50,PSS2_X32Y105,PS_DDR_DQ18_502
+R4,502,IOPAD_X1Y20,PSS2_X32Y105,PS_DDR_BA1_502
+R14,34,IOB_X1Y87,RIOB33_X73Y87,IO_L6N_T0_VREF_34
+R16,34,IOB_X1Y62,RIOB33_X73Y61,IO_L19P_T3_34
+R17,34,IOB_X1Y61,RIOB33_X73Y61,IO_L19N_T3_VREF_34
+R18,34,IOB_X1Y59,RIOB33_X73Y59,IO_L20N_T3_34
+R19,34,IOB_X1Y99,RIOB33_SING_X73Y99,IO_0_34
+T1,502,IOPAD_X1Y30,PSS2_X32Y105,PS_DDR_DM2_502
+T2,502,IOPAD_X1Y66,PSS2_X32Y105,PS_DDR_DQS_N2_502
+T4,502,IOPAD_X1Y52,PSS2_X32Y105,PS_DDR_DQ20_502
+T5,13,IOB_X0Y12,LIOB33_X0Y11,IO_L19P_T3_13
+T9,13,IOB_X0Y26,LIOB33_X0Y25,IO_L12P_T1_MRCC_13
+T10,34,IOB_X1Y97,RIOB33_X73Y97,IO_L1N_T0_34
+T11,34,IOB_X1Y98,RIOB33_X73Y97,IO_L1P_T0_34
+T12,34,IOB_X1Y96,RIOB33_X73Y95,IO_L2P_T0_34
+T14,34,IOB_X1Y90,RIOB33_X73Y89,IO_L5P_T0_34
+T15,34,IOB_X1Y89,RIOB33_X73Y89,IO_L5N_T0_34
+T16,34,IOB_X1Y82,RIOB33_X73Y81,IO_L9P_T1_DQS_34
+T17,34,IOB_X1Y60,RIOB33_X73Y59,IO_L20P_T3_34
+T19,34,IOB_X1Y50,RIOB33_SING_X73Y50,IO_25_34
+T20,34,IOB_X1Y70,RIOB33_X73Y69,IO_L15P_T2_DQS_34
+U2,502,IOPAD_X1Y54,PSS2_X32Y105,PS_DDR_DQ22_502
+U3,502,IOPAD_X1Y55,PSS2_X32Y105,PS_DDR_DQ23_502
+U4,502,IOPAD_X1Y53,PSS2_X32Y105,PS_DDR_DQ21_502
+U5,13,IOB_X0Y11,LIOB33_X0Y11,IO_L19N_T3_VREF_13
+U7,13,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_13
+U8,13,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_13
+U9,13,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_13
+U10,13,IOB_X0Y25,LIOB33_X0Y25,IO_L12N_T1_MRCC_13
+U12,34,IOB_X1Y95,RIOB33_X73Y95,IO_L2N_T0_34
+U13,34,IOB_X1Y94,RIOB33_X73Y93,IO_L3P_T0_DQS_PUDC_B_34
+U14,34,IOB_X1Y78,RIOB33_X73Y77,IO_L11P_T1_SRCC_34
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diff --git a/zynq7/xc7z020clg400-2/part.json b/zynq7/xc7z020clg400-2/part.json
new file mode 100644
index 0000000..7615789
--- /dev/null
+++ b/zynq7/xc7z020clg400-2/part.json
@@ -0,0 +1,775 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ },
+ "4": {
+ "frame_count": 128
+ },
+ "5": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
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+ }
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+ "4": {
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+ "5": {
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+ }
+ }
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+ "CLB_IO_CLK": {
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+ },
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+ }
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+ }
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+ },
+ "73": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 57831571,
+ "iobanks": {
+ "0": "X185Y130",
+ "13": "X1Y26",
+ "34": "X185Y78",
+ "35": "X185Y130"
+ }
+}
diff --git a/zynq7/xc7z020clg400-2/part.yaml b/zynq7/xc7z020clg400-2/part.yaml
new file mode 100644
index 0000000..44218dc
--- /dev/null
+++ b/zynq7/xc7z020clg400-2/part.yaml
@@ -0,0 +1,505 @@
+!<xilinx/xc7series/part>
+idcode: 0x3727093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
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+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
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+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
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diff --git a/zynq7/xc7z020clg400-3/package_pins.csv b/zynq7/xc7z020clg400-3/package_pins.csv
new file mode 100644
index 0000000..8c78375
--- /dev/null
+++ b/zynq7/xc7z020clg400-3/package_pins.csv
@@ -0,0 +1,258 @@
+pin,bank,site,tile,pin_function
+A1,502,IOPAD_X1Y28,PSS2_X32Y105,PS_DDR_DM0_502
+A2,502,IOPAD_X1Y34,PSS2_X32Y105,PS_DDR_DQ2_502
+A4,502,IOPAD_X1Y35,PSS2_X32Y105,PS_DDR_DQ3_502
+A5,500,IOPAD_X1Y83,PSS2_X32Y105,PS_MIO6_500
+A6,500,IOPAD_X1Y82,PSS2_X32Y105,PS_MIO5_500
+A7,500,IOPAD_X1Y78,PSS2_X32Y105,PS_MIO1_500
+A9,501,IOPAD_X1Y120,PSS2_X32Y105,PS_MIO43_501
+A10,501,IOPAD_X1Y114,PSS2_X32Y105,PS_MIO37_501
+A11,501,IOPAD_X1Y113,PSS2_X32Y105,PS_MIO36_501
+A12,501,IOPAD_X1Y111,PSS2_X32Y105,PS_MIO34_501
+A14,501,IOPAD_X1Y109,PSS2_X32Y105,PS_MIO32_501
+A15,501,IOPAD_X1Y103,PSS2_X32Y105,PS_MIO26_501
+A16,501,IOPAD_X1Y101,PSS2_X32Y105,PS_MIO24_501
+A17,501,IOPAD_X1Y97,PSS2_X32Y105,PS_MIO20_501
+A19,501,IOPAD_X1Y93,PSS2_X32Y105,PS_MIO16_501
+A20,35,IOB_X1Y145,RIOB33_X73Y145,IO_L2N_T0_AD8N_35
+B2,502,IOPAD_X1Y64,PSS2_X32Y105,PS_DDR_DQS_N0_502
+B3,502,IOPAD_X1Y33,PSS2_X32Y105,PS_DDR_DQ1_502
+B4,502,IOPAD_X1Y72,PSS2_X32Y105,PS_DDR_DRST_B_502
+B5,500,IOPAD_X1Y86,PSS2_X32Y105,PS_MIO9_500
+B7,500,IOPAD_X1Y81,PSS2_X32Y105,PS_MIO4_500
+B8,500,IOPAD_X1Y79,PSS2_X32Y105,PS_MIO2_500
+B9,501,IOPAD_X1Y128,PSS2_X32Y105,PS_MIO51_501
+B10,501,IOPAD_X1Y134,PSS2_X32Y105,PS_SRST_B_501
+B12,501,IOPAD_X1Y125,PSS2_X32Y105,PS_MIO48_501
+B13,501,IOPAD_X1Y127,PSS2_X32Y105,PS_MIO50_501
+B14,501,IOPAD_X1Y124,PSS2_X32Y105,PS_MIO47_501
+B15,501,IOPAD_X1Y122,PSS2_X32Y105,PS_MIO45_501
+B17,501,IOPAD_X1Y99,PSS2_X32Y105,PS_MIO22_501
+B18,501,IOPAD_X1Y95,PSS2_X32Y105,PS_MIO18_501
+B19,35,IOB_X1Y146,RIOB33_X73Y145,IO_L2P_T0_AD8P_35
+B20,35,IOB_X1Y147,RIOB33_X73Y147,IO_L1N_T0_AD0N_35
+C1,502,IOPAD_X1Y38,PSS2_X32Y105,PS_DDR_DQ6_502
+C2,502,IOPAD_X1Y68,PSS2_X32Y105,PS_DDR_DQS_P0_502
+C3,502,IOPAD_X1Y32,PSS2_X32Y105,PS_DDR_DQ0_502
+C5,500,IOPAD_X1Y91,PSS2_X32Y105,PS_MIO14_500
+C6,500,IOPAD_X1Y88,PSS2_X32Y105,PS_MIO11_500
+C7,500,IOPAD_X1Y132,PSS2_X32Y105,PS_POR_B_500
+C8,500,IOPAD_X1Y92,PSS2_X32Y105,PS_MIO15_500
+C10,501,IOPAD_X1Y129,PSS2_X32Y105,PS_MIO52_501
+C11,501,IOPAD_X1Y130,PSS2_X32Y105,PS_MIO53_501
+C12,501,IOPAD_X1Y126,PSS2_X32Y105,PS_MIO49_501
+C13,501,IOPAD_X1Y106,PSS2_X32Y105,PS_MIO29_501
+C15,501,IOPAD_X1Y107,PSS2_X32Y105,PS_MIO30_501
+C16,501,IOPAD_X1Y105,PSS2_X32Y105,PS_MIO28_501
+C17,501,IOPAD_X1Y118,PSS2_X32Y105,PS_MIO41_501
+C18,501,IOPAD_X1Y116,PSS2_X32Y105,PS_MIO39_501
+C20,35,IOB_X1Y148,RIOB33_X73Y147,IO_L1P_T0_AD0P_35
+D1,502,IOPAD_X1Y37,PSS2_X32Y105,PS_DDR_DQ5_502
+D3,502,IOPAD_X1Y36,PSS2_X32Y105,PS_DDR_DQ4_502
+D4,502,IOPAD_X1Y18,PSS2_X32Y105,PS_DDR_A13_502
+D5,500,IOPAD_X1Y85,PSS2_X32Y105,PS_MIO8_500
+D6,500,IOPAD_X1Y80,PSS2_X32Y105,PS_MIO3_500
+D8,500,IOPAD_X1Y84,PSS2_X32Y105,PS_MIO7_500
+D9,500,IOPAD_X1Y89,PSS2_X32Y105,PS_MIO12_500
+D10,501,IOPAD_X1Y96,PSS2_X32Y105,PS_MIO19_501
+D11,501,IOPAD_X1Y100,PSS2_X32Y105,PS_MIO23_501
+D13,501,IOPAD_X1Y104,PSS2_X32Y105,PS_MIO27_501
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diff --git a/zynq7/xc7z020clg400-3/part.json b/zynq7/xc7z020clg400-3/part.json
new file mode 100644
index 0000000..7615789
--- /dev/null
+++ b/zynq7/xc7z020clg400-3/part.json
@@ -0,0 +1,775 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ },
+ "4": {
+ "frame_count": 128
+ },
+ "5": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
+ "frame_count": 36
+ },
+ "3": {
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+ },
+ "4": {
+ "frame_count": 36
+ },
+ "5": {
+ "frame_count": 36
+ },
+ "6": {
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+ },
+ "7": {
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+ },
+ "8": {
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+ },
+ "9": {
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+ },
+ "10": {
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+ },
+ "11": {
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+ },
+ "12": {
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+ },
+ "13": {
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+ },
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+ },
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+ },
+ "16": {
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+ },
+ "17": {
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+ },
+ "18": {
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+ },
+ "19": {
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+ },
+ "20": {
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+ },
+ "21": {
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+ },
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+ },
+ "23": {
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+ },
+ "24": {
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+ },
+ "25": {
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+ },
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+ },
+ "27": {
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+ },
+ "28": {
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+ },
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+ },
+ "30": {
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+ },
+ "31": {
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+ },
+ "32": {
+ "frame_count": 36
+ },
+ "33": {
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+ },
+ "34": {
+ "frame_count": 36
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+ }
+ }
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+ }
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+ },
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+ }
+ }
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+ "CLB_IO_CLK": {
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+ },
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+ },
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+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 57831571,
+ "iobanks": {
+ "0": "X185Y130",
+ "13": "X1Y26",
+ "34": "X185Y78",
+ "35": "X185Y130"
+ }
+}
diff --git a/zynq7/xc7z020clg400-3/part.yaml b/zynq7/xc7z020clg400-3/part.yaml
new file mode 100644
index 0000000..44218dc
--- /dev/null
+++ b/zynq7/xc7z020clg400-3/part.yaml
@@ -0,0 +1,505 @@
+!<xilinx/xc7series/part>
+idcode: 0x3727093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 58: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 59: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 62: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 65: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 66: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 67: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 68: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 69: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 70: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 71: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 72: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 73: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
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+ frame_count: 30
+ 73: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
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+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
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+ 62: !<xilinx/xc7series/configuration_column>
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+ 63: !<xilinx/xc7series/configuration_column>
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+ 64: !<xilinx/xc7series/configuration_column>
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+ 65: !<xilinx/xc7series/configuration_column>
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+ 66: !<xilinx/xc7series/configuration_column>
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+ 67: !<xilinx/xc7series/configuration_column>
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+ 69: !<xilinx/xc7series/configuration_column>
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+ 70: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 71: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 72: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 73: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/zynq7/xc7z020clg484-2/package_pins.csv b/zynq7/xc7z020clg484-2/package_pins.csv
new file mode 100644
index 0000000..d543dee
--- /dev/null
+++ b/zynq7/xc7z020clg484-2/package_pins.csv
@@ -0,0 +1,333 @@
+pin,bank,site,tile,pin_function
+A1,500,IOPAD_X1Y78,PSS2_X32Y105,PS_MIO1_500
+A2,500,IOPAD_X1Y79,PSS2_X32Y105,PS_MIO2_500
+A3,500,IOPAD_X1Y82,PSS2_X32Y105,PS_MIO5_500
+A4,500,IOPAD_X1Y83,PSS2_X32Y105,PS_MIO6_500
+A6,500,IOPAD_X1Y90,PSS2_X32Y105,PS_MIO13_500
+A7,501,IOPAD_X1Y95,PSS2_X32Y105,PS_MIO18_501
+A8,501,IOPAD_X1Y97,PSS2_X32Y105,PS_MIO20_501
+A9,501,IOPAD_X1Y113,PSS2_X32Y105,PS_MIO36_501
+A11,501,IOPAD_X1Y107,PSS2_X32Y105,PS_MIO30_501
+A12,501,IOPAD_X1Y105,PSS2_X32Y105,PS_MIO28_501
+A13,501,IOPAD_X1Y103,PSS2_X32Y105,PS_MIO26_501
+A14,501,IOPAD_X1Y99,PSS2_X32Y105,PS_MIO22_501
+A16,35,IOB_X1Y132,RIOB33_X73Y131,IO_L9P_T1_DQS_AD3P_35
+A17,35,IOB_X1Y131,RIOB33_X73Y131,IO_L9N_T1_DQS_AD3N_35
+A18,35,IOB_X1Y130,RIOB33_X73Y129,IO_L10P_T1_AD11P_35
+A19,35,IOB_X1Y129,RIOB33_X73Y129,IO_L10N_T1_AD11N_35
+A21,35,IOB_X1Y120,RIOB33_X73Y119,IO_L15P_T2_DQS_AD12P_35
+A22,35,IOB_X1Y119,RIOB33_X73Y119,IO_L15N_T2_DQS_AD12N_35
+AA1,502,IOPAD_X1Y58,PSS2_X32Y105,PS_DDR_DQ26_502
+AA2,502,IOPAD_X1Y31,PSS2_X32Y105,PS_DDR_DM3_502
+AA3,502,IOPAD_X1Y56,PSS2_X32Y105,PS_DDR_DQ24_502
+AA4,13,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_13
+AA6,13,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_13
+AA7,13,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_13
+AA8,13,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_13
+AA9,13,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_13
+AA11,13,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_13
+AA12,13,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_13
+AA13,33,IOB_X1Y3,RIOB33_X73Y3,IO_L23N_T3_33
+AA14,33,IOB_X1Y5,RIOB33_X73Y5,IO_L22N_T3_33
+AA16,33,IOB_X1Y14,RIOB33_X73Y13,IO_L18P_T2_33
+AA17,33,IOB_X1Y16,RIOB33_X73Y15,IO_L17P_T2_33
+AA18,33,IOB_X1Y25,RIOB33_X73Y25,IO_L12N_T1_MRCC_33
+AA19,33,IOB_X1Y27,RIOB33_X73Y27,IO_L11N_T1_SRCC_33
+AA21,33,IOB_X1Y34,RIOB33_X73Y33,IO_L8P_T1_33
+AA22,33,IOB_X1Y36,RIOB33_X73Y35,IO_L7P_T1_33
+AB1,13,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_13
+AB2,13,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_13
+AB4,13,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_13
+AB5,13,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_13
+AB6,13,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_13
+AB7,13,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_13
+AB9,13,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_13
+AB10,13,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_13
+AB11,13,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_13
+AB12,13,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_13
+AB14,33,IOB_X1Y2,RIOB33_X73Y1,IO_L24P_T3_33
+AB15,33,IOB_X1Y1,RIOB33_X73Y1,IO_L24N_T3_33
+AB16,33,IOB_X1Y13,RIOB33_X73Y13,IO_L18N_T2_33
+AB17,33,IOB_X1Y15,RIOB33_X73Y15,IO_L17N_T2_33
+AB19,33,IOB_X1Y30,RIOB33_X73Y29,IO_L10P_T1_33
+AB20,33,IOB_X1Y29,RIOB33_X73Y29,IO_L10N_T1_33
+AB21,33,IOB_X1Y33,RIOB33_X73Y33,IO_L8N_T1_33
+AB22,33,IOB_X1Y35,RIOB33_X73Y35,IO_L7N_T1_33
+B1,502,IOPAD_X1Y28,PSS2_X32Y105,PS_DDR_DM0_502
+B2,502,IOPAD_X1Y34,PSS2_X32Y105,PS_DDR_DQ2_502
+B4,500,IOPAD_X1Y88,PSS2_X32Y105,PS_MIO11_500
+B5,500,IOPAD_X1Y132,PSS2_X32Y105,PS_POR_B_500
+B6,500,IOPAD_X1Y91,PSS2_X32Y105,PS_MIO14_500
+B7,501,IOPAD_X1Y101,PSS2_X32Y105,PS_MIO24_501
+B9,501,IOPAD_X1Y122,PSS2_X32Y105,PS_MIO45_501
+B10,501,IOPAD_X1Y124,PSS2_X32Y105,PS_MIO47_501
+B11,501,IOPAD_X1Y120,PSS2_X32Y105,PS_MIO43_501
+B12,501,IOPAD_X1Y111,PSS2_X32Y105,PS_MIO34_501
+B14,501,IOPAD_X1Y114,PSS2_X32Y105,PS_MIO37_501
+B15,35,IOB_X1Y135,RIOB33_X73Y135,IO_L7N_T1_AD2N_35
+B16,35,IOB_X1Y134,RIOB33_X73Y133,IO_L8P_T1_AD10P_35
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+B20,35,IOB_X1Y123,RIOB33_X73Y123,IO_L13N_T2_MRCC_35
+B21,35,IOB_X1Y114,RIOB33_X73Y113,IO_L18P_T2_AD13P_35
+B22,35,IOB_X1Y113,RIOB33_X73Y113,IO_L18N_T2_AD13N_35
+C2,502,IOPAD_X1Y68,PSS2_X32Y105,PS_DDR_DQS_P0_502
+C3,502,IOPAD_X1Y33,PSS2_X32Y105,PS_DDR_DQ1_502
+C4,500,IOPAD_X1Y86,PSS2_X32Y105,PS_MIO9_500
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+C13,501,IOPAD_X1Y116,PSS2_X32Y105,PS_MIO39_501
+C14,501,IOPAD_X1Y126,PSS2_X32Y105,PS_MIO49_501
+C15,35,IOB_X1Y136,RIOB33_X73Y135,IO_L7P_T1_AD2P_35
+C17,35,IOB_X1Y128,RIOB33_X73Y127,IO_L11P_T1_SRCC_35
+C18,35,IOB_X1Y127,RIOB33_X73Y127,IO_L11N_T1_SRCC_35
+C19,35,IOB_X1Y125,RIOB33_X73Y125,IO_L12N_T1_MRCC_35
+C20,35,IOB_X1Y121,RIOB33_X73Y121,IO_L14N_T2_AD4N_SRCC_35
+C22,35,IOB_X1Y117,RIOB33_X73Y117,IO_L16N_T2_35
+D1,502,IOPAD_X1Y32,PSS2_X32Y105,PS_DDR_DQ0_502
+D2,502,IOPAD_X1Y64,PSS2_X32Y105,PS_DDR_DQS_N0_502
+D3,502,IOPAD_X1Y35,PSS2_X32Y105,PS_DDR_DQ3_502
+D5,500,IOPAD_X1Y84,PSS2_X32Y105,PS_MIO7_500
+D6,501,IOPAD_X1Y93,PSS2_X32Y105,PS_MIO16_501
+D7,501,IOPAD_X1Y104,PSS2_X32Y105,PS_MIO27_501
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+D10,501,IOPAD_X1Y129,PSS2_X32Y105,PS_MIO52_501
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+D12,501,IOPAD_X1Y123,PSS2_X32Y105,PS_MIO46_501
+D13,501,IOPAD_X1Y127,PSS2_X32Y105,PS_MIO50_501
+D15,35,IOB_X1Y143,RIOB33_X73Y143,IO_L3N_T0_DQS_AD1N_35
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+D17,35,IOB_X1Y145,RIOB33_X73Y145,IO_L2N_T0_AD8N_35
+D18,35,IOB_X1Y126,RIOB33_X73Y125,IO_L12P_T1_MRCC_35
+D20,35,IOB_X1Y122,RIOB33_X73Y121,IO_L14P_T2_AD4P_SRCC_35
+D21,35,IOB_X1Y115,RIOB33_X73Y115,IO_L17N_T2_AD5N_35
+D22,35,IOB_X1Y118,RIOB33_X73Y117,IO_L16P_T2_35
+E1,502,IOPAD_X1Y37,PSS2_X32Y105,PS_DDR_DQ5_502
+E3,502,IOPAD_X1Y36,PSS2_X32Y105,PS_DDR_DQ4_502
+E4,500,IOPAD_X1Y81,PSS2_X32Y105,PS_MIO4_500
+E5,500,IOPAD_X1Y85,PSS2_X32Y105,PS_MIO8_500
+E6,500,IOPAD_X1Y92,PSS2_X32Y105,PS_MIO15_500
+E8,501,IOPAD_X1Y106,PSS2_X32Y105,PS_MIO29_501
+E9,501,IOPAD_X1Y94,PSS2_X32Y105,PS_MIO17_501
+E10,501,IOPAD_X1Y96,PSS2_X32Y105,PS_MIO19_501
+E11,501,IOPAD_X1Y100,PSS2_X32Y105,PS_MIO23_501
+E13,501,IOPAD_X1Y121,PSS2_X32Y105,PS_MIO44_501
+E14,501,IOPAD_X1Y117,PSS2_X32Y105,PS_MIO40_501
+E15,35,IOB_X1Y144,RIOB33_X73Y143,IO_L3P_T0_DQS_AD1P_35
+E16,35,IOB_X1Y147,RIOB33_X73Y147,IO_L1N_T0_AD0N_35
+E18,35,IOB_X1Y139,RIOB33_X73Y139,IO_L5N_T0_AD9N_35
+E19,35,IOB_X1Y108,RIOB33_X73Y107,IO_L21P_T3_DQS_AD14P_35
+E20,35,IOB_X1Y107,RIOB33_X73Y107,IO_L21N_T3_DQS_AD14N_35
+E21,35,IOB_X1Y116,RIOB33_X73Y115,IO_L17P_T2_AD5P_35
+F1,502,IOPAD_X1Y39,PSS2_X32Y105,PS_DDR_DQ7_502
+F2,502,IOPAD_X1Y38,PSS2_X32Y105,PS_DDR_DQ6_502
+F3,502,IOPAD_X1Y72,PSS2_X32Y105,PS_DDR_DRST_B_502
+F4,502,IOPAD_X1Y18,PSS2_X32Y105,PS_DDR_A13_502
+F6,500,IOPAD_X1Y80,PSS2_X32Y105,PS_MIO3_500
+F7,500,IOPAD_X1Y26,PSS2_X32Y105,PS_CLK_500
+F9,501,IOPAD_X1Y108,PSS2_X32Y105,PS_MIO31_501
+F11,501,IOPAD_X1Y98,PSS2_X32Y105,PS_MIO21_501
+F12,501,IOPAD_X1Y102,PSS2_X32Y105,PS_MIO25_501
+F13,501,IOPAD_X1Y115,PSS2_X32Y105,PS_MIO38_501
+F14,501,IOPAD_X1Y112,PSS2_X32Y105,PS_MIO35_501
+F16,35,IOB_X1Y148,RIOB33_X73Y147,IO_L1P_T0_AD0P_35
+F17,35,IOB_X1Y137,RIOB33_X73Y137,IO_L6N_T0_VREF_35
+F18,35,IOB_X1Y140,RIOB33_X73Y139,IO_L5P_T0_AD9P_35
+F19,35,IOB_X1Y109,RIOB33_X73Y109,IO_L20N_T3_AD6N_35
+F21,35,IOB_X1Y104,RIOB33_X73Y103,IO_L23P_T3_35
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diff --git a/zynq7/xc7z020clg484-2/part.json b/zynq7/xc7z020clg484-2/part.json
new file mode 100644
index 0000000..89d54d9
--- /dev/null
+++ b/zynq7/xc7z020clg484-2/part.json
@@ -0,0 +1,776 @@
+{
+ "global_clock_regions": {
+ "bottom": {
+ "rows": {
+ "0": {
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+ "configuration_columns": {
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+ }
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+ }
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+ }
+ }
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+ },
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+ },
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+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
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+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
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+ },
+ "2": {
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+ },
+ "3": {
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+ },
+ "4": {
+ "frame_count": 128
+ },
+ "5": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
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+ },
+ "2": {
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+ },
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+ },
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+ },
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+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 57831571,
+ "iobanks": {
+ "0": "X185Y130",
+ "13": "X1Y26",
+ "33": "X185Y26",
+ "34": "X185Y78",
+ "35": "X185Y130"
+ }
+}
diff --git a/zynq7/xc7z020clg484-2/part.yaml b/zynq7/xc7z020clg484-2/part.yaml
new file mode 100644
index 0000000..44218dc
--- /dev/null
+++ b/zynq7/xc7z020clg484-2/part.yaml
@@ -0,0 +1,505 @@
+!<xilinx/xc7series/part>
+idcode: 0x3727093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 58: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 59: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 62: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 65: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 66: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 67: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 68: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 69: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 70: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 71: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 72: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 73: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
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+ 55: !<xilinx/xc7series/configuration_column>
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+ 56: !<xilinx/xc7series/configuration_column>
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+ 57: !<xilinx/xc7series/configuration_column>
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+ 58: !<xilinx/xc7series/configuration_column>
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+ 59: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 60: !<xilinx/xc7series/configuration_column>
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+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 62: !<xilinx/xc7series/configuration_column>
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+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 65: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 66: !<xilinx/xc7series/configuration_column>
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+ 70: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 71: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 72: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 73: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
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+ 4: !<xilinx/xc7series/configuration_column>
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+ 5: !<xilinx/xc7series/configuration_column>
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+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
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+ 17: !<xilinx/xc7series/configuration_column>
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+ 18: !<xilinx/xc7series/configuration_column>
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+ 19: !<xilinx/xc7series/configuration_column>
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+ 20: !<xilinx/xc7series/configuration_column>
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+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
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+ 24: !<xilinx/xc7series/configuration_column>
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+ 25: !<xilinx/xc7series/configuration_column>
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+ 26: !<xilinx/xc7series/configuration_column>
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+ 27: !<xilinx/xc7series/configuration_column>
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+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
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+ 31: !<xilinx/xc7series/configuration_column>
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+ 32: !<xilinx/xc7series/configuration_column>
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+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
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+ 39: !<xilinx/xc7series/configuration_column>
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+ 40: !<xilinx/xc7series/configuration_column>
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+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
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+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 58: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 59: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 62: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 65: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 66: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 67: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 68: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 69: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 70: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 71: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 72: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 73: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
diff --git a/zynq7/xc7z020clg484-3/package_pins.csv b/zynq7/xc7z020clg484-3/package_pins.csv
new file mode 100644
index 0000000..d543dee
--- /dev/null
+++ b/zynq7/xc7z020clg484-3/package_pins.csv
@@ -0,0 +1,333 @@
+pin,bank,site,tile,pin_function
+A1,500,IOPAD_X1Y78,PSS2_X32Y105,PS_MIO1_500
+A2,500,IOPAD_X1Y79,PSS2_X32Y105,PS_MIO2_500
+A3,500,IOPAD_X1Y82,PSS2_X32Y105,PS_MIO5_500
+A4,500,IOPAD_X1Y83,PSS2_X32Y105,PS_MIO6_500
+A6,500,IOPAD_X1Y90,PSS2_X32Y105,PS_MIO13_500
+A7,501,IOPAD_X1Y95,PSS2_X32Y105,PS_MIO18_501
+A8,501,IOPAD_X1Y97,PSS2_X32Y105,PS_MIO20_501
+A9,501,IOPAD_X1Y113,PSS2_X32Y105,PS_MIO36_501
+A11,501,IOPAD_X1Y107,PSS2_X32Y105,PS_MIO30_501
+A12,501,IOPAD_X1Y105,PSS2_X32Y105,PS_MIO28_501
+A13,501,IOPAD_X1Y103,PSS2_X32Y105,PS_MIO26_501
+A14,501,IOPAD_X1Y99,PSS2_X32Y105,PS_MIO22_501
+A16,35,IOB_X1Y132,RIOB33_X73Y131,IO_L9P_T1_DQS_AD3P_35
+A17,35,IOB_X1Y131,RIOB33_X73Y131,IO_L9N_T1_DQS_AD3N_35
+A18,35,IOB_X1Y130,RIOB33_X73Y129,IO_L10P_T1_AD11P_35
+A19,35,IOB_X1Y129,RIOB33_X73Y129,IO_L10N_T1_AD11N_35
+A21,35,IOB_X1Y120,RIOB33_X73Y119,IO_L15P_T2_DQS_AD12P_35
+A22,35,IOB_X1Y119,RIOB33_X73Y119,IO_L15N_T2_DQS_AD12N_35
+AA1,502,IOPAD_X1Y58,PSS2_X32Y105,PS_DDR_DQ26_502
+AA2,502,IOPAD_X1Y31,PSS2_X32Y105,PS_DDR_DM3_502
+AA3,502,IOPAD_X1Y56,PSS2_X32Y105,PS_DDR_DQ24_502
+AA4,13,IOB_X0Y13,LIOB33_X0Y13,IO_L18N_T2_13
+AA6,13,IOB_X0Y21,LIOB33_X0Y21,IO_L14N_T2_SRCC_13
+AA7,13,IOB_X0Y22,LIOB33_X0Y21,IO_L14P_T2_SRCC_13
+AA8,13,IOB_X0Y27,LIOB33_X0Y27,IO_L11N_T1_SRCC_13
+AA9,13,IOB_X0Y28,LIOB33_X0Y27,IO_L11P_T1_SRCC_13
+AA11,13,IOB_X0Y34,LIOB33_X0Y33,IO_L8P_T1_13
+AA12,13,IOB_X0Y36,LIOB33_X0Y35,IO_L7P_T1_13
+AA13,33,IOB_X1Y3,RIOB33_X73Y3,IO_L23N_T3_33
+AA14,33,IOB_X1Y5,RIOB33_X73Y5,IO_L22N_T3_33
+AA16,33,IOB_X1Y14,RIOB33_X73Y13,IO_L18P_T2_33
+AA17,33,IOB_X1Y16,RIOB33_X73Y15,IO_L17P_T2_33
+AA18,33,IOB_X1Y25,RIOB33_X73Y25,IO_L12N_T1_MRCC_33
+AA19,33,IOB_X1Y27,RIOB33_X73Y27,IO_L11N_T1_SRCC_33
+AA21,33,IOB_X1Y34,RIOB33_X73Y33,IO_L8P_T1_33
+AA22,33,IOB_X1Y36,RIOB33_X73Y35,IO_L7P_T1_33
+AB1,13,IOB_X0Y19,LIOB33_X0Y19,IO_L15N_T2_DQS_13
+AB2,13,IOB_X0Y20,LIOB33_X0Y19,IO_L15P_T2_DQS_13
+AB4,13,IOB_X0Y17,LIOB33_X0Y17,IO_L16N_T2_13
+AB5,13,IOB_X0Y18,LIOB33_X0Y17,IO_L16P_T2_13
+AB6,13,IOB_X0Y15,LIOB33_X0Y15,IO_L17N_T2_13
+AB7,13,IOB_X0Y16,LIOB33_X0Y15,IO_L17P_T2_13
+AB9,13,IOB_X0Y31,LIOB33_X0Y31,IO_L9N_T1_DQS_13
+AB10,13,IOB_X0Y32,LIOB33_X0Y31,IO_L9P_T1_DQS_13
+AB11,13,IOB_X0Y33,LIOB33_X0Y33,IO_L8N_T1_13
+AB12,13,IOB_X0Y35,LIOB33_X0Y35,IO_L7N_T1_13
+AB14,33,IOB_X1Y2,RIOB33_X73Y1,IO_L24P_T3_33
+AB15,33,IOB_X1Y1,RIOB33_X73Y1,IO_L24N_T3_33
+AB16,33,IOB_X1Y13,RIOB33_X73Y13,IO_L18N_T2_33
+AB17,33,IOB_X1Y15,RIOB33_X73Y15,IO_L17N_T2_33
+AB19,33,IOB_X1Y30,RIOB33_X73Y29,IO_L10P_T1_33
+AB20,33,IOB_X1Y29,RIOB33_X73Y29,IO_L10N_T1_33
+AB21,33,IOB_X1Y33,RIOB33_X73Y33,IO_L8N_T1_33
+AB22,33,IOB_X1Y35,RIOB33_X73Y35,IO_L7N_T1_33
+B1,502,IOPAD_X1Y28,PSS2_X32Y105,PS_DDR_DM0_502
+B2,502,IOPAD_X1Y34,PSS2_X32Y105,PS_DDR_DQ2_502
+B4,500,IOPAD_X1Y88,PSS2_X32Y105,PS_MIO11_500
+B5,500,IOPAD_X1Y132,PSS2_X32Y105,PS_POR_B_500
+B6,500,IOPAD_X1Y91,PSS2_X32Y105,PS_MIO14_500
+B7,501,IOPAD_X1Y101,PSS2_X32Y105,PS_MIO24_501
+B9,501,IOPAD_X1Y122,PSS2_X32Y105,PS_MIO45_501
+B10,501,IOPAD_X1Y124,PSS2_X32Y105,PS_MIO47_501
+B11,501,IOPAD_X1Y120,PSS2_X32Y105,PS_MIO43_501
+B12,501,IOPAD_X1Y111,PSS2_X32Y105,PS_MIO34_501
+B14,501,IOPAD_X1Y114,PSS2_X32Y105,PS_MIO37_501
+B15,35,IOB_X1Y135,RIOB33_X73Y135,IO_L7N_T1_AD2N_35
+B16,35,IOB_X1Y134,RIOB33_X73Y133,IO_L8P_T1_AD10P_35
+B17,35,IOB_X1Y133,RIOB33_X73Y133,IO_L8N_T1_AD10N_35
+B19,35,IOB_X1Y124,RIOB33_X73Y123,IO_L13P_T2_MRCC_35
+B20,35,IOB_X1Y123,RIOB33_X73Y123,IO_L13N_T2_MRCC_35
+B21,35,IOB_X1Y114,RIOB33_X73Y113,IO_L18P_T2_AD13P_35
+B22,35,IOB_X1Y113,RIOB33_X73Y113,IO_L18N_T2_AD13N_35
+C2,502,IOPAD_X1Y68,PSS2_X32Y105,PS_DDR_DQS_P0_502
+C3,502,IOPAD_X1Y33,PSS2_X32Y105,PS_DDR_DQ1_502
+C4,500,IOPAD_X1Y86,PSS2_X32Y105,PS_MIO9_500
+C5,500,IOPAD_X1Y89,PSS2_X32Y105,PS_MIO12_500
+C7,501,IOPAD_X1Y109,PSS2_X32Y105,PS_MIO32_501
+C8,501,IOPAD_X1Y118,PSS2_X32Y105,PS_MIO41_501
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+C12,501,IOPAD_X1Y130,PSS2_X32Y105,PS_MIO53_501
+C13,501,IOPAD_X1Y116,PSS2_X32Y105,PS_MIO39_501
+C14,501,IOPAD_X1Y126,PSS2_X32Y105,PS_MIO49_501
+C15,35,IOB_X1Y136,RIOB33_X73Y135,IO_L7P_T1_AD2P_35
+C17,35,IOB_X1Y128,RIOB33_X73Y127,IO_L11P_T1_SRCC_35
+C18,35,IOB_X1Y127,RIOB33_X73Y127,IO_L11N_T1_SRCC_35
+C19,35,IOB_X1Y125,RIOB33_X73Y125,IO_L12N_T1_MRCC_35
+C20,35,IOB_X1Y121,RIOB33_X73Y121,IO_L14N_T2_AD4N_SRCC_35
+C22,35,IOB_X1Y117,RIOB33_X73Y117,IO_L16N_T2_35
+D1,502,IOPAD_X1Y32,PSS2_X32Y105,PS_DDR_DQ0_502
+D2,502,IOPAD_X1Y64,PSS2_X32Y105,PS_DDR_DQS_N0_502
+D3,502,IOPAD_X1Y35,PSS2_X32Y105,PS_DDR_DQ3_502
+D5,500,IOPAD_X1Y84,PSS2_X32Y105,PS_MIO7_500
+D6,501,IOPAD_X1Y93,PSS2_X32Y105,PS_MIO16_501
+D7,501,IOPAD_X1Y104,PSS2_X32Y105,PS_MIO27_501
+D8,501,IOPAD_X1Y119,PSS2_X32Y105,PS_MIO42_501
+D10,501,IOPAD_X1Y129,PSS2_X32Y105,PS_MIO52_501
+D11,501,IOPAD_X1Y125,PSS2_X32Y105,PS_MIO48_501
+D12,501,IOPAD_X1Y123,PSS2_X32Y105,PS_MIO46_501
+D13,501,IOPAD_X1Y127,PSS2_X32Y105,PS_MIO50_501
+D15,35,IOB_X1Y143,RIOB33_X73Y143,IO_L3N_T0_DQS_AD1N_35
+D16,35,IOB_X1Y146,RIOB33_X73Y145,IO_L2P_T0_AD8P_35
+D17,35,IOB_X1Y145,RIOB33_X73Y145,IO_L2N_T0_AD8N_35
+D18,35,IOB_X1Y126,RIOB33_X73Y125,IO_L12P_T1_MRCC_35
+D20,35,IOB_X1Y122,RIOB33_X73Y121,IO_L14P_T2_AD4P_SRCC_35
+D21,35,IOB_X1Y115,RIOB33_X73Y115,IO_L17N_T2_AD5N_35
+D22,35,IOB_X1Y118,RIOB33_X73Y117,IO_L16P_T2_35
+E1,502,IOPAD_X1Y37,PSS2_X32Y105,PS_DDR_DQ5_502
+E3,502,IOPAD_X1Y36,PSS2_X32Y105,PS_DDR_DQ4_502
+E4,500,IOPAD_X1Y81,PSS2_X32Y105,PS_MIO4_500
+E5,500,IOPAD_X1Y85,PSS2_X32Y105,PS_MIO8_500
+E6,500,IOPAD_X1Y92,PSS2_X32Y105,PS_MIO15_500
+E8,501,IOPAD_X1Y106,PSS2_X32Y105,PS_MIO29_501
+E9,501,IOPAD_X1Y94,PSS2_X32Y105,PS_MIO17_501
+E10,501,IOPAD_X1Y96,PSS2_X32Y105,PS_MIO19_501
+E11,501,IOPAD_X1Y100,PSS2_X32Y105,PS_MIO23_501
+E13,501,IOPAD_X1Y121,PSS2_X32Y105,PS_MIO44_501
+E14,501,IOPAD_X1Y117,PSS2_X32Y105,PS_MIO40_501
+E15,35,IOB_X1Y144,RIOB33_X73Y143,IO_L3P_T0_DQS_AD1P_35
+E16,35,IOB_X1Y147,RIOB33_X73Y147,IO_L1N_T0_AD0N_35
+E18,35,IOB_X1Y139,RIOB33_X73Y139,IO_L5N_T0_AD9N_35
+E19,35,IOB_X1Y108,RIOB33_X73Y107,IO_L21P_T3_DQS_AD14P_35
+E20,35,IOB_X1Y107,RIOB33_X73Y107,IO_L21N_T3_DQS_AD14N_35
+E21,35,IOB_X1Y116,RIOB33_X73Y115,IO_L17P_T2_AD5P_35
+F1,502,IOPAD_X1Y39,PSS2_X32Y105,PS_DDR_DQ7_502
+F2,502,IOPAD_X1Y38,PSS2_X32Y105,PS_DDR_DQ6_502
+F3,502,IOPAD_X1Y72,PSS2_X32Y105,PS_DDR_DRST_B_502
+F4,502,IOPAD_X1Y18,PSS2_X32Y105,PS_DDR_A13_502
+F6,500,IOPAD_X1Y80,PSS2_X32Y105,PS_MIO3_500
+F7,500,IOPAD_X1Y26,PSS2_X32Y105,PS_CLK_500
+F9,501,IOPAD_X1Y108,PSS2_X32Y105,PS_MIO31_501
+F11,501,IOPAD_X1Y98,PSS2_X32Y105,PS_MIO21_501
+F12,501,IOPAD_X1Y102,PSS2_X32Y105,PS_MIO25_501
+F13,501,IOPAD_X1Y115,PSS2_X32Y105,PS_MIO38_501
+F14,501,IOPAD_X1Y112,PSS2_X32Y105,PS_MIO35_501
+F16,35,IOB_X1Y148,RIOB33_X73Y147,IO_L1P_T0_AD0P_35
+F17,35,IOB_X1Y137,RIOB33_X73Y137,IO_L6N_T0_VREF_35
+F18,35,IOB_X1Y140,RIOB33_X73Y139,IO_L5P_T0_AD9P_35
+F19,35,IOB_X1Y109,RIOB33_X73Y109,IO_L20N_T3_AD6N_35
+F21,35,IOB_X1Y104,RIOB33_X73Y103,IO_L23P_T3_35
+F22,35,IOB_X1Y103,RIOB33_X73Y103,IO_L23N_T3_35
+G1,502,IOPAD_X1Y41,PSS2_X32Y105,PS_DDR_DQ9_502
+G2,502,IOPAD_X1Y40,PSS2_X32Y105,PS_DDR_DQ8_502
+G4,502,IOPAD_X1Y17,PSS2_X32Y105,PS_DDR_A14_502
+G5,502,IOPAD_X1Y15,PSS2_X32Y105,PS_DDR_A11_502
+G6,500,IOPAD_X1Y77,PSS2_X32Y105,PS_MIO0_500
+G7,500,IOPAD_X1Y87,PSS2_X32Y105,PS_MIO10_500
+G13,501,IOPAD_X1Y110,PSS2_X32Y105,PS_MIO33_501
+G15,35,IOB_X1Y142,RIOB33_X73Y141,IO_L4P_T0_35
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diff --git a/zynq7/xc7z020clg484-3/part.json b/zynq7/xc7z020clg484-3/part.json
new file mode 100644
index 0000000..89d54d9
--- /dev/null
+++ b/zynq7/xc7z020clg484-3/part.json
@@ -0,0 +1,776 @@
+{
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+ },
+ "73": {
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+ }
+ }
+ }
+ }
+ },
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+ "frame_count": 128
+ },
+ "1": {
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+ },
+ "2": {
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+ },
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+ },
+ "4": {
+ "frame_count": 128
+ },
+ "5": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
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+ "frame_count": 42
+ },
+ "1": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ "frame_count": 30
+ },
+ "73": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "top": {
+ "rows": {
+ "0": {
+ "configuration_buses": {
+ "BLOCK_RAM": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 128
+ },
+ "1": {
+ "frame_count": 128
+ },
+ "2": {
+ "frame_count": 128
+ },
+ "3": {
+ "frame_count": 128
+ },
+ "4": {
+ "frame_count": 128
+ },
+ "5": {
+ "frame_count": 128
+ }
+ }
+ },
+ "CLB_IO_CLK": {
+ "configuration_columns": {
+ "0": {
+ "frame_count": 42
+ },
+ "1": {
+ "frame_count": 30
+ },
+ "2": {
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+ },
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+ },
+ "31": {
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+ },
+ "32": {
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+ },
+ "33": {
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+ },
+ "34": {
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+ },
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+ },
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+ },
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+ },
+ "38": {
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ },
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+ "frame_count": 36
+ },
+ "71": {
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+ },
+ "72": {
+ "frame_count": 30
+ },
+ "73": {
+ "frame_count": 42
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "idcode": 57831571,
+ "iobanks": {
+ "0": "X185Y130",
+ "13": "X1Y26",
+ "33": "X185Y26",
+ "34": "X185Y78",
+ "35": "X185Y130"
+ }
+}
diff --git a/zynq7/xc7z020clg484-3/part.yaml b/zynq7/xc7z020clg484-3/part.yaml
new file mode 100644
index 0000000..44218dc
--- /dev/null
+++ b/zynq7/xc7z020clg484-3/part.yaml
@@ -0,0 +1,505 @@
+!<xilinx/xc7series/part>
+idcode: 0x3727093
+global_clock_regions:
+ top: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 58: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 59: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 62: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 65: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 66: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 67: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 68: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 69: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 70: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 71: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 72: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 73: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ bottom: !<xilinx/xc7series/global_clock_region>
+ rows:
+ 0: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 58: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 59: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 62: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 65: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 66: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 67: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 68: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 69: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 70: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 71: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 72: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 73: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/row>
+ configuration_buses:
+ CLB_IO_CLK: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 6: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 7: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 8: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 9: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 10: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 11: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 12: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 13: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 14: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 15: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 16: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 17: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 18: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 19: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 20: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 21: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 22: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 23: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 24: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 25: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 26: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 27: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 28: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 29: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 30: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 31: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 32: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 33: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 34: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 35: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 36: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 37: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 38: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 39: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 40: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 41: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 42: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 43: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 44: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 45: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 46: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 47: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 48: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 49: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 50: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 51: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 52: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 53: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 54: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 55: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 56: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 57: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 58: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 59: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 60: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 61: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 62: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 63: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 64: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 65: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 66: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 67: !<xilinx/xc7series/configuration_column>
+ frame_count: 28
+ 68: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 69: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 70: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 71: !<xilinx/xc7series/configuration_column>
+ frame_count: 36
+ 72: !<xilinx/xc7series/configuration_column>
+ frame_count: 30
+ 73: !<xilinx/xc7series/configuration_column>
+ frame_count: 42
+ BLOCK_RAM: !<xilinx/xc7series/configuration_bus>
+ configuration_columns:
+ 0: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 1: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 2: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 3: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 4: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
+ 5: !<xilinx/xc7series/configuration_column>
+ frame_count: 128
