diff --git a/Info.md b/Info.md
index 731d096..a9a9f16 100644
--- a/Info.md
+++ b/Info.md
@@ -37,20 +37,20 @@
 
 # Details
 
-Last updated on Tue 29 Oct 2019 05:19:37 PM UTC (2019-10-29T17:19:37+00:00).
+Last updated on Wed 30 Oct 2019 11:49:37 PM UTC (2019-10-30T23:49:37+00:00).
 
-Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [844036dd](https://github.com/SymbiFlow/prjxray/commit/844036dd83dc0470b927a0c44c1fe28fe6cf981e).
+Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [daf28415](https://github.com/SymbiFlow/prjxray/commit/daf284151c160efb67ec57d4215a76826be3071e).
 
 Latest commit was;
 ```
-commit 844036dd83dc0470b927a0c44c1fe28fe6cf981e
-Merge: 0802ccbc 6a5076dd
-Author: Tim Ansell <me@mith.ro>
-Date:   Mon Oct 28 07:12:19 2019 -0700
+commit daf284151c160efb67ec57d4215a76826be3071e
+Merge: 78cf96be 43fe925f
+Author: litghost <537074+litghost@users.noreply.github.com>
+Date:   Wed Oct 30 10:40:01 2019 -0700
 
-    Merge pull request #1123 from SymbiFlow/dependabot/submodules/third_party/abseil-cpp-078b89b
+    Merge pull request #1119 from antmicro/litex_litedram
     
-    build(deps): bump third_party/abseil-cpp from `e4c8d0e` to `078b89b`
+    minitests: Add test for Litex DRAM memory interface
 ```
 
 
@@ -59,7 +59,7 @@
 
 ### Settings
 
-Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/844036dd83dc0470b927a0c44c1fe28fe6cf981e/settings/artix7.sh)
+Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/daf284151c160efb67ec57d4215a76826be3071e/settings/artix7.sh)
 ```shell
 export XRAY_DATABASE="artix7"
 export XRAY_PART="xc7a50tfgg484-1"
@@ -149,13 +149,13 @@
  * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd  ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./artix7/mask_hclk_r.origin_info.db`](./artix7/mask_hclk_r.origin_info.db)
  * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./artix7/mask_liob33.db`](./artix7/mask_liob33.db)
- * [`25361d286759cd0d8a876ae458ba1d2145422f056dad5c400a2e1c74d9b9e60e  ./artix7/mask_lioi3.db`](./artix7/mask_lioi3.db)
- * [`25361d286759cd0d8a876ae458ba1d2145422f056dad5c400a2e1c74d9b9e60e  ./artix7/mask_lioi3_tbytesrc.db`](./artix7/mask_lioi3_tbytesrc.db)
- * [`25361d286759cd0d8a876ae458ba1d2145422f056dad5c400a2e1c74d9b9e60e  ./artix7/mask_lioi3_tbyteterm.db`](./artix7/mask_lioi3_tbyteterm.db)
+ * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./artix7/mask_lioi3.db`](./artix7/mask_lioi3.db)
+ * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./artix7/mask_lioi3_tbytesrc.db`](./artix7/mask_lioi3_tbytesrc.db)
+ * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./artix7/mask_lioi3_tbyteterm.db`](./artix7/mask_lioi3_tbyteterm.db)
  * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./artix7/mask_riob33.db`](./artix7/mask_riob33.db)
- * [`25361d286759cd0d8a876ae458ba1d2145422f056dad5c400a2e1c74d9b9e60e  ./artix7/mask_rioi3.db`](./artix7/mask_rioi3.db)
- * [`25361d286759cd0d8a876ae458ba1d2145422f056dad5c400a2e1c74d9b9e60e  ./artix7/mask_rioi3_tbytesrc.db`](./artix7/mask_rioi3_tbytesrc.db)
- * [`25361d286759cd0d8a876ae458ba1d2145422f056dad5c400a2e1c74d9b9e60e  ./artix7/mask_rioi3_tbyteterm.db`](./artix7/mask_rioi3_tbyteterm.db)
+ * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./artix7/mask_rioi3.db`](./artix7/mask_rioi3.db)
+ * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./artix7/mask_rioi3_tbytesrc.db`](./artix7/mask_rioi3_tbytesrc.db)
+ * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./artix7/mask_rioi3_tbyteterm.db`](./artix7/mask_rioi3_tbyteterm.db)
  * [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf  ./artix7/ppips_bram_int_interface_l.db`](./artix7/ppips_bram_int_interface_l.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./artix7/ppips_bram_int_interface_l.origin_info.db`](./artix7/ppips_bram_int_interface_l.origin_info.db)
  * [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae  ./artix7/ppips_bram_int_interface_r.db`](./artix7/ppips_bram_int_interface_r.db)
@@ -239,10 +239,10 @@
  * [`796d0c51db5d34d08e5e63d3c0484cd51b9b693f7b169cf6c7a9faa12ba4b641  ./artix7/segbits_clk_hrow_bot_r.origin_info.db`](./artix7/segbits_clk_hrow_bot_r.origin_info.db)
  * [`8ab24467b7f56fa8ff0dd334c0588cb196a4d875895abb48afcd33e1e2ba1deb  ./artix7/segbits_clk_hrow_top_r.db`](./artix7/segbits_clk_hrow_top_r.db)
  * [`9aaf521930e3632c7e8aac861a3cd3dd48b95401905f7a1cabfabf0caf836045  ./artix7/segbits_clk_hrow_top_r.origin_info.db`](./artix7/segbits_clk_hrow_top_r.origin_info.db)
- * [`86e644b4402a2f9889b1b816ec75fe6ff312ca5caa21ee2f40452a577abd9bf0  ./artix7/segbits_cmt_top_l_upper_t.db`](./artix7/segbits_cmt_top_l_upper_t.db)
- * [`dc2e5dfe1240812d522e8d4641cf5444ab5fbeedcacb2f7282a7a4a67ccbf7de  ./artix7/segbits_cmt_top_l_upper_t.origin_info.db`](./artix7/segbits_cmt_top_l_upper_t.origin_info.db)
- * [`34eea9806fcf0de805b4657aa91851eef1360006588d58eddbc656efee38e43c  ./artix7/segbits_cmt_top_r_upper_t.db`](./artix7/segbits_cmt_top_r_upper_t.db)
- * [`9a043aa3d3723270607e7901b72c09e834f8d954fe2abef1bec4c02852c9471a  ./artix7/segbits_cmt_top_r_upper_t.origin_info.db`](./artix7/segbits_cmt_top_r_upper_t.origin_info.db)
+ * [`58e94fa2c72dc551e01e492d170db05556ac90bfa09fb1c46b38804cb680a196  ./artix7/segbits_cmt_top_l_upper_t.db`](./artix7/segbits_cmt_top_l_upper_t.db)
+ * [`0e38f50896c11f0134f79a920fba0906f015305d296d30c45cd20601fad2c57f  ./artix7/segbits_cmt_top_l_upper_t.origin_info.db`](./artix7/segbits_cmt_top_l_upper_t.origin_info.db)
+ * [`616a0118601d5541e896267dfecb5409a3704b957946644994ae48061be270aa  ./artix7/segbits_cmt_top_r_upper_t.db`](./artix7/segbits_cmt_top_r_upper_t.db)
+ * [`4e8cebea5342f4404affa6c91e3245b960d2f75d1f3a4e3ceb875760a56666c9  ./artix7/segbits_cmt_top_r_upper_t.origin_info.db`](./artix7/segbits_cmt_top_r_upper_t.origin_info.db)
  * [`0c4a6e4bc385a8b3a43d05a06d8e87c8822cf2cc1742593167244ff194af4a5e  ./artix7/segbits_dsp_l.db`](./artix7/segbits_dsp_l.db)
  * [`85105e324b53c9b8a3d60a3631e125c2e6dc1329e017636232313c4aa8e1576d  ./artix7/segbits_dsp_l.origin_info.db`](./artix7/segbits_dsp_l.origin_info.db)
  * [`b014d7e2b101b0b0540a539cb74a76ccbe3a494e225e8e510bf258a457b18685  ./artix7/segbits_dsp_r.db`](./artix7/segbits_dsp_r.db)
@@ -260,7 +260,7 @@
  * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520  ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
  * [`3c1ed23386f51a5d35afbb6e837110d97a57ea34140dc67d60784b397ad9776c  ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db)
  * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556  ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
- * [`b696b765aadeaca42a1360d6e0a71ac04531a3fdee2a049b6fc31eb4853880e8  ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
+ * [`80d6f8d86143a77710ce6aac70ef5ba94c0eb4a45fa006cba120e10a5c9e4de9  ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db)
  * [`92913f6d38cfdb14fb9c16e70a47d75e507c0ee4764bcc7941f2e0ac3e784e88  ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db)
  * [`2772dce8b6a4f6f6691ca0c0b30535c230041ebad17d318ce9962161e607be5c  ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db)
  * [`cf4f6a2b44d13e094f588464a902c315080d2150a522e4241c82ca201a4771e0  ./artix7/segbits_lioi3.db`](./artix7/segbits_lioi3.db)
@@ -499,7 +499,7 @@
 
 ### Settings
 
-Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/844036dd83dc0470b927a0c44c1fe28fe6cf981e/settings/kintex7.sh)
+Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/daf284151c160efb67ec57d4215a76826be3071e/settings/kintex7.sh)
 ```shell
 export XRAY_DATABASE="kintex7"
 export XRAY_PART="xc7k70tfbg676-2"
@@ -567,13 +567,13 @@
  * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd  ./kintex7/mask_hclk_r.db`](./kintex7/mask_hclk_r.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./kintex7/mask_hclk_r.origin_info.db`](./kintex7/mask_hclk_r.origin_info.db)
  * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./kintex7/mask_liob33.db`](./kintex7/mask_liob33.db)
- * [`bb15395b2160fb36875915d4eb580cbdc0afd52d77fc93f4d540aaddc7b8b965  ./kintex7/mask_lioi3.db`](./kintex7/mask_lioi3.db)
- * [`bb15395b2160fb36875915d4eb580cbdc0afd52d77fc93f4d540aaddc7b8b965  ./kintex7/mask_lioi3_tbytesrc.db`](./kintex7/mask_lioi3_tbytesrc.db)
- * [`bb15395b2160fb36875915d4eb580cbdc0afd52d77fc93f4d540aaddc7b8b965  ./kintex7/mask_lioi3_tbyteterm.db`](./kintex7/mask_lioi3_tbyteterm.db)
+ * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./kintex7/mask_lioi3.db`](./kintex7/mask_lioi3.db)
+ * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./kintex7/mask_lioi3_tbytesrc.db`](./kintex7/mask_lioi3_tbytesrc.db)
+ * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./kintex7/mask_lioi3_tbyteterm.db`](./kintex7/mask_lioi3_tbyteterm.db)
  * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./kintex7/mask_riob33.db`](./kintex7/mask_riob33.db)
- * [`bb15395b2160fb36875915d4eb580cbdc0afd52d77fc93f4d540aaddc7b8b965  ./kintex7/mask_rioi3.db`](./kintex7/mask_rioi3.db)
- * [`bb15395b2160fb36875915d4eb580cbdc0afd52d77fc93f4d540aaddc7b8b965  ./kintex7/mask_rioi3_tbytesrc.db`](./kintex7/mask_rioi3_tbytesrc.db)
- * [`bb15395b2160fb36875915d4eb580cbdc0afd52d77fc93f4d540aaddc7b8b965  ./kintex7/mask_rioi3_tbyteterm.db`](./kintex7/mask_rioi3_tbyteterm.db)
+ * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./kintex7/mask_rioi3.db`](./kintex7/mask_rioi3.db)
+ * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./kintex7/mask_rioi3_tbytesrc.db`](./kintex7/mask_rioi3_tbytesrc.db)
+ * [`7db4e012a058ddedde6f42fd3cf00105d56ae9695e6755b52c421bfc32e404a8  ./kintex7/mask_rioi3_tbyteterm.db`](./kintex7/mask_rioi3_tbyteterm.db)
  * [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf  ./kintex7/ppips_bram_int_interface_l.db`](./kintex7/ppips_bram_int_interface_l.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./kintex7/ppips_bram_int_interface_l.origin_info.db`](./kintex7/ppips_bram_int_interface_l.origin_info.db)
  * [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae  ./kintex7/ppips_bram_int_interface_r.db`](./kintex7/ppips_bram_int_interface_r.db)
@@ -653,10 +653,10 @@
  * [`98a0bebc0686e678d32b844f2675e81ea11d6236d161da1a1362b8745633f8bd  ./kintex7/segbits_clk_hrow_bot_r.origin_info.db`](./kintex7/segbits_clk_hrow_bot_r.origin_info.db)
  * [`89ca5e5d4e9bc222815bd81e6d94cbff6950b99e3d2e80ac677334dcde40e4c2  ./kintex7/segbits_clk_hrow_top_r.db`](./kintex7/segbits_clk_hrow_top_r.db)
  * [`ba635ce2ad2f1e907c65f943bd4c5500e9c6b135a7f0b2334e7a0a021ed07389  ./kintex7/segbits_clk_hrow_top_r.origin_info.db`](./kintex7/segbits_clk_hrow_top_r.origin_info.db)
- * [`17a25c5ed3a670a3fe612f59bee920df981ccff474eeeb12e8fb72d20267f070  ./kintex7/segbits_cmt_top_l_upper_t.db`](./kintex7/segbits_cmt_top_l_upper_t.db)
- * [`cd5e9413d2b05bd806b3fc45a7e1c8e581c8ae7544c2c4804256c867c085b55b  ./kintex7/segbits_cmt_top_l_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_l_upper_t.origin_info.db)
- * [`9dd188916b72375540ec4177f30c8bf965ef50aaac8346bfd99593b73fd7fa37  ./kintex7/segbits_cmt_top_r_upper_t.db`](./kintex7/segbits_cmt_top_r_upper_t.db)
- * [`e684d8323dfea73289cff48af79f6a74fc3df8def5de3265ee5a22f6ac8f5e77  ./kintex7/segbits_cmt_top_r_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_r_upper_t.origin_info.db)
+ * [`2a7535f456758251b4d8bc9d5a8b4d3ea803b88bbb30572e08ae552d92d209f1  ./kintex7/segbits_cmt_top_l_upper_t.db`](./kintex7/segbits_cmt_top_l_upper_t.db)
+ * [`d3db1fc1c0a06f0cbea022affc6376c51960636e1fcd739b07851f87cb4c673d  ./kintex7/segbits_cmt_top_l_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_l_upper_t.origin_info.db)
+ * [`fda7e0c2805de552580b0c4740534d6ae7e8974aee15fc7adc82ec8f8bbe9653  ./kintex7/segbits_cmt_top_r_upper_t.db`](./kintex7/segbits_cmt_top_r_upper_t.db)
+ * [`15270ddb444e16c84f678eb03f0e704a90c60ba3e7c94d191dc6545ebce1cac1  ./kintex7/segbits_cmt_top_r_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_r_upper_t.origin_info.db)
  * [`0c4a6e4bc385a8b3a43d05a06d8e87c8822cf2cc1742593167244ff194af4a5e  ./kintex7/segbits_dsp_l.db`](./kintex7/segbits_dsp_l.db)
  * [`85105e324b53c9b8a3d60a3631e125c2e6dc1329e017636232313c4aa8e1576d  ./kintex7/segbits_dsp_l.origin_info.db`](./kintex7/segbits_dsp_l.origin_info.db)
  * [`b014d7e2b101b0b0540a539cb74a76ccbe3a494e225e8e510bf258a457b18685  ./kintex7/segbits_dsp_r.db`](./kintex7/segbits_dsp_r.db)
@@ -867,7 +867,7 @@
 
 ### Settings
 
-Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/844036dd83dc0470b927a0c44c1fe28fe6cf981e/settings/zynq7.sh)
+Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/daf284151c160efb67ec57d4215a76826be3071e/settings/zynq7.sh)
 ```shell
 export XRAY_DATABASE="zynq7"
 export XRAY_PART="xc7z010clg400-1"
@@ -938,13 +938,13 @@
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./zynq7/mask_hclk_l.origin_info.db`](./zynq7/mask_hclk_l.origin_info.db)
  * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd  ./zynq7/mask_hclk_r.db`](./zynq7/mask_hclk_r.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./zynq7/mask_hclk_r.origin_info.db`](./zynq7/mask_hclk_r.origin_info.db)
- * [`8e2f44ff09fd16757b49b2d98ffb0f274317fbc04fa0de0d466def6d35ef8bf9  ./zynq7/mask_lioi3.db`](./zynq7/mask_lioi3.db)
- * [`8e2f44ff09fd16757b49b2d98ffb0f274317fbc04fa0de0d466def6d35ef8bf9  ./zynq7/mask_lioi3_tbytesrc.db`](./zynq7/mask_lioi3_tbytesrc.db)
- * [`8e2f44ff09fd16757b49b2d98ffb0f274317fbc04fa0de0d466def6d35ef8bf9  ./zynq7/mask_lioi3_tbyteterm.db`](./zynq7/mask_lioi3_tbyteterm.db)
+ * [`0b62252a0c7638e7cccd730ccf26ea2fe891f753cf77648461254f77f2ad5529  ./zynq7/mask_lioi3.db`](./zynq7/mask_lioi3.db)
+ * [`0b62252a0c7638e7cccd730ccf26ea2fe891f753cf77648461254f77f2ad5529  ./zynq7/mask_lioi3_tbytesrc.db`](./zynq7/mask_lioi3_tbytesrc.db)
+ * [`0b62252a0c7638e7cccd730ccf26ea2fe891f753cf77648461254f77f2ad5529  ./zynq7/mask_lioi3_tbyteterm.db`](./zynq7/mask_lioi3_tbyteterm.db)
  * [`a0777dc0808e70052a6f6b2e1056f6e9dd225032c01195919d927be7ba1b97d6  ./zynq7/mask_riob33.db`](./zynq7/mask_riob33.db)
- * [`8e2f44ff09fd16757b49b2d98ffb0f274317fbc04fa0de0d466def6d35ef8bf9  ./zynq7/mask_rioi3.db`](./zynq7/mask_rioi3.db)
- * [`8e2f44ff09fd16757b49b2d98ffb0f274317fbc04fa0de0d466def6d35ef8bf9  ./zynq7/mask_rioi3_tbytesrc.db`](./zynq7/mask_rioi3_tbytesrc.db)
- * [`8e2f44ff09fd16757b49b2d98ffb0f274317fbc04fa0de0d466def6d35ef8bf9  ./zynq7/mask_rioi3_tbyteterm.db`](./zynq7/mask_rioi3_tbyteterm.db)
+ * [`0b62252a0c7638e7cccd730ccf26ea2fe891f753cf77648461254f77f2ad5529  ./zynq7/mask_rioi3.db`](./zynq7/mask_rioi3.db)
+ * [`0b62252a0c7638e7cccd730ccf26ea2fe891f753cf77648461254f77f2ad5529  ./zynq7/mask_rioi3_tbytesrc.db`](./zynq7/mask_rioi3_tbytesrc.db)
+ * [`0b62252a0c7638e7cccd730ccf26ea2fe891f753cf77648461254f77f2ad5529  ./zynq7/mask_rioi3_tbyteterm.db`](./zynq7/mask_rioi3_tbyteterm.db)
  * [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf  ./zynq7/ppips_bram_int_interface_l.db`](./zynq7/ppips_bram_int_interface_l.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./zynq7/ppips_bram_int_interface_l.origin_info.db`](./zynq7/ppips_bram_int_interface_l.origin_info.db)
  * [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae  ./zynq7/ppips_bram_int_interface_r.db`](./zynq7/ppips_bram_int_interface_r.db)
@@ -1018,8 +1018,8 @@
  * [`8454c4735a9df6aed62e15df3a7a6ff53fb4b7aaf14b9ac8d13f4fc913924841  ./zynq7/segbits_clk_hrow_bot_r.origin_info.db`](./zynq7/segbits_clk_hrow_bot_r.origin_info.db)
  * [`063d0e4f5a34a6b65fc7083d47860ebcc548950ac2c39b74f0cc37728d976d6c  ./zynq7/segbits_clk_hrow_top_r.db`](./zynq7/segbits_clk_hrow_top_r.db)
  * [`6b63e363bf0573eb3820db68f1d4a101c5e5f8923b65b97bd0475590b9b0f206  ./zynq7/segbits_clk_hrow_top_r.origin_info.db`](./zynq7/segbits_clk_hrow_top_r.origin_info.db)
- * [`4ed063af5123971fca48e0eec5398d147f7fc7894e5662f0d5adcf7567a4fd45  ./zynq7/segbits_cmt_top_l_upper_t.db`](./zynq7/segbits_cmt_top_l_upper_t.db)
- * [`48d087f9daa912ebcde82411341c178ffe55d3d6c0d601f2d5fa8b5d23eb62ae  ./zynq7/segbits_cmt_top_l_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_l_upper_t.origin_info.db)
+ * [`ac4c4b1a3ae7a4ae6ef829a4ac6a7c8a286477e03875c9662ea6dac694f2dde2  ./zynq7/segbits_cmt_top_l_upper_t.db`](./zynq7/segbits_cmt_top_l_upper_t.db)
+ * [`e23a62d0f57948dd166b5a33b77afb1699b46c526f72dc4e376da04f36e0e1be  ./zynq7/segbits_cmt_top_l_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_l_upper_t.origin_info.db)
  * [`6b205562d2e870f43d7959a05b1b8fbd75bfbb08878bb7ec5239d6b419ce3117  ./zynq7/segbits_cmt_top_r_upper_t.db`](./zynq7/segbits_cmt_top_r_upper_t.db)
  * [`29023fed85b544c2d849067d1c945cb9cdc64fa2f4070acf6496ea132f9f3997  ./zynq7/segbits_cmt_top_r_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_r_upper_t.origin_info.db)
  * [`0c4a6e4bc385a8b3a43d05a06d8e87c8822cf2cc1742593167244ff194af4a5e  ./zynq7/segbits_dsp_l.db`](./zynq7/segbits_dsp_l.db)
@@ -1035,9 +1035,9 @@
  * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9  ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db)
  * [`0e9b5da6def4776e2ca8dd59af8f4334bf5cfb88d99b323be25dd6ba2e3386f7  ./zynq7/segbits_hclk_r.origin_info.db`](./zynq7/segbits_hclk_r.origin_info.db)
  * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520  ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db)
- * [`115ea4bd077008e5308104a5b6ec4ef43b986e9fcf4d162d5ad57bc13bbb0321  ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
+ * [`7641073505be3aa9be78f640d5112e2a615a39f3ca8b8d1037440b5f7c2f4b9f  ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db)
  * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556  ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db)
- * [`831ad7a69ffbf7ab4fce10ba0c7c72585c9dc4920e595e2422e47f2ae388cda7  ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
+ * [`7bbf7bc8d1ea43573749a06dd83d43aec0f8c44fc532b7ebf719df2d10b85422  ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db)
  * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855  ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db)
  * [`cf4f6a2b44d13e094f588464a902c315080d2150a522e4241c82ca201a4771e0  ./zynq7/segbits_lioi3.db`](./zynq7/segbits_lioi3.db)
diff --git a/artix7/mask_lioi3.db b/artix7/mask_lioi3.db
index 14db8b8..4c3181d 100644
--- a/artix7/mask_lioi3.db
+++ b/artix7/mask_lioi3.db
@@ -1,7 +1,6 @@
 bit 25_07
 bit 25_20
 bit 25_21
-bit 25_24
 bit 25_31
 bit 25_32
 bit 25_34
diff --git a/artix7/mask_lioi3_tbytesrc.db b/artix7/mask_lioi3_tbytesrc.db
index 14db8b8..4c3181d 100644
--- a/artix7/mask_lioi3_tbytesrc.db
+++ b/artix7/mask_lioi3_tbytesrc.db
@@ -1,7 +1,6 @@
 bit 25_07
 bit 25_20
 bit 25_21
-bit 25_24
 bit 25_31
 bit 25_32
 bit 25_34
diff --git a/artix7/mask_lioi3_tbyteterm.db b/artix7/mask_lioi3_tbyteterm.db
index 14db8b8..4c3181d 100644
--- a/artix7/mask_lioi3_tbyteterm.db
+++ b/artix7/mask_lioi3_tbyteterm.db
@@ -1,7 +1,6 @@
 bit 25_07
 bit 25_20
 bit 25_21
-bit 25_24
 bit 25_31
 bit 25_32
 bit 25_34
diff --git a/artix7/mask_rioi3.db b/artix7/mask_rioi3.db
index 14db8b8..4c3181d 100644
--- a/artix7/mask_rioi3.db
+++ b/artix7/mask_rioi3.db
@@ -1,7 +1,6 @@
 bit 25_07
 bit 25_20
 bit 25_21
-bit 25_24
 bit 25_31
 bit 25_32
 bit 25_34
diff --git a/artix7/mask_rioi3_tbytesrc.db b/artix7/mask_rioi3_tbytesrc.db
index 14db8b8..4c3181d 100644
--- a/artix7/mask_rioi3_tbytesrc.db
+++ b/artix7/mask_rioi3_tbytesrc.db
@@ -1,7 +1,6 @@
 bit 25_07
 bit 25_20
 bit 25_21
-bit 25_24
 bit 25_31
 bit 25_32
 bit 25_34
diff --git a/artix7/mask_rioi3_tbyteterm.db b/artix7/mask_rioi3_tbyteterm.db
index 14db8b8..4c3181d 100644
--- a/artix7/mask_rioi3_tbyteterm.db
+++ b/artix7/mask_rioi3_tbyteterm.db
@@ -1,7 +1,6 @@
 bit 25_07
 bit 25_20
 bit 25_21
-bit 25_24
 bit 25_31
 bit 25_32
 bit 25_34
diff --git a/artix7/ppips_cmt_top_l_lower_b.db b/artix7/ppips_cmt_top_l_lower_b.db
new file mode 100644
index 0000000..d367998
--- /dev/null
+++ b/artix7/ppips_cmt_top_l_lower_b.db
@@ -0,0 +1,155 @@
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB0.MMCM_CLK_FREQ_BB_NS3 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB1.MMCM_CLK_FREQ_BB_NS2 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB2.MMCM_CLK_FREQ_BB_NS1 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB3.MMCM_CLK_FREQ_BB_NS0 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN1_INT.CMT_TOP_CLK0_15 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN2_INT.CMT_TOP_CLK1_15 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN3_INT.CMT_TOP_CLK0_14 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM1.CMT_LR_LOWER_B_MMCM_CLKOUT0B always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM2.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM3.CMT_LR_LOWER_B_MMCM_CLKOUT1B always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM4.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM5.CMT_LR_LOWER_B_MMCM_CLKOUT2B always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM6.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM7.CMT_LR_LOWER_B_MMCM_CLKOUT3B always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM8.CMT_LR_LOWER_B_MMCM_CLKOUT4 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM9.CMT_LR_LOWER_B_MMCM_CLKOUT5 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM10.CMT_LR_LOWER_B_MMCM_CLKOUT6 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM11.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM12.CMT_LR_LOWER_B_MMCM_CLKFBOUTB always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM13.CMT_LR_LOWER_B_MMCM_TMUXOUT always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSEL.CMT_TOP_IMUX0_2 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DCLK.CMT_TOP_CLK0_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DEN.CMT_TOP_IMUX15_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DWE.CMT_TOP_IMUX22_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSCLK.CMT_TOP_CLK0_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSEN.CMT_TOP_IMUX1_2 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSINCDEC.CMT_TOP_IMUX2_2 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PWRDWN.CMT_TOP_IMUX47_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_RST.CMT_TOP_IMUX34_2 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR0.CMT_TOP_IMUX0_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR1.CMT_TOP_IMUX1_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR2.CMT_TOP_IMUX2_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR3.CMT_TOP_IMUX34_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR4.CMT_TOP_IMUX3_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR5.CMT_TOP_IMUX35_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR6.CMT_TOP_IMUX44_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI0.CMT_TOP_IMUX0_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI1.CMT_TOP_IMUX32_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI2.CMT_TOP_IMUX1_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI3.CMT_TOP_IMUX33_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI4.CMT_TOP_IMUX2_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI5.CMT_TOP_IMUX34_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI6.CMT_TOP_IMUX3_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI7.CMT_TOP_IMUX35_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI8.CMT_TOP_IMUX4_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI9.CMT_TOP_IMUX36_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI10.CMT_TOP_IMUX5_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI11.CMT_TOP_IMUX37_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI12.CMT_TOP_IMUX6_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI13.CMT_TOP_IMUX38_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI14.CMT_TOP_IMUX7_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI15.CMT_TOP_IMUX39_0 always
+CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI.CMT_MMCM_PHASER_IN_A_ICLK always
+CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI.CMT_MMCM_PHASER_IN_A_ICLKDIV always
+CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK always
+CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLKDIV always
+CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK1X_90 always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_0.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_1.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_2.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_3.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_4.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_5.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_6.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_7.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_8.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_9.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_10.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_11.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_12.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_13.CMT_MMCM_PHASER_IN_B_ICLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_14.CMT_MMCM_PHASER_IN_B_ICLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_15.CMT_MMCM_PHASER_IN_B_ICLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_12.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_13.CMT_MMCM_PHASER_IN_B_ICLKDIV always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_14.CMT_MMCM_PHASER_IN_B_ICLKDIV always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_15.CMT_MMCM_PHASER_IN_B_ICLKDIV always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_0.CMT_LR_LOWER_B_MMCM_DO2 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_8.CMT_MMCM_PHASERA_DQSBUS0 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_LR_LOWER_B_MMCM_DO10 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_0.CMT_LR_LOWER_B_MMCM_DO6 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_8.CMT_MMCM_PHASERA_DQSBUS1 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_LR_LOWER_B_MMCM_DO14 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B8_0.CMT_LR_LOWER_B_MMCM_DO0 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B10_0.CMT_LR_LOWER_B_MMCM_DO8 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B13_0.CMT_LR_LOWER_B_MMCM_DO4 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_MMCM_PHASERA_DTSBUS0 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_8.CMT_MMCM_PHASERA_CTSBUS0 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_LR_LOWER_B_MMCM_DO12 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_LR_LOWER_B_MMCM_DO9 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_LR_LOWER_B_MMCM_DRDY always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_2.CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_LR_LOWER_B_MMCM_DO15 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_0.CMT_LR_LOWER_B_MMCM_DO1 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_1.CMT_LR_LOWER_B_MMCM_LOCKED always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B19_0.CMT_LR_LOWER_B_MMCM_DO7 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B20_0.CMT_LR_LOWER_B_MMCM_DO11 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_LR_LOWER_B_MMCM_DO13 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_LR_LOWER_B_MMCM_PSDONE always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B22_0.CMT_LR_LOWER_B_MMCM_DO3 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_0.CMT_LR_LOWER_B_MMCM_DO5 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_MMCM_PHASERA_DTSBUS1 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_MMCM_PHASERA_CTSBUS1 always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_0.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_1.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_2.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_3.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_4.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_5.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_6.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_7.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_8.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_9.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_10.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_11.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_12.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_13.CMT_MMCM_PHASER_OUT_B_OCLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_14.CMT_MMCM_PHASER_OUT_B_OCLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_15.CMT_MMCM_PHASER_OUT_B_OCLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK1X_90_8.CMT_PHASER_A_OCLK90_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_12.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_13.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_14.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_15.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
+CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_1.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
+CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_2.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
+CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_3.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
diff --git a/artix7/ppips_cmt_top_l_lower_t.db b/artix7/ppips_cmt_top_l_lower_t.db
new file mode 100644
index 0000000..94c8dfb
--- /dev/null
+++ b/artix7/ppips_cmt_top_l_lower_t.db
@@ -0,0 +1,234 @@
+CMT_TOP_L_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_0.CMT_TOP_CLK0_8 always
+CMT_TOP_L_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_1.CMT_TOP_CLK1_8 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI.CMT_PHASER_IN_B_ICLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI.CMT_PHASER_IN_B_ICLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI.CMT_PHASER_OUT_B_OCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI.CMT_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_ICLK.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_ICLKDIV.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_OCLK.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_OCLKDIV.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI.CMT_PHASER_OUT_B_OCLK1X_90 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_ICLK.CMT_PHASER_IN_CA_ICLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_ICLKDIV.CMT_PHASER_IN_A_WRCLK_TOFIFO always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_WREN_TOFIFO.CMT_PHASER_IN_CA_WRENABLE always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_RCLK0.CMT_PHASER_IN_CA_RCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLK.CMT_PHASER_IN_DB_ICLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLKDIV.CMT_PHASER_IN_B_WRCLK_TOFIFO always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_WREN_TOFIFO.CMT_PHASER_IN_DB_WRENABLE always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_RCLK1.CMT_PHASER_IN_DB_RCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX45_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX29_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX34_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX30_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX14_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_A always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX12_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX8_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX11_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX19_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX27_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX43_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX12_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX28_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX27_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX43_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHASER_BOT_IRANKA0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHASER_BOT_IRANKA1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX31_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX23_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX44_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX47_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_B always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX47_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX0_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX13_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX31_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHASER_BOT_IRANKB0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHASER_BOT_IRANKB1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLK.CMT_PHASER_OUT_CA_OCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLKDIV.CMT_PHASER_OUT_A_RDCLK_TOFIFO always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDEN_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK.CMT_PHASER_OUT_DB_OCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV.CMT_PHASER_OUT_B_RDCLK_TOFIFO always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDEN_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX47_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX31_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX32_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_A always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX13_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX29_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX45_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX14_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX30_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX46_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX15_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX23_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX25_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX14_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX45_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX39_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX23_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX0_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX30_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX29_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX13_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_B always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX47_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX20_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX21_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX46_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX15_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX25_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_CTSBUS0.CMT_PHASER_OUT_CA_CTSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_CTSBUS1.CMT_PHASER_OUT_CA_CTSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_DQSBUS0.CMT_PHASER_OUT_CA_DQSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_DQSBUS1.CMT_PHASER_OUT_CA_DQSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_DTSBUS0.CMT_PHASER_OUT_CA_DTSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_DTSBUS1.CMT_PHASER_OUT_CA_DTSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_0.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_1.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_2.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_3.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_4.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_5.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_6.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_7.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_8.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B0_4.CMT_PHASER_OUT_DB_DQSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B1_3.CMT_PHASER_IN_CA_FINEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_7.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B5_4.CMT_PHASER_OUT_DB_DQSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_OSERDESRST always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_ISERDESRST always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_8.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_8.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_OUT_CA_OSERDESRST always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_3.CMT_PHASER_OUT_DB_DTSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_4.CMT_PHASER_OUT_DB_CTSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_7.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_6.CMT_PHASER_IN_DB_DQSFOUND always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_PHASER_IN_CA_ISERDESRST always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_4.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_IN_CA_DQSFOUND always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_3.CMT_PHASER_OUT_DB_DTSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_4.CMT_PHASER_OUT_DB_CTSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_0.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_1.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_2.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_3.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_4.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_5.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_6.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_7.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_8.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK1X_90_4.CMT_PHASER_B_OCLK90_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_B_OCLKDIV_TOIOI always
diff --git a/artix7/ppips_cmt_top_l_upper_b.db b/artix7/ppips_cmt_top_l_upper_b.db
new file mode 100644
index 0000000..15fe6d6
--- /dev/null
+++ b/artix7/ppips_cmt_top_l_upper_b.db
@@ -0,0 +1,325 @@
+CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0.PLL_CLK_FREQBB_REBUFOUT0 always
+CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1.PLL_CLK_FREQBB_REBUFOUT1 always
+CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2.PLL_CLK_FREQBB_REBUFOUT2 always
+CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3.PLL_CLK_FREQBB_REBUFOUT3 always
+CMT_TOP_L_UPPER_B.CMT_L_TOP_UPPER_B_CLKINT_2.CMT_TOP_CLK0_0 always
+CMT_TOP_L_UPPER_B.CMT_L_TOP_UPPER_B_CLKINT_3.CMT_TOP_CLK1_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI.CMT_PHASER_IN_C_ICLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI.CMT_PHASER_IN_C_ICLKDIV always
+CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI.CMT_PHASER_OUT_C_OCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI.CMT_PHASER_OUT_C_OCLKDIV always
+CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI.CMT_PHASER_OUT_C_OCLK1X_90 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLK.CMT_PHASER_IN_CA_ICLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLKDIV.CMT_R_PHASER_IN_C_WRCLK_FIFO always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_WRENABLE_FIFO.CMT_PHASER_IN_CA_WRENABLE always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_RCLK2.CMT_PHASER_IN_CA_RCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX31_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX23_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX41_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX32_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX47_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_PHASERIN_C always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX11_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX0_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX44_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX13_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX29_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX45_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX14_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX30_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX34_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX3_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHY_CONTROL_IRANKC0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHY_CONTROL_IRANKC1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_ICLK.CMT_PHASER_IN_DB_ICLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_ICLKDIV.CMT_R_PHASER_IN_D_WRCLK_TOFIFO always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_WRENABLE_FIFO.CMT_PHASER_IN_DB_WRENABLE always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_RCLK3.CMT_PHASER_IN_DB_RCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX14_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX45_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX46_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX30_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_PHASERIN_D always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX39_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX8_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_8 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX19_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX27_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX43_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX12_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX28_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX44_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX23_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHY_CONTROL_IRANKD0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHY_CONTROL_IRANKD1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK.CMT_PHASER_OUT_CA_OCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV.CMT_R_PHASER_OUT_C_RDCLK_FIFO always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX31_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX15_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX47_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_C always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX20_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX44_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX13_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX29_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX45_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX14_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX30_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX46_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX17_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIB0.CMT_TOP_IMUX18_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLK.CMT_PHASER_OUT_DB_OCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLKDIV.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX32_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX16_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX27_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX11_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX19_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX9_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX8_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX43_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_D always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX34_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX0_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX1_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX9_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX17_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX41_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX2_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX18_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX34_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX3_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX37_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIB0.CMT_TOP_IMUX17_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKIN.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKOUT_TOHCLK.CMT_PHASER_REF_CLKOUT always
+CMT_TOP_L_UPPER_B.CMT_PHASER_REF_PWRDWN.CMT_TOP_IMUX45_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_REF_RST.CMT_TOP_IMUX15_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_REF_TMUXOUT_TOHCLK.CMT_PHASER_REF_TMUXOUT always
+CMT_TOP_L_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE0.CMT_TOP_IMUX0_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE1.CMT_TOP_IMUX16_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_CTSBUS0.CMT_PHASER_OUT_DB_CTSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_CTSBUS1.CMT_PHASER_OUT_DB_CTSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_DQSBUS0.CMT_PHASER_OUT_DB_DQSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_DQSBUS1.CMT_PHASER_OUT_DB_DQSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_DTSBUS0.CMT_PHASER_OUT_DB_DTSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_DTSBUS1.CMT_PHASER_OUT_DB_DTSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY.CMT_PHY_CONTROL_PHYCTLEMPTY always
+CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY.CMT_PHASER_TOP_SYNC_BB always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCLK.CMT_TOP_CLK0_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLMSTREMPTY.CMT_PHASERTOP_PHYCTLMSTREMPTY always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWRENABLE.CMT_TOP_IMUX47_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PLLLOCK.CMT_TOP_IMUX43_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_READCALIBENABLE.CMT_TOP_IMUX29_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_REFDLLLOCK.CMT_TOP_IMUX4_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_RESET.CMT_TOP_IMUX11_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_WRITECALIBENABLE.CMT_TOP_IMUX22_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0.CMT_PHY_CONTROL_PCENABLECALIB0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1.CMT_PHY_CONTROL_PCENABLECALIB1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING0.CMT_PHY_CONTROL_INBURSTPENDING0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING1.CMT_PHY_CONTROL_INBURSTPENDING1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2.CMT_PHY_CONTROL_INBURSTPENDING2 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3.CMT_PHY_CONTROL_INBURSTPENDING3 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKA0.CMT_PHY_CONTROL_INRANKA0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKA1.CMT_PHY_CONTROL_INRANKA1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKB0.CMT_PHY_CONTROL_INRANKB0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKB1.CMT_PHY_CONTROL_INRANKB1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC0.CMT_PHY_CONTROL_INRANKC0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC1.CMT_PHY_CONTROL_INRANKC1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD0.CMT_PHY_CONTROL_INRANKD0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD1.CMT_PHY_CONTROL_INRANKD1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING0.CMT_PHY_CONTROL_OUTBURSTPENDING0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING1.CMT_PHY_CONTROL_OUTBURSTPENDING1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2.CMT_PHY_CONTROL_OUTBURSTPENDING2 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3.CMT_PHY_CONTROL_OUTBURSTPENDING3 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD0.CMT_TOP_IMUX4_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD1.CMT_TOP_IMUX20_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD2.CMT_TOP_IMUX44_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD3.CMT_TOP_IMUX13_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD4.CMT_TOP_IMUX45_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD5.CMT_TOP_IMUX14_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD6.CMT_TOP_IMUX30_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD7.CMT_TOP_IMUX46_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD8.CMT_TOP_IMUX15_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD9.CMT_TOP_IMUX31_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD10.CMT_TOP_IMUX47_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD11.CMT_TOP_IMUX20_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD12.CMT_TOP_IMUX44_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD13.CMT_TOP_IMUX13_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD14.CMT_TOP_IMUX45_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD15.CMT_TOP_IMUX14_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD16.CMT_TOP_IMUX30_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD17.CMT_TOP_IMUX46_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD18.CMT_TOP_IMUX15_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD19.CMT_TOP_IMUX31_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD20.CMT_TOP_IMUX47_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD21.CMT_TOP_IMUX43_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD22.CMT_TOP_IMUX4_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD23.CMT_TOP_IMUX20_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD24.CMT_TOP_IMUX44_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD25.CMT_TOP_IMUX13_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD26.CMT_TOP_IMUX45_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD27.CMT_TOP_IMUX14_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD28.CMT_TOP_IMUX30_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD29.CMT_TOP_IMUX46_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD30.CMT_TOP_IMUX15_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD31.CMT_TOP_IMUX31_11 always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_C_WRCLK_FIFO.CMT_PHASER_IN_CA_ICLKDIV always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_D_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDCLK_FIFO.CMT_PHASER_OUT_CA_OCLKDIV always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDENABLE_FIFO.CMT_PHASER_OUT_CA_RDENABLE always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_0.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_1.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_2.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_3.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_4.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_5.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_6.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_7.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_8.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_9.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_10.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_11.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PHASER_OUT_CA_DQSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B1_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_2.CMT_PHASER_IN_CA_FINEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_9.CMT_PHY_CONTROL_AUXOUTPUT0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PHASER_OUT_CA_DQSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_DQSFOUND always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_7.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_9.CMT_PHY_CONTROL_PHYCTLALMOSTFULL always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_6.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_7.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_2.CMT_PHASER_OUT_CA_OSERDESRST always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_3.CMT_PHASER_IN_CA_ISERDESRST always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_REF_LOCKED always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PHASER_OUT_CA_DTSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_OUT_CA_CTSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_3.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_6.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B16_5.CMT_PHASER_OUT_DB_OSERDESRST always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_8.CMT_PHY_CONTROL_PHYCTLREADY always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_9.CMT_PHY_CONTROL_PHYCTLFULL always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_10.CMT_PHY_CONTROL_AUXOUTPUT2 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_11.CMT_PHY_CONTROL_AUXOUTPUT3 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_8.CMT_PHASER_IN_DB_ISERDESRST always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_6.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_9.CMT_PHY_CONTROL_AUXOUTPUT1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PHASER_OUT_CA_DTSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PHASER_OUT_CA_CTSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_PHASER_IN_DB_DQSFOUND always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_0.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_1.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_2.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_3.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_4.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_5.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_6.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_7.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_8.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_9.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_10.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_11.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK1X_90_7.CMT_PHASER_C_OCLK90_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_C_OCLKDIV_TOIOI always
diff --git a/artix7/ppips_cmt_top_l_upper_t.db b/artix7/ppips_cmt_top_l_upper_t.db
new file mode 100644
index 0000000..a5e25c4
--- /dev/null
+++ b/artix7/ppips_cmt_top_l_upper_t.db
@@ -0,0 +1,136 @@
+CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI.CMT_PLL_PHASER_IN_D_ICLK always
+CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI.CMT_PLL_PHASER_IN_D_ICLKDIV always
+CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK always
+CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI.CMT_PLL_PHASER_OUT_D_OCLKDIV always
+CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK1X_90 always
+CMT_TOP_L_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_UP.CMT_PLL_PHYCTRL_SYNC_BB_DN always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_0.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_1.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_2.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_3.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_4.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_5.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_6.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_7.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_8.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_9.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_10.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_11.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_12.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_9.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_10.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_11.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_12.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_CLKFBOUT2IN.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0.PLL_CLK_FREQ_BB0_NS always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1.PLL_CLK_FREQ_BB1_NS always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2.PLL_CLK_FREQ_BB2_NS always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3.PLL_CLK_FREQ_BB3_NS always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL4.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL5.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL6.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL7.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT.CMT_TOP_CLK0_1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT.CMT_TOP_CLK1_0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT.CMT_TOP_CLK0_0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PLL_PHASERD_DQSBUS0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_12.CMT_TOP_R_UPPER_T_PLLE2_DO13 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B2_12.CMT_TOP_R_UPPER_T_PLLE2_DO5 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PLL_PHASERD_DQSBUS1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_12.CMT_TOP_R_UPPER_T_PLLE2_DO9 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B7_12.CMT_TOP_R_UPPER_T_PLLE2_DO1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B8_12.CMT_TOP_R_UPPER_T_PLLE2_DO15 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B10_12.CMT_TOP_R_UPPER_T_PLLE2_DO7 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B13_12.CMT_TOP_R_UPPER_T_PLLE2_DO11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PLL_PHASERD_DTSBUS0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PLL_PHASERD_CTSBUS0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B15_12.CMT_TOP_R_UPPER_T_PLLE2_DO3 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_11.CMT_TOP_R_UPPER_T_PLLE2_DRDY always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_12.CMT_TOP_R_UPPER_T_PLLE2_DO6 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B17_12.CMT_TOP_R_UPPER_T_PLLE2_DO0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B18_12.CMT_TOP_R_UPPER_T_PLLE2_DO14 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B19_12.CMT_TOP_R_UPPER_T_PLLE2_DO8 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B20_12.CMT_TOP_R_UPPER_T_PLLE2_DO4 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_11.CMT_TOP_R_UPPER_T_PLLE2_LOCKED always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_12.CMT_TOP_R_UPPER_T_PLLE2_DO2 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B22_12.CMT_TOP_R_UPPER_T_PLLE2_DO12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PLL_PHASERD_DTSBUS1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PLL_PHASERD_CTSBUS1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_12.CMT_TOP_R_UPPER_T_PLLE2_DO10 always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_0.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_1.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_2.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_3.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_4.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_5.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_6.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_7.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_8.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_9.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_10.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_11.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_12.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK1X_90_7.CMT_PHASER_D_OCLK90_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_9.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_10.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_11.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_12.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL.CMT_TOP_IMUX47_10 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DCLK.CMT_TOP_CLK0_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DEN.CMT_TOP_IMUX1_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DWE.CMT_TOP_IMUX2_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_PWRDWN.CMT_TOP_IMUX0_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_RST.CMT_TOP_IMUX13_10 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR0.CMT_TOP_IMUX47_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR1.CMT_TOP_IMUX15_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR2.CMT_TOP_IMUX22_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR3.CMT_TOP_IMUX13_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR4.CMT_TOP_IMUX44_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR5.CMT_TOP_IMUX35_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR6.CMT_TOP_IMUX3_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI0.CMT_TOP_IMUX39_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI1.CMT_TOP_IMUX7_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI2.CMT_TOP_IMUX38_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI3.CMT_TOP_IMUX6_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI4.CMT_TOP_IMUX37_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI5.CMT_TOP_IMUX5_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI6.CMT_TOP_IMUX36_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI7.CMT_TOP_IMUX4_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI8.CMT_TOP_IMUX35_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI9.CMT_TOP_IMUX3_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI10.CMT_TOP_IMUX34_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI11.CMT_TOP_IMUX2_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI12.CMT_TOP_IMUX33_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI13.CMT_TOP_IMUX1_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI14.CMT_TOP_IMUX32_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI15.CMT_TOP_IMUX0_12 always
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS0.PLL_CLK_FREQ_BB0_NS always
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS1.PLL_CLK_FREQ_BB1_NS always
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS2.PLL_CLK_FREQ_BB2_NS always
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS3.PLL_CLK_FREQ_BB3_NS always
+CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
+CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
+CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
+CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
diff --git a/artix7/ppips_cmt_top_r_lower_b.db b/artix7/ppips_cmt_top_r_lower_b.db
new file mode 100644
index 0000000..e4e8a07
--- /dev/null
+++ b/artix7/ppips_cmt_top_r_lower_b.db
@@ -0,0 +1,155 @@
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSEL.CMT_TOP_IMUX0_2 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DCLK.CMT_TOP_CLK0_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DEN.CMT_TOP_IMUX15_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DWE.CMT_TOP_IMUX22_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSCLK.CMT_TOP_CLK0_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSEN.CMT_TOP_IMUX1_2 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSINCDEC.CMT_TOP_IMUX2_2 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PWRDWN.CMT_TOP_IMUX47_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_RST.CMT_TOP_IMUX34_2 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR0.CMT_TOP_IMUX0_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR1.CMT_TOP_IMUX1_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR2.CMT_TOP_IMUX2_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR3.CMT_TOP_IMUX34_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR4.CMT_TOP_IMUX3_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR5.CMT_TOP_IMUX35_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR6.CMT_TOP_IMUX44_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI0.CMT_TOP_IMUX0_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI1.CMT_TOP_IMUX32_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI2.CMT_TOP_IMUX1_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI3.CMT_TOP_IMUX33_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI4.CMT_TOP_IMUX2_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI5.CMT_TOP_IMUX34_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI6.CMT_TOP_IMUX3_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI7.CMT_TOP_IMUX35_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI8.CMT_TOP_IMUX4_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI9.CMT_TOP_IMUX36_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI10.CMT_TOP_IMUX5_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI11.CMT_TOP_IMUX37_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI12.CMT_TOP_IMUX6_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI13.CMT_TOP_IMUX38_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI14.CMT_TOP_IMUX7_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI15.CMT_TOP_IMUX39_0 always
+CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI.CMT_MMCM_PHASER_IN_A_ICLK always
+CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI.CMT_MMCM_PHASER_IN_A_ICLKDIV always
+CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK always
+CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLKDIV always
+CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK1X_90 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB0.MMCM_CLK_FREQ_BB_NS3 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB1.MMCM_CLK_FREQ_BB_NS2 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB2.MMCM_CLK_FREQ_BB_NS1 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB3.MMCM_CLK_FREQ_BB_NS0 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN1_INT.CMT_TOP_CLK0_15 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN2_INT.CMT_TOP_CLK1_15 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN3_INT.CMT_TOP_CLK0_14 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM1.CMT_LR_LOWER_B_MMCM_CLKOUT0B always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM2.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM3.CMT_LR_LOWER_B_MMCM_CLKOUT1B always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM4.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM5.CMT_LR_LOWER_B_MMCM_CLKOUT2B always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM6.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM7.CMT_LR_LOWER_B_MMCM_CLKOUT3B always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM8.CMT_LR_LOWER_B_MMCM_CLKOUT4 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM9.CMT_LR_LOWER_B_MMCM_CLKOUT5 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM10.CMT_LR_LOWER_B_MMCM_CLKOUT6 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM11.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM12.CMT_LR_LOWER_B_MMCM_CLKFBOUTB always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM13.CMT_LR_LOWER_B_MMCM_TMUXOUT always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_0.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_1.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_2.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_3.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_4.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_5.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_6.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_7.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_8.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_9.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_10.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_11.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_12.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_13.CMT_MMCM_PHASER_IN_B_ICLK always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_14.CMT_MMCM_PHASER_IN_B_ICLK always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_15.CMT_MMCM_PHASER_IN_B_ICLK always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_12.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_13.CMT_MMCM_PHASER_IN_B_ICLKDIV always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_14.CMT_MMCM_PHASER_IN_B_ICLKDIV always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_15.CMT_MMCM_PHASER_IN_B_ICLKDIV always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_0.CMT_LR_LOWER_B_MMCM_DO2 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_8.CMT_MMCM_PHASERA_DQSBUS0 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_LR_LOWER_B_MMCM_DO10 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_0.CMT_LR_LOWER_B_MMCM_DO6 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_8.CMT_MMCM_PHASERA_DQSBUS1 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_LR_LOWER_B_MMCM_DO14 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B8_0.CMT_LR_LOWER_B_MMCM_DO0 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B10_0.CMT_LR_LOWER_B_MMCM_DO8 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B13_0.CMT_LR_LOWER_B_MMCM_DO4 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_MMCM_PHASERA_DTSBUS0 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_8.CMT_MMCM_PHASERA_CTSBUS0 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_LR_LOWER_B_MMCM_DO12 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_LR_LOWER_B_MMCM_DO9 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_LR_LOWER_B_MMCM_DRDY always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_2.CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_LR_LOWER_B_MMCM_DO15 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_0.CMT_LR_LOWER_B_MMCM_DO1 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_1.CMT_LR_LOWER_B_MMCM_LOCKED always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B19_0.CMT_LR_LOWER_B_MMCM_DO7 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B20_0.CMT_LR_LOWER_B_MMCM_DO11 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_LR_LOWER_B_MMCM_DO13 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_LR_LOWER_B_MMCM_PSDONE always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B22_0.CMT_LR_LOWER_B_MMCM_DO3 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_0.CMT_LR_LOWER_B_MMCM_DO5 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_MMCM_PHASERA_DTSBUS1 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_MMCM_PHASERA_CTSBUS1 always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_0.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_1.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_2.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_3.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_4.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_5.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_6.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_7.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_8.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_9.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_10.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_11.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_12.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_13.CMT_MMCM_PHASER_OUT_B_OCLK always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_14.CMT_MMCM_PHASER_OUT_B_OCLK always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_15.CMT_MMCM_PHASER_OUT_B_OCLK always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK1X_90_8.CMT_PHASER_A_OCLK90_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_12.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_13.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_14.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_15.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
+CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_1.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
+CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_2.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
+CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_3.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
diff --git a/artix7/ppips_cmt_top_r_lower_t.db b/artix7/ppips_cmt_top_r_lower_t.db
new file mode 100644
index 0000000..8783fff
--- /dev/null
+++ b/artix7/ppips_cmt_top_r_lower_t.db
@@ -0,0 +1,234 @@
+CMT_TOP_R_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_0.CMT_TOP_CLK0_8 always
+CMT_TOP_R_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_1.CMT_TOP_CLK1_8 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI.CMT_PHASER_IN_B_ICLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI.CMT_PHASER_IN_B_ICLKDIV always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI.CMT_PHASER_OUT_B_OCLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI.CMT_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_ICLK.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_ICLKDIV.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_OCLK.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_OCLKDIV.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI.CMT_PHASER_OUT_B_OCLK1X_90 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_ICLK.CMT_PHASER_IN_CA_ICLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_ICLKDIV.CMT_PHASER_IN_A_WRCLK_TOFIFO always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_WREN_TOFIFO.CMT_PHASER_IN_CA_WRENABLE always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_RCLK0.CMT_PHASER_IN_CA_RCLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLK.CMT_PHASER_IN_DB_ICLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLKDIV.CMT_PHASER_IN_B_WRCLK_TOFIFO always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_WREN_TOFIFO.CMT_PHASER_IN_DB_WRENABLE always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_RCLK1.CMT_PHASER_IN_DB_RCLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX45_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX29_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX34_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX30_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX14_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_A always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX12_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX8_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX11_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX19_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX27_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX43_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX12_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX28_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX27_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX43_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHASER_BOT_IRANKA0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHASER_BOT_IRANKA1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX31_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX23_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_7 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX44_7 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX47_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_B always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX47_7 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX0_7 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX13_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX31_7 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHASER_BOT_IRANKB0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHASER_BOT_IRANKB1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLK.CMT_PHASER_OUT_CA_OCLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLKDIV.CMT_PHASER_OUT_A_RDCLK_TOFIFO always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_RDEN_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK.CMT_PHASER_OUT_DB_OCLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV.CMT_PHASER_OUT_B_RDCLK_TOFIFO always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_RDEN_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX47_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX31_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX32_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_A always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX13_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX29_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX45_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX14_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX30_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX46_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX15_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX23_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX25_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX14_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX45_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX39_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX23_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX0_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX30_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX29_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX13_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_B always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX47_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX20_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX21_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX46_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX15_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX25_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_R_LOWER_T.CMT_PHASERA_CTSBUS0.CMT_PHASER_OUT_CA_CTSBUS0 always
+CMT_TOP_R_LOWER_T.CMT_PHASERA_CTSBUS1.CMT_PHASER_OUT_CA_CTSBUS1 always
+CMT_TOP_R_LOWER_T.CMT_PHASERA_DQSBUS0.CMT_PHASER_OUT_CA_DQSBUS0 always
+CMT_TOP_R_LOWER_T.CMT_PHASERA_DQSBUS1.CMT_PHASER_OUT_CA_DQSBUS1 always
+CMT_TOP_R_LOWER_T.CMT_PHASERA_DTSBUS0.CMT_PHASER_OUT_CA_DTSBUS0 always
+CMT_TOP_R_LOWER_T.CMT_PHASERA_DTSBUS1.CMT_PHASER_OUT_CA_DTSBUS1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_0.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_1.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_2.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_3.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_4.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_5.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_6.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_7.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_8.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B0_4.CMT_PHASER_OUT_DB_DQSBUS0 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B1_3.CMT_PHASER_IN_CA_FINEOVERFLOW always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_7.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B5_4.CMT_PHASER_OUT_DB_DQSBUS1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_OSERDESRST always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_ISERDESRST always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_8.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_8.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_OUT_CA_OSERDESRST always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_3.CMT_PHASER_OUT_DB_DTSBUS0 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_4.CMT_PHASER_OUT_DB_CTSBUS0 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_7.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_6.CMT_PHASER_IN_DB_DQSFOUND always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_PHASER_IN_CA_ISERDESRST always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_4.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_IN_CA_DQSFOUND always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_3.CMT_PHASER_OUT_DB_DTSBUS1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_4.CMT_PHASER_OUT_DB_CTSBUS1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_0.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_1.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_2.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_3.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_4.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_5.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_6.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_7.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_8.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK1X_90_4.CMT_PHASER_B_OCLK90_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_B_OCLKDIV_TOIOI always
diff --git a/artix7/ppips_cmt_top_r_upper_b.db b/artix7/ppips_cmt_top_r_upper_b.db
new file mode 100644
index 0000000..7a1a641
--- /dev/null
+++ b/artix7/ppips_cmt_top_r_upper_b.db
@@ -0,0 +1,325 @@
+CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN0.PLL_CLK_FREQBB_REBUFOUT0 always
+CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN1.PLL_CLK_FREQBB_REBUFOUT1 always
+CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN2.PLL_CLK_FREQBB_REBUFOUT2 always
+CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN3.PLL_CLK_FREQBB_REBUFOUT3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI.CMT_PHASER_IN_C_ICLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI.CMT_PHASER_IN_C_ICLKDIV always
+CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI.CMT_PHASER_OUT_C_OCLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI.CMT_PHASER_OUT_C_OCLKDIV always
+CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI.CMT_PHASER_OUT_C_OCLK1X_90 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLK.CMT_PHASER_IN_CA_ICLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLKDIV.CMT_PHASER_IN_C_WRCLK_TOFIFO always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRENABLE_FIFO.CMT_PHASER_IN_CA_WRENABLE always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_RCLK2.CMT_PHASER_IN_CA_RCLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX31_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX23_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX41_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX32_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX47_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_PHASERIN_C always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX11_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX0_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX44_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX13_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX29_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX45_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX14_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX30_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX34_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX3_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHY_CONTROL_IRANKC0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHY_CONTROL_IRANKC1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_ICLK.CMT_PHASER_IN_DB_ICLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_ICLKDIV.CMT_PHASER_IN_D_WRCLK_TOFIFO always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRENABLE_FIFO.CMT_PHASER_IN_DB_WRENABLE always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_RCLK3.CMT_PHASER_IN_DB_RCLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX14_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX45_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX46_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX30_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_PHASERIN_D always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX39_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX8_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_8 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX19_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX27_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX43_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX12_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX28_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX44_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX23_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHY_CONTROL_IRANKD0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHY_CONTROL_IRANKD1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK.CMT_PHASER_OUT_CA_OCLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV.CMT_PHASER_OUT_C_RDCLK_TOFIFO always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDENABLE_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX31_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX15_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX47_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_C always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX20_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX44_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX13_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX29_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX45_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX14_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX30_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX46_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX17_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_ENCALIB0.CMT_TOP_IMUX18_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLK.CMT_PHASER_OUT_DB_OCLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLKDIV.CMT_PHASER_OUT_D_RDCLK_TOFIFO always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_RDENABLE_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX32_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX16_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX27_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX11_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX19_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX9_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX8_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX43_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_D always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX34_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX0_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX1_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX9_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX17_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX41_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX2_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX18_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX34_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX3_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX37_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_ENCALIB0.CMT_TOP_IMUX17_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_REF_CLKIN.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_REF_CLKOUT_TOHCLK.CMT_PHASER_REF_CLKOUT always
+CMT_TOP_R_UPPER_B.CMT_PHASER_REF_PWRDWN.CMT_TOP_IMUX45_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_REF_RST.CMT_TOP_IMUX15_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_REF_TMUXOUT_TOHCLK.CMT_PHASER_REF_TMUXOUT always
+CMT_TOP_R_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE0.CMT_TOP_IMUX0_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE1.CMT_TOP_IMUX16_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASERD_CTSBUS0.CMT_PHASER_OUT_DB_CTSBUS0 always
+CMT_TOP_R_UPPER_B.CMT_PHASERD_CTSBUS1.CMT_PHASER_OUT_DB_CTSBUS1 always
+CMT_TOP_R_UPPER_B.CMT_PHASERD_DQSBUS0.CMT_PHASER_OUT_DB_DQSBUS0 always
+CMT_TOP_R_UPPER_B.CMT_PHASERD_DQSBUS1.CMT_PHASER_OUT_DB_DQSBUS1 always
+CMT_TOP_R_UPPER_B.CMT_PHASERD_DTSBUS0.CMT_PHASER_OUT_DB_DTSBUS0 always
+CMT_TOP_R_UPPER_B.CMT_PHASERD_DTSBUS1.CMT_PHASER_OUT_DB_DTSBUS1 always
+CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY.CMT_PHY_CONTROL_PHYCTLEMPTY always
+CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY.CMT_PHASER_TOP_SYNC_BB always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCLK.CMT_TOP_CLK0_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLMSTREMPTY.CMT_PHASERTOP_PHYCTLMSTREMPTY always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWRENABLE.CMT_TOP_IMUX47_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PLLLOCK.CMT_TOP_IMUX43_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_READCALIBENABLE.CMT_TOP_IMUX29_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_REFDLLLOCK.CMT_TOP_IMUX4_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_RESET.CMT_TOP_IMUX11_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_WRITECALIBENABLE.CMT_TOP_IMUX22_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0.CMT_PHY_CONTROL_PCENABLECALIB0 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1.CMT_PHY_CONTROL_PCENABLECALIB1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING0.CMT_PHY_CONTROL_INBURSTPENDING0 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING1.CMT_PHY_CONTROL_INBURSTPENDING1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2.CMT_PHY_CONTROL_INBURSTPENDING2 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3.CMT_PHY_CONTROL_INBURSTPENDING3 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKA0.CMT_PHY_CONTROL_INRANKA0 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKA1.CMT_PHY_CONTROL_INRANKA1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKB0.CMT_PHY_CONTROL_INRANKB0 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKB1.CMT_PHY_CONTROL_INRANKB1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC0.CMT_PHY_CONTROL_INRANKC0 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC1.CMT_PHY_CONTROL_INRANKC1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD0.CMT_PHY_CONTROL_INRANKD0 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD1.CMT_PHY_CONTROL_INRANKD1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING0.CMT_PHY_CONTROL_OUTBURSTPENDING0 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING1.CMT_PHY_CONTROL_OUTBURSTPENDING1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2.CMT_PHY_CONTROL_OUTBURSTPENDING2 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3.CMT_PHY_CONTROL_OUTBURSTPENDING3 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD0.CMT_TOP_IMUX4_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD1.CMT_TOP_IMUX20_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD2.CMT_TOP_IMUX44_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD3.CMT_TOP_IMUX13_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD4.CMT_TOP_IMUX45_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD5.CMT_TOP_IMUX14_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD6.CMT_TOP_IMUX30_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD7.CMT_TOP_IMUX46_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD8.CMT_TOP_IMUX15_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD9.CMT_TOP_IMUX31_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD10.CMT_TOP_IMUX47_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD11.CMT_TOP_IMUX20_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD12.CMT_TOP_IMUX44_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD13.CMT_TOP_IMUX13_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD14.CMT_TOP_IMUX45_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD15.CMT_TOP_IMUX14_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD16.CMT_TOP_IMUX30_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD17.CMT_TOP_IMUX46_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD18.CMT_TOP_IMUX15_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD19.CMT_TOP_IMUX31_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD20.CMT_TOP_IMUX47_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD21.CMT_TOP_IMUX43_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD22.CMT_TOP_IMUX4_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD23.CMT_TOP_IMUX20_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD24.CMT_TOP_IMUX44_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD25.CMT_TOP_IMUX13_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD26.CMT_TOP_IMUX45_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD27.CMT_TOP_IMUX14_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD28.CMT_TOP_IMUX30_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD29.CMT_TOP_IMUX46_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD30.CMT_TOP_IMUX15_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD31.CMT_TOP_IMUX31_11 always
+CMT_TOP_R_UPPER_B.CMT_R_TOP_UPPER_B_CLKINT_2.CMT_TOP_CLK0_0 always
+CMT_TOP_R_UPPER_B.CMT_R_TOP_UPPER_B_CLKINT_3.CMT_TOP_CLK1_0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_0.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_1.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_2.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_3.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_4.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_5.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_6.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_7.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_8.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_9.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_10.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_11.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PHASER_OUT_CA_DQSBUS0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B1_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_2.CMT_PHASER_IN_CA_FINEOVERFLOW always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_9.CMT_PHY_CONTROL_AUXOUTPUT0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PHASER_OUT_CA_DQSBUS1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_DQSFOUND always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_7.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_9.CMT_PHY_CONTROL_PHYCTLALMOSTFULL always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_6.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_7.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_2.CMT_PHASER_OUT_CA_OSERDESRST always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_3.CMT_PHASER_IN_CA_ISERDESRST always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_REF_LOCKED always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PHASER_OUT_CA_DTSBUS0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_OUT_CA_CTSBUS0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_3.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_6.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B16_5.CMT_PHASER_OUT_DB_OSERDESRST always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_8.CMT_PHY_CONTROL_PHYCTLREADY always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_9.CMT_PHY_CONTROL_PHYCTLFULL always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_10.CMT_PHY_CONTROL_AUXOUTPUT2 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_11.CMT_PHY_CONTROL_AUXOUTPUT3 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_8.CMT_PHASER_IN_DB_ISERDESRST always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_6.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_9.CMT_PHY_CONTROL_AUXOUTPUT1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PHASER_OUT_CA_DTSBUS1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PHASER_OUT_CA_CTSBUS1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_PHASER_IN_DB_DQSFOUND always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_0.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_1.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_2.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_3.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_4.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_5.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_6.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_7.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_8.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_9.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_10.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_11.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK1X_90_7.CMT_PHASER_C_OCLK90_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_C_OCLKDIV_TOIOI always
diff --git a/artix7/ppips_cmt_top_r_upper_t.db b/artix7/ppips_cmt_top_r_upper_t.db
new file mode 100644
index 0000000..1a48889
--- /dev/null
+++ b/artix7/ppips_cmt_top_r_upper_t.db
@@ -0,0 +1,136 @@
+CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI.CMT_PLL_PHASER_IN_D_ICLK always
+CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI.CMT_PLL_PHASER_IN_D_ICLKDIV always
+CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK always
+CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI.CMT_PLL_PHASER_OUT_D_OCLKDIV always
+CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK1X_90 always
+CMT_TOP_R_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_UP.CMT_PLL_PHYCTRL_SYNC_BB_DN always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_0.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_1.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_2.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_3.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_4.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_5.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_6.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_7.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_8.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_9.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_10.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_11.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_12.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_9.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_10.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_11.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_12.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PLL_PHASERD_DQSBUS0 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_12.CMT_TOP_R_UPPER_T_PLLE2_DO13 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B2_12.CMT_TOP_R_UPPER_T_PLLE2_DO5 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PLL_PHASERD_DQSBUS1 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_12.CMT_TOP_R_UPPER_T_PLLE2_DO9 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B7_12.CMT_TOP_R_UPPER_T_PLLE2_DO1 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B8_12.CMT_TOP_R_UPPER_T_PLLE2_DO15 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B10_12.CMT_TOP_R_UPPER_T_PLLE2_DO7 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B13_12.CMT_TOP_R_UPPER_T_PLLE2_DO11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PLL_PHASERD_DTSBUS0 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PLL_PHASERD_CTSBUS0 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B15_12.CMT_TOP_R_UPPER_T_PLLE2_DO3 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_11.CMT_TOP_R_UPPER_T_PLLE2_DRDY always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_12.CMT_TOP_R_UPPER_T_PLLE2_DO6 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B17_12.CMT_TOP_R_UPPER_T_PLLE2_DO0 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B18_12.CMT_TOP_R_UPPER_T_PLLE2_DO14 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B19_12.CMT_TOP_R_UPPER_T_PLLE2_DO8 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B20_12.CMT_TOP_R_UPPER_T_PLLE2_DO4 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_11.CMT_TOP_R_UPPER_T_PLLE2_LOCKED always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_12.CMT_TOP_R_UPPER_T_PLLE2_DO2 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B22_12.CMT_TOP_R_UPPER_T_PLLE2_DO12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PLL_PHASERD_DTSBUS1 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PLL_PHASERD_CTSBUS1 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_12.CMT_TOP_R_UPPER_T_PLLE2_DO10 always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_0.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_1.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_2.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_3.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_4.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_5.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_6.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_7.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_8.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_9.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_10.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_11.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_12.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK1X_90_7.CMT_PHASER_D_OCLK90_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_9.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_10.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_11.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_12.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_CLKFBOUT2IN.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB0.PLL_CLK_FREQ_BB0_NS always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB1.PLL_CLK_FREQ_BB1_NS always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB2.PLL_CLK_FREQ_BB2_NS always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB3.PLL_CLK_FREQ_BB3_NS always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL4.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL5.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL6.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL7.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT.CMT_TOP_CLK0_1 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT.CMT_TOP_CLK1_0 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT.CMT_TOP_CLK0_0 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL.CMT_TOP_IMUX47_10 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DCLK.CMT_TOP_CLK0_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DEN.CMT_TOP_IMUX1_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DWE.CMT_TOP_IMUX2_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_PWRDWN.CMT_TOP_IMUX0_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_RST.CMT_TOP_IMUX13_10 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR0.CMT_TOP_IMUX47_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR1.CMT_TOP_IMUX15_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR2.CMT_TOP_IMUX22_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR3.CMT_TOP_IMUX13_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR4.CMT_TOP_IMUX44_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR5.CMT_TOP_IMUX35_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR6.CMT_TOP_IMUX3_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI0.CMT_TOP_IMUX39_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI1.CMT_TOP_IMUX7_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI2.CMT_TOP_IMUX38_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI3.CMT_TOP_IMUX6_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI4.CMT_TOP_IMUX37_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI5.CMT_TOP_IMUX5_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI6.CMT_TOP_IMUX36_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI7.CMT_TOP_IMUX4_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI8.CMT_TOP_IMUX35_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI9.CMT_TOP_IMUX3_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI10.CMT_TOP_IMUX34_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI11.CMT_TOP_IMUX2_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI12.CMT_TOP_IMUX33_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI13.CMT_TOP_IMUX1_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI14.CMT_TOP_IMUX32_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI15.CMT_TOP_IMUX0_12 always
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS0.PLL_CLK_FREQ_BB0_NS always
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS1.PLL_CLK_FREQ_BB1_NS always
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS2.PLL_CLK_FREQ_BB2_NS always
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS3.PLL_CLK_FREQ_BB3_NS always
+CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
+CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
+CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
+CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
diff --git a/artix7/ppips_hclk_cmt.db b/artix7/ppips_hclk_cmt.db
new file mode 100644
index 0000000..a233287
--- /dev/null
+++ b/artix7/ppips_hclk_cmt.db
@@ -0,0 +1,4 @@
+HCLK_CMT.HCLK_CMT_BUFMR_PHASEREF0.HCLK_CMT_BUFMRCE_O0 always
+HCLK_CMT.HCLK_CMT_BUFMR_PHASEREF1.HCLK_CMT_BUFMRCE_O1 always
+HCLK_CMT.HCLK_CMT_BUFMRCE_CEINP0.HCLK_CMT_BUFMR_CE0 always
+HCLK_CMT.HCLK_CMT_BUFMRCE_CEINP1.HCLK_CMT_BUFMR_CE1 always
diff --git a/artix7/ppips_hclk_ioi3.db b/artix7/ppips_hclk_ioi3.db
new file mode 100644
index 0000000..71375b7
--- /dev/null
+++ b/artix7/ppips_hclk_ioi3.db
@@ -0,0 +1,48 @@
+HCLK_IOI3.HCLK_IOI_CK_BUFRCLK0.HCLK_IOI_RCLK2RCLK0 always
+HCLK_IOI3.HCLK_IOI_CK_BUFRCLK1.HCLK_IOI_RCLK2RCLK1 always
+HCLK_IOI3.HCLK_IOI_CK_BUFRCLK2.HCLK_IOI_RCLK2RCLK2 always
+HCLK_IOI3.HCLK_IOI_CK_BUFRCLK3.HCLK_IOI_RCLK2RCLK3 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK0.HCLK_IOI_CK_BUFHCLK0 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK1.HCLK_IOI_CK_BUFHCLK1 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK2.HCLK_IOI_CK_BUFHCLK2 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK3.HCLK_IOI_CK_BUFHCLK3 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK4.HCLK_IOI_CK_BUFHCLK4 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK5.HCLK_IOI_CK_BUFHCLK5 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK6.HCLK_IOI_CK_BUFHCLK6 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK7.HCLK_IOI_CK_BUFHCLK7 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK8.HCLK_IOI_CK_BUFHCLK8 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK9.HCLK_IOI_CK_BUFHCLK9 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK10.HCLK_IOI_CK_BUFHCLK10 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK11.HCLK_IOI_CK_BUFHCLK11 always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0.HCLK_IOI_IO_PLL_CLK0_DMUX always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1.HCLK_IOI_IO_PLL_CLK1_DMUX always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2.HCLK_IOI_IO_PLL_CLK2_DMUX always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3.HCLK_IOI_IO_PLL_CLK3_DMUX always
+HCLK_IOI3.HCLK_IOI_RCLK_OUT0.HCLK_IOI_RCLK_BEFORE_DIV0 always
+HCLK_IOI3.HCLK_IOI_RCLK_OUT1.HCLK_IOI_RCLK_BEFORE_DIV1 always
+HCLK_IOI3.HCLK_IOI_RCLK_OUT2.HCLK_IOI_RCLK_BEFORE_DIV2 always
+HCLK_IOI3.HCLK_IOI_RCLK_OUT3.HCLK_IOI_RCLK_BEFORE_DIV3 always
+HCLK_IOI3.HCLK_IOI_BUFR0_CE.HCLK_RCLK_DIV_CE0 always
+HCLK_IOI3.HCLK_IOI_BUFR0_CLR.HCLK_RCLK_DIV_CLR0 always
+HCLK_IOI3.HCLK_IOI_BUFR1_CE.HCLK_RCLK_DIV_CE1 always
+HCLK_IOI3.HCLK_IOI_BUFR1_CLR.HCLK_RCLK_DIV_CLR1 always
+HCLK_IOI3.HCLK_IOI_BUFR2_CE.HCLK_RCLK_DIV_CE2 always
+HCLK_IOI3.HCLK_IOI_BUFR2_CLR.HCLK_RCLK_DIV_CLR2 always
+HCLK_IOI3.HCLK_IOI_BUFR3_CE.HCLK_RCLK_DIV_CE3 always
+HCLK_IOI3.HCLK_IOI_BUFR3_CLR.HCLK_RCLK_DIV_CLR3 always
+HCLK_IOI3.HCLK_IOI_IOCLK0.HCLK_IOI_BUFIO_O0 always
+HCLK_IOI3.HCLK_IOI_IOCLK1.HCLK_IOI_BUFIO_O1 always
+HCLK_IOI3.HCLK_IOI_IOCLK2.HCLK_IOI_BUFIO_O2 always
+HCLK_IOI3.HCLK_IOI_IOCLK3.HCLK_IOI_BUFIO_O3 always
+HCLK_IOI3.HCLK_IOI_RCLK0.HCLK_IOI_IO_PLL_CLK0_DMUX always
+HCLK_IOI3.HCLK_IOI_RCLK1.HCLK_IOI_IO_PLL_CLK1_DMUX always
+HCLK_IOI3.HCLK_IOI_RCLK2.HCLK_IOI_IO_PLL_CLK2_DMUX always
+HCLK_IOI3.HCLK_IOI_RCLK3.HCLK_IOI_IO_PLL_CLK3_DMUX always
+HCLK_IOI3.HCLK_IOI_RCLK2IO0.HCLK_IOI_CK_BUFRCLK0 always
+HCLK_IOI3.HCLK_IOI_RCLK2IO1.HCLK_IOI_CK_BUFRCLK1 always
+HCLK_IOI3.HCLK_IOI_RCLK2IO2.HCLK_IOI_CK_BUFRCLK2 always
+HCLK_IOI3.HCLK_IOI_RCLK2IO3.HCLK_IOI_CK_BUFRCLK3 always
+HCLK_IOI3.HCLK_IOI_RCLK2RCLK0.HCLK_IOI_RCLK_OUT0 always
+HCLK_IOI3.HCLK_IOI_RCLK2RCLK1.HCLK_IOI_RCLK_OUT1 always
+HCLK_IOI3.HCLK_IOI_RCLK2RCLK2.HCLK_IOI_RCLK_OUT2 always
+HCLK_IOI3.HCLK_IOI_RCLK2RCLK3.HCLK_IOI_RCLK_OUT3 always
diff --git a/artix7/ppips_int_interface_l.db b/artix7/ppips_int_interface_l.db
new file mode 100644
index 0000000..3b34932
--- /dev/null
+++ b/artix7/ppips_int_interface_l.db
@@ -0,0 +1,24 @@
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L14.INT_INTERFACE_LOGIC_OUTS_L_B14 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always
diff --git a/artix7/ppips_int_interface_r.db b/artix7/ppips_int_interface_r.db
new file mode 100644
index 0000000..61aa2e4
--- /dev/null
+++ b/artix7/ppips_int_interface_r.db
@@ -0,0 +1,24 @@
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always
diff --git a/artix7/segbits_cmt_top_l_upper_t.db b/artix7/segbits_cmt_top_l_upper_t.db
index b2dcb57..59c6d1d 100644
--- a/artix7/segbits_cmt_top_l_upper_t.db
+++ b/artix7/segbits_cmt_top_l_upper_t.db
@@ -1,9 +1,22 @@
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT 29_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 !28_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 !29_07
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT 29_07
-CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK 29_11
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN !28_11 28_43 !28_44 !29_10 !29_11 29_42 29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN !28_11 !28_43 28_44 !29_10 29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_11 !28_43 !28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT !28_11 !28_43 28_44 29_10 29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_09 !28_10 !29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 28_09 !28_10 !29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 !28_09 !28_10 29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 28_09 !28_10 29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 !28_09 28_10 !29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_09 28_10 !29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_08 !29_07 !29_08
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_08 29_07 !29_08
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 28_08 !29_07 !29_08
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 28_08 29_07 !29_08
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 !28_08 !29_07 29_08
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT !28_08 29_07 29_08
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
diff --git a/artix7/segbits_cmt_top_l_upper_t.origin_info.db b/artix7/segbits_cmt_top_l_upper_t.origin_info.db
index 14f50b5..e124544 100644
--- a/artix7/segbits_cmt_top_l_upper_t.origin_info.db
+++ b/artix7/segbits_cmt_top_l_upper_t.origin_info.db
@@ -1,9 +1,22 @@
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips 29_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips 28_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !29_07
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips 29_07
-CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK origin:034-cmt-pll-pips 29_11
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN origin:034-cmt-pll-pips !28_11 !28_44 !29_10 !29_11 28_43 29_42 29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_42 !29_43 28_44 29_11
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_11 !29_42 !29_43 28_44
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_11 !28_43 !28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_43 !29_10 !29_11 !29_42 !29_43 28_11 28_44
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_43 !29_11 !29_42 !29_43 28_11 28_44 29_10
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_11 !28_43 !29_42 !29_43 28_44 29_10 29_11
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_9 !29_9 28_10
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_10 !28_9 !29_9
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_10 !29_9 28_9
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_10 !28_9 29_9
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_10 28_9 29_9
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !29_9 28_10 28_9
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_8 !29_7 29_8
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_8 !29_7 !29_8
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_8 !29_8 29_7
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !29_7 !29_8 28_8
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !29_8 28_8 29_7
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_8 29_7 29_8
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
diff --git a/artix7/segbits_cmt_top_r_upper_t.db b/artix7/segbits_cmt_top_r_upper_t.db
index 5f9c8db..a1874b9 100644
--- a/artix7/segbits_cmt_top_r_upper_t.db
+++ b/artix7/segbits_cmt_top_r_upper_t.db
@@ -1,10 +1,22 @@
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN !29_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT 29_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 !28_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT 28_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 !29_07
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT 29_07
-CMT_TOP_R_UPPER_T.EXTERNAL_FEEDBACK 29_11
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN !28_11 28_43 !28_44 !29_10 !29_11 29_42 29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN !28_11 !28_43 28_44 !29_10 29_11 !29_42 !29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 !28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT !28_11 !28_43 28_44 29_10 29_11 !29_42 !29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_09 !28_10 !29_09
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 28_09 !28_10 !29_09
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 !28_09 !28_10 29_09
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 28_09 !28_10 29_09
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 !28_09 28_10 !29_09
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT 28_09 28_10 !29_09
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_08 !29_07 !29_08
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 !28_08 29_07 !29_08
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 28_08 !29_07 !29_08
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 28_08 29_07 !29_08
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 !28_08 !29_07 29_08
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT !28_08 29_07 29_08
 CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
 CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
 CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
diff --git a/artix7/segbits_cmt_top_r_upper_t.origin_info.db b/artix7/segbits_cmt_top_r_upper_t.origin_info.db
index 34d9db0..f0326b1 100644
--- a/artix7/segbits_cmt_top_r_upper_t.origin_info.db
+++ b/artix7/segbits_cmt_top_r_upper_t.origin_info.db
@@ -1,10 +1,22 @@
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !29_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips 29_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips 28_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !29_07
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips 29_07
-CMT_TOP_R_UPPER_T.EXTERNAL_FEEDBACK origin:034-cmt-pll-pips 29_11
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN origin:034-cmt-pll-pips !28_11 !28_44 !29_10 !29_11 28_43 29_42 29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_42 !29_43 28_44 29_11
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_11 !29_42 !29_43 28_44
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_11 !28_43 !29_11 !29_42 !29_43 28_44 29_10
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_43 !29_10 !29_11 !29_42 !29_43 28_11 28_44
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_43 !29_11 !29_42 !29_43 28_11 28_44 29_10
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_11 !28_43 !29_42 !29_43 28_44 29_10 29_11
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_9 !29_9 28_10
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_10 !28_9 !29_9
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_10 !29_9 28_9
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_10 !28_9 29_9
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_10 28_9 29_9
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !29_9 28_10 28_9
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_8 !29_7 29_8
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_8 !29_7 !29_8
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_8 !29_8 29_7
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !29_7 !29_8 28_8
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !29_8 28_8 29_7
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_8 29_7 29_8
 CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
 CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
 CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
diff --git a/artix7/segbits_int_r.origin_info.db b/artix7/segbits_int_r.origin_info.db
index 255421f..2a48ab4 100644
--- a/artix7/segbits_int_r.origin_info.db
+++ b/artix7/segbits_int_r.origin_info.db
@@ -413,7 +413,7 @@
 INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
 INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
 INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
+INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
 INT_R.EL1BEG0.EE2END1 origin:050-pip-seed 07_20 15_21
 INT_R.EL1BEG0.EE4END1 origin:050-pip-seed 07_20 12_21
 INT_R.EL1BEG0.EL1END1 origin:050-pip-seed 11_21 13_21
@@ -2431,7 +2431,7 @@
 INT_R.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
 INT_R.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
 INT_R.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
-INT_R.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
+INT_R.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
 INT_R.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
 INT_R.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
 INT_R.NR1BEG0.EE2END0 origin:050-pip-seed 10_07 15_07
@@ -2609,7 +2609,7 @@
 INT_R.NW6BEG0.NW2END0 origin:050-pip-seed 02_02 03_02
 INT_R.NW6BEG0.NW6END0 origin:050-pip-seed 02_02 07_03
 INT_R.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00
-INT_R.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03
+INT_R.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03
 INT_R.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00
 INT_R.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03
 INT_R.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03
@@ -2827,7 +2827,7 @@
 INT_R.SE6BEG3.NE2END3 origin:050-pip-seed 03_58 04_56
 INT_R.SE6BEG3.NE6END3 origin:050-pip-seed 04_56 04_59
 INT_R.SE6BEG3.NN2END3 origin:050-pip-seed 02_59 04_56
-INT_R.SE6BEG3.NN6END3 origin:056-pip-rem 04_56 07_59
+INT_R.SE6BEG3.NN6END3 origin:050-pip-seed 04_56 07_59
 INT_R.SE6BEG3.SE2END3 origin:050-pip-seed 02_58 03_58
 INT_R.SE6BEG3.SE6END3 origin:050-pip-seed 02_58 07_59
 INT_R.SE6BEG3.SS2END3 origin:050-pip-seed 02_59 05_58
@@ -3275,7 +3275,7 @@
 INT_R.SW6BEG1.WW2END1 origin:050-pip-seed 03_28 05_31
 INT_R.SW6BEG1.WW4END2 origin:050-pip-seed 05_28 05_31
 INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
 INT_R.SW6BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_44 04_46
 INT_R.SW6BEG2.LOGIC_OUTS14 origin:050-pip-seed 03_44 07_45
 INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
@@ -3603,7 +3603,7 @@
 INT_R.WW4BEG2.LVB0 origin:056-pip-rem 04_34 05_32
 INT_R.WW4BEG2.LVB12 origin:056-pip-rem 05_32 07_33
 INT_R.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35
-INT_R.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35
+INT_R.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35
 INT_R.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35
 INT_R.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32
 INT_R.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
diff --git a/kintex7/mask_lioi3.db b/kintex7/mask_lioi3.db
index 56809ef..4c3181d 100644
--- a/kintex7/mask_lioi3.db
+++ b/kintex7/mask_lioi3.db
@@ -1,5 +1,4 @@
 bit 25_07
-bit 25_08
 bit 25_20
 bit 25_21
 bit 25_31
diff --git a/kintex7/mask_lioi3_tbytesrc.db b/kintex7/mask_lioi3_tbytesrc.db
index 56809ef..4c3181d 100644
--- a/kintex7/mask_lioi3_tbytesrc.db
+++ b/kintex7/mask_lioi3_tbytesrc.db
@@ -1,5 +1,4 @@
 bit 25_07
-bit 25_08
 bit 25_20
 bit 25_21
 bit 25_31
diff --git a/kintex7/mask_lioi3_tbyteterm.db b/kintex7/mask_lioi3_tbyteterm.db
index 56809ef..4c3181d 100644
--- a/kintex7/mask_lioi3_tbyteterm.db
+++ b/kintex7/mask_lioi3_tbyteterm.db
@@ -1,5 +1,4 @@
 bit 25_07
-bit 25_08
 bit 25_20
 bit 25_21
 bit 25_31
diff --git a/kintex7/mask_rioi3.db b/kintex7/mask_rioi3.db
index 56809ef..4c3181d 100644
--- a/kintex7/mask_rioi3.db
+++ b/kintex7/mask_rioi3.db
@@ -1,5 +1,4 @@
 bit 25_07
-bit 25_08
 bit 25_20
 bit 25_21
 bit 25_31
diff --git a/kintex7/mask_rioi3_tbytesrc.db b/kintex7/mask_rioi3_tbytesrc.db
index 56809ef..4c3181d 100644
--- a/kintex7/mask_rioi3_tbytesrc.db
+++ b/kintex7/mask_rioi3_tbytesrc.db
@@ -1,5 +1,4 @@
 bit 25_07
-bit 25_08
 bit 25_20
 bit 25_21
 bit 25_31
diff --git a/kintex7/mask_rioi3_tbyteterm.db b/kintex7/mask_rioi3_tbyteterm.db
index 56809ef..4c3181d 100644
--- a/kintex7/mask_rioi3_tbyteterm.db
+++ b/kintex7/mask_rioi3_tbyteterm.db
@@ -1,5 +1,4 @@
 bit 25_07
-bit 25_08
 bit 25_20
 bit 25_21
 bit 25_31
diff --git a/kintex7/ppips_cmt_top_l_lower_b.db b/kintex7/ppips_cmt_top_l_lower_b.db
new file mode 100644
index 0000000..d367998
--- /dev/null
+++ b/kintex7/ppips_cmt_top_l_lower_b.db
@@ -0,0 +1,155 @@
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB0.MMCM_CLK_FREQ_BB_NS3 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB1.MMCM_CLK_FREQ_BB_NS2 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB2.MMCM_CLK_FREQ_BB_NS1 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB3.MMCM_CLK_FREQ_BB_NS0 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN1_INT.CMT_TOP_CLK0_15 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN2_INT.CMT_TOP_CLK1_15 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN3_INT.CMT_TOP_CLK0_14 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM1.CMT_LR_LOWER_B_MMCM_CLKOUT0B always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM2.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM3.CMT_LR_LOWER_B_MMCM_CLKOUT1B always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM4.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM5.CMT_LR_LOWER_B_MMCM_CLKOUT2B always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM6.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM7.CMT_LR_LOWER_B_MMCM_CLKOUT3B always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM8.CMT_LR_LOWER_B_MMCM_CLKOUT4 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM9.CMT_LR_LOWER_B_MMCM_CLKOUT5 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM10.CMT_LR_LOWER_B_MMCM_CLKOUT6 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM11.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM12.CMT_LR_LOWER_B_MMCM_CLKFBOUTB always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM13.CMT_LR_LOWER_B_MMCM_TMUXOUT always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSEL.CMT_TOP_IMUX0_2 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DCLK.CMT_TOP_CLK0_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DEN.CMT_TOP_IMUX15_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DWE.CMT_TOP_IMUX22_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSCLK.CMT_TOP_CLK0_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSEN.CMT_TOP_IMUX1_2 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSINCDEC.CMT_TOP_IMUX2_2 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PWRDWN.CMT_TOP_IMUX47_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_RST.CMT_TOP_IMUX34_2 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR0.CMT_TOP_IMUX0_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR1.CMT_TOP_IMUX1_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR2.CMT_TOP_IMUX2_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR3.CMT_TOP_IMUX34_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR4.CMT_TOP_IMUX3_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR5.CMT_TOP_IMUX35_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR6.CMT_TOP_IMUX44_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI0.CMT_TOP_IMUX0_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI1.CMT_TOP_IMUX32_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI2.CMT_TOP_IMUX1_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI3.CMT_TOP_IMUX33_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI4.CMT_TOP_IMUX2_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI5.CMT_TOP_IMUX34_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI6.CMT_TOP_IMUX3_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI7.CMT_TOP_IMUX35_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI8.CMT_TOP_IMUX4_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI9.CMT_TOP_IMUX36_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI10.CMT_TOP_IMUX5_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI11.CMT_TOP_IMUX37_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI12.CMT_TOP_IMUX6_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI13.CMT_TOP_IMUX38_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI14.CMT_TOP_IMUX7_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI15.CMT_TOP_IMUX39_0 always
+CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI.CMT_MMCM_PHASER_IN_A_ICLK always
+CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI.CMT_MMCM_PHASER_IN_A_ICLKDIV always
+CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK always
+CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLKDIV always
+CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK1X_90 always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_0.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_1.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_2.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_3.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_4.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_5.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_6.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_7.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_8.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_9.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_10.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_11.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_12.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_13.CMT_MMCM_PHASER_IN_B_ICLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_14.CMT_MMCM_PHASER_IN_B_ICLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_15.CMT_MMCM_PHASER_IN_B_ICLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_12.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_13.CMT_MMCM_PHASER_IN_B_ICLKDIV always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_14.CMT_MMCM_PHASER_IN_B_ICLKDIV always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_15.CMT_MMCM_PHASER_IN_B_ICLKDIV always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_0.CMT_LR_LOWER_B_MMCM_DO2 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_8.CMT_MMCM_PHASERA_DQSBUS0 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_LR_LOWER_B_MMCM_DO10 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_0.CMT_LR_LOWER_B_MMCM_DO6 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_8.CMT_MMCM_PHASERA_DQSBUS1 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_LR_LOWER_B_MMCM_DO14 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B8_0.CMT_LR_LOWER_B_MMCM_DO0 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B10_0.CMT_LR_LOWER_B_MMCM_DO8 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B13_0.CMT_LR_LOWER_B_MMCM_DO4 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_MMCM_PHASERA_DTSBUS0 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_8.CMT_MMCM_PHASERA_CTSBUS0 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_LR_LOWER_B_MMCM_DO12 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_LR_LOWER_B_MMCM_DO9 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_LR_LOWER_B_MMCM_DRDY always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_2.CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_LR_LOWER_B_MMCM_DO15 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_0.CMT_LR_LOWER_B_MMCM_DO1 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_1.CMT_LR_LOWER_B_MMCM_LOCKED always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B19_0.CMT_LR_LOWER_B_MMCM_DO7 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B20_0.CMT_LR_LOWER_B_MMCM_DO11 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_LR_LOWER_B_MMCM_DO13 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_LR_LOWER_B_MMCM_PSDONE always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B22_0.CMT_LR_LOWER_B_MMCM_DO3 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_0.CMT_LR_LOWER_B_MMCM_DO5 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_MMCM_PHASERA_DTSBUS1 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_MMCM_PHASERA_CTSBUS1 always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_0.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_1.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_2.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_3.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_4.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_5.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_6.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_7.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_8.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_9.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_10.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_11.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_12.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_13.CMT_MMCM_PHASER_OUT_B_OCLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_14.CMT_MMCM_PHASER_OUT_B_OCLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_15.CMT_MMCM_PHASER_OUT_B_OCLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK1X_90_8.CMT_PHASER_A_OCLK90_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_12.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_13.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_14.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_15.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
+CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_1.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
+CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_2.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
+CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_3.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
diff --git a/kintex7/ppips_cmt_top_l_lower_t.db b/kintex7/ppips_cmt_top_l_lower_t.db
new file mode 100644
index 0000000..94c8dfb
--- /dev/null
+++ b/kintex7/ppips_cmt_top_l_lower_t.db
@@ -0,0 +1,234 @@
+CMT_TOP_L_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_0.CMT_TOP_CLK0_8 always
+CMT_TOP_L_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_1.CMT_TOP_CLK1_8 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI.CMT_PHASER_IN_B_ICLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI.CMT_PHASER_IN_B_ICLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI.CMT_PHASER_OUT_B_OCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI.CMT_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_ICLK.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_ICLKDIV.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_OCLK.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_OCLKDIV.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI.CMT_PHASER_OUT_B_OCLK1X_90 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_ICLK.CMT_PHASER_IN_CA_ICLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_ICLKDIV.CMT_PHASER_IN_A_WRCLK_TOFIFO always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_WREN_TOFIFO.CMT_PHASER_IN_CA_WRENABLE always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_RCLK0.CMT_PHASER_IN_CA_RCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLK.CMT_PHASER_IN_DB_ICLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLKDIV.CMT_PHASER_IN_B_WRCLK_TOFIFO always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_WREN_TOFIFO.CMT_PHASER_IN_DB_WRENABLE always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_RCLK1.CMT_PHASER_IN_DB_RCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX45_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX29_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX34_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX30_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX14_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_A always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX12_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX8_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX11_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX19_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX27_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX43_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX12_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX28_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX27_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX43_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHASER_BOT_IRANKA0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHASER_BOT_IRANKA1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX31_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX23_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX44_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX47_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_B always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX47_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX0_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX13_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX31_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHASER_BOT_IRANKB0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHASER_BOT_IRANKB1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLK.CMT_PHASER_OUT_CA_OCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLKDIV.CMT_PHASER_OUT_A_RDCLK_TOFIFO always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDEN_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK.CMT_PHASER_OUT_DB_OCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV.CMT_PHASER_OUT_B_RDCLK_TOFIFO always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDEN_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX47_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX31_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX32_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_A always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX13_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX29_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX45_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX14_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX30_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX46_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX15_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX23_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX25_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX14_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX45_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX39_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX23_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX0_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX30_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX29_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX13_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_B always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX47_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX20_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX21_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX46_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX15_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX25_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_CTSBUS0.CMT_PHASER_OUT_CA_CTSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_CTSBUS1.CMT_PHASER_OUT_CA_CTSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_DQSBUS0.CMT_PHASER_OUT_CA_DQSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_DQSBUS1.CMT_PHASER_OUT_CA_DQSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_DTSBUS0.CMT_PHASER_OUT_CA_DTSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_DTSBUS1.CMT_PHASER_OUT_CA_DTSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_0.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_1.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_2.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_3.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_4.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_5.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_6.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_7.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_8.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B0_4.CMT_PHASER_OUT_DB_DQSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B1_3.CMT_PHASER_IN_CA_FINEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_7.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B5_4.CMT_PHASER_OUT_DB_DQSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_OSERDESRST always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_ISERDESRST always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_8.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_8.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_OUT_CA_OSERDESRST always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_3.CMT_PHASER_OUT_DB_DTSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_4.CMT_PHASER_OUT_DB_CTSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_7.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_6.CMT_PHASER_IN_DB_DQSFOUND always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_PHASER_IN_CA_ISERDESRST always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_4.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_IN_CA_DQSFOUND always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_3.CMT_PHASER_OUT_DB_DTSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_4.CMT_PHASER_OUT_DB_CTSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_0.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_1.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_2.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_3.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_4.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_5.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_6.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_7.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_8.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK1X_90_4.CMT_PHASER_B_OCLK90_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_B_OCLKDIV_TOIOI always
diff --git a/kintex7/ppips_cmt_top_l_upper_b.db b/kintex7/ppips_cmt_top_l_upper_b.db
new file mode 100644
index 0000000..15fe6d6
--- /dev/null
+++ b/kintex7/ppips_cmt_top_l_upper_b.db
@@ -0,0 +1,325 @@
+CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0.PLL_CLK_FREQBB_REBUFOUT0 always
+CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1.PLL_CLK_FREQBB_REBUFOUT1 always
+CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2.PLL_CLK_FREQBB_REBUFOUT2 always
+CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3.PLL_CLK_FREQBB_REBUFOUT3 always
+CMT_TOP_L_UPPER_B.CMT_L_TOP_UPPER_B_CLKINT_2.CMT_TOP_CLK0_0 always
+CMT_TOP_L_UPPER_B.CMT_L_TOP_UPPER_B_CLKINT_3.CMT_TOP_CLK1_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI.CMT_PHASER_IN_C_ICLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI.CMT_PHASER_IN_C_ICLKDIV always
+CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI.CMT_PHASER_OUT_C_OCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI.CMT_PHASER_OUT_C_OCLKDIV always
+CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI.CMT_PHASER_OUT_C_OCLK1X_90 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLK.CMT_PHASER_IN_CA_ICLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLKDIV.CMT_R_PHASER_IN_C_WRCLK_FIFO always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_WRENABLE_FIFO.CMT_PHASER_IN_CA_WRENABLE always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_RCLK2.CMT_PHASER_IN_CA_RCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX31_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX23_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX41_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX32_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX47_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_PHASERIN_C always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX11_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX0_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX44_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX13_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX29_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX45_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX14_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX30_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX34_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX3_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHY_CONTROL_IRANKC0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHY_CONTROL_IRANKC1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_ICLK.CMT_PHASER_IN_DB_ICLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_ICLKDIV.CMT_R_PHASER_IN_D_WRCLK_TOFIFO always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_WRENABLE_FIFO.CMT_PHASER_IN_DB_WRENABLE always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_RCLK3.CMT_PHASER_IN_DB_RCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX14_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX45_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX46_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX30_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_PHASERIN_D always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX39_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX8_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_8 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX19_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX27_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX43_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX12_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX28_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX44_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX23_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHY_CONTROL_IRANKD0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHY_CONTROL_IRANKD1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK.CMT_PHASER_OUT_CA_OCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV.CMT_R_PHASER_OUT_C_RDCLK_FIFO always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX31_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX15_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX47_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_C always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX20_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX44_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX13_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX29_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX45_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX14_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX30_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX46_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX17_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIB0.CMT_TOP_IMUX18_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLK.CMT_PHASER_OUT_DB_OCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLKDIV.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX32_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX16_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX27_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX11_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX19_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX9_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX8_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX43_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_D always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX34_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX0_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX1_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX9_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX17_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX41_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX2_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX18_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX34_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX3_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX37_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIB0.CMT_TOP_IMUX17_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKIN.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKOUT_TOHCLK.CMT_PHASER_REF_CLKOUT always
+CMT_TOP_L_UPPER_B.CMT_PHASER_REF_PWRDWN.CMT_TOP_IMUX45_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_REF_RST.CMT_TOP_IMUX15_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_REF_TMUXOUT_TOHCLK.CMT_PHASER_REF_TMUXOUT always
+CMT_TOP_L_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE0.CMT_TOP_IMUX0_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE1.CMT_TOP_IMUX16_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_CTSBUS0.CMT_PHASER_OUT_DB_CTSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_CTSBUS1.CMT_PHASER_OUT_DB_CTSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_DQSBUS0.CMT_PHASER_OUT_DB_DQSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_DQSBUS1.CMT_PHASER_OUT_DB_DQSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_DTSBUS0.CMT_PHASER_OUT_DB_DTSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_DTSBUS1.CMT_PHASER_OUT_DB_DTSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY.CMT_PHY_CONTROL_PHYCTLEMPTY always
+CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY.CMT_PHASER_TOP_SYNC_BB always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCLK.CMT_TOP_CLK0_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLMSTREMPTY.CMT_PHASERTOP_PHYCTLMSTREMPTY always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWRENABLE.CMT_TOP_IMUX47_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PLLLOCK.CMT_TOP_IMUX43_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_READCALIBENABLE.CMT_TOP_IMUX29_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_REFDLLLOCK.CMT_TOP_IMUX4_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_RESET.CMT_TOP_IMUX11_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_WRITECALIBENABLE.CMT_TOP_IMUX22_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0.CMT_PHY_CONTROL_PCENABLECALIB0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1.CMT_PHY_CONTROL_PCENABLECALIB1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING0.CMT_PHY_CONTROL_INBURSTPENDING0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING1.CMT_PHY_CONTROL_INBURSTPENDING1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2.CMT_PHY_CONTROL_INBURSTPENDING2 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3.CMT_PHY_CONTROL_INBURSTPENDING3 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKA0.CMT_PHY_CONTROL_INRANKA0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKA1.CMT_PHY_CONTROL_INRANKA1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKB0.CMT_PHY_CONTROL_INRANKB0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKB1.CMT_PHY_CONTROL_INRANKB1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC0.CMT_PHY_CONTROL_INRANKC0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC1.CMT_PHY_CONTROL_INRANKC1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD0.CMT_PHY_CONTROL_INRANKD0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD1.CMT_PHY_CONTROL_INRANKD1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING0.CMT_PHY_CONTROL_OUTBURSTPENDING0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING1.CMT_PHY_CONTROL_OUTBURSTPENDING1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2.CMT_PHY_CONTROL_OUTBURSTPENDING2 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3.CMT_PHY_CONTROL_OUTBURSTPENDING3 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD0.CMT_TOP_IMUX4_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD1.CMT_TOP_IMUX20_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD2.CMT_TOP_IMUX44_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD3.CMT_TOP_IMUX13_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD4.CMT_TOP_IMUX45_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD5.CMT_TOP_IMUX14_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD6.CMT_TOP_IMUX30_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD7.CMT_TOP_IMUX46_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD8.CMT_TOP_IMUX15_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD9.CMT_TOP_IMUX31_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD10.CMT_TOP_IMUX47_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD11.CMT_TOP_IMUX20_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD12.CMT_TOP_IMUX44_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD13.CMT_TOP_IMUX13_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD14.CMT_TOP_IMUX45_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD15.CMT_TOP_IMUX14_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD16.CMT_TOP_IMUX30_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD17.CMT_TOP_IMUX46_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD18.CMT_TOP_IMUX15_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD19.CMT_TOP_IMUX31_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD20.CMT_TOP_IMUX47_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD21.CMT_TOP_IMUX43_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD22.CMT_TOP_IMUX4_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD23.CMT_TOP_IMUX20_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD24.CMT_TOP_IMUX44_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD25.CMT_TOP_IMUX13_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD26.CMT_TOP_IMUX45_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD27.CMT_TOP_IMUX14_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD28.CMT_TOP_IMUX30_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD29.CMT_TOP_IMUX46_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD30.CMT_TOP_IMUX15_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD31.CMT_TOP_IMUX31_11 always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_C_WRCLK_FIFO.CMT_PHASER_IN_CA_ICLKDIV always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_D_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDCLK_FIFO.CMT_PHASER_OUT_CA_OCLKDIV always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDENABLE_FIFO.CMT_PHASER_OUT_CA_RDENABLE always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_0.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_1.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_2.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_3.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_4.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_5.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_6.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_7.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_8.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_9.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_10.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_11.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PHASER_OUT_CA_DQSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B1_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_2.CMT_PHASER_IN_CA_FINEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_9.CMT_PHY_CONTROL_AUXOUTPUT0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PHASER_OUT_CA_DQSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_DQSFOUND always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_7.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_9.CMT_PHY_CONTROL_PHYCTLALMOSTFULL always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_6.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_7.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_2.CMT_PHASER_OUT_CA_OSERDESRST always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_3.CMT_PHASER_IN_CA_ISERDESRST always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_REF_LOCKED always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PHASER_OUT_CA_DTSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_OUT_CA_CTSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_3.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_6.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B16_5.CMT_PHASER_OUT_DB_OSERDESRST always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_8.CMT_PHY_CONTROL_PHYCTLREADY always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_9.CMT_PHY_CONTROL_PHYCTLFULL always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_10.CMT_PHY_CONTROL_AUXOUTPUT2 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_11.CMT_PHY_CONTROL_AUXOUTPUT3 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_8.CMT_PHASER_IN_DB_ISERDESRST always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_6.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_9.CMT_PHY_CONTROL_AUXOUTPUT1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PHASER_OUT_CA_DTSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PHASER_OUT_CA_CTSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_PHASER_IN_DB_DQSFOUND always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_0.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_1.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_2.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_3.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_4.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_5.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_6.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_7.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_8.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_9.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_10.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_11.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK1X_90_7.CMT_PHASER_C_OCLK90_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_C_OCLKDIV_TOIOI always
diff --git a/kintex7/ppips_cmt_top_l_upper_t.db b/kintex7/ppips_cmt_top_l_upper_t.db
new file mode 100644
index 0000000..a5e25c4
--- /dev/null
+++ b/kintex7/ppips_cmt_top_l_upper_t.db
@@ -0,0 +1,136 @@
+CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI.CMT_PLL_PHASER_IN_D_ICLK always
+CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI.CMT_PLL_PHASER_IN_D_ICLKDIV always
+CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK always
+CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI.CMT_PLL_PHASER_OUT_D_OCLKDIV always
+CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK1X_90 always
+CMT_TOP_L_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_UP.CMT_PLL_PHYCTRL_SYNC_BB_DN always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_0.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_1.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_2.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_3.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_4.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_5.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_6.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_7.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_8.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_9.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_10.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_11.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_12.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_9.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_10.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_11.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_12.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_CLKFBOUT2IN.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0.PLL_CLK_FREQ_BB0_NS always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1.PLL_CLK_FREQ_BB1_NS always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2.PLL_CLK_FREQ_BB2_NS always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3.PLL_CLK_FREQ_BB3_NS always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL4.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL5.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL6.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL7.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT.CMT_TOP_CLK0_1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT.CMT_TOP_CLK1_0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT.CMT_TOP_CLK0_0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PLL_PHASERD_DQSBUS0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_12.CMT_TOP_R_UPPER_T_PLLE2_DO13 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B2_12.CMT_TOP_R_UPPER_T_PLLE2_DO5 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PLL_PHASERD_DQSBUS1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_12.CMT_TOP_R_UPPER_T_PLLE2_DO9 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B7_12.CMT_TOP_R_UPPER_T_PLLE2_DO1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B8_12.CMT_TOP_R_UPPER_T_PLLE2_DO15 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B10_12.CMT_TOP_R_UPPER_T_PLLE2_DO7 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B13_12.CMT_TOP_R_UPPER_T_PLLE2_DO11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PLL_PHASERD_DTSBUS0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PLL_PHASERD_CTSBUS0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B15_12.CMT_TOP_R_UPPER_T_PLLE2_DO3 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_11.CMT_TOP_R_UPPER_T_PLLE2_DRDY always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_12.CMT_TOP_R_UPPER_T_PLLE2_DO6 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B17_12.CMT_TOP_R_UPPER_T_PLLE2_DO0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B18_12.CMT_TOP_R_UPPER_T_PLLE2_DO14 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B19_12.CMT_TOP_R_UPPER_T_PLLE2_DO8 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B20_12.CMT_TOP_R_UPPER_T_PLLE2_DO4 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_11.CMT_TOP_R_UPPER_T_PLLE2_LOCKED always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_12.CMT_TOP_R_UPPER_T_PLLE2_DO2 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B22_12.CMT_TOP_R_UPPER_T_PLLE2_DO12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PLL_PHASERD_DTSBUS1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PLL_PHASERD_CTSBUS1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_12.CMT_TOP_R_UPPER_T_PLLE2_DO10 always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_0.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_1.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_2.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_3.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_4.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_5.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_6.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_7.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_8.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_9.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_10.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_11.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_12.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK1X_90_7.CMT_PHASER_D_OCLK90_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_9.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_10.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_11.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_12.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL.CMT_TOP_IMUX47_10 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DCLK.CMT_TOP_CLK0_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DEN.CMT_TOP_IMUX1_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DWE.CMT_TOP_IMUX2_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_PWRDWN.CMT_TOP_IMUX0_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_RST.CMT_TOP_IMUX13_10 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR0.CMT_TOP_IMUX47_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR1.CMT_TOP_IMUX15_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR2.CMT_TOP_IMUX22_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR3.CMT_TOP_IMUX13_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR4.CMT_TOP_IMUX44_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR5.CMT_TOP_IMUX35_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR6.CMT_TOP_IMUX3_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI0.CMT_TOP_IMUX39_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI1.CMT_TOP_IMUX7_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI2.CMT_TOP_IMUX38_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI3.CMT_TOP_IMUX6_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI4.CMT_TOP_IMUX37_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI5.CMT_TOP_IMUX5_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI6.CMT_TOP_IMUX36_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI7.CMT_TOP_IMUX4_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI8.CMT_TOP_IMUX35_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI9.CMT_TOP_IMUX3_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI10.CMT_TOP_IMUX34_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI11.CMT_TOP_IMUX2_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI12.CMT_TOP_IMUX33_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI13.CMT_TOP_IMUX1_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI14.CMT_TOP_IMUX32_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI15.CMT_TOP_IMUX0_12 always
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS0.PLL_CLK_FREQ_BB0_NS always
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS1.PLL_CLK_FREQ_BB1_NS always
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS2.PLL_CLK_FREQ_BB2_NS always
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS3.PLL_CLK_FREQ_BB3_NS always
+CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
+CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
+CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
+CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
diff --git a/kintex7/ppips_cmt_top_r_lower_b.db b/kintex7/ppips_cmt_top_r_lower_b.db
new file mode 100644
index 0000000..e4e8a07
--- /dev/null
+++ b/kintex7/ppips_cmt_top_r_lower_b.db
@@ -0,0 +1,155 @@
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSEL.CMT_TOP_IMUX0_2 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DCLK.CMT_TOP_CLK0_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DEN.CMT_TOP_IMUX15_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DWE.CMT_TOP_IMUX22_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSCLK.CMT_TOP_CLK0_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSEN.CMT_TOP_IMUX1_2 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSINCDEC.CMT_TOP_IMUX2_2 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PWRDWN.CMT_TOP_IMUX47_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_RST.CMT_TOP_IMUX34_2 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR0.CMT_TOP_IMUX0_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR1.CMT_TOP_IMUX1_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR2.CMT_TOP_IMUX2_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR3.CMT_TOP_IMUX34_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR4.CMT_TOP_IMUX3_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR5.CMT_TOP_IMUX35_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR6.CMT_TOP_IMUX44_1 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI0.CMT_TOP_IMUX0_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI1.CMT_TOP_IMUX32_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI2.CMT_TOP_IMUX1_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI3.CMT_TOP_IMUX33_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI4.CMT_TOP_IMUX2_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI5.CMT_TOP_IMUX34_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI6.CMT_TOP_IMUX3_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI7.CMT_TOP_IMUX35_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI8.CMT_TOP_IMUX4_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI9.CMT_TOP_IMUX36_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI10.CMT_TOP_IMUX5_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI11.CMT_TOP_IMUX37_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI12.CMT_TOP_IMUX6_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI13.CMT_TOP_IMUX38_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI14.CMT_TOP_IMUX7_0 always
+CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DI15.CMT_TOP_IMUX39_0 always
+CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI.CMT_MMCM_PHASER_IN_A_ICLK always
+CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI.CMT_MMCM_PHASER_IN_A_ICLKDIV always
+CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK always
+CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLKDIV always
+CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK1X_90 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB0.MMCM_CLK_FREQ_BB_NS3 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB1.MMCM_CLK_FREQ_BB_NS2 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB2.MMCM_CLK_FREQ_BB_NS1 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB3.MMCM_CLK_FREQ_BB_NS0 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN1_INT.CMT_TOP_CLK0_15 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN2_INT.CMT_TOP_CLK1_15 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN3_INT.CMT_TOP_CLK0_14 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM1.CMT_LR_LOWER_B_MMCM_CLKOUT0B always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM2.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM3.CMT_LR_LOWER_B_MMCM_CLKOUT1B always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM4.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM5.CMT_LR_LOWER_B_MMCM_CLKOUT2B always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM6.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM7.CMT_LR_LOWER_B_MMCM_CLKOUT3B always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM8.CMT_LR_LOWER_B_MMCM_CLKOUT4 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM9.CMT_LR_LOWER_B_MMCM_CLKOUT5 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM10.CMT_LR_LOWER_B_MMCM_CLKOUT6 always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM11.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM12.CMT_LR_LOWER_B_MMCM_CLKFBOUTB always
+CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_MMCM13.CMT_LR_LOWER_B_MMCM_TMUXOUT always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_0.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_1.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_2.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_3.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_4.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_5.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_6.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_7.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_8.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_9.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_10.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_11.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_12.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_13.CMT_MMCM_PHASER_IN_B_ICLK always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_14.CMT_MMCM_PHASER_IN_B_ICLK always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLK_15.CMT_MMCM_PHASER_IN_B_ICLK always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_12.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_13.CMT_MMCM_PHASER_IN_B_ICLKDIV always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_14.CMT_MMCM_PHASER_IN_B_ICLKDIV always
+CMT_TOP_R_LOWER_B.CMT_TOP_ICLKDIV_15.CMT_MMCM_PHASER_IN_B_ICLKDIV always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_0.CMT_LR_LOWER_B_MMCM_DO2 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_8.CMT_MMCM_PHASERA_DQSBUS0 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_LR_LOWER_B_MMCM_DO10 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_0.CMT_LR_LOWER_B_MMCM_DO6 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_8.CMT_MMCM_PHASERA_DQSBUS1 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_LR_LOWER_B_MMCM_DO14 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B8_0.CMT_LR_LOWER_B_MMCM_DO0 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B10_0.CMT_LR_LOWER_B_MMCM_DO8 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B13_0.CMT_LR_LOWER_B_MMCM_DO4 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_MMCM_PHASERA_DTSBUS0 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_8.CMT_MMCM_PHASERA_CTSBUS0 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_LR_LOWER_B_MMCM_DO12 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_LR_LOWER_B_MMCM_DO9 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_LR_LOWER_B_MMCM_DRDY always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_2.CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_LR_LOWER_B_MMCM_DO15 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_0.CMT_LR_LOWER_B_MMCM_DO1 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_1.CMT_LR_LOWER_B_MMCM_LOCKED always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B19_0.CMT_LR_LOWER_B_MMCM_DO7 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B20_0.CMT_LR_LOWER_B_MMCM_DO11 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_LR_LOWER_B_MMCM_DO13 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_LR_LOWER_B_MMCM_PSDONE always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B22_0.CMT_LR_LOWER_B_MMCM_DO3 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_0.CMT_LR_LOWER_B_MMCM_DO5 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_MMCM_PHASERA_DTSBUS1 always
+CMT_TOP_R_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_MMCM_PHASERA_CTSBUS1 always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_0.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_1.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_2.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_3.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_4.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_5.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_6.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_7.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_8.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_9.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_10.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_11.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_12.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_13.CMT_MMCM_PHASER_OUT_B_OCLK always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_14.CMT_MMCM_PHASER_OUT_B_OCLK always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK_15.CMT_MMCM_PHASER_OUT_B_OCLK always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLK1X_90_8.CMT_PHASER_A_OCLK90_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_12.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_13.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_14.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_R_LOWER_B.CMT_TOP_OCLKDIV_15.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
+CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_1.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
+CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_2.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
+CMT_TOP_R_LOWER_B.MMCMOUT_CLK_FREQ_BB_3.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
diff --git a/kintex7/ppips_cmt_top_r_lower_t.db b/kintex7/ppips_cmt_top_r_lower_t.db
new file mode 100644
index 0000000..8783fff
--- /dev/null
+++ b/kintex7/ppips_cmt_top_r_lower_t.db
@@ -0,0 +1,234 @@
+CMT_TOP_R_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_0.CMT_TOP_CLK0_8 always
+CMT_TOP_R_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_1.CMT_TOP_CLK1_8 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI.CMT_PHASER_IN_B_ICLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI.CMT_PHASER_IN_B_ICLKDIV always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI.CMT_PHASER_OUT_B_OCLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI.CMT_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_ICLK.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_ICLKDIV.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_OCLK.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_TOMMCM_OCLKDIV.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI.CMT_PHASER_OUT_B_OCLK1X_90 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_ICLK.CMT_PHASER_IN_CA_ICLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_ICLKDIV.CMT_PHASER_IN_A_WRCLK_TOFIFO always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_WREN_TOFIFO.CMT_PHASER_IN_CA_WRENABLE always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_RCLK0.CMT_PHASER_IN_CA_RCLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLK.CMT_PHASER_IN_DB_ICLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLKDIV.CMT_PHASER_IN_B_WRCLK_TOFIFO always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_WREN_TOFIFO.CMT_PHASER_IN_DB_WRENABLE always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_RCLK1.CMT_PHASER_IN_DB_RCLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX45_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX29_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX34_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX30_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX14_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_A always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX12_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX8_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX11_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX19_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX27_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX43_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX12_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX28_3 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX27_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX43_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHASER_BOT_IRANKA0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHASER_BOT_IRANKA1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX31_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX23_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_7 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX44_7 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX47_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_B always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX47_7 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX0_7 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX13_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_6 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX31_7 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHASER_BOT_IRANKB0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHASER_BOT_IRANKB1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLK.CMT_PHASER_OUT_CA_OCLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_OCLKDIV.CMT_PHASER_OUT_A_RDCLK_TOFIFO always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_RDEN_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK.CMT_PHASER_OUT_DB_OCLK always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV.CMT_PHASER_OUT_B_RDCLK_TOFIFO always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_RDEN_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX47_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX31_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX32_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_A always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX13_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX29_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX45_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX14_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX30_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX46_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX15_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX23_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX25_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX14_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX45_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX39_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX23_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX0_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX30_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX29_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX13_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_B always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX47_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX20_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX21_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX46_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX15_4 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX25_5 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_R_LOWER_T.CMT_PHASERA_CTSBUS0.CMT_PHASER_OUT_CA_CTSBUS0 always
+CMT_TOP_R_LOWER_T.CMT_PHASERA_CTSBUS1.CMT_PHASER_OUT_CA_CTSBUS1 always
+CMT_TOP_R_LOWER_T.CMT_PHASERA_DQSBUS0.CMT_PHASER_OUT_CA_DQSBUS0 always
+CMT_TOP_R_LOWER_T.CMT_PHASERA_DQSBUS1.CMT_PHASER_OUT_CA_DQSBUS1 always
+CMT_TOP_R_LOWER_T.CMT_PHASERA_DTSBUS0.CMT_PHASER_OUT_CA_DTSBUS0 always
+CMT_TOP_R_LOWER_T.CMT_PHASERA_DTSBUS1.CMT_PHASER_OUT_CA_DTSBUS1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_0.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_1.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_2.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_3.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_4.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_5.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_6.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_7.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLK_8.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B0_4.CMT_PHASER_OUT_DB_DQSBUS0 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B1_3.CMT_PHASER_IN_CA_FINEOVERFLOW always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_7.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B5_4.CMT_PHASER_OUT_DB_DQSBUS1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_OSERDESRST always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_ISERDESRST always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_8.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_8.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_OUT_CA_OSERDESRST always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_3.CMT_PHASER_OUT_DB_DTSBUS0 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_4.CMT_PHASER_OUT_DB_CTSBUS0 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_7.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_6.CMT_PHASER_IN_DB_DQSFOUND always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_PHASER_IN_CA_ISERDESRST always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_4.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_IN_CA_DQSFOUND always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_3.CMT_PHASER_OUT_DB_DTSBUS1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_4.CMT_PHASER_OUT_DB_CTSBUS1 always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_0.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_1.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_2.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_3.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_4.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_5.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_6.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_7.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK_8.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLK1X_90_4.CMT_PHASER_B_OCLK90_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_R_LOWER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_B_OCLKDIV_TOIOI always
diff --git a/kintex7/ppips_cmt_top_r_upper_b.db b/kintex7/ppips_cmt_top_r_upper_b.db
new file mode 100644
index 0000000..7a1a641
--- /dev/null
+++ b/kintex7/ppips_cmt_top_r_upper_b.db
@@ -0,0 +1,325 @@
+CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN0.PLL_CLK_FREQBB_REBUFOUT0 always
+CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN1.PLL_CLK_FREQBB_REBUFOUT1 always
+CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN2.PLL_CLK_FREQBB_REBUFOUT2 always
+CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN3.PLL_CLK_FREQBB_REBUFOUT3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI.CMT_PHASER_IN_C_ICLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI.CMT_PHASER_IN_C_ICLKDIV always
+CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI.CMT_PHASER_OUT_C_OCLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI.CMT_PHASER_OUT_C_OCLKDIV always
+CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI.CMT_PHASER_OUT_C_OCLK1X_90 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLK.CMT_PHASER_IN_CA_ICLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLKDIV.CMT_PHASER_IN_C_WRCLK_TOFIFO always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRENABLE_FIFO.CMT_PHASER_IN_CA_WRENABLE always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_RCLK2.CMT_PHASER_IN_CA_RCLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX31_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX23_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX41_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX32_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX47_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_PHASERIN_C always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX11_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX0_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX44_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX13_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX29_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX45_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX14_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX30_3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX34_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX3_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHY_CONTROL_IRANKC0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHY_CONTROL_IRANKC1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_ICLK.CMT_PHASER_IN_DB_ICLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_ICLKDIV.CMT_PHASER_IN_D_WRCLK_TOFIFO always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRENABLE_FIFO.CMT_PHASER_IN_DB_WRENABLE always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_RCLK3.CMT_PHASER_IN_DB_RCLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX14_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX45_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX46_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX30_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_PHASERIN_D always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX39_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX8_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_8 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX19_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX27_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX43_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX12_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX28_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX44_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX23_7 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHY_CONTROL_IRANKD0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHY_CONTROL_IRANKD1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK.CMT_PHASER_OUT_CA_OCLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV.CMT_PHASER_OUT_C_RDCLK_TOFIFO always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDENABLE_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX31_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX15_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX47_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_C always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX20_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX44_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX13_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX29_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX45_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX14_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX30_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX46_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX17_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_ENCALIB0.CMT_TOP_IMUX18_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLK.CMT_PHASER_OUT_DB_OCLK always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_OCLKDIV.CMT_PHASER_OUT_D_RDCLK_TOFIFO always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_RDENABLE_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING3 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX32_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX16_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX27_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX11_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX19_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX9_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX8_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX43_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_D always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX34_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX0_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX1_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX9_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX17_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX41_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX2_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX18_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX34_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX3_5 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX37_4 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_ENCALIB0.CMT_TOP_IMUX17_6 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_REF_CLKIN.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_REF_CLKOUT_TOHCLK.CMT_PHASER_REF_CLKOUT always
+CMT_TOP_R_UPPER_B.CMT_PHASER_REF_PWRDWN.CMT_TOP_IMUX45_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_REF_RST.CMT_TOP_IMUX15_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_REF_TMUXOUT_TOHCLK.CMT_PHASER_REF_TMUXOUT always
+CMT_TOP_R_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE0.CMT_TOP_IMUX0_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE1.CMT_TOP_IMUX16_0 always
+CMT_TOP_R_UPPER_B.CMT_PHASERD_CTSBUS0.CMT_PHASER_OUT_DB_CTSBUS0 always
+CMT_TOP_R_UPPER_B.CMT_PHASERD_CTSBUS1.CMT_PHASER_OUT_DB_CTSBUS1 always
+CMT_TOP_R_UPPER_B.CMT_PHASERD_DQSBUS0.CMT_PHASER_OUT_DB_DQSBUS0 always
+CMT_TOP_R_UPPER_B.CMT_PHASERD_DQSBUS1.CMT_PHASER_OUT_DB_DQSBUS1 always
+CMT_TOP_R_UPPER_B.CMT_PHASERD_DTSBUS0.CMT_PHASER_OUT_DB_DTSBUS0 always
+CMT_TOP_R_UPPER_B.CMT_PHASERD_DTSBUS1.CMT_PHASER_OUT_DB_DTSBUS1 always
+CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY.CMT_PHY_CONTROL_PHYCTLEMPTY always
+CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY.CMT_PHASER_TOP_SYNC_BB always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCLK.CMT_TOP_CLK0_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLMSTREMPTY.CMT_PHASERTOP_PHYCTLMSTREMPTY always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWRENABLE.CMT_TOP_IMUX47_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PLLLOCK.CMT_TOP_IMUX43_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_READCALIBENABLE.CMT_TOP_IMUX29_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_REFDLLLOCK.CMT_TOP_IMUX4_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_RESET.CMT_TOP_IMUX11_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_WRITECALIBENABLE.CMT_TOP_IMUX22_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0.CMT_PHY_CONTROL_PCENABLECALIB0 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1.CMT_PHY_CONTROL_PCENABLECALIB1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING0.CMT_PHY_CONTROL_INBURSTPENDING0 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING1.CMT_PHY_CONTROL_INBURSTPENDING1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2.CMT_PHY_CONTROL_INBURSTPENDING2 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3.CMT_PHY_CONTROL_INBURSTPENDING3 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKA0.CMT_PHY_CONTROL_INRANKA0 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKA1.CMT_PHY_CONTROL_INRANKA1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKB0.CMT_PHY_CONTROL_INRANKB0 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKB1.CMT_PHY_CONTROL_INRANKB1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC0.CMT_PHY_CONTROL_INRANKC0 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC1.CMT_PHY_CONTROL_INRANKC1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD0.CMT_PHY_CONTROL_INRANKD0 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD1.CMT_PHY_CONTROL_INRANKD1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING0.CMT_PHY_CONTROL_OUTBURSTPENDING0 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING1.CMT_PHY_CONTROL_OUTBURSTPENDING1 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2.CMT_PHY_CONTROL_OUTBURSTPENDING2 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3.CMT_PHY_CONTROL_OUTBURSTPENDING3 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD0.CMT_TOP_IMUX4_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD1.CMT_TOP_IMUX20_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD2.CMT_TOP_IMUX44_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD3.CMT_TOP_IMUX13_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD4.CMT_TOP_IMUX45_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD5.CMT_TOP_IMUX14_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD6.CMT_TOP_IMUX30_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD7.CMT_TOP_IMUX46_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD8.CMT_TOP_IMUX15_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD9.CMT_TOP_IMUX31_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD10.CMT_TOP_IMUX47_9 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD11.CMT_TOP_IMUX20_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD12.CMT_TOP_IMUX44_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD13.CMT_TOP_IMUX13_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD14.CMT_TOP_IMUX45_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD15.CMT_TOP_IMUX14_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD16.CMT_TOP_IMUX30_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD17.CMT_TOP_IMUX46_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD18.CMT_TOP_IMUX15_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD19.CMT_TOP_IMUX31_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD20.CMT_TOP_IMUX47_10 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD21.CMT_TOP_IMUX43_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD22.CMT_TOP_IMUX4_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD23.CMT_TOP_IMUX20_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD24.CMT_TOP_IMUX44_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD25.CMT_TOP_IMUX13_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD26.CMT_TOP_IMUX45_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD27.CMT_TOP_IMUX14_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD28.CMT_TOP_IMUX30_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD29.CMT_TOP_IMUX46_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD30.CMT_TOP_IMUX15_11 always
+CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD31.CMT_TOP_IMUX31_11 always
+CMT_TOP_R_UPPER_B.CMT_R_TOP_UPPER_B_CLKINT_2.CMT_TOP_CLK0_0 always
+CMT_TOP_R_UPPER_B.CMT_R_TOP_UPPER_B_CLKINT_3.CMT_TOP_CLK1_0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_0.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_1.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_2.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_3.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_4.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_5.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_6.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_7.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_8.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_9.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_10.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLK_11.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PHASER_OUT_CA_DQSBUS0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B1_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_2.CMT_PHASER_IN_CA_FINEOVERFLOW always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_9.CMT_PHY_CONTROL_AUXOUTPUT0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PHASER_OUT_CA_DQSBUS1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_DQSFOUND always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_7.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_9.CMT_PHY_CONTROL_PHYCTLALMOSTFULL always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_6.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_7.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_2.CMT_PHASER_OUT_CA_OSERDESRST always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_3.CMT_PHASER_IN_CA_ISERDESRST always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_REF_LOCKED always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PHASER_OUT_CA_DTSBUS0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_OUT_CA_CTSBUS0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_3.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_6.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B16_5.CMT_PHASER_OUT_DB_OSERDESRST always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_8.CMT_PHY_CONTROL_PHYCTLREADY always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_9.CMT_PHY_CONTROL_PHYCTLFULL always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_10.CMT_PHY_CONTROL_AUXOUTPUT2 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_11.CMT_PHY_CONTROL_AUXOUTPUT3 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_8.CMT_PHASER_IN_DB_ISERDESRST always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_6.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_9.CMT_PHY_CONTROL_AUXOUTPUT1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PHASER_OUT_CA_DTSBUS1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PHASER_OUT_CA_CTSBUS1 always
+CMT_TOP_R_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_PHASER_IN_DB_DQSFOUND always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_0.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_1.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_2.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_3.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_4.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_5.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_6.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_7.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_8.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_9.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_10.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK_11.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLK1X_90_7.CMT_PHASER_C_OCLK90_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_C_OCLKDIV_TOIOI always
diff --git a/kintex7/ppips_cmt_top_r_upper_t.db b/kintex7/ppips_cmt_top_r_upper_t.db
new file mode 100644
index 0000000..1a48889
--- /dev/null
+++ b/kintex7/ppips_cmt_top_r_upper_t.db
@@ -0,0 +1,136 @@
+CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI.CMT_PLL_PHASER_IN_D_ICLK always
+CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI.CMT_PLL_PHASER_IN_D_ICLKDIV always
+CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK always
+CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI.CMT_PLL_PHASER_OUT_D_OCLKDIV always
+CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK1X_90 always
+CMT_TOP_R_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_UP.CMT_PLL_PHYCTRL_SYNC_BB_DN always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_0.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_1.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_2.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_3.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_4.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_5.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_6.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_7.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_8.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_9.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_10.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_11.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLK_12.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_9.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_10.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_11.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_ICLKDIV_12.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PLL_PHASERD_DQSBUS0 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_12.CMT_TOP_R_UPPER_T_PLLE2_DO13 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B2_12.CMT_TOP_R_UPPER_T_PLLE2_DO5 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PLL_PHASERD_DQSBUS1 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_12.CMT_TOP_R_UPPER_T_PLLE2_DO9 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B7_12.CMT_TOP_R_UPPER_T_PLLE2_DO1 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B8_12.CMT_TOP_R_UPPER_T_PLLE2_DO15 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B10_12.CMT_TOP_R_UPPER_T_PLLE2_DO7 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B13_12.CMT_TOP_R_UPPER_T_PLLE2_DO11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PLL_PHASERD_DTSBUS0 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PLL_PHASERD_CTSBUS0 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B15_12.CMT_TOP_R_UPPER_T_PLLE2_DO3 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_11.CMT_TOP_R_UPPER_T_PLLE2_DRDY always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_12.CMT_TOP_R_UPPER_T_PLLE2_DO6 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B17_12.CMT_TOP_R_UPPER_T_PLLE2_DO0 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B18_12.CMT_TOP_R_UPPER_T_PLLE2_DO14 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B19_12.CMT_TOP_R_UPPER_T_PLLE2_DO8 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B20_12.CMT_TOP_R_UPPER_T_PLLE2_DO4 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_11.CMT_TOP_R_UPPER_T_PLLE2_LOCKED always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_12.CMT_TOP_R_UPPER_T_PLLE2_DO2 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B22_12.CMT_TOP_R_UPPER_T_PLLE2_DO12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PLL_PHASERD_DTSBUS1 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PLL_PHASERD_CTSBUS1 always
+CMT_TOP_R_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_12.CMT_TOP_R_UPPER_T_PLLE2_DO10 always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_0.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_1.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_2.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_3.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_4.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_5.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_6.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_7.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_8.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_9.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_10.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_11.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK_12.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLK1X_90_7.CMT_PHASER_D_OCLK90_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_9.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_10.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_11.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_OCLKDIV_12.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_CLKFBOUT2IN.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB0.PLL_CLK_FREQ_BB0_NS always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB1.PLL_CLK_FREQ_BB1_NS always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB2.PLL_CLK_FREQ_BB2_NS always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB3.PLL_CLK_FREQ_BB3_NS always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL4.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL5.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL6.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKPLL7.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT.CMT_TOP_CLK0_1 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT.CMT_TOP_CLK1_0 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT.CMT_TOP_CLK0_0 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL.CMT_TOP_IMUX47_10 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DCLK.CMT_TOP_CLK0_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DEN.CMT_TOP_IMUX1_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DWE.CMT_TOP_IMUX2_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_PWRDWN.CMT_TOP_IMUX0_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_RST.CMT_TOP_IMUX13_10 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR0.CMT_TOP_IMUX47_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR1.CMT_TOP_IMUX15_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR2.CMT_TOP_IMUX22_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR3.CMT_TOP_IMUX13_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR4.CMT_TOP_IMUX44_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR5.CMT_TOP_IMUX35_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR6.CMT_TOP_IMUX3_11 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI0.CMT_TOP_IMUX39_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI1.CMT_TOP_IMUX7_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI2.CMT_TOP_IMUX38_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI3.CMT_TOP_IMUX6_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI4.CMT_TOP_IMUX37_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI5.CMT_TOP_IMUX5_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI6.CMT_TOP_IMUX36_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI7.CMT_TOP_IMUX4_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI8.CMT_TOP_IMUX35_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI9.CMT_TOP_IMUX3_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI10.CMT_TOP_IMUX34_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI11.CMT_TOP_IMUX2_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI12.CMT_TOP_IMUX33_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI13.CMT_TOP_IMUX1_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI14.CMT_TOP_IMUX32_12 always
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI15.CMT_TOP_IMUX0_12 always
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS0.PLL_CLK_FREQ_BB0_NS always
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS1.PLL_CLK_FREQ_BB1_NS always
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS2.PLL_CLK_FREQ_BB2_NS always
+CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS3.PLL_CLK_FREQ_BB3_NS always
+CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
+CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
+CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
+CMT_TOP_R_UPPER_T.PLLOUT_CLK_FREQ_BB_3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
diff --git a/kintex7/ppips_hclk_cmt.db b/kintex7/ppips_hclk_cmt.db
new file mode 100644
index 0000000..a233287
--- /dev/null
+++ b/kintex7/ppips_hclk_cmt.db
@@ -0,0 +1,4 @@
+HCLK_CMT.HCLK_CMT_BUFMR_PHASEREF0.HCLK_CMT_BUFMRCE_O0 always
+HCLK_CMT.HCLK_CMT_BUFMR_PHASEREF1.HCLK_CMT_BUFMRCE_O1 always
+HCLK_CMT.HCLK_CMT_BUFMRCE_CEINP0.HCLK_CMT_BUFMR_CE0 always
+HCLK_CMT.HCLK_CMT_BUFMRCE_CEINP1.HCLK_CMT_BUFMR_CE1 always
diff --git a/kintex7/ppips_hclk_ioi3.db b/kintex7/ppips_hclk_ioi3.db
new file mode 100644
index 0000000..71375b7
--- /dev/null
+++ b/kintex7/ppips_hclk_ioi3.db
@@ -0,0 +1,48 @@
+HCLK_IOI3.HCLK_IOI_CK_BUFRCLK0.HCLK_IOI_RCLK2RCLK0 always
+HCLK_IOI3.HCLK_IOI_CK_BUFRCLK1.HCLK_IOI_RCLK2RCLK1 always
+HCLK_IOI3.HCLK_IOI_CK_BUFRCLK2.HCLK_IOI_RCLK2RCLK2 always
+HCLK_IOI3.HCLK_IOI_CK_BUFRCLK3.HCLK_IOI_RCLK2RCLK3 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK0.HCLK_IOI_CK_BUFHCLK0 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK1.HCLK_IOI_CK_BUFHCLK1 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK2.HCLK_IOI_CK_BUFHCLK2 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK3.HCLK_IOI_CK_BUFHCLK3 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK4.HCLK_IOI_CK_BUFHCLK4 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK5.HCLK_IOI_CK_BUFHCLK5 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK6.HCLK_IOI_CK_BUFHCLK6 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK7.HCLK_IOI_CK_BUFHCLK7 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK8.HCLK_IOI_CK_BUFHCLK8 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK9.HCLK_IOI_CK_BUFHCLK9 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK10.HCLK_IOI_CK_BUFHCLK10 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK11.HCLK_IOI_CK_BUFHCLK11 always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0.HCLK_IOI_IO_PLL_CLK0_DMUX always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1.HCLK_IOI_IO_PLL_CLK1_DMUX always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2.HCLK_IOI_IO_PLL_CLK2_DMUX always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3.HCLK_IOI_IO_PLL_CLK3_DMUX always
+HCLK_IOI3.HCLK_IOI_RCLK_OUT0.HCLK_IOI_RCLK_BEFORE_DIV0 always
+HCLK_IOI3.HCLK_IOI_RCLK_OUT1.HCLK_IOI_RCLK_BEFORE_DIV1 always
+HCLK_IOI3.HCLK_IOI_RCLK_OUT2.HCLK_IOI_RCLK_BEFORE_DIV2 always
+HCLK_IOI3.HCLK_IOI_RCLK_OUT3.HCLK_IOI_RCLK_BEFORE_DIV3 always
+HCLK_IOI3.HCLK_IOI_BUFR0_CE.HCLK_RCLK_DIV_CE0 always
+HCLK_IOI3.HCLK_IOI_BUFR0_CLR.HCLK_RCLK_DIV_CLR0 always
+HCLK_IOI3.HCLK_IOI_BUFR1_CE.HCLK_RCLK_DIV_CE1 always
+HCLK_IOI3.HCLK_IOI_BUFR1_CLR.HCLK_RCLK_DIV_CLR1 always
+HCLK_IOI3.HCLK_IOI_BUFR2_CE.HCLK_RCLK_DIV_CE2 always
+HCLK_IOI3.HCLK_IOI_BUFR2_CLR.HCLK_RCLK_DIV_CLR2 always
+HCLK_IOI3.HCLK_IOI_BUFR3_CE.HCLK_RCLK_DIV_CE3 always
+HCLK_IOI3.HCLK_IOI_BUFR3_CLR.HCLK_RCLK_DIV_CLR3 always
+HCLK_IOI3.HCLK_IOI_IOCLK0.HCLK_IOI_BUFIO_O0 always
+HCLK_IOI3.HCLK_IOI_IOCLK1.HCLK_IOI_BUFIO_O1 always
+HCLK_IOI3.HCLK_IOI_IOCLK2.HCLK_IOI_BUFIO_O2 always
+HCLK_IOI3.HCLK_IOI_IOCLK3.HCLK_IOI_BUFIO_O3 always
+HCLK_IOI3.HCLK_IOI_RCLK0.HCLK_IOI_IO_PLL_CLK0_DMUX always
+HCLK_IOI3.HCLK_IOI_RCLK1.HCLK_IOI_IO_PLL_CLK1_DMUX always
+HCLK_IOI3.HCLK_IOI_RCLK2.HCLK_IOI_IO_PLL_CLK2_DMUX always
+HCLK_IOI3.HCLK_IOI_RCLK3.HCLK_IOI_IO_PLL_CLK3_DMUX always
+HCLK_IOI3.HCLK_IOI_RCLK2IO0.HCLK_IOI_CK_BUFRCLK0 always
+HCLK_IOI3.HCLK_IOI_RCLK2IO1.HCLK_IOI_CK_BUFRCLK1 always
+HCLK_IOI3.HCLK_IOI_RCLK2IO2.HCLK_IOI_CK_BUFRCLK2 always
+HCLK_IOI3.HCLK_IOI_RCLK2IO3.HCLK_IOI_CK_BUFRCLK3 always
+HCLK_IOI3.HCLK_IOI_RCLK2RCLK0.HCLK_IOI_RCLK_OUT0 always
+HCLK_IOI3.HCLK_IOI_RCLK2RCLK1.HCLK_IOI_RCLK_OUT1 always
+HCLK_IOI3.HCLK_IOI_RCLK2RCLK2.HCLK_IOI_RCLK_OUT2 always
+HCLK_IOI3.HCLK_IOI_RCLK2RCLK3.HCLK_IOI_RCLK_OUT3 always
diff --git a/kintex7/ppips_int_interface_l.db b/kintex7/ppips_int_interface_l.db
new file mode 100644
index 0000000..3b34932
--- /dev/null
+++ b/kintex7/ppips_int_interface_l.db
@@ -0,0 +1,24 @@
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L14.INT_INTERFACE_LOGIC_OUTS_L_B14 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always
diff --git a/kintex7/ppips_int_interface_r.db b/kintex7/ppips_int_interface_r.db
new file mode 100644
index 0000000..61aa2e4
--- /dev/null
+++ b/kintex7/ppips_int_interface_r.db
@@ -0,0 +1,24 @@
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always
diff --git a/kintex7/segbits_cmt_top_l_upper_t.db b/kintex7/segbits_cmt_top_l_upper_t.db
index c8d927a..ce2c2b5 100644
--- a/kintex7/segbits_cmt_top_l_upper_t.db
+++ b/kintex7/segbits_cmt_top_l_upper_t.db
@@ -1,9 +1,22 @@
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT 29_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 !28_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 !29_07
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT 29_07
-CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK 29_11
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN !28_11 28_43 !28_44 !29_10 !29_11 29_42 29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN !28_11 !28_43 28_44 !29_10 29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_11 !28_43 !28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT !28_11 !28_43 28_44 29_10 29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_09 !28_10 !29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 28_09 !28_10 !29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 !28_09 !28_10 29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 28_09 !28_10 29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 !28_09 28_10 !29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_09 28_10 !29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_08 !29_07 !29_08
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_08 29_07 !29_08
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 28_08 !29_07 !29_08
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 28_08 29_07 !29_08
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 !28_08 !29_07 29_08
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT !28_08 29_07 29_08
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
diff --git a/kintex7/segbits_cmt_top_l_upper_t.origin_info.db b/kintex7/segbits_cmt_top_l_upper_t.origin_info.db
index 16bb993..83d816c 100644
--- a/kintex7/segbits_cmt_top_l_upper_t.origin_info.db
+++ b/kintex7/segbits_cmt_top_l_upper_t.origin_info.db
@@ -1,9 +1,22 @@
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips 29_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips 28_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !29_07
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips 29_07
-CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK origin:034-cmt-pll-pips 29_11
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN origin:034-cmt-pll-pips !28_11 !28_44 !29_10 !29_11 28_43 29_42 29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_42 !29_43 28_44 29_11
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_11 !29_42 !29_43 28_44
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_11 !28_43 !28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_43 !29_10 !29_11 !29_42 !29_43 28_11 28_44
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_43 !29_11 !29_42 !29_43 28_11 28_44 29_10
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_11 !28_43 !29_42 !29_43 28_44 29_10 29_11
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_9 !29_9 28_10
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_10 !28_9 !29_9
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_10 !29_9 28_9
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_10 !28_9 29_9
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_10 28_9 29_9
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !29_9 28_10 28_9
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_8 !29_7 29_8
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_8 !29_7 !29_8
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_8 !29_8 29_7
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !29_7 !29_8 28_8
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !29_8 28_8 29_7
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_8 29_7 29_8
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
diff --git a/kintex7/segbits_cmt_top_r_upper_t.db b/kintex7/segbits_cmt_top_r_upper_t.db
index eaf5b97..b688916 100644
--- a/kintex7/segbits_cmt_top_r_upper_t.db
+++ b/kintex7/segbits_cmt_top_r_upper_t.db
@@ -1,10 +1,22 @@
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN !29_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT 29_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 !28_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT 28_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 !29_07
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT 29_07
-CMT_TOP_R_UPPER_T.EXTERNAL_FEEDBACK 29_11
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN !28_11 28_43 !28_44 !29_10 !29_11 29_42 29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN !28_11 !28_43 28_44 !29_10 29_11 !29_42 !29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 !28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT !28_11 !28_43 28_44 29_10 29_11 !29_42 !29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_09 !28_10 !29_09
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 28_09 !28_10 !29_09
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 !28_09 !28_10 29_09
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 28_09 !28_10 29_09
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 !28_09 28_10 !29_09
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT 28_09 28_10 !29_09
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 !28_08 !29_07 !29_08
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 !28_08 29_07 !29_08
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 28_08 !29_07 !29_08
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 28_08 29_07 !29_08
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 !28_08 !29_07 29_08
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT !28_08 29_07 29_08
 CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
 CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
 CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
diff --git a/kintex7/segbits_cmt_top_r_upper_t.origin_info.db b/kintex7/segbits_cmt_top_r_upper_t.origin_info.db
index 64e69e9..bdb2538 100644
--- a/kintex7/segbits_cmt_top_r_upper_t.origin_info.db
+++ b/kintex7/segbits_cmt_top_r_upper_t.origin_info.db
@@ -1,10 +1,22 @@
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !29_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips 29_10
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips 28_09
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !29_07
-CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips 29_07
-CMT_TOP_R_UPPER_T.EXTERNAL_FEEDBACK origin:034-cmt-pll-pips 29_11
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_CLKFBOUT2IN origin:034-cmt-pll-pips !28_11 !28_44 !29_10 !29_11 28_43 29_42 29_43
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_42 !29_43 28_44 29_11
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_11 !29_42 !29_43 28_44
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_11 !28_43 !29_11 !29_42 !29_43 28_44 29_10
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_43 !29_10 !29_11 !29_42 !29_43 28_11 28_44
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_43 !29_11 !29_42 !29_43 28_11 28_44 29_10
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_11 !28_43 !29_42 !29_43 28_44 29_10 29_11
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_9 !29_9 28_10
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_10 !28_9 !29_9
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_10 !29_9 28_9
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_10 !28_9 29_9
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_10 28_9 29_9
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !29_9 28_10 28_9
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_8 !29_7 29_8
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_8 !29_7 !29_8
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_8 !29_8 29_7
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !29_7 !29_8 28_8
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !29_8 28_8 29_7
+CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_8 29_7 29_8
 CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
 CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
 CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
diff --git a/zynq7/mask_lioi3.db b/zynq7/mask_lioi3.db
index 2880ad5..0fc283f 100644
--- a/zynq7/mask_lioi3.db
+++ b/zynq7/mask_lioi3.db
@@ -20,6 +20,7 @@
 bit 25_96
 bit 25_98
 bit 25_99
+bit 25_103
 bit 25_115
 bit 25_116
 bit 25_122
diff --git a/zynq7/mask_lioi3_tbytesrc.db b/zynq7/mask_lioi3_tbytesrc.db
index 2880ad5..0fc283f 100644
--- a/zynq7/mask_lioi3_tbytesrc.db
+++ b/zynq7/mask_lioi3_tbytesrc.db
@@ -20,6 +20,7 @@
 bit 25_96
 bit 25_98
 bit 25_99
+bit 25_103
 bit 25_115
 bit 25_116
 bit 25_122
diff --git a/zynq7/mask_lioi3_tbyteterm.db b/zynq7/mask_lioi3_tbyteterm.db
index 2880ad5..0fc283f 100644
--- a/zynq7/mask_lioi3_tbyteterm.db
+++ b/zynq7/mask_lioi3_tbyteterm.db
@@ -20,6 +20,7 @@
 bit 25_96
 bit 25_98
 bit 25_99
+bit 25_103
 bit 25_115
 bit 25_116
 bit 25_122
diff --git a/zynq7/mask_rioi3.db b/zynq7/mask_rioi3.db
index 2880ad5..0fc283f 100644
--- a/zynq7/mask_rioi3.db
+++ b/zynq7/mask_rioi3.db
@@ -20,6 +20,7 @@
 bit 25_96
 bit 25_98
 bit 25_99
+bit 25_103
 bit 25_115
 bit 25_116
 bit 25_122
diff --git a/zynq7/mask_rioi3_tbytesrc.db b/zynq7/mask_rioi3_tbytesrc.db
index 2880ad5..0fc283f 100644
--- a/zynq7/mask_rioi3_tbytesrc.db
+++ b/zynq7/mask_rioi3_tbytesrc.db
@@ -20,6 +20,7 @@
 bit 25_96
 bit 25_98
 bit 25_99
+bit 25_103
 bit 25_115
 bit 25_116
 bit 25_122
diff --git a/zynq7/mask_rioi3_tbyteterm.db b/zynq7/mask_rioi3_tbyteterm.db
index 2880ad5..0fc283f 100644
--- a/zynq7/mask_rioi3_tbyteterm.db
+++ b/zynq7/mask_rioi3_tbyteterm.db
@@ -20,6 +20,7 @@
 bit 25_96
 bit 25_98
 bit 25_99
+bit 25_103
 bit 25_115
 bit 25_116
 bit 25_122
diff --git a/zynq7/ppips_cmt_top_l_lower_b.db b/zynq7/ppips_cmt_top_l_lower_b.db
new file mode 100644
index 0000000..d367998
--- /dev/null
+++ b/zynq7/ppips_cmt_top_l_lower_b.db
@@ -0,0 +1,155 @@
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB0.MMCM_CLK_FREQ_BB_NS3 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB1.MMCM_CLK_FREQ_BB_NS2 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB2.MMCM_CLK_FREQ_BB_NS1 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB3.MMCM_CLK_FREQ_BB_NS0 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN1_INT.CMT_TOP_CLK0_15 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN2_INT.CMT_TOP_CLK1_15 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN3_INT.CMT_TOP_CLK0_14 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM1.CMT_LR_LOWER_B_MMCM_CLKOUT0B always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM2.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM3.CMT_LR_LOWER_B_MMCM_CLKOUT1B always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM4.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM5.CMT_LR_LOWER_B_MMCM_CLKOUT2B always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM6.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM7.CMT_LR_LOWER_B_MMCM_CLKOUT3B always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM8.CMT_LR_LOWER_B_MMCM_CLKOUT4 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM9.CMT_LR_LOWER_B_MMCM_CLKOUT5 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM10.CMT_LR_LOWER_B_MMCM_CLKOUT6 always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM11.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM12.CMT_LR_LOWER_B_MMCM_CLKFBOUTB always
+CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_MMCM13.CMT_LR_LOWER_B_MMCM_TMUXOUT always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN.CMT_LR_LOWER_B_MMCM_CLKFBOUT always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSEL.CMT_TOP_IMUX0_2 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DCLK.CMT_TOP_CLK0_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DEN.CMT_TOP_IMUX15_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DWE.CMT_TOP_IMUX22_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSCLK.CMT_TOP_CLK0_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSEN.CMT_TOP_IMUX1_2 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSINCDEC.CMT_TOP_IMUX2_2 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PWRDWN.CMT_TOP_IMUX47_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_RST.CMT_TOP_IMUX34_2 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR0.CMT_TOP_IMUX0_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR1.CMT_TOP_IMUX1_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR2.CMT_TOP_IMUX2_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR3.CMT_TOP_IMUX34_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR4.CMT_TOP_IMUX3_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR5.CMT_TOP_IMUX35_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DADDR6.CMT_TOP_IMUX44_1 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI0.CMT_TOP_IMUX0_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI1.CMT_TOP_IMUX32_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI2.CMT_TOP_IMUX1_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI3.CMT_TOP_IMUX33_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI4.CMT_TOP_IMUX2_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI5.CMT_TOP_IMUX34_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI6.CMT_TOP_IMUX3_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI7.CMT_TOP_IMUX35_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI8.CMT_TOP_IMUX4_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI9.CMT_TOP_IMUX36_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI10.CMT_TOP_IMUX5_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI11.CMT_TOP_IMUX37_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI12.CMT_TOP_IMUX6_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI13.CMT_TOP_IMUX38_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI14.CMT_TOP_IMUX7_0 always
+CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DI15.CMT_TOP_IMUX39_0 always
+CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI.CMT_MMCM_PHASER_IN_A_ICLK always
+CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI.CMT_MMCM_PHASER_IN_A_ICLKDIV always
+CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK always
+CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLKDIV always
+CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI.CMT_MMCM_PHASER_OUT_A_OCLK1X_90 always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_0.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_1.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_2.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_3.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_4.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_5.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_6.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_7.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_8.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_9.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_10.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_11.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_12.CMT_PHASER_A_ICLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_13.CMT_MMCM_PHASER_IN_B_ICLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_14.CMT_MMCM_PHASER_IN_B_ICLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLK_15.CMT_MMCM_PHASER_IN_B_ICLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_12.CMT_PHASER_A_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_13.CMT_MMCM_PHASER_IN_B_ICLKDIV always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_14.CMT_MMCM_PHASER_IN_B_ICLKDIV always
+CMT_TOP_L_LOWER_B.CMT_TOP_ICLKDIV_15.CMT_MMCM_PHASER_IN_B_ICLKDIV always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_0.CMT_LR_LOWER_B_MMCM_DO2 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B0_8.CMT_MMCM_PHASERA_DQSBUS0 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_LR_LOWER_B_MMCM_DO10 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_0.CMT_LR_LOWER_B_MMCM_DO6 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B5_8.CMT_MMCM_PHASERA_DQSBUS1 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_LR_LOWER_B_MMCM_DO14 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B8_0.CMT_LR_LOWER_B_MMCM_DO0 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B10_0.CMT_LR_LOWER_B_MMCM_DO8 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B13_0.CMT_LR_LOWER_B_MMCM_DO4 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_MMCM_PHASERA_DTSBUS0 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B14_8.CMT_MMCM_PHASERA_CTSBUS0 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_LR_LOWER_B_MMCM_DO12 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_LR_LOWER_B_MMCM_DO9 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_LR_LOWER_B_MMCM_DRDY always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B16_2.CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_LR_LOWER_B_MMCM_DO15 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_0.CMT_LR_LOWER_B_MMCM_DO1 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_1.CMT_LR_LOWER_B_MMCM_LOCKED always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B19_0.CMT_LR_LOWER_B_MMCM_DO7 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B20_0.CMT_LR_LOWER_B_MMCM_DO11 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_LR_LOWER_B_MMCM_DO13 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_LR_LOWER_B_MMCM_PSDONE always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B22_0.CMT_LR_LOWER_B_MMCM_DO3 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_0.CMT_LR_LOWER_B_MMCM_DO5 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_MMCM_PHASERA_DTSBUS1 always
+CMT_TOP_L_LOWER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_MMCM_PHASERA_CTSBUS1 always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_0.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_1.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_2.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_3.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_4.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_5.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_6.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_7.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_8.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_9.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_10.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_11.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_12.CMT_PHASER_A_OCLK_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_13.CMT_MMCM_PHASER_OUT_B_OCLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_14.CMT_MMCM_PHASER_OUT_B_OCLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK_15.CMT_MMCM_PHASER_OUT_B_OCLK always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLK1X_90_8.CMT_PHASER_A_OCLK90_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_12.CMT_PHASER_A_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_13.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_14.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_L_LOWER_B.CMT_TOP_OCLKDIV_15.CMT_MMCM_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_0.CMT_LR_LOWER_B_MMCM_CLKOUT0 always
+CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_1.CMT_LR_LOWER_B_MMCM_CLKOUT1 always
+CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_2.CMT_LR_LOWER_B_MMCM_CLKOUT2 always
+CMT_TOP_L_LOWER_B.MMCMOUT_CLK_FREQ_BB_3.CMT_LR_LOWER_B_MMCM_CLKOUT3 always
diff --git a/zynq7/ppips_cmt_top_l_lower_t.db b/zynq7/ppips_cmt_top_l_lower_t.db
new file mode 100644
index 0000000..94c8dfb
--- /dev/null
+++ b/zynq7/ppips_cmt_top_l_lower_t.db
@@ -0,0 +1,234 @@
+CMT_TOP_L_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_0.CMT_TOP_CLK0_8 always
+CMT_TOP_L_LOWER_T.CMT_BOT_HCLKMUX_CLKINT_1.CMT_TOP_CLK1_8 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI.CMT_PHASER_IN_B_ICLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI.CMT_PHASER_IN_B_ICLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI.CMT_PHASER_OUT_B_OCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI.CMT_PHASER_OUT_B_OCLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_ICLK.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_ICLKDIV.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_OCLK.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_TOMMCM_OCLKDIV.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI.CMT_PHASER_OUT_B_OCLK1X_90 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_ICLK.CMT_PHASER_IN_CA_ICLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_ICLKDIV.CMT_PHASER_IN_A_WRCLK_TOFIFO always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO.CMT_PHASER_IN_CA_ICLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_WREN_TOFIFO.CMT_PHASER_IN_CA_WRENABLE always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_RCLK0.CMT_PHASER_IN_CA_RCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLK.CMT_PHASER_IN_DB_ICLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLKDIV.CMT_PHASER_IN_B_WRCLK_TOFIFO always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_WREN_TOFIFO.CMT_PHASER_IN_DB_WRENABLE always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_RCLK1.CMT_PHASER_IN_DB_RCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX45_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX29_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX34_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX30_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX14_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_A always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX12_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX8_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX11_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX19_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX27_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX43_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX12_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX28_3 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX27_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX43_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHASER_BOT_IRANKA0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHASER_BOT_IRANKA1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_IBURSTPENDING1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX31_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX23_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX44_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX47_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASERIN_B always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX47_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX0_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX13_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_6 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX31_7 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHASER_BOT_IRANKB0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHASER_BOT_IRANKB1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLK.CMT_PHASER_OUT_CA_OCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_OCLKDIV.CMT_PHASER_OUT_A_RDCLK_TOFIFO always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO.CMT_PHASER_OUT_CA_OCLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDEN_TOFIFO.CMT_PHASER_OUT_CA_RDENABLE always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK.CMT_PHASER_OUT_DB_OCLK always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV.CMT_PHASER_OUT_B_RDCLK_TOFIFO always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDEN_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX47_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX31_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX32_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_A always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX13_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX29_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX45_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX14_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX30_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX46_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX15_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX23_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX25_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHASER_BOT_OBURSTPENDING1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX14_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX45_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX39_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX23_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX0_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX30_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX29_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX13_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_PHASER_BOT_REFMUX_0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_PHASER_BOT_REFMUX_1 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_DOWN_PHASEROUT_B always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX47_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX20_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SYNCIN.CMT_PHASER_BOT_REFMUX_2 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX44_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX21_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX29_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX45_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX14_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX30_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX46_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX15_4 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX25_5 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHASER_BOT_ENCALIB0 always
+CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHASER_BOT_ENCALIB1 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_CTSBUS0.CMT_PHASER_OUT_CA_CTSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_CTSBUS1.CMT_PHASER_OUT_CA_CTSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_DQSBUS0.CMT_PHASER_OUT_CA_DQSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_DQSBUS1.CMT_PHASER_OUT_CA_DQSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_DTSBUS0.CMT_PHASER_OUT_CA_DTSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_PHASERA_DTSBUS1.CMT_PHASER_OUT_CA_DTSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_0.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_1.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_2.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_3.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_4.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_5.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_6.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_7.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLK_8.CMT_PHASER_B_ICLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_B_ICLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B0_4.CMT_PHASER_OUT_DB_DQSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B1_3.CMT_PHASER_IN_CA_FINEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B2_7.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B3_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B5_4.CMT_PHASER_OUT_DB_DQSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_OSERDESRST always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_ISERDESRST always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B6_8.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B10_8.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_OUT_CA_OSERDESRST always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_3.CMT_PHASER_OUT_DB_DTSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_4.CMT_PHASER_OUT_DB_CTSBUS0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B15_7.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_0.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B16_6.CMT_PHASER_IN_DB_DQSFOUND always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_2.CMT_PHASER_IN_CA_ISERDESRST always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_4.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B21_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_IN_CA_DQSFOUND always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_3.CMT_PHASER_OUT_DB_DTSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_LOGIC_OUTS_L_B23_4.CMT_PHASER_OUT_DB_CTSBUS1 always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_0.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_1.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_2.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_3.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_4.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_5.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_6.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_7.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK_8.CMT_PHASER_B_OCLK_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLK1X_90_4.CMT_PHASER_B_OCLK90_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_B_OCLKDIV_TOIOI always
+CMT_TOP_L_LOWER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_B_OCLKDIV_TOIOI always
diff --git a/zynq7/ppips_cmt_top_l_upper_b.db b/zynq7/ppips_cmt_top_l_upper_b.db
new file mode 100644
index 0000000..15fe6d6
--- /dev/null
+++ b/zynq7/ppips_cmt_top_l_upper_b.db
@@ -0,0 +1,325 @@
+CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0.PLL_CLK_FREQBB_REBUFOUT0 always
+CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1.PLL_CLK_FREQBB_REBUFOUT1 always
+CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2.PLL_CLK_FREQBB_REBUFOUT2 always
+CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3.PLL_CLK_FREQBB_REBUFOUT3 always
+CMT_TOP_L_UPPER_B.CMT_L_TOP_UPPER_B_CLKINT_2.CMT_TOP_CLK0_0 always
+CMT_TOP_L_UPPER_B.CMT_L_TOP_UPPER_B_CLKINT_3.CMT_TOP_CLK1_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI.CMT_PHASER_IN_C_ICLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI.CMT_PHASER_IN_C_ICLKDIV always
+CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI.CMT_PHASER_OUT_C_OCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI.CMT_PHASER_OUT_C_OCLKDIV always
+CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI.CMT_PHASER_OUT_C_OCLK1X_90 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLK.CMT_PHASER_IN_CA_ICLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLKDIV.CMT_R_PHASER_IN_C_WRCLK_FIFO always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_WRENABLE_FIFO.CMT_PHASER_IN_CA_WRENABLE always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_RCLK2.CMT_PHASER_IN_CA_RCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADEN.CMT_TOP_IMUX31_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADEN.CMT_TOP_IMUX23_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DIVIDERST.CMT_TOP_IMUX19_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_EDGEADV.CMT_TOP_IMUX41_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEENABLE.CMT_TOP_IMUX32_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEINC.CMT_TOP_IMUX47_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK.CMT_PHASERREF_PHASERIN_C always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RCLK.CMT_PHASER_IN_CA_PHASEREFCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RST.CMT_TOP_IMUX11_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RSTDQSFIND.CMT_TOP_IMUX0_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_SYSCLK.CMT_TOP_CLK0_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL0.CMT_TOP_IMUX44_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL1.CMT_TOP_IMUX13_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL2.CMT_TOP_IMUX29_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL3.CMT_TOP_IMUX45_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL4.CMT_TOP_IMUX14_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERLOADVAL5.CMT_TOP_IMUX30_3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSEL0.CMT_TOP_IMUX34_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSEL1.CMT_TOP_IMUX3_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY0.CMT_PHY_CONTROL_IRANKC0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RANKSELPHY1.CMT_PHY_CONTROL_IRANKC1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_ICLK.CMT_PHASER_IN_DB_ICLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_ICLKDIV.CMT_R_PHASER_IN_D_WRCLK_TOFIFO always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_WRENABLE_FIFO.CMT_PHASER_IN_DB_WRENABLE always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_D_RCLK3.CMT_PHASER_IN_DB_RCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_IBURSTPENDING3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADEN.CMT_TOP_IMUX14_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADEN.CMT_TOP_IMUX45_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DIVIDERST.CMT_TOP_IMUX19_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_EDGEADV.CMT_TOP_IMUX14_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEENABLE.CMT_TOP_IMUX46_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEINC.CMT_TOP_IMUX30_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK.CMT_PHASERREF_PHASERIN_D always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RCLK.CMT_PHASER_IN_DB_PHASEREFCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RST.CMT_TOP_IMUX39_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RSTDQSFIND.CMT_TOP_IMUX8_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_SYSCLK.CMT_TOP_CLK0_8 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL0.CMT_TOP_IMUX19_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL1.CMT_TOP_IMUX27_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL2.CMT_TOP_IMUX43_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL3.CMT_TOP_IMUX12_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL4.CMT_TOP_IMUX28_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERLOADVAL5.CMT_TOP_IMUX44_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSEL0.CMT_TOP_IMUX15_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSEL1.CMT_TOP_IMUX23_7 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY0.CMT_PHY_CONTROL_IRANKD0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RANKSELPHY1.CMT_PHY_CONTROL_IRANKD1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK.CMT_PHASER_OUT_CA_OCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90.CMT_PHASER_OUT_CA_OCLKDELAYED always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV.CMT_R_PHASER_OUT_C_RDCLK_FIFO always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEENABLE.CMT_TOP_IMUX41_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEINC.CMT_TOP_IMUX9_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADEN.CMT_TOP_IMUX31_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADEN.CMT_TOP_IMUX15_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DIVIDERST.CMT_TOP_IMUX0_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_EDGEADV.CMT_TOP_IMUX2_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEENABLE.CMT_TOP_IMUX1_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEINC.CMT_TOP_IMUX47_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_C always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_RST.CMT_TOP_IMUX27_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SELFINEOCLKDELAY.CMT_TOP_IMUX0_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_SYSCLK.CMT_TOP_CLK0_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL0.CMT_TOP_IMUX20_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL1.CMT_TOP_IMUX44_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL2.CMT_TOP_IMUX13_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL3.CMT_TOP_IMUX29_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL4.CMT_TOP_IMUX45_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL5.CMT_TOP_IMUX14_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL6.CMT_TOP_IMUX30_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL7.CMT_TOP_IMUX46_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERLOADVAL8.CMT_TOP_IMUX17_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIB0.CMT_TOP_IMUX18_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLK.CMT_PHASER_OUT_DB_OCLK always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLK1X_90.CMT_PHASER_OUT_DB_OCLKDELAYED always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_D_OCLKDIV.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_BURSTPENDINGPHY.CMT_PHY_CONTROL_OBURSTPENDING3 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEENABLE.CMT_TOP_IMUX32_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEINC.CMT_TOP_IMUX16_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADEN.CMT_TOP_IMUX27_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADEN.CMT_TOP_IMUX11_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DIVIDERST.CMT_TOP_IMUX19_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_EDGEADV.CMT_TOP_IMUX9_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEENABLE.CMT_TOP_IMUX8_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEINC.CMT_TOP_IMUX43_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FREQREFCLK.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_PHASEREFCLK.CMT_PHASERREF_PHASEROUT_D always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_RST.CMT_TOP_IMUX34_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SELFINEOCLKDELAY.CMT_TOP_IMUX0_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_SYSCLK.CMT_TOP_CLK0_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL0.CMT_TOP_IMUX1_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL1.CMT_TOP_IMUX9_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL2.CMT_TOP_IMUX17_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL3.CMT_TOP_IMUX41_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL4.CMT_TOP_IMUX2_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL5.CMT_TOP_IMUX18_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL6.CMT_TOP_IMUX34_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL7.CMT_TOP_IMUX3_5 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERLOADVAL8.CMT_TOP_IMUX37_4 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIB0.CMT_TOP_IMUX17_6 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY0.CMT_PHY_CONTROL_ECALIB0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_ENCALIBPHY1.CMT_PHY_CONTROL_ECALIB1 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKIN.CMT_FREQ_PHASER_REFMUX_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKOUT_TOHCLK.CMT_PHASER_REF_CLKOUT always
+CMT_TOP_L_UPPER_B.CMT_PHASER_REF_PWRDWN.CMT_TOP_IMUX45_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_REF_RST.CMT_TOP_IMUX15_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_REF_TMUXOUT_TOHCLK.CMT_PHASER_REF_TMUXOUT always
+CMT_TOP_L_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE0.CMT_TOP_IMUX0_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASER_UP_BUFMRCE_CE1.CMT_TOP_IMUX16_0 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_CTSBUS0.CMT_PHASER_OUT_DB_CTSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_CTSBUS1.CMT_PHASER_OUT_DB_CTSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_DQSBUS0.CMT_PHASER_OUT_DB_DQSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_DQSBUS1.CMT_PHASER_OUT_DB_DQSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_DTSBUS0.CMT_PHASER_OUT_DB_DTSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_PHASERD_DTSBUS1.CMT_PHASER_OUT_DB_DTSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY.CMT_PHY_CONTROL_PHYCTLEMPTY always
+CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY.CMT_PHASER_TOP_SYNC_BB always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_MEMREFCLK.CMT_FREQ_PHASER_REFMUX_1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCLK.CMT_TOP_CLK0_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLMSTREMPTY.CMT_PHASERTOP_PHYCTLMSTREMPTY always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWRENABLE.CMT_TOP_IMUX47_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PLLLOCK.CMT_TOP_IMUX43_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_READCALIBENABLE.CMT_TOP_IMUX29_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_REFDLLLOCK.CMT_TOP_IMUX4_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_RESET.CMT_TOP_IMUX11_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_SYNCIN.CMT_FREQ_PHASER_REFMUX_2 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_WRITECALIBENABLE.CMT_TOP_IMUX22_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0.CMT_PHY_CONTROL_PCENABLECALIB0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1.CMT_PHY_CONTROL_PCENABLECALIB1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING0.CMT_PHY_CONTROL_INBURSTPENDING0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING1.CMT_PHY_CONTROL_INBURSTPENDING1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2.CMT_PHY_CONTROL_INBURSTPENDING2 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3.CMT_PHY_CONTROL_INBURSTPENDING3 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKA0.CMT_PHY_CONTROL_INRANKA0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKA1.CMT_PHY_CONTROL_INRANKA1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKB0.CMT_PHY_CONTROL_INRANKB0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKB1.CMT_PHY_CONTROL_INRANKB1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC0.CMT_PHY_CONTROL_INRANKC0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC1.CMT_PHY_CONTROL_INRANKC1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD0.CMT_PHY_CONTROL_INRANKD0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD1.CMT_PHY_CONTROL_INRANKD1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING0.CMT_PHY_CONTROL_OUTBURSTPENDING0 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING1.CMT_PHY_CONTROL_OUTBURSTPENDING1 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2.CMT_PHY_CONTROL_OUTBURSTPENDING2 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3.CMT_PHY_CONTROL_OUTBURSTPENDING3 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD0.CMT_TOP_IMUX4_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD1.CMT_TOP_IMUX20_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD2.CMT_TOP_IMUX44_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD3.CMT_TOP_IMUX13_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD4.CMT_TOP_IMUX45_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD5.CMT_TOP_IMUX14_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD6.CMT_TOP_IMUX30_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD7.CMT_TOP_IMUX46_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD8.CMT_TOP_IMUX15_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD9.CMT_TOP_IMUX31_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD10.CMT_TOP_IMUX47_9 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD11.CMT_TOP_IMUX20_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD12.CMT_TOP_IMUX44_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD13.CMT_TOP_IMUX13_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD14.CMT_TOP_IMUX45_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD15.CMT_TOP_IMUX14_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD16.CMT_TOP_IMUX30_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD17.CMT_TOP_IMUX46_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD18.CMT_TOP_IMUX15_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD19.CMT_TOP_IMUX31_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD20.CMT_TOP_IMUX47_10 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD21.CMT_TOP_IMUX43_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD22.CMT_TOP_IMUX4_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD23.CMT_TOP_IMUX20_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD24.CMT_TOP_IMUX44_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD25.CMT_TOP_IMUX13_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD26.CMT_TOP_IMUX45_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD27.CMT_TOP_IMUX14_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD28.CMT_TOP_IMUX30_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD29.CMT_TOP_IMUX46_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD30.CMT_TOP_IMUX15_11 always
+CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLWD31.CMT_TOP_IMUX31_11 always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_C_WRCLK_FIFO.CMT_PHASER_IN_CA_ICLKDIV always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_D_WRCLK_TOFIFO.CMT_PHASER_IN_DB_ICLKDIV always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDCLK_FIFO.CMT_PHASER_OUT_CA_OCLKDIV always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDENABLE_FIFO.CMT_PHASER_OUT_CA_RDENABLE always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO.CMT_PHASER_OUT_DB_OCLKDIV always
+CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO.CMT_PHASER_OUT_DB_RDENABLE always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_0.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_1.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_2.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_3.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_4.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_5.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_6.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_7.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_8.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_9.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_10.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLK_11.CMT_PHASER_C_ICLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_0.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_1.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_2.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_3.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_4.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_5.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_6.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_7.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_8.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_9.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_10.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_ICLKDIV_11.CMT_PHASER_C_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PHASER_OUT_CA_DQSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B1_7.CMT_PHASER_IN_DB_COUNTERREADVAL3 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_1.CMT_PHASER_OUT_CA_FINEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_2.CMT_PHASER_IN_CA_FINEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B2_5.CMT_PHASER_OUT_DB_COUNTERREADVAL4 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_0.CMT_PHASER_OUT_CA_COUNTERREADVAL0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_1.CMT_PHASER_OUT_CA_COUNTERREADVAL5 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_2.CMT_PHASER_IN_CA_COUNTERREADVAL1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_3.CMT_PHASER_IN_CA_COUNTERREADVAL4 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_4.CMT_PHASER_OUT_DB_COUNTERREADVAL0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_5.CMT_PHASER_OUT_DB_COUNTERREADVAL6 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B3_9.CMT_PHY_CONTROL_AUXOUTPUT0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PHASER_OUT_CA_DQSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_3.CMT_PHASER_IN_CA_DQSFOUND always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_5.CMT_PHASER_OUT_DB_COUNTERREADVAL8 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_6.CMT_PHASER_IN_DB_FINEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B6_7.CMT_PHASER_IN_DB_COUNTERREADVAL5 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_0.CMT_PHASER_OUT_CA_COUNTERREADVAL2 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_1.CMT_PHASER_OUT_CA_COUNTERREADVAL7 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_2.CMT_PHASER_IN_CA_COUNTERREADVAL3 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_4.CMT_PHASER_OUT_DB_COUNTERREADVAL2 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B7_9.CMT_PHY_CONTROL_PHYCTLALMOSTFULL always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_6.CMT_PHASER_IN_DB_DQSOUTOFRANGE always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B9_7.CMT_PHASER_IN_DB_COUNTERREADVAL4 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_2.CMT_PHASER_OUT_CA_OSERDESRST always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B10_3.CMT_PHASER_IN_CA_ISERDESRST always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_0.CMT_PHASER_REF_LOCKED always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_5.CMT_PHASER_OUT_DB_COARSEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PHASER_OUT_CA_DTSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PHASER_OUT_CA_CTSBUS0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_0.CMT_PHASER_OUT_CA_COARSEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_1.CMT_PHASER_OUT_CA_COUNTERREADVAL4 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_2.CMT_PHASER_IN_CA_COUNTERREADVAL0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_3.CMT_PHASER_IN_CA_DQSOUTOFRANGE always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_5.CMT_PHASER_OUT_DB_COUNTERREADVAL5 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B15_6.CMT_PHASER_IN_DB_COUNTERREADVAL0 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B16_5.CMT_PHASER_OUT_DB_OSERDESRST always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_0.CMT_PHASER_OUT_CA_COUNTERREADVAL3 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_2.CMT_PHASER_IN_CA_PHASELOCKED always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_4.CMT_PHASER_OUT_DB_COUNTERREADVAL3 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_6.CMT_PHASER_IN_DB_PHASELOCKED always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_8.CMT_PHY_CONTROL_PHYCTLREADY always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_9.CMT_PHY_CONTROL_PHYCTLFULL always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_10.CMT_PHY_CONTROL_AUXOUTPUT2 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B17_11.CMT_PHY_CONTROL_AUXOUTPUT3 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_6.CMT_PHASER_OUT_DB_FINEOVERFLOW always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_7.CMT_PHASER_IN_DB_COUNTERREADVAL2 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B18_8.CMT_PHASER_IN_DB_ISERDESRST always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_0.CMT_PHASER_OUT_CA_COUNTERREADVAL1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_1.CMT_PHASER_OUT_CA_COUNTERREADVAL6 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_2.CMT_PHASER_IN_CA_COUNTERREADVAL2 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_3.CMT_PHASER_IN_CA_COUNTERREADVAL5 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_4.CMT_PHASER_OUT_DB_COUNTERREADVAL1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_5.CMT_PHASER_OUT_DB_COUNTERREADVAL7 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_6.CMT_PHASER_IN_DB_COUNTERREADVAL1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B21_9.CMT_PHY_CONTROL_AUXOUTPUT1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_2.CMT_PHASER_OUT_CA_COUNTERREADVAL8 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PHASER_OUT_CA_DTSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PHASER_OUT_CA_CTSBUS1 always
+CMT_TOP_L_UPPER_B.CMT_TOP_LOGIC_OUTS_L_B23_8.CMT_PHASER_IN_DB_DQSFOUND always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_0.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_1.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_2.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_3.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_4.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_5.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_6.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_7.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_8.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_9.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_10.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK_11.CMT_PHASER_C_OCLK_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLK1X_90_7.CMT_PHASER_C_OCLK90_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_0.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_1.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_2.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_3.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_4.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_5.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_6.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_7.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_8.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_9.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_10.CMT_PHASER_C_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_B.CMT_TOP_OCLKDIV_11.CMT_PHASER_C_OCLKDIV_TOIOI always
diff --git a/zynq7/ppips_cmt_top_l_upper_t.db b/zynq7/ppips_cmt_top_l_upper_t.db
new file mode 100644
index 0000000..a5e25c4
--- /dev/null
+++ b/zynq7/ppips_cmt_top_l_upper_t.db
@@ -0,0 +1,136 @@
+CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI.CMT_PLL_PHASER_IN_D_ICLK always
+CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI.CMT_PLL_PHASER_IN_D_ICLKDIV always
+CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK always
+CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI.CMT_PLL_PHASER_OUT_D_OCLKDIV always
+CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK1X_90 always
+CMT_TOP_L_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_UP.CMT_PLL_PHYCTRL_SYNC_BB_DN always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_0.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_1.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_2.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_3.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_4.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_5.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_6.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_7.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_8.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_9.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_10.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_11.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_12.CMT_PHASER_D_ICLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_9.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_10.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_11.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_12.CMT_PHASER_D_ICLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_CLKFBOUT2IN.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0.PLL_CLK_FREQ_BB0_NS always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1.PLL_CLK_FREQ_BB1_NS always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2.PLL_CLK_FREQ_BB2_NS always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3.PLL_CLK_FREQ_BB3_NS always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL4.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL5.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL6.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL7.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT.CMT_TOP_CLK0_1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT.CMT_TOP_CLK1_0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT.CMT_TOP_CLK0_0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PLL_PHASERD_DQSBUS0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_12.CMT_TOP_R_UPPER_T_PLLE2_DO13 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B2_12.CMT_TOP_R_UPPER_T_PLLE2_DO5 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PLL_PHASERD_DQSBUS1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_12.CMT_TOP_R_UPPER_T_PLLE2_DO9 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B7_12.CMT_TOP_R_UPPER_T_PLLE2_DO1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B8_12.CMT_TOP_R_UPPER_T_PLLE2_DO15 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B10_12.CMT_TOP_R_UPPER_T_PLLE2_DO7 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B13_12.CMT_TOP_R_UPPER_T_PLLE2_DO11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PLL_PHASERD_DTSBUS0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PLL_PHASERD_CTSBUS0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B15_12.CMT_TOP_R_UPPER_T_PLLE2_DO3 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_11.CMT_TOP_R_UPPER_T_PLLE2_DRDY always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_12.CMT_TOP_R_UPPER_T_PLLE2_DO6 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B17_12.CMT_TOP_R_UPPER_T_PLLE2_DO0 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B18_12.CMT_TOP_R_UPPER_T_PLLE2_DO14 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B19_12.CMT_TOP_R_UPPER_T_PLLE2_DO8 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B20_12.CMT_TOP_R_UPPER_T_PLLE2_DO4 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_11.CMT_TOP_R_UPPER_T_PLLE2_LOCKED always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_12.CMT_TOP_R_UPPER_T_PLLE2_DO2 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B22_12.CMT_TOP_R_UPPER_T_PLLE2_DO12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PLL_PHASERD_DTSBUS1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PLL_PHASERD_CTSBUS1 always
+CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_12.CMT_TOP_R_UPPER_T_PLLE2_DO10 always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_0.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_1.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_2.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_3.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_4.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_5.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_6.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_7.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_8.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_9.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_10.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_11.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_12.CMT_PHASER_D_OCLK_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLK1X_90_7.CMT_PHASER_D_OCLK90_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_9.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_10.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_11.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_12.CMT_PHASER_D_OCLKDIV_TOIOI always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL.CMT_TOP_IMUX47_10 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DCLK.CMT_TOP_CLK0_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DEN.CMT_TOP_IMUX1_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DWE.CMT_TOP_IMUX2_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_PWRDWN.CMT_TOP_IMUX0_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_RST.CMT_TOP_IMUX13_10 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR0.CMT_TOP_IMUX47_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR1.CMT_TOP_IMUX15_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR2.CMT_TOP_IMUX22_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR3.CMT_TOP_IMUX13_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR4.CMT_TOP_IMUX44_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR5.CMT_TOP_IMUX35_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR6.CMT_TOP_IMUX3_11 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI0.CMT_TOP_IMUX39_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI1.CMT_TOP_IMUX7_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI2.CMT_TOP_IMUX38_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI3.CMT_TOP_IMUX6_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI4.CMT_TOP_IMUX37_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI5.CMT_TOP_IMUX5_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI6.CMT_TOP_IMUX36_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI7.CMT_TOP_IMUX4_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI8.CMT_TOP_IMUX35_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI9.CMT_TOP_IMUX3_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI10.CMT_TOP_IMUX34_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI11.CMT_TOP_IMUX2_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI12.CMT_TOP_IMUX33_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI13.CMT_TOP_IMUX1_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI14.CMT_TOP_IMUX32_12 always
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI15.CMT_TOP_IMUX0_12 always
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS0.PLL_CLK_FREQ_BB0_NS always
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS1.PLL_CLK_FREQ_BB1_NS always
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS2.PLL_CLK_FREQ_BB2_NS always
+CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS3.PLL_CLK_FREQ_BB3_NS always
+CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
+CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
+CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
+CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
diff --git a/zynq7/ppips_hclk_ioi3.db b/zynq7/ppips_hclk_ioi3.db
new file mode 100644
index 0000000..71375b7
--- /dev/null
+++ b/zynq7/ppips_hclk_ioi3.db
@@ -0,0 +1,48 @@
+HCLK_IOI3.HCLK_IOI_CK_BUFRCLK0.HCLK_IOI_RCLK2RCLK0 always
+HCLK_IOI3.HCLK_IOI_CK_BUFRCLK1.HCLK_IOI_RCLK2RCLK1 always
+HCLK_IOI3.HCLK_IOI_CK_BUFRCLK2.HCLK_IOI_RCLK2RCLK2 always
+HCLK_IOI3.HCLK_IOI_CK_BUFRCLK3.HCLK_IOI_RCLK2RCLK3 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK0.HCLK_IOI_CK_BUFHCLK0 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK1.HCLK_IOI_CK_BUFHCLK1 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK2.HCLK_IOI_CK_BUFHCLK2 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK3.HCLK_IOI_CK_BUFHCLK3 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK4.HCLK_IOI_CK_BUFHCLK4 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK5.HCLK_IOI_CK_BUFHCLK5 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK6.HCLK_IOI_CK_BUFHCLK6 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK7.HCLK_IOI_CK_BUFHCLK7 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK8.HCLK_IOI_CK_BUFHCLK8 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK9.HCLK_IOI_CK_BUFHCLK9 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK10.HCLK_IOI_CK_BUFHCLK10 always
+HCLK_IOI3.HCLK_IOI_CK_IGCLK11.HCLK_IOI_CK_BUFHCLK11 always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0.HCLK_IOI_IO_PLL_CLK0_DMUX always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1.HCLK_IOI_IO_PLL_CLK1_DMUX always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2.HCLK_IOI_IO_PLL_CLK2_DMUX always
+HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3.HCLK_IOI_IO_PLL_CLK3_DMUX always
+HCLK_IOI3.HCLK_IOI_RCLK_OUT0.HCLK_IOI_RCLK_BEFORE_DIV0 always
+HCLK_IOI3.HCLK_IOI_RCLK_OUT1.HCLK_IOI_RCLK_BEFORE_DIV1 always
+HCLK_IOI3.HCLK_IOI_RCLK_OUT2.HCLK_IOI_RCLK_BEFORE_DIV2 always
+HCLK_IOI3.HCLK_IOI_RCLK_OUT3.HCLK_IOI_RCLK_BEFORE_DIV3 always
+HCLK_IOI3.HCLK_IOI_BUFR0_CE.HCLK_RCLK_DIV_CE0 always
+HCLK_IOI3.HCLK_IOI_BUFR0_CLR.HCLK_RCLK_DIV_CLR0 always
+HCLK_IOI3.HCLK_IOI_BUFR1_CE.HCLK_RCLK_DIV_CE1 always
+HCLK_IOI3.HCLK_IOI_BUFR1_CLR.HCLK_RCLK_DIV_CLR1 always
+HCLK_IOI3.HCLK_IOI_BUFR2_CE.HCLK_RCLK_DIV_CE2 always
+HCLK_IOI3.HCLK_IOI_BUFR2_CLR.HCLK_RCLK_DIV_CLR2 always
+HCLK_IOI3.HCLK_IOI_BUFR3_CE.HCLK_RCLK_DIV_CE3 always
+HCLK_IOI3.HCLK_IOI_BUFR3_CLR.HCLK_RCLK_DIV_CLR3 always
+HCLK_IOI3.HCLK_IOI_IOCLK0.HCLK_IOI_BUFIO_O0 always
+HCLK_IOI3.HCLK_IOI_IOCLK1.HCLK_IOI_BUFIO_O1 always
+HCLK_IOI3.HCLK_IOI_IOCLK2.HCLK_IOI_BUFIO_O2 always
+HCLK_IOI3.HCLK_IOI_IOCLK3.HCLK_IOI_BUFIO_O3 always
+HCLK_IOI3.HCLK_IOI_RCLK0.HCLK_IOI_IO_PLL_CLK0_DMUX always
+HCLK_IOI3.HCLK_IOI_RCLK1.HCLK_IOI_IO_PLL_CLK1_DMUX always
+HCLK_IOI3.HCLK_IOI_RCLK2.HCLK_IOI_IO_PLL_CLK2_DMUX always
+HCLK_IOI3.HCLK_IOI_RCLK3.HCLK_IOI_IO_PLL_CLK3_DMUX always
+HCLK_IOI3.HCLK_IOI_RCLK2IO0.HCLK_IOI_CK_BUFRCLK0 always
+HCLK_IOI3.HCLK_IOI_RCLK2IO1.HCLK_IOI_CK_BUFRCLK1 always
+HCLK_IOI3.HCLK_IOI_RCLK2IO2.HCLK_IOI_CK_BUFRCLK2 always
+HCLK_IOI3.HCLK_IOI_RCLK2IO3.HCLK_IOI_CK_BUFRCLK3 always
+HCLK_IOI3.HCLK_IOI_RCLK2RCLK0.HCLK_IOI_RCLK_OUT0 always
+HCLK_IOI3.HCLK_IOI_RCLK2RCLK1.HCLK_IOI_RCLK_OUT1 always
+HCLK_IOI3.HCLK_IOI_RCLK2RCLK2.HCLK_IOI_RCLK_OUT2 always
+HCLK_IOI3.HCLK_IOI_RCLK2RCLK3.HCLK_IOI_RCLK_OUT3 always
diff --git a/zynq7/ppips_int_interface_l.db b/zynq7/ppips_int_interface_l.db
new file mode 100644
index 0000000..3b34932
--- /dev/null
+++ b/zynq7/ppips_int_interface_l.db
@@ -0,0 +1,24 @@
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L0.INT_INTERFACE_LOGIC_OUTS_L_B0 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L1.INT_INTERFACE_LOGIC_OUTS_L_B1 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L2.INT_INTERFACE_LOGIC_OUTS_L_B2 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L3.INT_INTERFACE_LOGIC_OUTS_L_B3 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L4.INT_INTERFACE_LOGIC_OUTS_L_B4 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L5.INT_INTERFACE_LOGIC_OUTS_L_B5 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L6.INT_INTERFACE_LOGIC_OUTS_L_B6 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L7.INT_INTERFACE_LOGIC_OUTS_L_B7 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L8.INT_INTERFACE_LOGIC_OUTS_L_B8 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L9.INT_INTERFACE_LOGIC_OUTS_L_B9 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L10.INT_INTERFACE_LOGIC_OUTS_L_B10 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L11.INT_INTERFACE_LOGIC_OUTS_L_B11 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L12.INT_INTERFACE_LOGIC_OUTS_L_B12 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L13.INT_INTERFACE_LOGIC_OUTS_L_B13 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L14.INT_INTERFACE_LOGIC_OUTS_L_B14 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L15.INT_INTERFACE_LOGIC_OUTS_L_B15 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L16.INT_INTERFACE_LOGIC_OUTS_L_B16 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L17.INT_INTERFACE_LOGIC_OUTS_L_B17 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L18.INT_INTERFACE_LOGIC_OUTS_L_B18 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L19.INT_INTERFACE_LOGIC_OUTS_L_B19 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L20.INT_INTERFACE_LOGIC_OUTS_L_B20 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L21.INT_INTERFACE_LOGIC_OUTS_L_B21 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L22.INT_INTERFACE_LOGIC_OUTS_L_B22 always
+INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L23.INT_INTERFACE_LOGIC_OUTS_L_B23 always
diff --git a/zynq7/ppips_int_interface_r.db b/zynq7/ppips_int_interface_r.db
new file mode 100644
index 0000000..61aa2e4
--- /dev/null
+++ b/zynq7/ppips_int_interface_r.db
@@ -0,0 +1,24 @@
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS0.INT_INTERFACE_LOGIC_OUTS_B0 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS1.INT_INTERFACE_LOGIC_OUTS_B1 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS2.INT_INTERFACE_LOGIC_OUTS_B2 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS3.INT_INTERFACE_LOGIC_OUTS_B3 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS4.INT_INTERFACE_LOGIC_OUTS_B4 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS5.INT_INTERFACE_LOGIC_OUTS_B5 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS6.INT_INTERFACE_LOGIC_OUTS_B6 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS7.INT_INTERFACE_LOGIC_OUTS_B7 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS8.INT_INTERFACE_LOGIC_OUTS_B8 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS9.INT_INTERFACE_LOGIC_OUTS_B9 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS10.INT_INTERFACE_LOGIC_OUTS_B10 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS11.INT_INTERFACE_LOGIC_OUTS_B11 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS12.INT_INTERFACE_LOGIC_OUTS_B12 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS13.INT_INTERFACE_LOGIC_OUTS_B13 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS14.INT_INTERFACE_LOGIC_OUTS_B14 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS15.INT_INTERFACE_LOGIC_OUTS_B15 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS16.INT_INTERFACE_LOGIC_OUTS_B16 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS17.INT_INTERFACE_LOGIC_OUTS_B17 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS18.INT_INTERFACE_LOGIC_OUTS_B18 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS19.INT_INTERFACE_LOGIC_OUTS_B19 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS20.INT_INTERFACE_LOGIC_OUTS_B20 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS21.INT_INTERFACE_LOGIC_OUTS_B21 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS22.INT_INTERFACE_LOGIC_OUTS_B22 always
+INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS23.INT_INTERFACE_LOGIC_OUTS_B23 always
diff --git a/zynq7/segbits_cmt_top_l_upper_t.db b/zynq7/segbits_cmt_top_l_upper_t.db
index 9f39c9f..e50e31c 100644
--- a/zynq7/segbits_cmt_top_l_upper_t.db
+++ b/zynq7/segbits_cmt_top_l_upper_t.db
@@ -1,9 +1,22 @@
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT 29_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 !28_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 !29_07
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT 29_07
-CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK 29_11
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN !28_11 28_43 !28_44 !29_10 !29_11 29_42 29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN !28_11 !28_43 28_44 !29_10 29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_11 !28_43 !28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 28_11 !28_43 28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 28_11 !28_43 28_44 29_10 !29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT !28_11 !28_43 28_44 29_10 29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_09 !28_10 !29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 28_09 !28_10 !29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 !28_09 !28_10 29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 28_09 !28_10 29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 !28_09 28_10 !29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_09 28_10 !29_09
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 !28_08 !29_07 !29_08
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 !28_08 29_07 !29_08
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 28_08 !29_07 !29_08
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 28_08 29_07 !29_08
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 !28_08 !29_07 29_08
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT !28_08 29_07 29_08
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164
diff --git a/zynq7/segbits_cmt_top_l_upper_t.origin_info.db b/zynq7/segbits_cmt_top_l_upper_t.origin_info.db
index ebb5a10..a2748e6 100644
--- a/zynq7/segbits_cmt_top_l_upper_t.origin_info.db
+++ b/zynq7/segbits_cmt_top_l_upper_t.origin_info.db
@@ -1,9 +1,22 @@
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips 29_10
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips 28_09
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !29_07
-CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips 29_07
-CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK origin:034-cmt-pll-pips 29_11
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_CLKFBOUT2IN origin:034-cmt-pll-pips !28_11 !28_44 !29_10 !29_11 28_43 29_42 29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_CLKFBIN origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_42 !29_43 28_44 29_11
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_11 !28_43 !29_10 !29_11 !29_42 !29_43 28_44
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_11 !28_43 !28_44 !29_10 !29_11 !29_42 !29_43
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_43 !29_10 !29_11 !29_42 !29_43 28_11 28_44
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_43 !29_11 !29_42 !29_43 28_11 28_44 29_10
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips !28_11 !28_43 !29_42 !29_43 28_44 29_10 29_11
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_CLKIN1 origin:034-cmt-pll-pips !28_9 !29_9 28_10
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_10 !28_9 !29_9
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_10 !29_9 28_9
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !28_10 !28_9 29_9
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !28_10 28_9 29_9
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips !29_9 28_10 28_9
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_CLKIN2 origin:034-cmt-pll-pips !28_8 !29_7 29_8
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB0 origin:034-cmt-pll-pips !28_8 !29_7 !29_8
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB1 origin:034-cmt-pll-pips !28_8 !29_8 29_7
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB2 origin:034-cmt-pll-pips !29_7 !29_8 28_8
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_FREQ_BB3 origin:034-cmt-pll-pips !29_8 28_8 29_7
+CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips !28_8 29_7 29_8
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163
 CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164
diff --git a/zynq7/segbits_int_l.origin_info.db b/zynq7/segbits_int_l.origin_info.db
index bbd79c5..48a18dd 100644
--- a/zynq7/segbits_int_l.origin_info.db
+++ b/zynq7/segbits_int_l.origin_info.db
@@ -353,7 +353,7 @@
 INT_L.EE4BEG0.SS2END0 origin:050-pip-seed 03_08 05_11
 INT_L.EE4BEG0.SS6END0 origin:050-pip-seed 05_11 06_08
 INT_L.EE4BEG0.SW2END0 origin:050-pip-seed 02_09 05_11
-INT_L.EE4BEG0.SW6END0 origin:056-pip-rem 05_08 05_11
+INT_L.EE4BEG0.SW6END0 origin:050-pip-seed 05_08 05_11
 INT_L.EE4BEG1.EE2END1 origin:050-pip-seed 03_24 03_25
 INT_L.EE4BEG1.EE4END1 origin:050-pip-seed 03_25 05_24
 INT_L.EE4BEG1.LH6 origin:056-pip-rem 05_24 07_25
@@ -413,7 +413,7 @@
 INT_L.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
 INT_L.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
 INT_L.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_L.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
+INT_L.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
 INT_L.EL1BEG0.EE2END1 origin:050-pip-seed 07_20 15_21
 INT_L.EL1BEG0.EE4END1 origin:050-pip-seed 07_20 12_21
 INT_L.EL1BEG0.EL1END1 origin:050-pip-seed 11_21 13_21
@@ -584,7 +584,7 @@
 INT_L.FAN_ALT0.GFAN0 origin:054-pip-fan-alt !22_00 !23_00 !24_00 21_00 25_00
 INT_L.FAN_ALT0.LOGIC_OUTS_L0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
 INT_L.FAN_ALT0.LOGIC_OUTS_L12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
-INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
+INT_L.FAN_ALT0.LOGIC_OUTS_L22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
 INT_L.FAN_ALT0.NE2END0 origin:050-pip-seed !22_00 !23_00 !25_00 18_01 24_00
 INT_L.FAN_ALT0.NL1END0 origin:050-pip-seed !22_00 19_01 23_00 24_00 25_00
 INT_L.FAN_ALT0.NN2END0 origin:050-pip-seed !22_00 !23_00 !24_00 18_01 25_00
@@ -2193,7 +2193,7 @@
 INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55
 INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52
 INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53
-INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52
+INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52
 INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17
 INT_L.NL1BEG0.LOGIC_OUTS_L13 origin:050-pip-seed 10_17 14_17
 INT_L.NL1BEG0.LOGIC_OUTS_L19 origin:050-pip-seed 08_17 14_17
@@ -2431,7 +2431,7 @@
 INT_L.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
 INT_L.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
 INT_L.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
-INT_L.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
+INT_L.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
 INT_L.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
 INT_L.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
 INT_L.NR1BEG0.EE2END0 origin:050-pip-seed 10_07 15_07
@@ -3307,7 +3307,7 @@
 INT_L.SW6BEG3.NW2END_S0_0 origin:050-pip-seed 02_61 05_63
 INT_L.SW6BEG3.NW6END_S0_0 origin:050-pip-seed 05_63 06_60
 INT_L.SW6BEG3.SE2END3 origin:050-pip-seed 02_61 04_61
-INT_L.SW6BEG3.SE6END3 origin:056-pip-rem 04_61 06_60
+INT_L.SW6BEG3.SE6END3 origin:050-pip-seed 04_61 06_60
 INT_L.SW6BEG3.SS2END3 origin:050-pip-seed 03_60 03_61
 INT_L.SW6BEG3.SS6END3 origin:050-pip-seed 03_61 06_60
 INT_L.SW6BEG3.SW2END3 origin:050-pip-seed 02_61 03_61
diff --git a/zynq7/segbits_int_r.origin_info.db b/zynq7/segbits_int_r.origin_info.db
index 454cdac..21a63e5 100644
--- a/zynq7/segbits_int_r.origin_info.db
+++ b/zynq7/segbits_int_r.origin_info.db
@@ -172,7 +172,7 @@
 INT_R.BYP_ALT7.EL1END_S3_0 origin:050-pip-seed !23_63 17_63 22_63 24_63 25_63
 INT_R.BYP_ALT7.ER1END3 origin:050-pip-seed !22_63 16_63 23_63 24_63 25_63
 INT_R.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63
-INT_R.BYP_ALT7.FAN_BOUNCE_S3_6 origin:056-pip-rem !22_63 21_63 23_63 24_63 25_63
+INT_R.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63
 INT_R.BYP_ALT7.GFAN1 origin:054-pip-fan-alt !22_63 !23_63 !25_63 20_63 24_63
 INT_R.BYP_ALT7.LOGIC_OUTS15 origin:051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63
 INT_R.BYP_ALT7.LOGIC_OUTS21 origin:051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63
@@ -373,7 +373,7 @@
 INT_R.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27
 INT_R.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24
 INT_R.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27
-INT_R.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27
+INT_R.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27
 INT_R.EE4BEG2.EE2END2 origin:050-pip-seed 03_40 03_41
 INT_R.EE4BEG2.EE4END2 origin:050-pip-seed 03_41 05_40
 INT_R.EE4BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_40 07_41
@@ -393,7 +393,7 @@
 INT_R.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43
 INT_R.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40
 INT_R.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43
-INT_R.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43
+INT_R.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43
 INT_R.EE4BEG3.EE2END3 origin:050-pip-seed 03_56 03_57
 INT_R.EE4BEG3.EE4END3 origin:050-pip-seed 03_57 05_56
 INT_R.EE4BEG3.LH0 origin:056-pip-rem 04_58 05_56
@@ -413,7 +413,7 @@
 INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59
 INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56
 INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59
-INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59
+INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59
 INT_R.EL1BEG0.EE2END1 origin:050-pip-seed 07_20 15_21
 INT_R.EL1BEG0.EE4END1 origin:050-pip-seed 07_20 12_21
 INT_R.EL1BEG0.EL1END1 origin:050-pip-seed 11_21 13_21
@@ -584,7 +584,7 @@
 INT_R.FAN_ALT0.GFAN0 origin:054-pip-fan-alt !22_00 !23_00 !24_00 21_00 25_00
 INT_R.FAN_ALT0.LOGIC_OUTS0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00
 INT_R.FAN_ALT0.LOGIC_OUTS12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00
-INT_R.FAN_ALT0.LOGIC_OUTS22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00
+INT_R.FAN_ALT0.LOGIC_OUTS22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00
 INT_R.FAN_ALT0.NE2END0 origin:050-pip-seed !22_00 !23_00 !25_00 18_01 24_00
 INT_R.FAN_ALT0.NL1END0 origin:050-pip-seed !22_00 19_01 23_00 24_00 25_00
 INT_R.FAN_ALT0.NN2END0 origin:050-pip-seed !22_00 !23_00 !24_00 18_01 25_00
@@ -678,7 +678,7 @@
 INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08
 INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08
 INT_R.FAN_ALT4.GFAN0 origin:054-pip-fan-alt !22_08 !23_08 !24_08 21_08 25_08
-INT_R.FAN_ALT4.LOGIC_OUTS18 origin:056-pip-rem !22_08 !23_08 !25_08 21_08 24_08
+INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08
 INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08
 INT_R.FAN_ALT4.LOGIC_OUTS8 origin:050-pip-seed !22_08 21_08 23_08 24_08 25_08
 INT_R.FAN_ALT4.NE2END0 origin:050-pip-seed !22_08 !23_08 !25_08 17_08 24_08
@@ -2173,7 +2173,7 @@
 INT_R.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39
 INT_R.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36
 INT_R.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37
-INT_R.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36
+INT_R.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36
 INT_R.NE6BEG3.EE2END3 origin:050-pip-seed 03_52 05_55
 INT_R.NE6BEG3.EE4END3 origin:050-pip-seed 05_52 05_55
 INT_R.NE6BEG3.LH0 origin:056-pip-rem 04_54 05_52
@@ -2431,7 +2431,7 @@
 INT_R.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52
 INT_R.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55
 INT_R.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54
-INT_R.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55
+INT_R.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55
 INT_R.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52
 INT_R.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55
 INT_R.NR1BEG0.EE2END0 origin:050-pip-seed 10_07 15_07
@@ -2609,7 +2609,7 @@
 INT_R.NW6BEG0.NW2END0 origin:050-pip-seed 02_02 03_02
 INT_R.NW6BEG0.NW6END0 origin:050-pip-seed 02_02 07_03
 INT_R.NW6BEG0.SS2END_N0_3 origin:050-pip-seed 02_03 04_00
-INT_R.NW6BEG0.SS6END_N0_3 origin:050-pip-seed 04_00 07_03
+INT_R.NW6BEG0.SS6END_N0_3 origin:056-pip-rem 04_00 07_03
 INT_R.NW6BEG0.SW2END_N0_3 origin:050-pip-seed 03_02 04_00
 INT_R.NW6BEG0.SW6END_N0_3 origin:050-pip-seed 04_00 04_03
 INT_R.NW6BEG0.WW2END_N0_3 origin:050-pip-seed 02_02 02_03
@@ -3275,7 +3275,7 @@
 INT_R.SW6BEG1.WW2END1 origin:050-pip-seed 03_28 05_31
 INT_R.SW6BEG1.WW4END2 origin:050-pip-seed 05_28 05_31
 INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45
-INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44
+INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44
 INT_R.SW6BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_44 04_46
 INT_R.SW6BEG2.LOGIC_OUTS14 origin:050-pip-seed 03_44 07_45
 INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44